Static nearest-neighbour lattice cx_nn

A connectivity primitive, not a qubit type: the interaction graph is frozen at mask level, each site coupling only to lithographic neighbours, because capacitive/inductive and exchange couplings decay over microns and nanometres. The anchor is Barends et al. (Google/UCSB, 2014-02): five Xmon qubits in a linear nearest-neighbour array, 2Q up to 99.4%, at the surface-code threshold D[284]. IBM's heavy-hex arrived in 2019 as a code construction — a surface/Bacon–Shor hybrid with flag qubits, cutting fixed-frequency collisions "by several orders of magnitude" at the cost of coordination number S[476]; the flagship has since returned to a square lattice C[49].
Attributes: fully fabricated affinity; no time constant, readout or control of its own — a topology, not a device; static, lithographic, coherent error: "heavy-hex (degree 2.3) or square lattice (degree 3.5–3.6) with on-chip couplers; ZZ crosstalk is the tax" (graph record).

The floor is not a coherence floor. Always-on coupling leaves residual ZZ; tunable couplers null the static part but add a flux line, a leakage path and flux-noise susceptibility S[476]. In the only published full error budget at code scale — Google's d=7 run on Willow — CZ crosstalk contributes 5.5×10⁻⁴ D[1]. The binding constraint is geometric: a stabiliser code with 2D-local checks obeys the Bravyi–Poulin–Terhal bound kd² ≲ n, so this topology hosts only the surface/colour family at order 2d² physical qubits per logical one — a rate no better qubit can raise. The second tax is routing: an arbitrary interaction on a degree-2.3–3.6 graph costs SWAP depth scaling with lattice diameter. Only breaking 2D locality moves the floor.

For digital simulation of time-independent, finite-range lattice Hamiltonians in a fixed dimension, nearest-neighbour connectivity is near-optimal: a nearest-neighbour circuit reaches depth O(T log(nT/ε)) with O(nT log(nT/ε)) gates and O(n) ancilla qubits, for n qubits, evolution time T and error ε, against an unconditional lower bound of Ω(log n / log log n) depth for uniform XXZ dynamics at fixed time P[894]. The count assumes exact single-qubit rotations; synthesis over a finite gate set adds a polylogarithmic factor.

Best demonstrated is an isolated pair: IQM's flux-tunable-coupler CZ at 99.93% over 40 hours, with 99.98% 1Q and >99.94% simultaneous readout on the same device D[38]. Typical at scale is IBM's fleet error per layered gate, 3.7×10⁻³ typical and 1.9×10⁻³ best (July 2026), measured full-width D[33]. That ≈5× gap between a characterised pair and a full-width layer is the lattice tax; inside it the two-qubit gate dominates, about 40% of Google's colour-code budget D[41]. Foundry spin arrays sit a generation behind, 2Q 99.04–99.56% D[189].

Superconducting lattices are Nb/Al junction films patterned by DUV or e-beam; EUV is not required and no fielded transmon lattice uses it — IBM runs 300 mm at Albany, Google in-house. Spin dot arrays are foundry-native and EUV-dependent: Intel 300 mm, >24,000 devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766]; GlobalFoundries 22FDX for Quantum Motion; STMicroelectronics FD-SOI for Quobly Cfact. Uniformity, not peak fidelity, limits that branch: imec's eight-qubit device had a validated two-qubit gate on one of four pairs D[197]. Export exposure attaches to the machine, not the topology (ECCN 4A906, 3A904, 3A901.a) G[301].

The lattice buys no wiring saving. Nighthawk carries 218 tunable couplers for 120 qubits: the coupler count — roughly 1.8 flux lines per qubit above drive and readout — sets the harness C[49]. At 10³ the harness is buildable; at 10⁴ it binds on cryostat area and heat load, which IBM's 0.53 m² wiring area and 2.75 m³ vacuum volume per modular cell are sized against C[50]; at 10⁶ nothing at room temperature closes. Both mitigations sit far below lattice scale: SEEQC's millikelvin SFQ control flip-chip-integrated with qubits, 1Q up to 99.9% D[304], and HRL's 4 K cryo-CMOS sequencer running 18 qubits with no room-temperature real-time electronics D[190].

It underlies the transmon architecture (IBM, Google, Rigetti, IQM, Fujitsu), the bosonic and dual-rail superconducting architectures, the silicon and germanium quantum-dot spin architecture (Intel, Diraq, Quantum Motion, HRL→IBM), the silicon donor-spin architecture, defect-spin nodes and the topological tetron (Majorana) architecture. It provides the 2D-local checks the rotated surface and colour codes need, and is the alternative to long-range on-chip couplers, shuttled spins and shared-line crossbars; switching costs a mask redesign. It conflicts with degree-≥6 qLDPC codes, all-to-all high-rate codes, transversal-permutation schemes and cm-scale 3D cavities. Having no transport step it adds zero to the transport term of the derived clock (= sum of the syndrome round: gate layers + transport + readout + reset); its cost hides in the gate term as SWAP depth. The neighbouring empty slot is a degree-≥6 static lattice at parity fidelity with degree-3.5.

Crosstalk and coupler figures come from randomised or cross-entropy benchmarking on pairs or small subsets. The 5.5×10⁻⁴ CZ crosstalk is a fitted component of Google's device-wide error budget, not an independent measurement; no vendor publishes full-lattice simultaneous crosstalk. Error per layered gate is the only full-width metric in fleet use and only IBM reports it, so cross-vendor comparison of the lattice tax is impossible today. Rigetti's 99.5%→99.1% median drop across its 36→108-qubit tiling is unattributed C[36].

The PatSnap patent counts come from secondary sources.

Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| IBM | Developer | US | Heavy-hex then square lattices; Nighthawk 120 q | C[49] |
| Google | Developer | US | Square lattices; d=7 code on 105 qubits | D[1] |
| Rigetti | Developer | US | Tiles chiplets into 108 qubits | C[36] |
| IQM | Developer | FI | Transmon line; isolated-pair CZ 99.93% | D[38] |
| GlobalFoundries | Supplier | US | 22FDX spin-dot wafers | Cfact |

Money.

• 2026-05-21 · US Dept of Commerce · CHIPS letters of intent, nine firms (IBM/Anderon $1 B, GlobalFoundries $375 M, Diraq ≤$38 M) · $2.013 B · LOI, non-binding fact
• 2026-06-02 · IBM · five-year quantum commitment · >$10 B · announced Cfact
• 2026-07-02 · IQM · Nasdaq/Helsinki listing · cash €337 M pro-forma · closed Cfact
• 2026-08 · Rigetti · Q2-2026 results · revenue $5.1 M, cash $541.3 M · reported Cfact

Market & supply chain. Transmon lattices consume DUV/e-beam tooling, flip-chip bonders, TWPA amplifiers and control racks; spin lattices consume ASML EUV inside Intel, GlobalFoundries and STMicroelectronics — a single point of failure the superconducting branch does not share. G1–G3 pay for the lattice; G4 is the goal it cannot reach unaided.

IP & standards. The IP is coupler-level: IBM US 11,727,297 B2 (granted 2023-08-15) claims an opposite-sign second coupling path cancelling coherent error Pfact. Aggregate quantum families in PatSnap's landscape published on 2026-06-30: IBM 4,388, Google 2,385 P[312]. No topology standard exists.

Roadmaps & track record. IBM Nighthawk (promised 2025-06-10, for 2025, delivered 2025-12) Cfact; Kookaburra, the first step off pure nearest-neighbour connectivity (promised 2022-05-10 for 2025, redefined for 2026, undelivered as of 2026-09-04) Rfact; Rigetti median 99.5% at 108 q (promised for end-2025, slipped to "later 2026", unmet) Rfact. IBM ships the base lattice on time and misses every date beyond it.

Strategic reading. If this topology stays the only manufacturable one, the winners own 2D-local decoding and yield — IBM and Google in superconductors, CMOS foundries in spins — and the losers are high-rate-code startups betting on connectivity nobody can fabricate. If degree rises, leverage moves to coupler and packaging IP — what IBM's coupler patents and the HRL purchase buy.

Confirm or demote within 12–24 months: does Kookaburra ship a qLDPC memory on c-coupled hardware or slip again; does Rigetti reach median 99.5% at 108 qubits; does any vendor publish a full-lattice simultaneous-crosstalk number. Best case by 2029: degree-6 on-chip routing ships without a fidelity penalty and a planar lattice hosts a high-rate memory. Worst case: coordination stays near 3.5 and scale is bought with 2d² overhead. Open: whether the pair-to-full-width gap is intrinsic.