Silicon / germanium quantum-dot spins on the map bar: CMOS spin qubits

The architecture in the report (§8.3)

8.3.13 CMOS spin qubits — Silicon / germanium quantum-dot spins (spin_qd)

The idea. A Gate-defined quantum-dot spin (qd_spin) is a transistor-sized gate stack: printed by a 300 mm CMOS foundry (fab_cmos), entangled by a pulse on the barrier to its neighbour, the Exchange gate (g_exch), read by Spin-to-charge conversion (ro_s2c), and coherent 1.31 ms (Hahn echo) on foundry ²⁸Si [D][197]. The bet: dots uniform enough to share calibration, with control moved into the cryostat, scale like transistors. The price: a readout-limited clock, 8.5 µs derived [S] against ~100–300 µs as run [G] (§7.4), and reach only to neighbours unless spins move.

What it needs. Exchange requires the dots and baseband pulses: its strength depends exponentially on barrier voltage, and HRL puts ~80% of its CNOT error on control and calibration [D][190], [191]. Carrier, cryo-CMOS, conveyor and the Cryogenic signal fan-out all require the foundry; the fan-out also requires cryo-CMOS behind it: Intel's Pando Tree serves up to 64 qubit terminals at 10–20 mK from one signal and nine digital lines of Horse Ridge II, 0.156 lines per terminal [C][272]. The surface code requires a 2D nearest-neighbour lattice, which no register device shows; qLDPC conflicts with it (long-range checks), needing the conveyor that replaces it. Crossbar lines conflict with per-pair calibration. Five layers hold one technology; none links modules.

Where it stands. Nine machines, six devices (Table 8.3): demonstrated, the HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots — Table 8.3's largest gate-capable device, level at 18 with Groove's, added to the register on 26 Sep 2026 [D][190], [191]), Tunnel Falls (Intel; 12 qubits [D][199]), the foundry 8-qubit array (Diraq/imec, exchange in one of four pairs [D][197]) and Groove Quantum's 18-qubit germanium spin processor (April 2026, no fidelities or paper [P][879]); deployed, RacQ (Equal1; sold as Bell-1 until May 2026, the name ESA still uses [C][237], [881]), installed at ESA's Frascati centre in July 2026 [C][881], and QM-One (Quantum Motion, count unpublished [200]); announced, the Diraq 8-qubit silicon spin quantum computer at Equinix Sydney and the Hitachi x Intel 18A spin programme; planned, Alloy Pioneer (Quobly), cloud access by end-2026 [R][201]. The best two-qubit error among devices, 3.0×10⁻³, is HRL's [D][190], [191]; Equal1's product page claims 99.3% (7.0×10⁻³) [C][273] where a press survey prints 98.4% [P][274]; no other machine publishes one. Off-register bests: 99.04–99.56% on foundry two-qubit devices [D][189]. HRL's bit-flip repetition code, error falling 4.7× from distance 3 to 5, sequenced from 4 K, is the architecture's only error-correction run [D][190], [191].

Exceptions and borrowings. No better-fitting architecture; two technology cells sit off the slots, HRL's error-detection code (code_detect) and RacQ's cryogenic decoder (dec_cryo), an alternate not yet run. Until 26 Sep 2026 the primaries described an absent machine — all eight rows used Single-spin (Loss–DiVincenzo) encoding, none Exchange-only encoding; HRL's device, now IBM's [204], is now the ninth row and the architecture's only carrier of its primary encoding, with its repetition code and parity decoder as Atlas gaps (∅G-repetition, ∅G-parity). The foundry 8-qubit array holds the only in-slot code cell, a roadmap qLDPC with shuttling as alternate (early stage), and carries 1.1×10⁻² from other devices at 1 K [D][194]. The on-die control of RacQ and QM-One is an Atlas gap (∅G-qsoc). Tunnel Falls mixes cryo-CMOS and room-temperature drive (hybrid); Equinix control is undisclosed. Only Tunnel Falls documents its fan-out; the cells of QM-One, RacQ and the Hitachi programme are inferred. Four drive single spins by ESR or EDSR, the Microwave / optical spin gates (g_mwspin) that layer 3 lists as the alternate; their gate cells name only the exchange gate. Borrowers: cryo-CMOS on five superconducting machines; the foundry on thirteen, eight ion traps.

The next test. By March 2028 (§5.2): a 300 mm array above 20 qubits with all-pairs two-qubit fidelity ≥ 99.5% and µs-class readout confirms; Diraq's 2029 target (150 k physical, 1 k logical [R][211], [212]) cut again demotes. If the Equinix system (due October 2026 [C][206]) and Alloy Pioneer reach 2028 without their own two-qubit error, the best number stays a vendor's.

What the builders say. Diraq argues from the foundry: its qubits are made like the chips in phones and laptops, a path to millions of qubits on one chip [C][861]. Quobly, making its chips on STMicroelectronics' 300 mm line, targets one million qubits by 2032, after cloud access to its first machine, Alloy Pioneer, by end-2026 [R][201]. Hitachi, with Intel and AIST, plans error-corrected prototypes of 100 qubits in fiscal 2028 and 1,000 in fiscal 2030 on Intel's 18A process [R][862]. HRL answers the wiring problem with a cryogenic CMOS controller that ran error correction on 18-qubit devices without room-temperature control [D][190], [191]. Equal1 fits a silicon-spin computer cooled to 0.3 K into one 19-inch rack [C][237]; Quantum Motion's QM-One takes three [C][200].

Machines of this architecture (register: 9, of them 6 devices, 6 gate-capable). Diraq — foundry 8-qubit array (demonstrated, 8); Diraq (with Equinix) — Diraq 8-qubit silicon spin quantum computer at Equinix Sydney (announced, 8); Equal1 — RacQ (Bell-1) (deployed, 6); Groove Quantum — Groove Quantum 18-qubit germanium spin processor (demonstrated, 18); HRL Laboratories (IBM since 26 Aug 2026) — HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots) (demonstrated, 18); Hitachi + Intel K.K. + AIST (G-QuAT) — Hitachi x Intel 18A spin programme (announced, 100); Intel — Tunnel Falls (demonstrated, 12); Quantum Motion — QM-One (deployed); Quobly — Alloy Pioneer (Quobly) (planned, 15).

Cells outside the architecture's slots (7). Diraq 8-qubit silicon spin quantum computer at Equinix Sydney: L5 undisclosed where the architecture expects a technology; RacQ (Bell-1): L5 ∅G-qsoc (Atlas gap — quantum system-on-chip: qubits, control electronics and error-correction logic on one CMOS); RacQ (Bell-1): L8 Cryogenic / on-chip decoder (cryo-CMOS, SFQ) (dec_cryo, alternate borrowed from another architecture); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L7 Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) (code_detect, primary off the architecture's slots); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L7 ∅G-repetition (Atlas gap — d=5 bit-flip repetition code on 7 exchange-only qubits, Λ5/3 = 4.7 over up to 200 rounds, ); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L8 ∅G-parity (Atlas gap — repetition-code syndromes interpreted after the run with a parity-check (majority) decoder); QM-One: L5 ∅G-qsoc (Atlas gap — cryo-CMOS integrated on the qubit die).