Hitachi x Intel 18A spin programme

Raveh Neeman

doi:10.5281/zenodo.22674814

Hitachi + Intel K.K. + AIST (G-QuAT) · semiconductor spins · ANNOUNCED (Jul 2026) · 100 physical qubits · access: planned AIST G-QuAT cloud by FY2027

architecture: Silicon / germanium quantum-dot spins · Open on the map

Register profile — the machine's variant of its architecture

qubit type: Si gate-defined electron spin

gate mechanism: exchange 2Q

connectivity: nearest neighbour

control: Hitachi is developing 3-D vertical stacking for cryogenic control; Intel contributes the Horse Ridge / Pando Tree lineage

control placement: cryo-CMOS

readout: spin-to-charge conversion

gate evidence: no published figure

flags: no device yet

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▨ 🔎 Si gate-defined electron spin; PLANNED 100+ qubits with error-correcting capability by FY2028, 1,000 by FY2030
2 Encoding	Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ◌ 🔎 bare electron spin-1/2, Loss–DiVincenzo encoding
3 Gate mechanism	Exchange gate (spins; incl. shuttled-spin CZ) · primary ▨ 🔎 exchange 2Q; 1Q > 99.7% cited from academic work on Intel's spin platform, not a Hitachi device
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▨ 🔎 nearest neighbour
5 Control	Cryo-CMOS controller (4 K / mK) · primary ▨ 🔎 Hitachi developing 3-D vertical stacking for cryogenic control against the wiring bottleneck; Intel contributes Horse Ridge / Pando Tree lineage
6 Readout	Spin-to-charge conversion + rf reflectometry · primary ◌ 🔎 spin-to-charge conversion
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code; "error-correcting capability" at FY2028 is unspecified
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder
9 Interconnect	Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) · primary ◌ 🔎 planned 3-D stacking of qubit chips and cryogenic control electronics with short dense interconnects against the wiring bottleneck (Hitachi; Jul 2026); no device published
10 Manufacturing	300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▨ 🔎 Intel 18A (1.8 nm-class); deliverable is a quantum PDK on 18A, the first for a 1.8 nm-class process

evidence: ✅ 0 / 10