Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) ic_fanout

Every gate of a spin qubit is a line. Fan-out routes the few lines a refrigerator carries to those gates: a router die at the MXC (Intel), multiplexers on the qubit die (Quantum Motion, Equal1), or qubit chip and control electronics stacked vertically (Hitachi). Vandersypen et al. (2017) judged wiring ~10⁸ sub-100 mK qubits to room temperature "impractical" and put electronics beside the qubits D[761]. Li et al. shared the lines — "the control lines define the qubit grid" D[762]; Schaal et al. and Paquelet Wuetz et al. put CMOS switches at millikelvin D[763]D[764]. Intel described Pando Tree on 2024-06-20 C[272]; the register's first dated fan-out record is from 2025.
Attributes: static interconnect; low-frequency signals at mK and 4 K; coherent error; CMOS fabrication.

Lines. In 2019 every platform wired each qubit directly, p = 1, against 0.36 for Intel's x86 processors; in Franke et al.'s example an added spin qubit costs two gates, t = 2 D[765] — 2×10⁶ lines at g = 10⁶. A crossbar gives T = 6√g − 1, 23 terminals for 16 dots D[520], ~6×10³ at 10⁶ S. At a 90 nm gate pitch D[197] routing must happen on or beside the die.
Heat. Large dilution refrigerators give "beyond 1 mW at 100 mK" D[761]. Delft generated and demultiplexed 96 voltages onto 648 devices at 66 mK for under 120 µW D[552]: ~1.25 µW per voltage, so a milliwatt holds ~800 — ~400 directly wired qubits or ~1.8×10⁴ crossbar dots S. Switching costs ∝ C·V²·f: strobing commercial multiplexers at 8 kHz lifted a 50 mK stage to 130 mK D[764]. A demultiplexer visits terminals in turn, each holding charge meanwhile — Schaal's cell stores it on the dot gate like a one-transistor–one-capacitor DRAM cell D[763] — so refresh rate trades droop against heat S.

No row is a gate benchmark through a router: Pando Tree shares a circuit board with a Tunnel Falls chip C[272], with no fidelity measured through it found, as of 2026-09-26. Nearest: a 32-cell millikelvin pulse chip costing ~0.07% single-qubit fidelity D[551] — generation, not routing. Dominant term: heat per addressed voltage.

Router dies are foundry CMOS run cold: 22 nm FinFET from Intel for Delft D[552], 22FDX for Quantum Motion D[767] and Equal1 C[273], Intel 18A for Hitachi's quantum PDK, "the first such interface for a 1.8nm-class process" P[769]. Tunnel Falls comes off a 300 mm line with extreme-ultraviolet lithography D[199]. Three routes compete: a separate router die (Intel), monolithic multiplexers (Quantum Motion, Equal1), and "stacking qubit chips and control electronics vertically" (Hitachi) P[769]. Cold wafer test gates all three — Intel's cryoprober is the published instance D[766] — and imec's SPINS pilot line adds 300 mm spin-qubit runs, PDKs and cryo-CMOS C[770]. Router and bond yields are unpublished as of 2026-09-26.

Pando Tree delivers "both constant voltage bias and high-speed voltage pulsing for up to 64 qubit terminals" from nine digital signals and one line from the 4 K Horse Ridge II controller C[272]: ten lines for 32 qubits at two terminals each (t = 2), ~0.3 lines per qubit S. The register's 0.0156 lines per qubit counts only the analogue line and reads terminals as qubits S. Intel's "approximately 20 cables" for a million qubits C[272] carries no heat or bandwidth budget, as of 2026-09-26. Readout fans in too: Diraq reads eight qubits through two SETs D[197]. At 1.25 µW per voltage and two terminals per qubit S, 10³ qubits need ~2.5 mW wired directly, ~0.2 mW on a crossbar; 10⁶ need ~2.5 W, or ~7.5 mW shared — only the combination nears one refrigerator's budget.

Slot 9, the only layer-9 entry, of "Silicon / germanium quantum-dot spins". It requires fab_cmos (foundry CMOS) — "a CMOS router die at cryogenic temperature" — and ct_cryocmos (cryogenic CMOS control), which generates what this technology routes; cx_crossbar (layer 4) shares lines inside the array. No provides edge is recorded. ic_mcm (coupled multi-chip modules) replaces it; neither spin architecture has an inter-module link, as of 2026-09-26. Four register machines carry it (4 as primary): Tunnel Falls, Hitachi × Intel 18A, RacQ (Bell-1) and QM-One — those whose makers name an artefact. Tunnel Falls' cell is ✅, on the Pando Tree demultiplexer; the others are inferred and 🔎. Gap G-spinl9, answered in part: slot 9 of the quantum-dot architecture now holds this technology, the proposed ic_router; slot 9 of the donor-spin architecture is still empty.

The figures of merit — channels per die, heat per line at the MXC, hold droop, refresh rate, switching crosstalk — sit in no register cell. The record is component-level: Delft's held voltages drift 60 µV/s to 18 mV/s D[552], slow coherent error that randomised benchmarking averages away S; the cryoprober and the 1,024-dot chip measure devices, not gates D[766]D[767]. Equal1's page lists 99.3% average two-qubit fidelity C[273], which the register holds beside a press survey's 98.4%; neither names the fan-out behind it. Missing, as of 2026-09-26: a benchmark through a millikelvin router, and Pando Tree's dissipation.

Not published: the process node of Intel's Pando Tree and any qubit fidelity measured through it, and the fan-out plans of SQC, Quobly and Groove Quantum.

Money.

• 2026-01-15 · Equal1 · round led by the Ireland Strategic Investment Fund, system "onto a single chip" · USD 60 M · announced C[771]
• 2026-03-18 · Rhonexum · pre-seed led by QDNL Participations · USD 1 M · announced P[560]
• 2026-04-03 · imec-led consortium · SPINS pilot line, EU Chips Joint Undertaking co-funding · EUR 50 M · launched C[770]
• 2026-05-07 · Quantum Motion · Series C, fan-out not named · USD 160 M · announced C[355]

Market & supply chain. Fan-out is bought with the qubit die; the one merchant entrant found, Lausanne's Rhonexum, is at pre-seed P[560]. Scarce inputs — cold device models, cold wafer test, foundry slots — are shared with ct_cryocmos. It serves G4 and G7 on the quantum-dot architecture.

IP & standards. No fan-out patent count from a named database and no interface standard, as of 2026-09-26; the nearest artefacts are PDKs — SPINS' C[770] and Hitachi's intended 18A kit P[769].

Roadmaps & track record. Intel: ~20 cables per million qubits, undated C[272]; no qubit data through Pando Tree since 2024-06-20, as of 2026-09-26. Hitachi: cloud access in fiscal 2027, 100 qubits in fiscal 2028, 1,000 in fiscal 2030 P[769]. Diraq: 150,000 physical qubits by 2029, over 2 million by 2031, fan-out unstated R[211]. No fan-out milestone has come due; nothing to score yet.

Strategic reading. Intel's separate router and the monolithic dies of Equal1 and Quantum Motion are rival bets on the millikelvin milliwatt. If routers fall well below a microwatt per voltage, value moves to foundries with cold device models and to cold wafer test; if not, qubits run hotter — Equal1 at 0.3 K C[768] — or split into modules, and ic_mcm takes the slot S.

Confirm if, by 2027-12-31, a peer-reviewed spin-qubit gate benchmark runs through a millikelvin router or on-die multiplexer and reports heat per channel; demote if Hitachi's fiscal-2028 prototype or Diraq's 2029 system ships with per-gate lines from 4 K or room temperature. Open questions. (1) What does Pando Tree dissipate per switched terminal? (2) What hold droop do exchange gates tolerate between refreshes? (3) Does time-multiplexed pulsing cap gate parallelism below what a surface-code round needs? (4) Can crossbar sharing and millikelvin routing share one die? (5) Will spin modules (ic_mcm) take the slot before routers reach 10⁴ channels?