Quantum Technology Atlas
Атлас квантовых технологий
אטלס הטכנולוגיות הקוונטיות
How to read the mapКак читать картуכיצד לקרוא את המפה
Columns are the ten layers of a quantum-computing stack, from the qubit’s carrier on the left to manufacturing on the right; each column holds the technologies that fill that layer. Within a column a technology sits higher the more natural its carrier is (atoms, ions and photons at the top) and lower the more fabricated (circuits, dots and cavities at the bottom). The order is not decoration: it predicts behaviour — natural carriers are identical and long-lived but slow and optically driven, fabricated ones are fast and wired but differ from unit to unit — and most technologies of a layer follow it. A hatched technology breaks the order — a *crossing technology*, one that takes a trait from the other side of the divide (§7.5). Coloured lines are the seventeen architectures, one technology per layer; dashed hollow technologies are slots nobody has filled. Click a technology for its brief, pick a lens to recolour the map by one attribute, or choose a machine to light the technologies it uses. Construction rules and derived tables: §7.
Колонки — десять слоёв стека квантового компьютера, от носителя кубита слева до производства справа; в каждой колонке — технологии, заполняющие этот слой. Внутри колонки технология стоит тем выше, чем естественнее её носитель (атомы, ионы и фотоны — вверху), и тем ниже, чем он искусственнее (схемы, квантовые точки и резонаторы — внизу). Этот порядок не украшение: он предсказывает поведение — естественные носители одинаковы и долгоживущи, но медленны и управляются оптически, искусственные быстры и подключены проводами, но различаются от экземпляра к экземпляру, — и большинство технологий слоя ему следует. Заштрихованная технология порядок нарушает — это *сквозная технология*, берущая свойство с другой стороны раздела (§7.5). Цветные линии — семнадцать архитектур, по одной технологии на слой; пунктирные полые технологии — слоты, которые никто не заполнил. Кликните технологию, чтобы открыть её обзор; выберите линзу, чтобы перекрасить карту по одному атрибуту, или машину, чтобы подсветить технологии, которые она использует. Правила построения и выведенные таблицы — в §7.
העמודות הן עשר השכבות של מחסנית המחשוב הקוונטי, מנושא הקיוביט משמאל ועד הייצור מימין; כל עמודה מכילה את הטכנולוגיות הממלאות את השכבה. בתוך עמודה, טכנולוגיה ממוקמת גבוה יותר ככל שהנושא שלה טבעי יותר (אטומים, יונים ופוטונים למעלה), ונמוך יותר ככל שהוא מיוצר יותר (מעגלים, נקודות קוונטיות ומהודים למטה). הסדר אינו קישוט: הוא מנבא התנהגות — נושאים טבעיים זהים זה לזה וארוכי חיים, אך איטיים ומונעים באופן אופטי; נושאים מיוצרים מהירים ומחווטים, אך שונים מיחידה ליחידה — ורוב הטכנולוגיות בשכבה נוהגות לפיו. טכנולוגיה מקווקוות שוברת את הסדר — זוהי *טכנולוגיה חוצה*, טכנולוגיה שלוקחת מאפיין מהצד השני של החלוקה (§7.5). הקווים הצבעוניים הם 17 הארכיטקטורות, טכנולוגיה אחת בכל שכבה; טכנולוגיות חלולות בעלות מתאר מקווקו הן משבצות שאיש לא מילא. לחץ על טכנולוגיה כדי לפתוח את התקציר שלה, בחר עדשה כדי לצבוע מחדש את המפה לפי תכונה אחת, או בחר מכונה כדי להאיר את הטכנולוגיות שהיא משתמשת בהן. כללי הבנייה והטבלאות הנגזרות: §7.
About the Atlas
For a first reading: About → §1 (the criteria) → §3.1 (the scores) → the map, with “How to read the map” open → one brief → §8 (the machines). Every record — technology, machine, architecture, organisation — also has a page of its own, linked from its card.
Why a Quantum Technology Atlas. Quantum computing has no universally best technology, because it has no single goal. Every platform presents a computation with an error channel, a clock (its error-correction cycle time), a qubit count and a scaling path, and every goal weighs the four differently: a cryptanalytic machine is a fast clock on ~10³ logical qubits; a lattice-gauge simulator wants many qubits, rich connectivity and high-dimensional local degrees of freedom, and tolerates a slow clock; a network node built from superconducting qubits waits on microwave-to-optical transduction, whose useful efficiency is still about three orders of magnitude away — the only carrier that leaves the cryostat is a photon. Comparisons are nevertheless made at the level of platforms — superconducting versus ions versus atoms — although a platform is an assembly of separable technologies, and the decisions that matter (what to research, what to build, whom to partner with, what to buy) are made one technology at a time. The material that exists today comes in three kinds, each blind in its own way: vendor roadmaps (intentions, not results), market monitors (money, not engineering) and academic reviews (engineering, not economics, and dated on arrival). The Atlas exists so that every technology in the quantum-computing stack can be read on the same attributes, against dated evidence, with its conflicts and its economics in one place — and so that the picture is refreshed several times a year rather than once.
What it is. A living reference in five connected parts. A goal-oriented comparison of platforms: a criteria set that is technology-agnostic by construction, every major platform graded separately on demonstrated results and on justified intentions, platforms mapped to goals — and only then the directions that look most promising. A technology graph: 110 self-contained technologies across ten stack layers, each described by seven design attributes and connected by four kinds of edge, with platforms drawn as architectures through the layers. A brief on every technology, with the same section skeleton from physics to economics. A register of 184 quantum machines — every system built, announced or planned that the sources allow to be placed — each joined to the map as an instance of one architecture, technology by technology, with the evidence for every joint graded; the machines are read as a population in §8, where the field's trends are stated as hypotheses, tested against the register, and turned into forecasts that the next edition scores. And an evidence system: every claim tagged by its standing, every figure traced to a dated, linked source, conflicts stated rather than averaged, open verification items listed. It is published as one interactive document in dated editions (2026.09), each archived with its own DOI — the concept DOI resolves to the latest; the data and the build live on GitHub.
Who should use it. Researchers choosing where to put the next years of work — the graph shows empty slots and unresolved conflicts, each conflict with its measured price — what the field has not solved. Architects and engineers designing a system — a platform is an architecture through the layers, and every technology on it comes with what it requires, what it can be swapped for, and what it collides with, priced. Investors and analysts — each brief carries the actors, the dated money, the supply chain and the roadmap-versus-delivery record of one technology, not of a company. Programme and policy staff — who is where, which suppliers are single points of failure, which export rules apply. Newcomers — the Atlas is a structured entry into a field whose literature is not. Vendors — to see how their claims read when tagged and dated. It is not a market-sizing exercise and not a ranking of companies.
What earns a place. A technology enters the map — a technology on the map, a node in the graph behind it — if it is self-contained — it can be replaced without redesigning the rest of the stack; principled — it rests on a distinct physical or mathematical mechanism, not on a product, a vendor or a parameter choice; and it belongs to exactly one layer. It must be locatable on all seven attributes: carrier affinity (natural ↔ fabricated), characteristic time and deterministic or heralded entangling, readout mechanism with its time, destructiveness and mid-circuit capability, mobility and connectivity, control modality and placement, dominant error structure as an error-correcting code sees it, and manufacturing technology. A demonstrated node needs at least one dated, sourced record; emerging or theoretical nodes are admitted when an architecture needs the slot, and slots with no technology at all are drawn as empty. Platforms and companies are never nodes: platforms are architectures, companies are actors. Machines are never nodes either, but they are not lost: each machine in the register occupies one technology per layer, so the map shows which technologies are in use, by whom, and with what evidence. Every node carries its attributes (design space, stable), its dated records (evaluation space), its actors and goals (annotation space), its edges, and its brief.
How it is organised. The unit of the map is a technology (in the graph mathematics of §7 it is a node). Ten layers run left to right — carrier, encoding, gate mechanism, connectivity and transport, control, readout, code, decoder, interconnect, manufacturing; the vertical position is carrier affinity, natural at the top and fabricated at the bottom, so the natural/fabricated diagonal is visible and every technology that breaks it — a crossing technology, one that takes a trait from the other side of the divide — is hatched. Coloured lines are architectures through one technology per layer. Four edge types connect technologies: requires/provides between layers; alternatives within a layer; conflicts, each with its mechanism, its measured price, its mitigation and a status; defines, dated records with sources. Lenses recolour every technology by one attribute and the legend doubles as a filter; the machine selector lights the technologies one registered machine actually uses. One rule governs what is lit: the intersection of the isolated architecture, the focused technology, the lens value and the chosen machine. Crossing technologies, empty slots and each architecture's clock are derived from the data, not asserted; every table can be sorted and restored, and the wide ones scaled to the window. The briefs follow one skeleton — identity and lineage, physics and limits, engineering state of the art, manufacturing and supply chain, control, readout and I/O burden, role in the stack, evidence (how the numbers were measured), actors and economics, outlook, sources, open verification items — at a depth set by the technology's centrality in the graph. Find (the button beside the contents, or the / key) searches the whole page at once — the report, every brief open or closed, the tables, the tooltips and the cards as they read on the screen, in one language or all — by a regular expression or plain text, whole word or substring, with or without case, listing the hits in their sentences, and walks them with Enter, opening whatever hides each one. Every technology's card carries a picture from the media register, and on a touch screen two fingers zoom the map about the place they touch.
Glossary — 231 terms as this Atlas uses them
- ∅
- Nothing to place here: either the machine runs something the map has no entry for, or it discloses nothing at this layer
- ✅
- Verified: the cited source — a paper, a whitepaper, a product page or a technical press release — was opened and seen to show this technology in this machine
- 🔎
- Unverified: the cited source was not re-opened, or the cell is an inference — the claim is plausible but was not checked against its source
- Alternates
- Where a layer offers several technologies, the first listed is the one the platform actually leads with; the rest are what it could swap in
- Announcement gap
- The widening share of the newest machines that are announcements and plans rather than hardware — 43% of the 2026 group against 4% in 2024
- Architecture
- A platform drawn as a line through the ten layers: one technology chosen per layer, with the alternatives listed beside it; a machine is an instance of one
- Architecture instance
- One real machine laid over one platform line: what it uses at each layer, and a marked hole wherever it uses something the map has no entry for
- Architectures
- A platform drawn as one line through the ten layers, one technology per layer — 17 such lines carry the 184 registered machines
- Attempts
- A machine read as an argument: this combination of technologies will reach the goal before the others — the register holds 184 of them
- Briefs
- The stand-alone article on one technology — same skeleton every time, from physics and manufacturing through verification and actors to what to watch
- [C]
- Company claim: stated by the vendor, with no peer-reviewed data behind it yet
- Carrier affinity
- The first design attribute: how far a technology belongs to natural carriers (ions, atoms, photons) or to fabricated ones (chip-made circuits, dots), scored from 0 (natural) to 1 (fabricated) — the vertical position on the map
- Centrality
- How much rests on a technology in the graph — how many platform families and architectures depend on it, and how recently it reached hardware; it sets a brief's depth, not a verdict
- Channel quality at scale
- How wrong an operation goes and in what way, measured with the whole device running at once rather than on a good pair
- Closed-loop decoding
- The error-correction decoder keeps up with the machine and acts inside the cycle, instead of analysing the run afterwards
- Cohort
- Machines grouped by the year of their status date — which may be first light, general availability or the latest milestone, so the grouping is rough by design
- Count race
- The competition over physical qubit count, which the register shows has stalled: the largest machines that actually run a gate have not grown for three and four years
- Count-with-quality
- How many qubits reach the good error rate at the same time, not how many are in the box — with the connectivity they have
- Crossing technology
- A technology that takes a trait from the other side of the natural/fabricated divide — a natural carrier under microwave control, erasure on a fabricated carrier; hatched on the map
- Cut-off
- The date every number in the report is read at, so that figures from different sources can be compared — later news is listed separately, not merged in
- [D]
- Demonstrated: a published or peer-reviewed result, read at September 2026 — the strongest standing a claim gets here
- Derived clock
- A cycle time the report computes from the platform's own published gate, readout and reset times rather than quoting a vendor figure
- Design attributes
- The seven properties every technology is placed on, chosen because they do not change when new results are published
- Device
- In the register's counts, a machine that exists — deployed, demonstrated or retired — as against an announcement, a plan or a component
- Empty slot
- A place in the stack where nothing has been demonstrated yet, drawn hollow — the map shows the hole instead of hiding it
- Erasure-native
- Built so that its dominant error is already an erasure: the qubit decays out of its working levels into states a check can detect — as in alkaline-earth(-like) atoms (Yb, Sr) — with no added encoding needed
- Evaluation-space attribute
- Anything that improves with new results — error rates, qubit counts, cycle times, funding; always dated and sourced, and never used to place a technology on the map
- Evidence cell
- One machine at one layer of the stack: what it uses there, plus the document that shows it — a machine has about a dozen, the register 2,006
- Evidence grade
- For any count: the share of the entries behind it that a document was seen to support — how much of the claim survives if press releases are struck out
- F1a
- One of the dated predictions this edition commits to: an indicator, its value now, the value expected next year, and what would prove it wrong
- Family
- A machine's qubit platform: superconducting circuits, trapped ions, neutral atoms, photonics, semiconductor or defect spins, topological, annealers
- FEASIBLE
- The roadmap reaches its own target algorithm on qubit count, error rate and gate budget together, not on one of the three
- Focus
- Selecting one technology so the map draws the edges that touch it — what it needs, what can replace it, what it collides with
- Forecast ledger
- The table of dated predictions this edition commits to, each with what would prove it wrong, scored in public by the editions that reach the date
- Four outputs
- The four things a technology choice is judged to change: the error channel, the cycle time, how many qubits stay good at once, and the route to a larger machine
- G1
- Goal: analogue and NISQ many-body simulation — qubit count, native connectivity and coherence on 10²–10⁴ qubits, no error correction
- G2
- Goal: error-mitigated utility circuits — 100–150 qubits and 10³–10⁴ two-qubit gates, decided by error rate at full width and shot throughput
- G3
- Goal: early fault tolerance — 10²–10³ logical qubits, 10⁵–10⁶ Toffoli gates, on 10⁴–10⁵ physical qubits, expected 2027–2031
- G4
- Goal: large-scale fault tolerance — 10³+ logical qubits and 10⁹–10¹⁰ Toffoli gates; here the cycle time decides, then fidelity and count
- G5
- Goal: heuristic optimisation and annealing — available today, and the one goal with no proven quantum advantage behind it
- G6
- Goal: networking and distributed computing — quantum-internet nodes and links between modules, on interface rate, fidelity and memory
- G7
- Goal: deployable systems — racks that run without a dilution refrigerator, judged on footprint, power and integration
- Gap
- A layer where the map has no entry for what the machine actually runs, or where the machine discloses nothing
- Gap share
- Per layer, the share of machines that disclose nothing there or run something the map has no entry for — worst by far for codes, decoders and links
- Gate-capable
- A machine that actually runs a two-qubit entangling operation — an array that only holds atoms, or an analogue simulator, does not qualify
- H1
- One of the statements about the field that this edition tests against the 184 registered machines, rather than asserting; H7 and H8 are retired to §8.1
- Hatched
- Drawing marks on the map itself: a technology is shaded when it breaks the natural-to-fabricated trend, and drawn hollow when nothing fills the slot yet
- Hero pairs
- A record error rate measured on one hand-picked pair of qubits instead of across the whole device; excluded from the register's bests and medians
- I/O wall
- The wiring limit: one refrigerator carries only so many control lines and so much heat; one of the four limits on qubit count (§0 item 5, §8.4–8.6) — the largest wired system has 1,536 lines
- Integrated control
- Qubits driven by electronics on the chip or inside the refrigerator, instead of racks of room-temperature instruments and free-space optics
- Interchange
- A technology several platform lines run through — the metro-map reading of a shared choice
- Isolate
- Showing one platform's line alone: its technologies stay lit, everything else dims
- Layer
- One of the ten columns of the stack, left to right: carrier, encoding, gate, connectivity, control, readout, code, decoder, interconnect, manufacturing
- Lens
- A view that recolours every technology on the map by one property at a time, with its legend doubling as a filter
- Link technology
- A demonstrated way of joining one module to another — the layer that is absent or undisclosed on 149 of the 184 machines
- Machine
- One row of the register: a named system some organisation has built, announced or merely planned
- Machine selector
- The control that lights the technologies one registered machine actually uses and marks the layers where it uses something the map has no entry for
- Natural/fabricated
- The two ends of carrier affinity: a natural carrier is a particle nature makes identical (an ion, an atom, a photon); a fabricated one is made on a chip and varies from device to device (a superconducting circuit, a quantum dot)
- NOT EVALUABLE
- The roadmap does not publish enough dated numbers to be checked at all — this is about disclosure, not about quality
- Not supported
- The register's own rows contradict the statement — it is printed because it was tested and failed
- Partly supported
- The register bears the statement out only in part: the trend is there but not on every test, or not year after year
- Quantum Machines Register
- The list of 184 quantum machines that accompanies this map, each placed on it technology by technology, with the evidence for every placement graded
- Qubit carrier
- The physical system that holds the qubit — an ion, a neutral atom, a photon, a superconducting circuit, a semiconductor spin or a defect; the first of the map's ten layers, on which every other choice depends
- [R]
- Roadmap: what the vendor's published plan would deliver by about 2029 if it is held — an intention, not a result
- Roadmap verdict
- The register's own check of a published roadmap against the algorithm it promises: does it reach it, miss it, or not publish enough to be checked
- SHORT
- The roadmap misses its own target algorithm, with the shortfall named — most often the error budget, rarely the qubit count
- Standard records
- The dated, sourced numbers held per technology — gate and readout times, coherence, error rates — that the report's own calculations are built from
- Supported
- The count run over the register's own rows bears the statement out
- #AQ
- Algorithmic qubits: IonQ's single-number benchmark — the largest size at which a suite of application circuits still passes a fidelity bar; a vendor metric, not a count of qubits
- 1Q
- Single-qubit: an operation on one qubit, usually ten to a hundred times more accurate than a two-qubit one
- [[20,2,6]]
- Quantinuum's C₄-Helix code: 20 physical ions carrying 2 protected qubits at distance 6 (any error on fewer than 6 ions is detected), made by concatenating the [[4,2,2]] (C₄) code with a [[10,2,3]] one — a preprint of September 2026, not yet peer-reviewed
- 2Q
- Two-qubit: the operation that entangles two qubits — the one whose error usually sets the limit of the whole machine
- All-to-all
- Any qubit can be entangled with any other directly, with no chain of swaps in between — it shortens circuits by a large factor
- AOD
- Acousto-optic deflector: a crystal in which a radio-frequency sound wave steers a laser beam; driven with several tones it makes movable tweezers — how atom machines rearrange qubits mid-run (ion machines use it to address ions)
- AOM
- Acousto-optic modulator: a crystal driven by a radio-frequency sound wave that switches a laser beam and shifts its frequency and phase — how ion and atom machines pulse and shape their light
- ASIC
- Application-specific integrated circuit: a custom chip built for one job — faster and lower-power than an FPGA but fixed once made; the route of cryogenic controllers and hardware decoders
- BB
- Bivariate bicycle codes: a family of qLDPC codes that store many logical qubits in one block with about a tenth of the physical qubits the surface code needs; each qubit is wired to six others, two of them by long-range links (a two-layer layout)
- Bell pairs
- The basic unit of entanglement: two qubits in a maximally entangled (Bell) state, whose measurement outcomes are perfectly correlated — the fuel spent on linking modules
- Below-threshold scaling
- The logical error falls each time the code is enlarged — the observable sign that correction is winning on that hardware; the factor by which it falls each time the code distance grows by two is Λ
- BP
- Belief propagation: a decoder that passes probabilities along the sparse network of checks until they agree — fast on low-density (LDPC) codes, but on quantum codes it needs a helper (ordered-statistics decoding, OSD) or a variant such as Relay-BP
- Braket
- Amazon's cloud service through which other companies' quantum machines are used on demand
- Break-even
- The point where a protected qubit outlives the best bare qubit in the same machine — or a logical operation beats its physical counterpart — the first evidence that coding pays
- BTO
- Barium titanate (BaTiO₃): a ferroelectric with a very strong Pockels (electro-optic) effect, grown as thin films on silicon wafers for fast, low-loss on-chip phase shifters — the switches photonic machines need for multiplexing and feed-forward
- Cat qubits
- A qubit stored in a microwave resonator as two coherent states of opposite phase, held there by a two-photon drive or dissipation; bit flips grow exponentially rarer as the photon number rises, while phase flips grow only linearly
- Certified randomness
- Random numbers with a proof that they are fresh and really came from the quantum machine rather than a classical imitation
- CHIPS
- The US CHIPS and Science Act (2022) and the Commerce Department's semiconductor-incentive programme it created — in 2026 it issued non-binding letters of intent to fund quantum companies
- Circuit QED
- Circuit / cavity quantum electrodynamics: a qubit or atom coupled to the field of a resonator — cavity QED with atoms in optical cavities, circuit QED with superconducting qubits and microwave resonators, the basis of their readout
- Clifford
- Clifford operations — those built from Hadamard, phase (S) and CNOT gates — are cheap on error-corrected machines and classically simulable; a non-Clifford gate (T, Toffoli) is needed for universal computation and is paid for with magic states
- CLOPS
- Circuit layer operations per second: IBM's speed benchmark — how many layers of a parametrised test circuit a system runs per second, classical overhead included
- CMOS
- Complementary metal–oxide–semiconductor: the transistor technology of ordinary chips — its 300 mm foundries are what spin qubits, cryogenic controllers and photonic chips borrow
- CNOT
- Controlled-NOT: a two-qubit operation that flips the second qubit when the first is set — the textbook entangling gate
- Code distance
- How many single errors it takes to corrupt protected data unnoticed — larger distance, stronger protection, more qubits
- Coherence
- A qubit's ability to stay in a superposition with a definite phase; its coherence time (T1, T2) is how long that lasts before noise scrambles it — the time budget a circuit has to fit into
- Colour code
- A grid code like the surface code, but with qubits at the corners of three-colourable tiles, each tile a check: all Clifford gates are transversal (cheap logical operations), at the price of heavier checks and harder decoding
- Continuous-variable
- Encoding in the quadratures — the continuous amplitude and phase components — of optical modes rather than in single photons: large entangled (cluster) states come deterministically from squeezed light, but error correction needs non-Gaussian (GKP) states
- Control modality
- Control modality: the kind of signal that drives the qubit — microwave pulses, laser light or voltage on a gate electrode
- Correction cycle
- One round of syndrome extraction, every check measured once — the clock of protected computation, with decoding running alongside: about 1 µs on superconducting circuits, milliseconds to a tenth of a second on ions and atoms
- Cryo-CMOS
- Cryogenic CMOS (complementary metal–oxide–semiconductor): ordinary chip electronics designed to work inside the cryostat, usually at the 4 K stage close to the qubits — the way out of one cable per qubit to room temperature
- Cultivation
- Growing one good magic state in place, checking as it goes, instead of distilling many poor ones — far cheaper when it works
- CV
- Continuous- and discrete-variable: whether the information rides on a light beam's amplitude and phase, or on single photons
- CVD
- Chemical vapour deposition: growing a material from reactive gases on a substrate — here, the synthetic single-crystal diamond that hosts NV, SiV and SnV centres
- CZ
- Controlled-Z: a standard two-qubit entangling operation — it flips the sign of the state when both qubits are set
- DAC
- Digital-to-analogue converter: the circuit that turns numbers into the voltage waveforms driving qubits — counted per qubit, a main cost of control electronics and wiring
- DARPA
- Defense Advanced Research Projects Agency: the US Department of Defense's research-funding agency — it runs the QBI and US2QC programmes whose stages many roadmaps cite
- DC
- Direct current: a static or slowly varying voltage or current — here the bias that sets a qubit's or coupler's operating point, as opposed to its oscillating drive
- DD
- Dynamical decoupling: a rhythm of corrective pulses that cancels slow noise and stretches how long a qubit keeps its phase
- Decoder
- The classical algorithm — in software, or wired into programmable (FPGA) or custom (ASIC) chips — that reads the check results and infers which correction to apply; it has to keep pace with the machine
- Dilution refrigerator
- A refrigerator that cools by diluting helium-3 into helium-4, reaching about 10 mK (a hundredth of a degree above absolute zero) — bulky and power-hungry, and needed by every superconducting-qubit machine and most spin-qubit ones
- Donor
- A single dopant atom (usually phosphorus) in silicon whose electron or nuclear spin is the qubit — among the most coherent solid-state qubits, and hard to place atom by atom
- DQI
- Decoded quantum interferometry: a recent algorithm for optimisation problems, one of the few new sources of candidate advantage
- Dual-rail
- A qubit encoded as one excitation in one of two modes — two cavities, two transmons or two optical paths; if it is lost, both modes are empty, which a check flags as an erasure: an error at a known place, far easier to correct
- ECC-256
- Elliptic-curve cryptography with 256-bit keys (the NIST P-256 curve, Bitcoin's secp256k1), used in most modern systems and crypto wallets — the second standard breaking target
- ECCN
- Export Control Classification Number: the code under the US Export Administration Regulations that says which licences an item needs — 4A906, for instance, covers quantum computers above set thresholds
- EDSR
- Electric-dipole spin resonance: turning a spin with an oscillating electric field, through a micromagnet's field gradient or spin–orbit coupling — how most quantum-dot spins are driven
- EO
- Exchange-only: a spin qubit encoded in three electron spins and driven by the exchange interaction alone, with no microwaves or magnets — HRL's silicon approach
- EPLG
- Error per layered gate: the average error per two-qubit gate, inferred from the fidelity of layers of simultaneous gates along an N-qubit chain (IBM reports N = 100) — so crosstalk is counted, unlike a gate measured on its own
- Erasure
- An error whose location is known because it is heralded — the qubit is detected as lost or as having left its working levels — much cheaper to correct than a silent flip
- ESR
- Electron spin resonance: turning an electron spin with an oscillating magnetic field from an on-chip antenna or line — how donor spins and some dot spins are driven
- EUV
- Extreme-ultraviolet lithography: chip patterning with 13.5 nm light, used for the finest commercial transistors — most qubit processes do not need it
- FD-SOI
- Fully depleted silicon-on-insulator: a CMOS process with a very thin silicon layer on buried oxide, whose back gate tunes the transistors — used for cryogenic controllers and spin-qubit foundry runs
- FeMoco
- The iron–molybdenum cofactor of nitrogenase, the enzyme that fixes nitrogen — the standard benchmark molecule of quantum-chemistry resource estimates
- Fidelity
- How close a prepared state or a performed operation is to the ideal, from 0 to 1 (1 = perfect); one minus it is the error. For gates it is an average over benchmarking runs that hides which errors occur and under what load
- Fluxonium
- A superconducting qubit: a small Josephson junction shunted by a superinductance (usually a long chain of larger junctions); its low frequency and large anharmonicity give long coherence and low error, at the cost of more complex control
- FPGA
- Field-programmable gate array: a reprogrammable logic chip — the usual platform of qubit control electronics and real-time decoders, slower and more power-hungry than a custom chip (ASIC)
- FT
- Fault tolerance: running the whole computation — preparation, gates, measurement and the correction cycle — on faulty parts so that faults cannot spread into uncorrectable errors; below a threshold error rate, enlarging the code drives the logical error down
- Fusion-based
- Fusion-based quantum computing: many small, identical entangled resource states of a few photons, joined by entangling (fusion) measurements; a fusion sometimes fails, but the failure is heralded and absorbed by the error-correcting code
- Ge
- Germanium: spin qubits made of holes in a Ge/SiGe quantum well, which can be driven by voltage alone, without micromagnets on the chip
- Genesis Q
- The US Department of Energy's Quantum Genesis Q competition (launched September 2026): it funds complete, deployed machines of at least 100 logical qubits running hundreds of millions of fault-tolerant operations, rather than components
- GHZ
- Greenberger–Horne–Zeilinger state: all qubits jointly 0 and jointly 1 in one superposition — the standard test of many-qubit entanglement, whose fidelity falls fast as qubits are added
- GKP
- Gottesman–Kitaev–Preskill code: a qubit stored in one oscillator as a grid of evenly spaced peaks in position and momentum, so small shifts can be measured — through an auxiliary qubit or mode — and corrected
- Gross code
- IBM's [[144,12,12]] bivariate bicycle code: 12 logical qubits in 144 data qubits (288 with the check qubits), at distance 12 — gross is the old word for a dozen dozen, 144
- Heralded
- Probabilistic, but each success or failure is announced by a detection signal — the herald — so successes are kept and failures discarded or corrected; the basis of photon sources, fusion and remote entanglement links
- HOM
- Hong–Ou–Mandel interference: two identical photons meeting on a beamsplitter always leave together; its visibility measures how indistinguishable the photons are, which sets fusion fidelity
- HPC
- High-performance computing: supercomputer centres — where quantum machines are being installed as accelerators beside classical processors
- HRL
- HRL Laboratories: the US research lab owned by Boeing and General Motors (formerly Hughes Research Laboratories) — the leading developer of exchange-only silicon spin qubits
- Hubbard
- A minimal model of electrons hopping between lattice sites and repelling when two share a site — the standard hard test for simulating materials
- Imec
- A Belgian chip research institute whose industrial silicon line other groups use to make qubits the way processors are made
- JJ
- Josephson junction: two superconductors separated by a thin insulating barrier (typically Al/AlOx/Al) — a lossless nonlinear inductor that makes the circuit's levels unevenly spaced; its fabrication spread sets the spread of qubit frequencies
- KT
- Boltzmann's constant times temperature — the thermal energy; at 20 mK it equals a photon of about 420 MHz, so a qubit transition below that, as in fluxonium, is thermally excited and needs reset
- Lattice surgery
- Operating on protected qubits by merging and splitting their patches on the grid, instead of moving any qubits
- LCD
- Local Clustering Decoder: Riverlane's real-time hardware decoder (FPGA, then ASIC), which grows and merges clusters of detection events locally — fast enough to keep pace with superconducting cycles
- Leakage
- A qubit slipping out of its two working levels into a third state, where no correction applies until it is reset
- Linear-optical
- Computing with photons using only passive optics (beamsplitters, phase shifters), single-photon sources, detectors and feed-forward — photons do not interact, so entangling gates are probabilistic and heralded
- Logical teleportation
- Teleportation of an encoded qubit: its state is moved into another code block through shared entanglement, a joint measurement and classical feed-forward — only the measurement results travel, not the qubit
- LOI
- Letter of intent: a non-binding statement that a funder means to award money on terms still to be agreed — not a contract or a payment
- MAGIC
- Magnetic-gradient-induced coupling: an ion gate scheme in which a static magnetic-field gradient couples the ions' spins to their motion, so microwaves rather than lasers drive the gates (eleQtron)
- Magic state
- A specially prepared state that is consumed to apply a non-Clifford gate (such as T or Toffoli), which the code's cheap native operations cannot supply — producing these states dominates the cost of real algorithms
- Majorana
- Majorana zero mode: a quasiparticle state bound at each end of a topological superconducting nanowire; four of them store one qubit non-locally in their joint parity, which local noise cannot read or flip — whether devices really host them is still contested
- MBE
- Molecular beam epitaxy: growing crystals one atomic layer at a time from atomic beams in ultra-high vacuum — how the III-V heterostructures of Majorana wires and quantum-dot photon sources are made
- MBQC
- Measurement-based quantum computing: computing by measuring, one by one, the qubits of a large pre-made entangled (cluster) state — the model photonic machines run
- MdB
- Millidecibel, a thousandth of a decibel: the unit of optical loss per component in photonic machines — 1 mdB loses about 0.023% of the light, and loss is their dominant error
- MEMS
- Micro-electro-mechanical systems: tiny mechanical or electrode structures made with chip processes — here, microfabricated ion-trap chips and moving-mirror optical switches
- MK
- The two cold stages of a machine: millikelvin, where the qubits live, and 4 K, where electronics can still run
- MWPM
- Minimum-weight perfect matching: the classic decoding algorithm — it pairs up the alarms by the cheapest explanation
- MZI
- Mach–Zehnder interferometer: two beamsplitters with a phase shifter between them — the programmable switch and routing cell of photonic chips, whose loss is counted per MZI
- Mølmer–Sørensen gate
- Mølmer–Sørensen gate: the standard entangling gate of trapped ions — a two-tone laser (or microwave) field couples the ions' spins through their shared motion and leaves the motion as it found it, so a warm ion crystal is tolerated
- [[n,k,d]]
- n physical qubits carrying k protected ones; any error touching fewer than d of them is detectable — the standard way to quote a code's size
- NISQ
- Noisy intermediate-scale quantum: machines of today's size with no error correction, where the circuit must finish before the noise wins
- Noise bias
- When one kind of error is far rarer than the other; a code can exploit the imbalance, but only if the gates do not destroy it
- NQCC
- National Quantum Computing Centre: the UK's national lab at Harwell, which hosts and tests machines from several vendors as a neutral evaluator
- NV
- Nitrogen-vacancy centre: a nitrogen atom beside a vacant lattice site in diamond; its electron spin can be initialised and read optically even at room temperature, but linking it to photons needs cryogenic operation (below about 10 K)
- NVQLink
- NVIDIA's link that puts a classical accelerator close enough to a quantum machine to decode its errors while the circuit runs
- OTOC
- Out-of-time-order correlator: a measure of how fast information scrambles in a quantum system — a favourite advantage benchmark
- P450
- Cytochrome P450: a family of enzymes the body uses to break down drugs; its iron-containing active site is a standard target of quantum-chemistry resource estimates
- PIC
- Photonic integrated circuit: a chip in which light is routed through waveguides instead of current through wires
- PMT
- Photomultiplier tube: a vacuum detector that turns one photon into a measurable pulse — it counts a trapped ion's fluorescence to read its state
- Post-selection
- Keeping only the runs in which no error was detected and discarding the rest — it flatters the numbers, so the share kept matters
- QBI
- Quantum Benchmarking Initiative: a programme of DARPA, the US defence research agency, that tests in Stages A–C whether a company's approach can reach utility-scale operation (value exceeding cost) by 2033; Stages A–B assess a concept and a plan, not a machine
- QCCD
- Quantum charge-coupled device: a trap chip divided into zones between which ions are shuttled, so every gate acts on a small, well-controlled group — the name borrowed from the charge-shifting camera sensor
- QCVV
- Quantum characterisation, verification and validation: the craft of measuring what a quantum machine really does and proving the measurement
- QD
- Quantum dot: a nanometre-scale semiconductor island that traps single charges — as an on-demand single-photon source in photonic machines, or as the host of a spin qubit
- QEC
- Quantum error correction: one usable qubit spread over many physical ones, so errors are caught and undone while the computation runs
- QFP
- Quantum flux parametron: an rf-SQUID flux latch that amplifies and holds a flux qubit's state for readout — the read chain of D-Wave's annealers and the cell of adiabatic superconducting logic
- QKD
- Quantum key distribution: sharing encryption keys over quantum light so that eavesdropping is detectable — a networking market, not computation
- QLDPC
- Quantum low-density parity-check codes: each check touches only a few qubits and each qubit sits in only a few checks — the surface code is the simplest case; the high-rate members buy the same protection for far fewer physical qubits
- QND
- Quantum non-demolition: a measurement that leaves the qubit in the state it reported, so repeating it gives the same answer — what repeated syndrome checks need
- QPU
- Quantum processing unit: the quantum chip itself, as distinct from the control electronics and the classical computer around it
- Quantum annealing
- A special-purpose quantum machine: a problem settles into a low-energy answer as quantum fluctuations are slowly switched off — no gate circuit, no fault-tolerant error correction, only mitigation
- Quasiparticle
- Quasiparticles are broken Cooper pairs — excitations of the superconductor that sap qubit energy; one radiation impact (a cosmic ray or stray radioactivity) can release a burst of them that hits many qubits at once
- QV
- Quantum volume: one number for the largest square random circuit a machine still runs correctly — a whole-machine benchmark, quoted as a power of two
- RB
- Randomised benchmarking: the standard way to measure gate error — run random Clifford sequences of growing length; the decay of the survival probability gives the average error per gate, free of state-preparation and measurement errors
- Readout
- Measuring a qubit and getting a 0 or a 1; mid-circuit means doing it partway through and carrying on — what error correction needs
- Real-time decoding
- Working out the correction while the circuit is still running, fast enough not to stall it, instead of afterwards in analysis
- Repetition code
- The simplest code — one bit copied across several qubits — catches only one kind of error (bit or phase flips): a test of the machinery on ordinary qubits, but the real outer code on cat qubits, whose other kind of error is already suppressed
- RF
- Radio frequency: oscillating signals from about a kilohertz to gigahertz — here the field that holds ions in a Paul trap, the probe of rf reflectometry readout, and the qubit drive lines
- RL
- Reinforcement learning: software that improves a machine's calibration or decoding by trial and error instead of a fixed rule
- RSA-2048
- RSA public-key encryption with a 2048-bit key, in wide use today — the standard yardstick for when a quantum computer would break encryption
- RT
- Room temperature: about 300 K, outside the cryostat — where most control electronics sit today, linked to the qubits by one line per channel
- Rydberg
- An atom with one electron briefly excited to a very high orbit (large principal quantum number n), which makes it interact strongly with neighbours micrometres away — the standard way neutral-atom machines entangle qubits
- SFQ
- Single flux quantum: superconducting digital logic whose bits are picosecond voltage pulses, each carrying one magnetic flux quantum; it can run in the cryostat beside the qubits, replacing much of the room-temperature wiring
- Shuttling
- Physically carrying qubits — ions in a trap, spins along a channel — to bring partners together instead of wiring them
- SHYPS
- Subsystem hypergraph product simplex codes: Photonic Inc.'s qLDPC code family (2025), claimed to need up to 20 times fewer physical qubits than the surface code
- Si/SiGe
- Silicon/silicon–germanium heterostructure: electrons held in a strained silicon quantum well buried under SiGe, away from the oxide interface that disturbs SiMOS dots; its weak point is a small valley splitting that varies from dot to dot
- SiMOS
- Silicon metal–oxide–semiconductor: spin qubits in quantum dots formed under gate electrodes at the Si/SiO₂ interface of a transistor-like stack — closest to mass manufacturing, but with more charge noise and disorder from that interface
- SiN
- Silicon nitride: a low-loss, glass-like material for on-chip light paths, made on standard silicon lines
- SLM
- Spatial light modulator: a programmable phase mask that shapes one laser beam into many static traps in any pattern — the fixed counterpart of the AOD's movable tweezers
- SNR
- Signal-to-noise ratio: how much larger the measured signal is than the noise on it — it sets how fast and how reliably a qubit can be read
- SNSPD
- Superconducting nanowire single-photon detector: the fast, highly efficient (> 90%) detector photonic machines depend on; it works at about 1–3 K and registers a click, not a photon count, unless built for photon-number resolution
- SnV
- Tin-vacancy centre: a tin atom between two vacant sites in diamond; inversion-symmetric, so its optical line is stable, and its spin stays coherent at around 1–2 K instead of millikelvin
- SPAM
- State preparation and measurement: the error of setting a qubit before the circuit and reading it after, counted apart from the gates
- Spin–photon
- An interface that entangles a stationary spin qubit with an emitted photon (or maps its state onto one) — how separate modules are linked over fibre
- SQC
- Silicon Quantum Computing: the Sydney company (a 2017 UNSW spin-out led by Michelle Simmons) that places phosphorus donors in silicon atom by atom with a scanning tunnelling microscope
- SQUID
- Superconducting quantum interference device: a superconducting loop with one (rf-SQUID) or two (dc-SQUID) Josephson junctions whose behaviour a magnetic flux tunes — a tunable coupler, a flux qubit and a sensitive detector
- STM
- Scanning tunnelling microscope: a sharp tip that images and moves single atoms on a surface — its hydrogen-resist lithography places phosphorus donors in silicon with atomic precision
- Stored qubit
- The encoded qubit is only kept — corrected round after round, never operated on; the first and easiest test of a code, and what the scaling result so far covers
- Surface code
- The standard error-correcting code: qubits on a square grid, each check measuring four neighbours; it tolerates about 1% error per operation — one of the highest thresholds — but needs about 2d² physical qubits per logical qubit at code distance d
- Syndrome
- The pattern of check results that shows an error occurred and narrows down where — the decoder infers the likeliest error from it — without revealing the protected data itself
- T centre
- A light-emitting defect in silicon that both holds a spin and sends a photon, making silicon chips linkable over fibre
- T1
- Energy-relaxation time: the time constant with which a qubit's excited state decays to the ground state — one of the two clocks every circuit has to fit inside
- T2
- Dephasing (coherence) time: how long a qubit keeps the relative phase of its superposition — at most twice T1 and usually the stricter of the two clocks; the figure reported is usually the echo value, measured with refocusing pulses
- T2*
- Ramsey dephasing time: the phase lifetime measured with no refocusing (echo) pulses — the raw figure; the echo value T2 is longer and is the one usually advertised
- TES
- Transition-edge sensor: a superconducting film held at its transition, where one photon's heat changes its resistance — it resolves photon number at about 95% efficiency, but is slow and needs about 100 mK
- Tesseract
- A name carried by three different things here: the 16-qubit tesseract colour code — [[16,6,4]], which Microsoft and Quantinuum ran in its [[16,4,4]] subsystem form — Nord Quantique's multimode bosonic code, and Google's search-based decoder
- Tetron
- The four-Majorana device Microsoft builds its qubit from — the smallest unit that can hold one such qubit
- TFLN
- Thin-film lithium niobate: a strongly electro-optic crystal film bonded onto an insulating substrate — a leading material for fast, low-loss on-chip switches and modulators, one of the switch options of photonic machines beside BTO
- THC
- Tensor hypercontraction: a low-rank factorisation of the chemistry Hamiltonian that cuts the circuit (Toffoli) cost of quantum chemistry, and with it the run times and qubit counts quoted for it
- TLS
- Two-level system: a microscopic defect in amorphous oxides and interfaces that absorbs qubit energy and drifts in frequency — the main loss of superconducting qubits and a source of their fluctuations
- Toffoli
- A three-qubit logic operation that flips the last qubit only when the first two are set — the building block of quantum arithmetic
- Transmon
- The workhorse superconducting qubit: a Josephson junction shunted by a large capacitor, which makes it insensitive to charge noise; driven by microwave pulses, made by chip lithography
- Transversal
- An operation applied qubit by qubit across a code block — or pairwise between matching qubits of two blocks, as in a transversal CNOT — so one fault cannot spread inside a block; fast and cheap where the code allows it
- TRL
- Technology readiness level: the 1–9 scale (NASA, EU) from a principle observed (1) to a system proven in operation (9) — a self-assessed maturity mark
- TSV
- Through-silicon via: a metal-filled hole through a chip that carries signals from one face to the other — superconducting TSVs bring control lines to the qubit layer from below
- Tweezer
- A tightly focused laser beam holding one atom and able to carry it elsewhere — how atom machines build and rearrange their arrays
- TWPA
- Travelling-wave parametric amplifier: the first and coldest amplifier in the readout chain — it sets how fast and how well a qubit is read
- UHV
- Ultra-high vacuum: pressures below about 10⁻⁹ mbar — atom and ion traps need it so background gas does not knock out the qubits, and so does atom-by-atom donor lithography
- US2QC
- Underexplored Systems for Utility-Scale Quantum Computing: a DARPA programme vetting unconventional approaches; Microsoft and PsiQuantum reached its final validation and co-design stage in 2025
- WISE
- Wiring using integrated switching electronics: an ion-trap architecture with switches under the trap, so a few signal generators drive many electrodes — the answer to one wire per electrode
- XEB
- Cross-entropy benchmarking: scoring random circuits by how often the machine returns the bitstrings the ideal circuit makes likely — Google's measure for beyond-classical claims, sensitive to all errors at once
- Zoned
- A machine split into areas for storage, gates and measurement, with qubits moved between them, so each area is tuned for one job
- ZZ
- A coupling that shifts one qubit's phase by the other's state: switched on, it makes a CZ gate; left on (residual ZZ), it is a crosstalk error that grows with the number of neighbours
- Λ
- How much the logical error falls each time the code distance grows by two — above 1 means a larger code is better; 2 means the error halves at each step
0Takeaways
- Three platforms lead, each on a different merit, so today they complement one another more than they compete. Superconducting circuits have the fastest error-correction cycle (about 1 µs) but the highest errors at scale (two-qubit ∼10-3, readout 5×10-3–10-2); trapped ions the lowest errors at scale (two-qubit 7.9×10-4, state preparation and measurement 3.3×10-4 across 98 qubits) at a millisecond-class cycle; neutral atoms the most qubits under full logical control (448) and rearrangeable connectivity, also at a millisecond cycle. No platform leads on two of the three merits, and the register of 184 machines (§8) shows the same split: the largest device that runs an entangling gate is a tweezer array, the lowest two-qubit error an ion trap, the fastest cycle a transmon lattice (§8.3). Hybrids are already hardware — photonic links between ion and atom modules, cryo-CMOS and SFQ control beside superconducting and spin qubits, bosonic cavities read out by transmons. For a decision-maker: choose by the binding constraint of the application — runtime, error budget or qubit count — not by platform. The claim fails the day one platform leads on two merits at once.
- Logical error that falls as the code grows — the condition fault tolerance rests on — has been shown for a stored qubit on one platform, and for a full set of logical operations on none. Fault tolerance is a property of a whole computation: preparation, gates, measurement and the correction cycle itself are arranged so that errors, including those the correction makes, are caught faster than they arise; enlarging the code then drives the logical error down, provided the physical errors stay below the code's threshold. On Google's Willow the error of a stored qubit fell by Λ=2.14 per step of code distance from 3 to 7 and a distance-5 memory ran 106 cycles with real-time decoding (December 2024) [1]; in July 2026 the same group brought the distance-7 error to 7.7×10-4 per cycle [2]; a second superconducting group reached Λ=1.40 at distance 7 once it removed leakage — the lever of claim 4 [3]. The neutral-atom 2.14× is a four-round logical circuit with loss detection, not a memory [4]. Trapped ions and neutral atoms lead on the number of logical qubits and on the logical operations shown (transversal gates, teleportation, magic-state distillation), and trapped ions, since September 2026, on the memory error per logical qubit and cycle — 4.6×10-5 with a [[20,2,6]] code on Helios without post-selection, at a cycle about a thousand times longer than the superconducting one (preprint, wide error bars) [5]. The first platform to show a scaling memory and a low-error universal set of logical gates sets the reference for the decade.
- For algorithms of practical size the gate clock sets the runtime; below that size, speed can be traded for other merits. Resource estimates for chemistry and code-breaking give runtimes about 103 longer with millisecond-class correction cycles (ions limited by transport and cooling, atoms by imaging and transport) than with microsecond cycles (superconducting circuits) [6]; the ratio follows the cycle — a 100 µs cycle costs 102, a millisecond 103 — for algorithms of 109–1010 Toffoli gates — RSA-2048 in under a week at a 1 µs cycle [7] — that is the gap between days and decades. Ions and atoms win part of it back with denser codes (more logical qubits per physical qubit), transversal logic and parallel operation: enough for 102–103 logical qubits and for workloads limited by the number of circuit repetitions, unproven at 109 gates. Below that scale speed still counts twice: in the repetitions that error-mitigated and variational methods need, and in the decoder's latency inside the correction loop.
- The quickest lever is the structure of errors, not their rate: structure raises the threshold in one step, while rates improve by a third to a half per year. Turning errors into flagged erasures (dual-rail circuits, metastable Yb/Sr atoms, photon loss), biasing them (cat qubits), removing leakage and decoding in real time: when nearly all errors (98%) arrive as erasures, the surface-code threshold rises from 0.94% to 4.15% in the circuit-level model of Wu et al. [8] — a factor of 4.4, the gain of two to four years of rate improvement at today's pace, taken in one step. It is also where the platforms' toolboxes differ most: of the 98 technologies registered machines use as their primary choice in a layer (105 counting alternates), only 22 are shared by two or more qubit families, and 5 of them by three or more (§8.1).
-
Six findings from the 184 registered machines (§8).
- (i) The qubit-count race has stalled where it counts: the largest devices with a benchmarked entangling gate have stood at 413 usable qubits (superconducting — Osprey, since 2022; Condor, the largest chip, is a scale demonstrator with no published gate figure) and 1,180 (tweezer arrays, since 2023); announcements run a decade ahead (10,000–22,000 qubits for 2028–2029), and thousand-atom arrays hold atoms without gating them. Four causes, not one: quality across the full width degrades with size; the I/O wall near 104 lines per cryostat; the industry's turn from count to quality after 2023; and the decision to scale by linking modules rather than by growing one chip (§8.4–8.6).
- (ii) Two-qubit error no longer converges at the median once each figure is read in its own comparability class — protocol, scope, statistic, conditioning — and only superconducting circuits have five or more device figures of one class (§8.4 H2); the frontier improves by a third to a half per year, and the median trails it by about three years.
- (iii) Running a code on the hardware is no longer rare — 53 machines have run one and 11 more name one in their roadmap — but the share does not yet rise by cohort, and a decoder in the loop is rare (4).
- (iv) The interconnect layer is undisclosed or absent on 149 machines.
- (v) Control stays outside the cryostat on 82 of the 110 machines of the cryogenic families (superconducting, spin, topological, annealing).
- (vi) Of the 65 roadmap checks that fall short, 49 quantify both a qubit deficit and an error deficit, and in 48 of them the error deficit is the larger — a median ×7 on qubits against ×1000 on error (40 more checks name no target the check can use) — so the machines that matter next are those that lower the logical error per operation, whatever their size.
-
Where the majors place their second bet says more about the roadmap than their press releases.
- Google added a neutral-atom track beside its superconducting one [2], [9];
- IBM bought HRL — silicon spins and cryo-CMOS control — beside its transmon programme [10];
- Microsoft sells neutral-atom machines with Atom Computing while its own topological programme has no demonstrated qubit [11]–[13];
- D-Wave bought Quantum Circuits (dual-rail erasure qubits) while its annealing revenue slid [14]–[17];
- IonQ bought Oxford Ionics (laser-free, microwave-driven gates — its "electronic qubit control") and a foundry [18], [19].
Google, IBM and Microsoft now each hold two qubit families — one fast, one dense; IonQ and D-Wave doubled down inside their own.
-
The platforms ranked by expected contribution to a utility-scale fault-tolerant machine around 2033 — each with the event that would move it (§5.2):
- (i) superconducting transmons with engineered error structure, qLDPC codes and cryo-integrated control — the only platform with a scaling memory, the fastest cycle and a 300 mm supply chain; demoted if no logical two-qubit gate beyond distance 3 appears by 2027;
- (ii) neutral atoms with zoned architectures, transversal or algorithmic fault tolerance and erasure conversion — the most qubits under full logical control and the richest set of logical operations; demoted if below-threshold memory with reloading is not shown;
- (iii) trapped ions with laser-free electronic gates on 2D chip traps — the lowest gate and readout errors at scale and the best logical memory reported (a preprint of September 2026); demoted if the millisecond cycle is not bought back by encoding rate at 10³ logical qubits;
- (iv) silicon spin qubits as the long-horizon manufacturability bet — 300 mm wafers and 4 K control; promoted once a device above 12 qubits publishes all-pairs two-qubit data;
- (v) photonics as the interconnect layer of every modular architecture and a compute bet demoted in this revision (October 2026): PsiQuantum no longer dates its first system — its June 2026 release sets cryoplant delivery for the second half of 2027 and names no operating date — so the "slipped system date" trigger below has fired; promoted back by a dated system or a fusion-based logical qubit;
- (vi) topological qubits — not yet a demonstrated qubit: one tetron has shown two parity measurements, but the test that they act as a qubit's non-commuting X and Z (a rapid X–Z sequence) is deferred by the authors themselves, no two-qubit operation or entanglement has been reported, and the topological interpretation is disputed [20]–[23];
- (vii) annealing — commercially eroding, with no route to the applications of §4 beyond optimisation (G5) and the spin-glass dynamics it simulates natively (G1).
Bosonic codes (cats, GKP, dual-rail) are a direction the superconducting mainstream will absorb, not a separate winner; and the machine that reaches the applications of §4 is more likely a composition of architectures joined by links than one architecture grown large (§8.6).
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1How the platforms are compared — criteria chosen for the goals, not for popularity
1.1 Why not fidelity
A two-qubit fidelity is an average-case, context-dependent, gate-set-dependent number. It hides error structure (coherent vs. stochastic vs. leakage vs. erasure), it is measured in isolation rather than under full parallel load, and it says nothing about time. Cross-technology comparison in fidelity space is meaningless: an ion "99.99%" and a transmon "99.9%" differ by 103 in gate duration and by 103–105 in QEC cycle time. The invariant object is the error channel per operation plus its duration, decomposed by the classes a code treats differently:
table
| Error class | Cost to fault tolerance | Where it dominates |
|---|---|---|
| Stochastic Pauli | linear, threshold ∼1% | all platforms after twirling |
| Coherent | accumulates ∼ n2; worst-case ∼√r | ions (laser phase), spins (calibration), transmons (ZZ) |
| Undetected leakage | non-Pauli, spreads; needs leakage-removal units | transmons |2⟩, Rydberg decay, valley states |
| Erasure (detected loss/leakage) | cheap: threshold ∼4% vs ∼1% | photons (loss), Yb/Sr atoms, dual-rail SC, metastable ions |
| Correlated bursts | catastrophic beyond code distance | transmon quasiparticle bursts (~hourly on Willow), global laser/field noise on ions/atoms |
1.2 The six axes (each scored 1–5 with fixed anchors)
table
| Axis | What it measures | 5 | 4 | 3 | 2 | 1 |
|---|---|---|---|---|---|---|
| A. Channel quality at scale | 2Q error and SPAM error under full-width parallel operation, plus error-class structure | ≤10-4 at ≥50 qubits | 10-4–10-3 at ≥50 qubits, or ≤5×10-3 with a demonstrated erasure or bias structure | 10-3–5×10-3 | 5×10-3–10-2 at ≥10 qubits, or better only in registers of ≤10 qubits | not shown beyond a few qubits |
| B. Logical clock | QEC-cycle time including measurement, reset, transport | ≤1 µs | 1–10 µs | ∼100 µs | 1–10 ms | ≥10 ms or undefined |
| C. Scale with quality | number of qubits that simultaneously meet axis-A quality; connectivity | ≥1,000 | 100–1,000 | 50–100 | 10–50 | <10 |
| D. Fault-tolerance progress | what has been demonstrated: break-even, Λ, logical gates, magic states, decoding | sustained Λ>2 + logical gates + magic states | Λ>1 memory below break-even plus logical gates, or Λ>2 memory without gates | many logical qubits beyond break-even (short circuits / detection codes) | a code run once, above break-even in no metric | none |
| E. Scaling path | fab, I/O, cryogenics, modularity — credibility of a route to 105–106 physical qubits | foundry-proven + modularity demonstrated | foundry-proven, modularity demonstrated at two modules | foundry-compatible, modularity on paper | bespoke process with one replication | bespoke materials, no replication |
| F. Roadmap credibility | track record (hits vs. slips), external validation (DARPA QBI stage), funding runway | consistent delivery, Stage B/C, multi-year runway | delivery mostly on time, Stage B | mixed record | one major slip, no external stage | repeated slips / no validation |
Two scores are given where they differ: [D] = demonstrated as of Sep 2026, [R] = what the roadmap would deliver by ~2029 if held. The maturity index is two sums: A–D, the four scores the anchors fix from measured figures and demonstrations, and E–F, the two judgement scores; neither is a ranking of usefulness — usefulness is decided in §4 by goal.
1.3 The goals
table
| Goal | What it needs (dominant → secondary) | Scale/time |
|---|---|---|
| G1 Analogue & NISQ many-body simulation (physics: gauge theories, spin glasses, thermalisation) | count × native connectivity × coherence; no QEC | 102–104 physical, now |
| G2 Error-mitigated utility circuits (100–150 qubits, 103–104 2Q gates; "advantage candidates", certified randomness) | channel quality at scale, shot throughput | 100–150 physical, now–2027 |
| G3 Early fault tolerance (102–103 logical qubits, 105–106 Toffolis: Hubbard models, small catalysts) | logical-qubit count × fidelity; clock secondary | 104–105 physical, 2027–2031 |
| G4 Large-scale fault tolerance (≥103 logical, 109–1010 Toffolis: RSA-2048, FeMoco, P450) | clock × fidelity × count × connectivity | 105–107 physical, 2030s |
| G5 Heuristic optimisation / annealing | — (no proven advantage) | now, contested |
| G6 Networking / distributed QC (quantum-internet nodes, inter-module links) | photonic interface rate × fidelity × memory | now–2030 |
| G7 Deployable / sovereign / HPC-embedded systems (racks, no dilution fridge, on-prem) | footprint, power, integration | now |
Resource anchors for G3/G4 (latest credible estimates): RSA-2048 with <106 noisy qubits in <1 week at 10-3 error and 1 µs cycles (Gidney, May 2025) [7]; FeMoco/P450 ∼0.5–7×106 physical qubits and days-to-months at µs cycles [24], [25] — becoming years to centuries at millisecond cycles unless offset by parallelism; 8×8 Hubbard ∼1.3×102 logical qubits and ∼3×105 physical, hours (Kivlichan 2020) [26]. 2026 updates: ECDLP-256 (the 256-bit elliptic-curve discrete-logarithm problem) in minutes with fewer than 0.5 M physical qubits on a planar lattice at 10-3 (Google, Mar 2026 — ~20× below Litinski 2023 [27]) [28]; RSA-2048 with fewer than 100,000 physical qubits using qLDPC codes at 10-3, 1 µs cycles (Iceberg Quantum 'Pinnacle', Feb 2026) [29]; on reconfigurable neutral atoms, Shor for P-256 in days with 10,000 atoms minimum (26,000 in the time-efficient variant), with RSA-2048 one to two orders of magnitude longer on the same architecture (Cain et al., Mar 2026); the RSA-2048 point on that trade curve is 5.6 days on 19 M qubits at a 1 ms cycle (ISCA 2025) [30], [31] — the count is no longer the barrier; the clock is. See sources [6], [7], [24]–[26].
Cost and energy are not a separate axis here (system power spans 3 kW for a room-temperature atom machine to 12.5 kW for an annealer and tens of kW for a large dilution-refrigerator installation; $/qubit is quoted only as a Diraq roadmap target of < $1); they enter through G7 and axis E. A reader pricing a deployment should add them explicitly.
2Platform profiles — demonstrated vs. intended
Legend: [D] demonstrated/published · [C] company claim without peer-reviewed data · [R] roadmap · [S] simulation or estimate · [G] established fact · [P] preprint, trade press or the author's own publication. Scores follow §1.2 anchors; "[D]/[R]" gives demonstrated / roadmap-if-held.
2.1 Superconducting circuits (transmons, fluxonium)
Demonstrated [D]. - Channel at scale: Google Willow (105 q, Dec 2024): device means 1Q 99.97%, 2Q 99.88%, readout 99.5%, T1 68 µs; the distance-7 memory experiment on a 101-qubit patch of the same chip ran a 1.1 µs QEC cycle [1], [32]. IBM fleet EPLG (error per layered gate, full-width) 3.7×10-3 typical, best 1.9×10-3 on ibm_boston (July 2026) [33], [34]. Zuchongzhi 3.0 (105 q): 2Q 99.62%, readout 99.18% [35]. Rigetti Cepheus-1-108Q (12 chiplets): median 2Q 99.1% [C] [36]. Records: IQM tunable-coupler CZ 99.93% over 40 h and Toshiba double-transmon coupler CZ 99.90% in 48 ns [37], [38]; fluxonium 2Q record CNOT 99.94% in 60 ns (Manucharyan group, PRX Quantum 6, 010349), above MIT's 99.922%, which is an RL-optimised mean [39], [40]. Dominant errors: 2Q gates (~40% of the colour-code budget), leakage, TLS drift, quasiparticle bursts about hourly on Willow [41]. - Fault tolerance: d=7 surface code, Λ=2.14, memory 2.4× best physical, real-time decoding 63 µs latency at d=5 [1]; colour code Λ3/5=1.56, lattice-surgery teleportation, magic injection >99% [41]; magic-state cultivation fidelity 0.9999(1) with 8% acceptance [42]; RL-steered calibration during QEC, record d=7 logical error 7.72×10-4/cycle (July 2026) [2]. China: USTC 107-qubit processor (reported as Zuchongzhi 3.2; the PRL does not name it) d=7 below threshold, Λ=1.40 [3]; USTC logical CNOT between d=3 patches (fidelity 0.643, no post-selection) [43]; Zhejiang 125-q lattice surgery [44]. IBM: 70 "logical" qubits in an error-detecting spacetime code, 468 T gates (July 2026) — a mitigation-class result, not fault tolerance [45], [46]; that instance was simulated exactly by tensor-network contraction in 37.3 min on 32 nodes × 8 H100 GPUs, the amplitudes of IBM's own bitstrings giving log-XEB 0.350, consistent with IBM's ≥0.284 (Aug 2026) [D] [47]; the paper's v3, now co-authored by the simulators, replaces it with 64 logical qubits on 76 physical (ibm_boston), depth 73, 314 T gates, fidelity ≥0.349 at 95% confidence (Sep 2026) [D] [45], [46]; Relay-BP decoder for the [[144,12,12]] gross code on FPGA <1 µs/cycle (simulation) [48]. - Scale/modularity: Nighthawk 120 q square lattice, 5,000 2Q gates per circuit [49]; IBM Loon (c-couplers, multilayer routing) fabricated and two coupled cryogenic cells (Aug 2026) [C] [50]; Rigetti's chiplet tiling is the only shipped multi-chip system and shows the fidelity cost of tiling (99.6%→99.1%) [36]; Fujitsu/RIKEN 256 q with 3D-stacked cells [51], [52]. Cryo-integrated control: SEEQC SFQ digital control of qubits at millikelvin temperature, 1Q fidelities >99% and up to 99.9% (Nature Electronics, Mar 2026); the 5-qubit / nW-per-qubit / no-quasiparticle-poisoning details are from SEEQC's press coverage [C] [53]; SEEQC–IBM SFQ integration under QBI (announced June 2025) [54]; Google absorbed Atlantic Quantum for its cold-stage control stack [55]; the wider superconductor-electronics field behind SFQ control — RSFQ (rapid single flux quantum), ERSFQ/eSFQ (energy-efficient RSFQ), RQL (reciprocal quantum logic), AQFP (adiabatic quantum-flux-parametron), their foundries and design flows — is tracked in the Superconductor Electronics Monitor [P] [56]. - Commercial: IBM $10 B commitment (June 2026) [57]; IQM Nasdaq listing [58]; 26 full-stack systems sold, 17 delivered, EUR 102 M order backlog (Sep 2026) [D] [59]; OQC £260 M Series C [60]; Rigetti $541 M cash and investments (30 Jun 2026) [D] [61] plus a US CHIPS R&D award of up to $100 M for a minority equity stake — readout electronics, cryostat architecture, high-connectivity chip fabrication (Sep 2026) [D] [62], [63]; Google Willow by proposal only [64]. DARPA QBI Stage B: IBM is the only transmon vendor; Google (which joined Stage A only in Sept 2025), Rigetti and Atlantic Quantum were not on the Nov-2025 Stage-B list — DARPA says further teams may still enter [65], [66].
Justified intentions [R]. IBM: Kookaburra (first qLDPC memory + logic module) 2026 — slipped one year from the 2023 roadmap; Cockatoo (L-couplers between modules) 2027; Starling 2029: 200 logical qubits, 108 gates; Blue Jay 2033: 2,000 logical, 109 gates [67], [68]. Track record: Heron r3, Nighthawk r1 and the decoder came on or ahead of time; the "quantum advantage by end-2026" claim rests on IBM's own definition. Google: six-milestone roadmap, next is the "long-lived logical qubit" (10-6); "commercially relevant" by end of decade [32]. Rigetti: 108 q at 99.5% slipped from end-2025 to "later 2026" [69]. IQM: 150-q Halocene at 99.7% (late 2026), FT 2030 [70], [71]. Fujitsu: 1,000 q in 2026 (unconfirmed), 250 logical FY2030 [51], [52].
Bottlenecks. Λ≈1.4–2.1 is too small: from 7.7×10-4 at d=7 with Λ≈2, reaching 10-6 requires d≈25 and >103 physical qubits per logical qubit unless physical errors fall well below 10-3. Readout (∼10-2 at scale) is the weakest link. Logical two-qubit gates exist only at d=3. No gross-code memory has run on hardware — as of the cutoff Kookaburra is not delivered and no gross-code/bivariate bicycle result exists on IBM hardware (the only BB-code hardware runs are IonQ's memories on one 40-ion trapped-ion chain, [[18,4,3]] to [[30,4,5]], and Zhejiang's 32-qubit [[18,4,4]] at 8.9%/cycle) [72]–[74]. Google has published no successor to Willow and no multi-chip result; the July-2026 record paper reports no Λ for the d=7 run [2], [9]. Fujitsu's 1,000-qubit machine is scheduled for fiscal 2026 (Apr 2026–Mar 2027), not yet launched [75], [76]. Per-qubit coax/flex wiring persists; cryo-CMOS/SFQ demos are ≤5 qubits. No cross-module QEC anywhere.
Scores. A 3 · B 4 · C 4 · D 4 · E 4 · F 4 → A–D 15/20 · E–F 8/10 [D]; [R] adds mainly on A (0.1%→0.05% targets) and C (modules).
2.2 Bosonic superconducting codes: cat, GKP, dual-rail erasure
Demonstrated [D]. - Cats: bit-flip times of 430 s (Alice & Bob Boson 4), mean 44 min on the 12-cat "Helium 2" chip (preliminary, Sept 2025), 22 s for a squeezed cat [77]–[79]; AWS Ocelot: 5 cat + 4 ancilla + 5 buffers, repetition code d=3 1.75% at |α|2=1 → d=5 1.65% at |α|2=1.5 per 2.8 µs cycle — two points at different mean photon numbers, not a distance scan, because the phase-flip is 9.6(4)×10-2 per CX at n̄=2 (bit-flip 3.5(4)×10-3) and the bias is only >25 under the gate, >30 idle [80]. No cat–cat CNOT has been demonstrated (AWS's July 2026 CNOT is theory) [81]. - GKP: Nord Quantique single-mode GKP: T1=360 µs, logical error 8.1×10-3/round, SPAM <10-3 with survival 0.24×0.39 (heavy post-selection) [82]; Yale/Google GKP qudits beyond break-even (gain 1.8–1.9) [83]. Best bosonic memory gain anywhere ≈2.3 — nothing resembling Λ scaling. - Dual-rail erasure: Yale/QCI (now D-Wave) cavity dual-rail CZ ~500 ns, erasure 0.53%/gate, remaining post-selected Pauli error <0.1% (0.12% bound at depth), bit-flips ∼10-6, SPAM ~0.02% (Nature, Aug 2026) — gate-level erasure fraction ≈80% [84]; AWS transmon dual-rail: 384 ns erasure check, residual 6×10-4, bias 42 [85]; 8-qubit Aqumen Seeker shipped (2024) [86]. - Commercial: Alice & Bob Series B extension with NVentures, French GENCI bought the first "Helium" (June 2026) — no logical-qubit performance data published for the 18-cat system; not selected for QBI Stage B [65], [66], [87], [88]. Nord Quantique: QBI Stage B, $1.4 B valuation (May 2026) [89], [90]. D-Wave acquired QCI for $550 M (Jan 2026) [14]; CHIPS R&D award of up to $100 M finalised 8 Sep 2026, the Department of Commerce taking a minority, non-controlling equity stake [91].
Justified intentions [R]. Alice & Bob: Graphene 2030 — 2,000 cats / 100 logical / 10-6, requiring ≥13-min bit-flip during CNOT [92]. Nord Quantique: 100+ logical by 2029, "1:1 physical:logical" [93]. D-Wave/QCI: 17 qubits 2026, 181 in 2028, 10 logical 2030, 100 logical 2032, target Λ=10 [94]; the CHIPS award (Sep 2026) supports a 10,000-qubit gate-model system "designed to enable 100 logical qubits" running more than 106 operations — 100 physical per logical, no date given [91].
Bottlenecks — are the "100–1000× fewer qubits" claims holding? No, not yet. The headline estimates (126,133 cats for ECC-256 in 9 h [95]; 758 cats for 100 logical qubits [96]) assume 0.1% phase-flip per cycle at n̄≈19; measured phase-flip per cycle is ∼10-1 — two orders of magnitude off. Bias-preserving cat–cat gates: undemonstrated. Erasure qubits are the credible part of this family: 82–90% erasure fraction with 10-3 residual Pauli is a good channel, but false-negative rates (1.5–8%) and ancilla transmons dominate the budget, and the marketed "99.9%" is post-selected.
Scores. A 2 · B 4 · C 1 · D 2 · E 3 · F 2 → A–D 9/20 · E–F 5/10 [D]; [R] if phase-flip falls 100×: A→4, D→4.
2.3 Trapped ions
Demonstrated [D]. - Channel at scale: Quantinuum Helios (98 Ba⁺): 1Q 2.5×10-5, 2Q 7.9×10-4, SPAM 3.3×10-4 (published value; the preprint gave 4.8×10-4), leakage 1.1×10-5/Clifford, all-to-all via ring + junction, 8 zones [97]. H2 (56 q): QV 225 [98]. IonQ Forte (36 q): 2Q 0.4%, SPAM 0.5% [C] [99]; its laser (MS) gates take 550–883 µs (median 672 µs) on 30+-ion chains, 1Q 110 µs [100], [101]; Tempo publishes only '99.9% fidelity' and #AQ 64 with no gate times [C]. Oxford Ionics' electronic gate lasts 225.8 µs (2025) / ≈120 µs (2024) [102]. Records: 2Q 8.4×10-5 with electronic (laser-free) gates, no ground-state cooling (IonQ/Oxford Ionics, Oct 2025) [102]; 1Q 1.5×10-7 (Oxford) [103]; hour-scale memory [104]. - Fault tolerance: Helios: 48 error-corrected logical qubits ([[80,48,4]]) with logical gate error ∼1×10-4 vs 8×10-4 physical, logical SPAM <8×10-6, 94 error-detected qubits in a GHZ state, 64-logical-qubit XY simulation (3.2% acceptance at depth) [105]; logical teleportation 99.82% [106]; magic states in [[6,2,2]] at 7×10-5 infidelity [107]; FT QAOA (quantum approximate optimisation algorithm) and HHL (Harrow–Hassidim–Lloyd algorithm) with a Steane-code T gate at 2.6×10-3 [108]; Helix, the [[20,2,6]] C₄-Helix code on Helios (preprint, Sep 2026) [P]: memory 4.6×10-5 per logical qubit per QEC cycle, logical two-qubit Clifford 2.8×10-4 (4.3× below the unencoded baseline), and a three-logical-qubit GHZ state spanning C₄-Helix and a distance-5 surface code at ≥99.925%, none post-selected [5]. IonQ: eight codes on 40 ions (nine in the June version), with break-even within error bars in one code the paper does not identify (3.95 ± 0.68 s vs 3.84 ± 0.48 s physical — the physical baseline revised from 3.3 ± 0.9 s in the arXiv version of 14 Sep 2026), with leakage post-selection; its bivariate bicycle [[18,4,3]] memory, 4 logical qubits in 18 ions, reaches 2.48 ± 0.40 s, below the physical lifetime [109]. No Λ-type distance scaling on any ion system; the nearest is one concatenation step in Helix — 2.1×10-4 ([[10,2,3]], d=3) to 4.6×10-5 ([[20,2,6]], d=6) per logical qubit per cycle — two points, not a distance series [5]. - Speed: Helios 2Q gate ~70 µs but ~55 ms per full-width layer (sorting, transport, cooling dominate); transport ≈60% of runtime on H2 [97], [110]; IonQ assumes 1–5 ms syndrome cycles [111]; its secp256k1 (256-bit elliptic-curve discrete logarithm) estimate assumes 6.7 ms per syndrome-extraction cycle and ≈29.5 ms per logical measurement layer: 25.7 days per attempt on 19,397 ions (~1,450 logical; 2Q error 10-4 assumed) (Sep 2026) [S] [112]. - Scale/modularity: Quantinuum grid trap with 2.5 kHz ion exchange; junction transport at 4 m/s [113], [114]; Oxford distributed QC over a 2 m photonic link: remote Bell 96.9% at 9.7 s⁻¹, teleported CZ 86% [115]; 250 s⁻¹ (Duke/Maryland) [116]; ion transport between two microchip modules (Universal Quantum's matter link): 2,424 transfers s⁻¹, transport infidelity <7×10-8, qubit phase coherence unaffected (Nat. Commun., Feb 2023) [117]. Trap chips from semiconductor fabs: Sol's 2D grid trap by Honeywell [118]; IonQ's first 256-qubit QPUs fabricated at its SkyWater foundry after six tapeouts in H1 2026 — qubit performance not yet published [C] [119]; 300 mm traps at GlobalFoundries under the CHIPS award (planned) [120]. Tsinghua 512-ion 2D crystal (analogue) [121]. - Commercial: Quantinuum $600 M at $10 B (Sep 2025), IPO June 2026 ($1.68 B, Nasdaq QNT), cash $2.1 B, four Helios systems [122]–[124]; $100 M CHIPS R&D award finalised 8 Sep 2026 — GlobalFoundries to fabricate next-generation ion traps and control electronics on 300 mm wafers, Monarch Quantum the lasers and optics [120]; IonQ $3 B equity raised in 2025, acquisitions of Oxford Ionics ($1.075 B), Lightsynq, ID Quantique, Vector Atomic, SkyWater foundry ($1.8 B, announced Jan 2026, closed July 2026) [18], [19]; Quantum Art $140 M Series A (Israel) [125]; eleQtron €57 M; QUDORA leads NFQC-1k, the only trapped-ion consortium among six selected in Germany's Quantum Computing Competition (22–23 Sep 2026; €122 M planned over five years; ≥1,000 physical and 50 logical qubits at logical gate error <0.01% by 2030 [R]; a working system meeting entry criteria due by 31 Mar 2027) [126], [127]; AQT rack-mounted, QV 32,768 [128], [129]. QBI Stage B: Quantinuum and IonQ [65], [66].
Justified intentions [R]. Quantinuum: Sol 2027 (192 physical, ~100 logical, 2D grid trap fabricated by Honeywell, in validation) → Apollo 2029 (thousands physical, hundreds logical, 10-6–10-10) [118]; "near five-nines logical fidelity with a novel code family" claimed on the Q2-2026 call [123], [124]; the nearest public result is the Helix preprint (Sep 2026) — memory 4.6×10-5 per logical qubit per cycle (≈99.995%) in the new C₄-Helix code, logical two-qubit Cliffords 2.8×10-4 — its link to the claim unconfirmed [P] [5]. Track record: strong — QV 10×/year promise met, Helios launched on schedule. IonQ: Superion 256 launched 8 Sep 2026 — orderable, first ions trapped in prototypes [C], customer deliveries 2027 (first orders: the NVIDIA Accelerated Quantum Research Center, installation 2027; Florida International University, late 2027); no 256-qubit gate fidelity published — the release cites the 99.99% set in Oct 2025 [119], [130], [131]; Superion 10K (CMOS on the trap chip, first generation for the Walking Cat architecture): 'full fault tolerance' in a 2027 lab setting, 'manufacturable, commercial' in 2028 [R] [119]; 2 M physical / 40–80 k logical by 2030 [132], [133]. Track record: the 2020 roadmap promised 4,000 qubits by 2026 (missed ~40×); the 99.99% gate is real, the 100→10,000 jump has no published 2D-trap heating, gate-time or interconnect data.
Bottlenecks. Clock: 103–105× slower than superconducting per layer; transport and cooling, not gates, set throughput. High-rate code demos discard 75–97% of shots at depth. 2D scaling unproven at product scale (Sol is the first test). Interconnects at 10–250 s⁻¹ vs ∼104 s⁻¹ needed. Optical complexity (Helios ≥7 laser wavelengths, 1,228 electrodes) — electronic gates remove lasers but have no published gate time at scale.
Scores. A 4 · B 2 · C 3 · D 4 · E 4 · F 3 (Quantinuum 4 / IonQ 2) → A–D 13/20 · E–F 7/10 [D]. A is 4, not 5, by the anchors: the ≤10-4 figures are two-ion records, the best figure at ≥50 qubits is Helios's 7.9×10-4 [97], [102]. E is 4 by the anchors: trap chips from semiconductor fabs and modularity demonstrated at two modules — the matter link [117] and the photonic link [115]; the low link rates are charged to B and C, not counted twice; [R] Sol/Apollo would lift C→4, B→3 (2× speed-ups per generation).
2.4 Neutral atoms (Rydberg tweezer arrays)
Demonstrated [D]. - Channel: CZ 99.854% raw / 99.941% loss-post-selected stable over 10 h (Harvard, Apr 2026) [134]; 99.72/99.40% (Atom Computing, Yb) [135]; 99.71% (Caltech, Sr) [136]; QuEra Gemini spec 2Q 99.2% global [137]. Non-destructive readout 0.46% bit-flip + 0.24% loss [4]; hyperfine T2 1.3 s, 12.6 s in a 6,100-atom Cs array [138], [139]. Dominant error: atom loss (>80% of leakage events) — detectable, hence erasure-convertible; Rydberg decay 0.05–0.1%; a 2026 review argues the standard CZ scheme saturates near 99.9% without new gate physics [140]. Erasure conversion demonstrated in metastable Yb (Princeton) and Sr (Caltech), with [[4,2,2]] logical teleportation under erasure-biased noise (Nature Physics, June 2026) [141]–[143]. - Scale: 448 atoms under full fault-tolerant control [4]; >3,000 qubits maintained >2 h with continuous reloading (300,000 atoms/s reloaded into tweezers, 30,000 initialised qubits/s) [144]; 6,100-atom Cs array with 12.6-s coherence [138], [139]; 11,000 Rb atoms trapped in 18,225 metasurface tweezers (Tsinghua, June 2026; no gates) [145]; Atom Computing 1,225-site Yb array; Pasqal defect-free arrays of up to 1,024 atoms at 4 K, ~5,000 s trap lifetime (Apr 2026) [P] [146]. - Fault tolerance: Harvard/MIT/QuEra 448-atom architecture (Nature, Nov 2025): surface codes d=3→5 with 2.14× suppression in a 4-round circuit, using atom-loss detection and machine-learning decoding (not long memory), [[7,1,3]], [[15,1,3]] with transversal T, [[16,6,4]] with up to 96 logical qubits active, hundreds of logical teleportations, mid-circuit qubit reuse [4]; logical magic-state distillation (5-to-1, d=3 and d=5 colour codes) [147]; Atom/Microsoft toric code: ΛZ≈1.9 but ΛX≈1.2 (average 1.30) over 4 cycles, 90 rounds sustained with reloading — but suppression vanished once reloading was included (0.63% vs 0.64%/cycle) [148]; Microsoft/Atom 24 entangled logical qubits, 28 running Bernstein–Vazirani better than physical (2024) [149]; Infleqtion 12 logical qubits with loss correction, Shor N=15 [150]; 30 entangled logical qubits in 80 atoms on Sqale — ten [[8,3,2]] blocks of distance 2, so errors are detected (lost atoms corrected), not corrected; an IQP (instantaneous quantum polynomial-time) circuit with four logical CCZ (controlled-controlled-Z) gates and ~1,000 physical operations, output ~1,000× the uniform-random baseline (Sep 2026; paper pending) [C] [151]. - Speed: CZ 270 ns, but imaging ~0.5–1 ms and transport ~100s µs give QEC rounds of ~1–4.5 ms [4], [31]; transversal + correlated decoding (algorithmic fault tolerance: constant syndrome rounds per logical gate) is the compensating theory [152]; RSA-2048 estimate for a transversal atom architecture: 19 M atoms, 5.6 days at 1 ms cycles [31]. - Commercial: QuEra $230 M+ Series B expansion, closed 9 Sept 2025 (Google, SoftBank Vision Fund 2, NVentures) [153]; Atom Computing $300 M+ incl. $100 M US DoC LOI (June 2026) [154]; Infleqtion NYSE listing Feb 2026 (>$550 M) + $100 M DoC LOI [155]; Pasqal SPAC closed Aug 2026 (~$360 M cash, €16.5 M 2025 revenue) [156]; H1 2026 revenue €4.9 M (+14%), €70.4 M booked and awarded, €312.9 M cash on 27 Aug 2026 [C] [157]; QuNorth ordered "Magne" (1,225 physical / 50 logical, €80 M) from Atom/Microsoft [11], [12]; Google opened a neutral-atom hardware track under Adam Kaufman (March 2026) [158]; Oratomic (Caltech spin-out led by Dolev Bluvstein with Manuel Endres) raised a $300 M Series A (Jul 2026) toward a ~10,000-atom machine [P] [159]. QBI Stage B: Atom Computing and QuEra [65], [66]. Germany's Quantum Computing Competition (federal research ministry BMFTR, up to €640 M for six consortia, two per platform) selected planqc's ytterbium-atom LOGIQC consortium (22 Sep 2026) [G] [160]; planqc's MAQCS hardware began arriving at the Leibniz Supercomputing Centre (LRZ) on 9 Sep 2026 after a 1,000-qubit demonstrator reached technology readiness level (TRL) 5, operation targeted by end-2027 [C] [161].
Justified intentions [R]. QuEra: Jan-2024 roadmap promised 100 logical qubits in 2026 → now "Libra" 2028 (>256 logical, 10-6, on Braket) and a gigaquop system 2028–29 (>1,000 logical, >20,000 physical per core) — a two-year slip [162], [163]. Atom/Microsoft: Magne ~50 logical / >1,200 physical qubits; its Copenhagen facility was completed and installation began in Sep 2026, fully operational early 2027 [11], [12], [164], [165]. Pasqal: 10,000 physical slipped 2026→2028; 100 logical 2029 [166], [167]. Infleqtion: 30 logical 2026 — met in error-detected form (distance 2, Sep 2026) [C] [168]; >50 logical Illinois system 2027 [150]; 100 logical by 2028, 1,000 by 2030 (restated Sep 2026) [168]. Google: QEC-focused, no commercial date.
Bottlenecks. The millisecond cycle (103× slower than superconducting) is the single structural disadvantage; decoders must keep up in real time. Below-threshold operation shown only in short circuits — no long-memory Λ>2 with reloading yet. Scale-with-quality gap: 11,000 trapped vs 448 with logical control. Laser power and beam steering bind above ~104 qubits: an acousto-optic deflector's spot count is its rf bandwidth times the acoustic transit across the beam, a transit that also bounds how fast it re-points, and liquid-crystal modulators reframe at tens of hertz; multi-core interconnects unproven.
Scores. A 4 · B 2 · C 4 · D 4 · E 4 · F 3 → A–D 14/20 · E–F 7/10 [D]; [R] Libra/Magne would lift D→5, C→5.
2.5 Photonic (linear-optical / fusion-based / continuous-variable)
Demonstrated [D]. - Components (excellent): PsiQuantum Omega (300 mm GlobalFoundries): purity 99.5%, HOM 99.5%, fusion Bell fidelity 99.22%, chip-to-chip Bell 99.72% over 42 m, waveguide loss 0.5 dB/m, 2 K [169]; USTC quantum-dot source 71.2% system efficiency — reported as the first above the 2/3 loss-tolerance threshold [170]; Sparrow Quantum quantum-dot source: >500 MHz single-photon flux into fibre at 1 GHz, 51.5–56.2% efficiency, but HOM indistinguishability 55% unfiltered (92.3% filtered) — rate traded against quality (preprint, Sep 2026) [P] [171]; Xanadu edge-coupling 0.085 dB/facet (June 2026) [C] [172]. - Systems: Xanadu Aurora — 35 chips, 12 modes per 1 MHz cycle, a 12×N cluster state generated for 2 h, at ~14 dB total loss, no error-corrected computation [173]; on-chip GKP state at 0.62 dB effective squeezing vs ~10 dB needed [174]; Jiuzhang 4.0 boson sampling, 3,050 photon clicks (Nature, May 2026) — non-universal, contested by loss-exploiting classical algorithms [175]; Quandela 12-qubit Belenos/Lucy delivered to CEA (Oct 2025) [176]; QuiX 8-qubit universal MBQC subsystems delivered to DLR (July 2026), commissioning pending [177]. - Fault tolerance: no photonic logical qubit exists. Xanadu states its loss is 24× above threshold in 2026, targets 1× in 2030 [178]. Theory: fusion-based QC tolerates 2.7% per-photon loss with 6-ring resource states, up to 17% with 168-qubit resource states that no one has yet made [179]. - Commercial: PsiQuantum $1 B Series E at $7 B (Sep 2025) [180], DARPA QBI Stage C via US2QC: $31.8 M + $125 M expanded (July 2026) for validation of barium-titanate (BTO) switches, packaging and cryogenics [181]; US CHIPS R&D award of up to $100 M finalised 8 Sep 2026 (manufacturing integration, electro-optic materials, high-temperature single-photon detectors, ultra-low-loss packaging) [62]; its foundry GlobalFoundries finalised a $375 M five-year, milestone-based CHIPS quantum award (cryo-CMOS, advanced packaging, heterogeneous integration) the same day, beside a $300 M silicon-photonics letter of intent [182]; Brisbane site changed and groundbreaking slipped to June 2026, cryoplant 2H 2027 — the "useful by end-2027" target is at risk; CEO change Feb 2026 [183]. Xanadu SPAC closed Mar 2026 (~$302 M, 40% below plan), CAD 195 M Canadian factory funding (Aug 2026), first quantified roadmap 31 Aug 2026: FT milestone 2028–29, up to 200 logical qubits by 2029, 500 by 2030, 1,000+ by 2031 [178], [184]; ASML collaboration on lithography to cut line-edge roughness, a key source of waveguide loss (9 Sep 2026; exploratory, no loss target published) [185]. Photonic Inc $200 M at $2 B (T centres, spin–photon) [186], proposing a multi-tenant Canadian semiconductor fab of up to CAD 500 M (Project VANGUARD, 14 Sep 2026; unfunded) [R] [187]; QBI Stage B: Xanadu, Photonic Inc; Quandela Stage A (June 2026) [65], [66], [188].
Justified intentions [R]. PsiQuantum "before 2033" utility scale; Xanadu 1,000+ logical by 2031; Quandela 50 logical by 2028 (its 2025 first-logical-qubit milestone was missed); ORCA PT-3 (2026) not delivered.
Bottlenecks. Loss is the whole game: every switch costs 0.1–0.2 dB against a total budget of ~0.5 dB; GKP squeezing is 9 dB short; sources are probabilistic, forcing multiplexing depth ~10; thousands of cryogenic detector channels and MHz–GHz feed-forward are unproven at system level. PsiQuantum has published no 2026 hardware demonstration — its progress is visible only through DARPA verification-and-validation (V&V) contracts.
Scores. A 2 (component-level) · B — (design 4) · C 1 · D 1 · E 3 · F 2 → A–D 4/20 · E–F 5/10 [D] (A–D 8 with the design-level clock); [R] if loss falls 20×: D→3–4, C→4.
2.6 Semiconductor spin qubits (Si/SiGe, SiMOS, Ge, donors) and solid-state defects
Demonstrated [D]. - Channel: 1Q up to 99.97% (Diraq/imec 300 mm), 2×10-4 mean over 18 exchange-only qubits (HRL) [189]–[191]; 2Q 99.04–99.56% on foundry 300 mm devices (Diraq/imec, Nature Sep 2025) [189]; 99.90% donor nuclear-spin CZ (SQC) [192]; CZ between moving spins 98.86% (Delft, May 2026) [193]; 1 K operation at 98.9% 2Q [194]. Readout 1–100 µs; no erasure channel. Dominant errors: residual ²⁹Si, charge noise, and — per HRL — ~80% of CNOT error is extrinsic control/calibration [190], [191]. - Scale: 18-qubit Ge array at identical voltages (Groove/QuTech), 18 exchange-only (EO) qubits from 54 dots (HRL), 12 (Intel Tunnel Falls), 10-qubit 2D Ge lattice; conveyor-mode shuttling over an effective 10 µm (back and forth) at 99.5% [195], [196]; 8-qubit imec device with exchange working in only 1 of 4 pairs [197]. - Fault tolerance: HRL: d=5 repetition code, 200 rounds, Λ5/3=4.7, [[4,2,2]] logical fidelity 0.95 (post-selected), all sequenced by a 4 K cryo-CMOS controller with no room-temperature real-time electronics (Nature, July 2026) [190], [191]; donor [[4,2,2]] universal gate set (SUSTech) [198]. No below-threshold logical memory on any spin platform. - Manufacturing: Intel 300 mm EUV (>24,000 devices/wafer [199]; 96% of 232 twelve-dot devices on one wafer fully working — every contact, gate and dot — at 1.6 K [766]); GlobalFoundries 22FDX (Quantum Motion: 1,024 dots characterised in 5 min; full-stack system at UK NQCC) [200]; STMicro FD-SOI (Quobly: qubit readout, one- and two-qubit gates on a single QSOI® 300 mm chip, figures deferred to a forthcoming paper [C] [201]; 377 dots with 69% first-electron detection yield and a ±35 mV spread of the first-electron position [P] [202], Sep 2026); mK cryo-CMOS co-located with qubits (UNSW/Diraq, Nature 2025) [203]. - Commercial: IBM acquired HRL Laboratories (announced July 2026, completed 26 Aug 2026) to add spin qubits, cryo-CMOS control and packaging to its roadmap [10], [204]; Quantum Motion $160 M Series C plus a second close in Sep 2026 (amount undisclosed) [205]; Quobly €115 M; Diraq >$100 M + $38 M CHIPS LOI, and an 8-qubit Diraq system to run inside an Equinix data centre in Sydney (installation due Oct 2026, <20 kW; announced 31 Aug 2026) [C] [206]; SQC A$60 M; QBI Stage B: Diraq, Quantum Motion, SQC, Photonic — four of eleven [65], [66]. Intel: no new chip since Tunnel Falls; a 12-qubit processor was deployed at Argonne under Q-NEXT (Jan 2026) with Intel stating it will 'scale to hundreds of dots' — the programme is alive but without a dated roadmap [207]. Photonic (T centres) put forward Project VANGUARD, a multi-tenant Canadian semiconductor fab of up to C$500 M — a proposal to investors, not funded (Sep 2026) [C] [187]. - Defect qubits (NV/SiV/SnV/T centre): gate errors <0.1% (Fujitsu/QuTech NV); SiV entanglement over 35 km deployed fibre at ~1 Hz (Harvard); T-centre teleported CNOT between cryostats — network nodes, not processors [208], [209]. Fujitsu (joint research with TU Delft and QuTech since 2020) unveiled a diamond-spin quantum computer prototype — tin-vacancy (SnV) centres in photonic integrated circuits, operated at −271.6 °C and usable through its hybrid quantum platform in a test environment — with no qubit count or fidelity disclosed; a multi-module prototype is due by 2027 (Sep 2026) [C] [R] [210].
Justified intentions [R]. Diraq: 150 k physical / 1 k logical by 2029, >2 M physical by 2031 at <$1/qubit — but six weeks earlier its release said "thousands by 2029" (inconsistent messaging) [211], [212]; Iceberg Quantum and Diraq report that Pinnacle qLDPC compilation reaches 1,000 logical from 150,000 physical qubits, the Pinnacle paper's counts falling within 5% of hardware-aware estimates for Diraq devices, with shuttling-dependent noise simulated on NVIDIA CUDA-Q Logical — simulation, not hardware (Sep 2026) [S] [213]. Quobly: one million qubits by 2032, with its Alloy Pioneer system in the cloud for early users by end-2026 [201]. SQC: commercial scale 2033. Quantum Motion: "commercially useful this decade", NQCC delivery on schedule.
Bottlenecks. No device >12 qubits has published all-pairs 2Q fidelities; 2Q plateau at 99–99.6% in foundry devices; readout is slow and sensor-hungry (cycle ~100s of µs); hot operation costs ~1% fidelity; roadmaps are >100× beyond any demonstrated device. The 2026 signal is nonetheless real: HRL's self-sequenced QEC and IBM's acquisition are the first evidence that the CMOS argument is being taken seriously by a hyperscaler.
Scores. A 2 · B 3 · C 2 · D 2 · E 3 (ceiling 5) · F 3 → A–D 9/20 · E–F 6/10 [D]; [R] is the widest spread of any platform.
2.7 Topological (Majorana) qubits
Demonstrated [D]. Single-shot parity readout of one InAs–Al nanowire: 1% assignment error, ms dwell times (Nature, Feb 2025) — with an editor's note that the results do not by themselves establish Majorana zero modes in the devices [13], [214]. Tetron Z-loop parity lifetime 12.4 ms vs X-loop 14.5 µs (~1000× shorter), preprint July 2025 — other tunings in the same preprint give ~9.3 ms and ~4 µs, so the ~10³ ratio is robust but the point values are not, and the paper attributes the short X-loop lifetime to parity switches inside the wire and the long Z-loop lifetime to quasiparticle poisoning from outside; the test that the two loops act as non-commuting X and Z measurements — a rapid X–Z succession — is deferred by the authors to "the next step of our roadmap" [20]. "Majorana 2" (arXiv:2606.03884, June 2026): InAs–Pb, ~20-s parity switching time in one wire of one tetron — a parity switching time, not a qubit lifetime; no braiding, no joint-parity/X measurement, no two-qubit operation, no entanglement, no Bell test, no qubit T1/T2 [21]. Microsoft's blog calls the 20 s a "qubit lifetime" and re-states a 2029 fault-tolerant target [215]. Independent: QuTech "poor man's" Kitaev-chain parity readout >1 ms and a coherent minimal-Kitaev-chain parity qubit with "only limited protection" (2026) [216], [217]; Legg's critique became a Nature Matters Arising (June 2026); Microsoft's multi-author reply concedes nothing [22], [23]. DARPA: US2QC final phase (Feb 2025), not in QBI Stage B [218]; since Sep 2026 a Majorana 2 system sits in Microsoft's new Maryland research centre (Discovery District) with full on-site access for DARPA's independent test and evaluation — access, not a new result [C] [219].
Justified intentions [R]. "Years not decades" (2025) → "2029" (2026). Given the 2018 retraction, the contested topological gap protocol (TGP) and the absence of any two-qubit result, the roadmap has no demonstrated base.
Assessment. No topological qubit has been demonstrated. What exists is high-fidelity single-wire parity readout in a better material, whose topological origin is contested and untestable until X/Z-comparable lifetimes, two-qubit operations, or independent replication appear.
Scores. A 1 · B — · C 1 · D 1 · E 1 · F 1 → A–D 3/20 · E–F 2/10 [D].
2.8 Quantum annealing and analogue machines
Demonstrated [D]. D-Wave Advantage2 GA (May 2025): 4,400+ qubits, Zephyr 20-way connectivity, 12.5 kW [220]. "Beyond-classical" spin-glass dynamics (Science, Mar 2025) was substantially eroded within weeks by belief-propagation tensor networks (Tindall et al., Science May 2026) and t-VMC (Mauron & Carleo); D-Wave maintains that its largest/most-frustrated instances remain unmatched — unresolved but the classical frontier moved [221]–[224]. Finances: FY2025 revenue $24.6 M; H1-2026 revenue $5.9 M (−67% YoY), CFO resigned Aug 2026 [15]–[17]; up to $100 M of US CHIPS and Science Act funding finalised Sep 2026, the Department of Commerce taking a minority, non-controlling equity stake [C], for development toward a 100,000-qubit annealing system and a 10,000-qubit gate-model system aimed at 100 logical qubits [R] [91]; pivot to gate model via QCI (§2.2). Analogue simulators: Google 69-q analogue-digital simulator (beyond-classical only for XEB-style benchmarking) [225]; QuEra Aquila (256 atoms, on Braket) string-breaking in a gauge theory — no advantage claim [226]; Quantinuum digital magnetism (Nature 2026) — heuristic claim [227].
Sober view. No analogue machine has solved a scientifically posed problem demonstrably beyond classical reach with an unchallenged claim; the value of analogue platforms is as physics instruments (G1) and as stepping stones (QuEra/Pasqal analogue → digital).
Scores. Not comparable on A–D (no gate channel); E 4 (mature manufacturing), F 2. Roadmap: 20,000 qubits 2029, 100,000 in 2031 [15]–[17].
3Scoreboards
3.1 Platform scores on the six criteria (demonstrated, Sep 2026)
table
| Platform | A Channel at scale | B Logical clock | C Scale w/ quality | D FT progress | E Scaling path | F Roadmap credibility | A–D, anchored | E–F, judgement |
|---|---|---|---|---|---|---|---|---|
| Superconducting | 3 | 4 | 4 | 4 | 4 | 4 | 15 | 8 |
| Neutral atoms | 4 | 2 | 4 | 4 | 4 | 3 | 14 | 7 |
| Trapped ions | 4 | 2 | 3 | 4 | 4 | 3 | 13 | 7 |
| Bosonic (cat/GKP/dual-rail) | 2 | 4 | 1 | 2 | 3 | 2 | 9 | 5 |
| Spin qubits (Si/Ge) | 2 | 3 | 2 | 2 | 3 | 3 | 9 | 6 |
| Photonic | 2 | (4 design) | 1 | 1 | 3 | 2 | 4 (8) | 5 |
| Topological | 1 | — | 1 | 1 | 1 | 1 | 3 | 2 |
| Annealing | n/a | n/a | n/a | n/a | 4 | 2 | n/a | 6 |
Profiles by axis (A channel · B clock · C scale · D FT progress · E scaling path · F roadmap credibility). The shape is the information: superconducting is round, ions are tall on A and short on B, atoms mirror ions on C/D, bosonic and photonic are B-only spikes.
A–D follow the anchors of §1.2 — A, B and C from the register's figures, D from the demonstrations of §3.2; E–F are the editor's judgement.
Axis A, the evidence behind each score (register, Sep 2026).
table
| Platform | Best figure at scale (qubits) | Best figure in a small register | Score |
|---|---|---|---|
| Superconducting | Willow 1.5×10-3 median 2Q at 105 q; IBM Heron r2 2.0×10-3 at 156 q | fluxonium CNOT 6×10-4 (2 q) | 3 |
| Neutral atoms | 448-atom processor 5.0×10-3 (CZ 99.3–99.6% by RB) at 448 q; Sqale 2.7×10-3 post-selected (unconditioned 6.5×10-3) at 100 q, loss erasure-convertible | 99.7% CZ class (≤60 q) | 4 |
| Trapped ions | Helios 7.9×10-4 at 98 q; H2 <10-3 at 56 q | 8.4×10-5 (2 ions, Oxford Ionics) | 4 |
| Bosonic | Ocelot / cat devices ≤12 q, no 2Q error at scale | dual-rail CZ erasure 0.53%/gate, residual Pauli <0.1% | 2 |
| Spin qubits | 11-qubit donor processor 3.6×10-3 | 99.3% class (2–6 q) | 2 |
| Photonic | Belenos 6.2×10-2 at 12 q | fusion 7.8×10-3 (chipset) | 2 |
| Topological | none | none | 1 |
The index measures how much of the fault-tolerance stack has been shown to work, not usefulness. Read it together with §3.3 and §4.
Sensitivity. Each cell is a judgment with ±1 uncertainty. On A–D the three leading platforms stand one point apart — superconducting circuits 15, neutral atoms 14, trapped ions 13 — and any single ±1 change reverses an order, so read them as a group: superconducting circuits ahead on the clock, atoms on scale with quality, ions on channel quality; on E–F atoms and ions tie (7 and 7) behind superconducting circuits (8); both score 4 on the scaling path for different reasons (array optics at 6,000–11,000 sites vs fab-made traps with two-module links). Axis F mixes vendors inside a platform (Quantinuum ≈ 4, IonQ ≈ 2; QuEra/Pasqal ≈ 2–3 after two-year slips, Atom/Infleqtion ≈ 3–4): read F per leading vendor, not per platform. Every number behind these scores carries a [D]/[C]/[R] tag in §2; a score built mainly on [C] figures (bosonic F, photonic E) inherits that weakness.
3.2 Fault-tolerance primitives — who has shown what
table
| Primitive | Superconducting | Trapped ions | Neutral atoms | Bosonic | Photonic | Spin |
|---|---|---|---|---|---|---|
| Below-threshold scaling (Λ) | Λ=2.14 (d=3→5→7); separate 106-cycle real-time-decoded run at d=5; d=7 at 7.7×10-4 | none (concatenation instead) | 2.14× (d=3→5, 4 rounds); ΛZ≈1.9 / avg 1.3 (4 cycles), lost with reloading | repetition-cat "flat" below threshold | none | repetition d=5 Λ=4.7 (bit-flip only) |
| Most logical qubits beyond break-even | 1–2 | 48 corrected / 94 detected | 96 (d=4 blocks) / 28 in algorithm | 1 | 0 | 0 |
| Logical 2Q gates | d=3 lattice surgery (CNOT 0.64); colour-code teleportation | transversal + lattice surgery (0.85–0.98), teleportation 99.8% | transversal CNOTs, hundreds of teleportations | — | — | — |
| Magic states on logical qubits | cultivation 0.9999 (8% accept) | code-switching 5×10-4; [[6,2,2]] 7×10-5 | 5-to-1 distillation on d=3/5 colour codes | — | — | — |
| Real-time decoding | 63 µs at d=5; FPGA <1 µs/round (sim); RL calibration in-loop | in-loop (teleportation); GPU on Helios | offline ML (1.7× gain) | — | detection only | self-sequenced by cryo-CMOS |
| qLDPC on hardware | components (Loon); gross code pending | BB memories up to [[30,4,5]] on one 40-ion chain; break-even within error bars in one code the paper does not identify, not in the 4-logical-in-18-ion [[18,4,3]]; leakage post-selected | theory: 10-13/round at p=10-3 | — | SHYPS codes (theory) | — |
| QEC cycle | 1.1 µs | ~1–5 ms (55 ms/full layer) | ~1–4.5 ms | 2.8 µs | MHz by design | ~100s µs |
3.3 Revealed preferences — how the majors hedge (2025–26)
table
| Actor | Primary bet | Second bet | Signal |
|---|---|---|---|
| superconducting (Willow, next: long-lived logical qubit) | neutral atoms — new hardware track, Mar 2026 | superconducting processors are "easier to scale in the time dimension", neutral atoms "in the space dimension" — Hartmut Neven, founder and lead of Google Quantum AI, Mar 2026 [2], [9] | |
| IBM | superconducting + qLDPC (Starling 2029), $10 B | silicon spin — HRL acquisition (announced Jul 2026, completed 26 Aug 2026) [204] | wants CMOS density + cryo-CMOS control; its 300 mm pure-play quantum foundry Anderon (Albany) finalised a $1 B CHIPS award backed by a further $1 B from IBM — superconducting-qubit wafers running, other modalities to follow (16 Sep 2026) [228] |
| Microsoft | topological (no qubit yet) | neutral atoms — sells Magne with Atom Computing | revenue comes from the hedge |
| AWS | cat qubits (Ocelot), dual-rail erasure | neutral atoms / ions / SC via Braket, QuEra co-design | hardware-efficient QEC as research, everything else as marketplace |
| NVIDIA | none | NVQLink + investments in Quantinuum, QuEra, Alice & Bob, others; open-source CUDA-Q Logical, an orchestration layer for fault-tolerant applications, with IQM, IonQ, Infleqtion, Quandela, Diraq and Quantum Motion among its partners (14 Sep 2026) [229] | the decoding/control layer is platform-agnostic |
| IonQ | trapped ions | electronic gates (Oxford Ionics) + foundry (SkyWater) + photonic networking (Lightsynq) | vertical integration, ion-only |
| D-Wave | annealing (revenue −67%) | dual-rail erasure SC (QCI, $550 M) | annealing is being abandoned as the growth story, though the CHIPS R&D award (Sep 2026) supports a 100,000-qubit annealer beside the 10,000-qubit gate-model system [91] |
| DARPA QBI Stage B (11) | atoms ×2, ions ×2, SC ×1, bosonic ×1, spin ×3, spin–photon ×1, photonic ×1 | Stage C: PsiQuantum, Microsoft (via US2QC) | Google, Rigetti, Alice & Bob, Oxford Ionics were not on the Nov-2025 list (DARPA: more teams may still enter) |
The pattern among the three that hold two families is the same: Google, IBM and Microsoft each pair one fast platform (superconducting, in some form) with one dense one (atoms or spins); IonQ and D-Wave stayed inside their own family. Nobody pairs two slow platforms. That is the market's estimate of §1.3: speed matters for G4, density for G3.
4Goals × technologies — fit matrix
●●● best fit · ●● good · ● marginal · ○ unsuitable. Left symbol = demonstrated (2026), right = credible trajectory (~2029) where different.
table
| Goal | Superconducting | Trapped ions | Neutral atoms | Bosonic SC | Photonic | Spin | Topological | Annealing |
|---|---|---|---|---|---|---|---|---|
| G1 Analogue / NISQ many-body physics | ●●● | ●● | ●●● | ○ | ● | ○ | ○ | ●● |
| G2 Error-mitigated utility (100–150 q) | ●●● | ●●● | ●● → ●●● | ○ | ● | ○ | ○ | ○ |
| G3 Early FT (102–103 logical) | ●● → ●●● | ●●● | ●●● | ● → ●● | ○ → ● | ○ → ● | ○ | ○ |
| G4 Large-scale FT (RSA-2048, FeMoco) | ●● → ●●● | ● | ● → ●● | ● → ●● | ○ → ●● | ○ → ●● | ○ → ? | ○ |
| G5 Heuristic optimisation | ● | ● | ● | ○ | ○ | ○ | ○ | ●● (contested) |
| G6 Networking / distributed QC | ● | ●●● | ●● | ● | ●●● | ●●● (defects) | ○ | ○ |
| G7 Deployable / on-prem / HPC-embedded | ●● | ●●● | ●●● | ● | ●● | ●● | ○ | ●● |
Why the cells are what they are.
- G1. Atoms (Aquila 256, 6,100-atom Cs, gauge-theory string breaking) and superconducting (Google's 69-q analogue-digital simulator, Quantinuum's digital magnetism on ions as the runner-up) are the instruments physicists actually use; annealers do genuine spin-glass dynamics but every "beyond classical" claim is under active erosion.
- G2. Superconducting wins on throughput (IBM Nighthawk: 5,000–7,500 2Q gates per circuit, 100 kHz-class shot rates; Q-CTRL 120 q with 104 gates) and ions win on per-shot quality (Helios; certified randomness) but lose on shots/s (~18/s at full width). The 2026 "advantage candidates" (IBM doped-Clifford — its 70-q instance simulated exactly in 37 min on 256 GPUs, Aug 2026 [47], and replaced by a 64-q one on ibm_boston, Sep 2026 [45], [46]; Qedma 74-q Floquet cross-checked on Helios; Google OTOC [230]–[233]) all live here.
- G3. This is the ions' and atoms' window: 48 corrected logical qubits today (Helios), 50 (Magne) in early 2027, ~100 (Sol) in 2027, >256 (Libra) in 2028 — all with transversal or high-rate codes that superconducting nearest-neighbour lattices cannot use. Superconducting reaches the same count only via qLDPC modules (Kookaburra → Starling 2029). Hubbard-class problems (∼105–106 Toffolis, hours at µs cycles) tolerate a slow clock: at 1 ms cycles they take days-to-weeks, which is acceptable.
- G4. Only the microsecond-class platforms can run 109–1010-Toffoli algorithms in days rather than decades. Superconducting is the only fast platform with demonstrated Λ; bosonic codes, photonics and spins are fast by design but have not shown a logical qubit (photonic, spin) or a working phase-flip budget (cats). Atoms can partially compensate through transversal architectures (19 M atoms, 5.6 days for RSA-2048 in one estimate) — plausible, unproven. Ions at 1–5 ms syndrome cycles with 104-qubit chips that do not yet exist cannot be placed above ● today; IonQ's own 256-bit elliptic-curve estimate needs 19,397 ions and 25.7 days per attempt at 6.7 ms per syndrome cycle (Sep 2026) [S] [112].
- G5. No platform has a credible optimisation advantage: Grover-type speedups offer no practical advantage on early fault-tolerant hardware, decoded quantum interferometry (DQI) gains on a contrived problem [234], [235], QAOA evidence is noiseless simulation ≤40 qubits. Annealing gets ●● only for being deployed and occasionally useful as a heuristic.
- G6. Photonics is the interconnect no matter who wins compute; ions (Oxford's distributed CZ) and defect spins (SiV over 35 km, T centres) are the demonstrated network nodes; atoms are joining (Atom Computing–Nu Quantum/Cisco; Infleqtion–Cisco research collaboration on neutral-atom quantum memory and optical transduction, Sep 2026 [236]); superconducting lacks a microwave-to-optical transducer of useful efficiency.
- G7. Room-temperature racks (AQT, IonQ Tempo, ORCA, Quandela), self-contained cryogenic racks with no dilution refrigerator (Equal1 RacQ: qubits at 0.3 K on an integrated closed-cycle cryocooler, 1,600 W [C] [237]) and <4 kW atom systems (Pasqal) versus dilution-refrigerator superconducting — though IQM's 26 systems sold (17 delivered, Sep 2026) [59] show on-prem superconducting is a real market.
5Most promising directions
Ranked by expected contribution to a utility-scale fault-tolerant computer by ~2033, weighting demonstrated physics ×2, scaling path ×1, roadmap credibility ×1. "Direction" is deliberately narrower than "platform": within each platform, one specific line of work carries the promise.
1. Superconducting transmons with engineered error structure, qLDPC codes and cold-stage control. The only platform with demonstrated Λ scaling in long memory, a microsecond clock, a 300 mm fab line, modular cryogenics, and a $10 B balance sheet behind a dated roadmap. The specific direction that matters is not "better transmons": it is (a) converting the error channel — dual-rail erasure (D-Wave/QCI, AWS), leakage removal, bias — so that the effective threshold rises 3–4×; (b) qLDPC memory modules (Kookaburra 2026 is the test); (c) real-time decoding and in-loop RL calibration (Google's 3.5× drift robustness); (d) moving control into the cold stage — cryo-CMOS (Google/Atlantic Quantum, HRL/IBM) or SFQ (SEEQC at millikelvin temperature, IBM–SEEQC under QBI) — because wiring and heat are one of the four limits on the count (§0 item 5, §8.4–8.6). Risks: Λ≈2 implies >103 physical per logical; readout at 10-2; no logical 2Q gate beyond d=3; no cross-module QEC.
2. Neutral atoms with zoned architectures, transversal/algorithmic fault tolerance, and erasure conversion. The best scaling "in the space dimension" (Hartmut Neven's phrase for qubit count, [2], [9]): thousands of atoms with second-scale coherence, all-to-all connectivity by transport, the richest logical-operation demonstrations (96 logical blocks, magic-state distillation, hundreds of teleportations), continuous reloading, and an erasure-convertible dominant error (loss). Google's new track, Microsoft/Atom's commercial machines, AWS–QuEra co-design and two QBI Stage-B slots make this the consensus second bet. The direction that matters: erasure-native isotopes (Yb, Sr), transversal + correlated decoding to amortise the millisecond cycle, high-rate qLDPC (rate >1/2 simulated at 10-13/round), and sub-ms imaging/transport. Risks: no sustained Λ>2 with reloading; the 103× clock gap; roadmaps have slipped two years at QuEra and Pasqal.
3. Trapped ions with laser-free electronic gates on 2D chip traps (and QCCD as the near-term product). Highest channel quality at scale (Helios) and the most convincing logical-qubit results today (48 corrected qubits at 10-4 logical gate error; a qLDPC memory at break-even within error bars, leakage post-selected, at IonQ). The direction with a real scaling story is Oxford Ionics'/IonQ's electronic gates at 8.4×10-5 without ground-state cooling on foundry chips — removing lasers, the historic scaling blocker — plus SkyWater as an in-house fab, and photonic interconnects. Quantinuum's Sol (2027) is the first product-scale 2D trap. Risks: speed (103–105× per layer), 75–97% post-selection in high-rate demos, interconnect rates 102× short, and IonQ's roadmap (2 M qubits by 2030) has no published 2D-heating or gate-time data.
4. Silicon/germanium spin qubits as the long-horizon manufacturability bet. The past year gave the CMOS argument its evidence: 2Q >99% on 300 mm imec wafers, HRL's self-sequenced d=5 repetition code (Λ=4.7) under a 4 K cryo-CMOS controller, 18-qubit arrays at identical voltages, spin shuttling at 99.5%, IBM's acquisition of HRL, and four of eleven QBI Stage-B slots. The ceiling (transistor density, under $1 per qubit) is the highest of any platform; the floor (no device >12 qubits with all-pairs 2Q data; readout-limited ~100 µs cycles) is the lowest of the top four. Direction: 2×N tileable cells with shuttling buses, cryo-CMOS co-integration, and isotopically purified 300 mm processes.
5. Photonics: certain as interconnect, high-variance as compute. Component metrics are superb (fusion 99.22%, foundry-scale SiN + BTO + SNSPDs, 300 mm), the money is real ($1 B, QBI Stage C V&V), and modularity for every other platform will run on photonic links. But no photonic logical qubit exists, loss is 10–25× above threshold, GKP squeezing is 9 dB short, and PsiQuantum's 2027 "useful" target is gone: its June 2026 release dates only the cryoplant (second half of 2027) and names no operating date, the demote trigger of §5.2 — the compute bet is demoted in this revision (October 2026). Treat as a 2030s option with a binary outcome; watch for the first multi-photon resource state / fusion network demonstration, which would move it two places up.
6. Bosonic codes (cats, GKP, dual-rail) — a direction, not a winner. The erasure half of this family (dual-rail transmons and cavities: 82–90% erasure fraction, 10-3 residual Pauli) is being absorbed by the superconducting mainstream and belongs in direction 1. The cat half has solved bit-flips (hours) and not phase-flips (10-1/cycle vs the 10-3 the resource estimates assume); until a bias-preserving cat–cat CNOT exists, the "100× fewer qubits" claim is a projection. GKP remains post-selected. Nord Quantique's QBI Stage-B slot is the one external validation.
7. Topological qubits — not a qubit yet. Long parity lifetimes in a better material are progress in materials science; without an X-measurement lifetime comparable to Z, a two-qubit operation, or independent replication, there is no basis to rank the platform. Microsoft's own commercial position (selling neutral atoms) is the tell.
8. Quantum annealing — commercially eroding. Classical belief-propagation tensor networks closed most of the 2025 gap; revenue fell 67% in H1 2026; the company bought a gate-model platform. Its one scientific result that classical methods have not fully reproduced — the 2025 spin-glass dynamics fit — belongs to G1, where analogue atom, ion and superconducting simulators now compete without the annealing form factor.
5.1 Cross-cutting directions (technology-agnostic value)
- Error-structure engineeringErasure conversion, noise bias, leakage removal: the one lever that raises thresholds 3–4× without touching gate physics. Every top-four platform now has an erasure programme.
- Real-time decoding and in-loop calibrationFPGA/GPU/on-chip decoders at <1 µs/round (Riverlane, IBM Relay-BP, IQM–Zurich Instruments <4 µs end-to-end [238], [239]), RL calibration during QEC (Google), self-sequencing controllers (HRL). At a millisecond cycle one CPU keeps up — so far in simulation: IonQ's end-to-end decoder on a single CPU (Apple M4 Max) handled workloads of up to 408 logical qubits (68 qLDPC memory blocks, 20 magic-state factories, up to 106 T gates), stretching the run by <0.3% at pCNOT=10-4 and <12% at 5×10-4 with 1–5 ms cycles assumed (preprint Aug 2026, announced 22 Sep 2026) [S] [111], [240]. NVIDIA's NVQLink makes this a platform-agnostic layer.
- qLDPC and transversal/algorithmic fault toleranceThe overhead reduction from ∼103 to ∼102 physical per logical qubit. qLDPC (bivariate bicycle) hardware runs: IonQ (eight codes on one 40-ion chain, bivariate bicycle up to [[30,4,5]]; break-even within error bars, with leakage post-selected, in one code the paper does not identify — not in the 4-logical-in-18-ion [[18,4,3]]) and Zhejiang ([[18,4,4]], not break-even). High-rate transversal block codes: Quantinuum and Harvard/QuEra (tesseract [[16,6,4]]). IBM's gross code is the 2026–27 test.
- Cold-stage control integrationCryo-CMOS or SFQ: wiring and heat load are one of the four limits on qubit count for superconducting and spin platforms (§0 item 5, §8.4–8.6); the largest wired system has 1,536 lines, so a 104 ceiling is a projection, not a measurement. 2026 delivered the first 4 K cryo-CMOS-sequenced QEC and peer-reviewed millikelvin SFQ single-qubit control.
- Photonic interconnectsFor every modular architecture; current rates (10–250 Bell pairs/s) are 102–104× short of logical clock rates.
5.2 Falsifiable watch-list for the next 12–18 months
table
| Direction | Milestone that would confirm | Milestone that would demote |
|---|---|---|
| Superconducting | sustained Λ≥3 at d≥9 with a logical 2Q gate; a gross-code memory on Kookaburra; cold-stage (cryo-CMOS or SFQ) control of ≥50 qubits; a benchmarked device above the 413 usable qubits the family has stood at since 2022 (§8.5, F1a) | Kookaburra slips again; readout stuck at 10-2; Google's next milestone missed |
| Neutral atoms | Λ>2 in a ≥100-round memory with reloading; Magne delivers 50 logical qubits; sub-ms QEC round; a gate-capable tweezer processor above 1,180 qubits (§8.5, F1b) | Libra slips past 2028; CZ plateau at 99.9% confirmed with no new gate scheme |
| Trapped ions | Sol at 192 q with electronic or ≥99.9% gates in 2D; IonQ 256-q chip at 99.99% commissioned; Λ-type scaling on any ion code | 256-q system slips beyond 2027; Sol heating/transport data disappoint |
| Bosonic | cat phase-flip ≤10-2/cycle at n̄≈10 with a bias-preserving CNOT; dual-rail 17-qubit system with logical error 2× below physical | Helium ships without logical data through 2027 |
| Photonic | a fusion network / multi-photon resource state beyond Bell pairs; loss within 10× of threshold | PsiQuantum 2027 target formally moved — met in June 2026 (no operating date; cryoplant 2H 2027), demoted October 2026; Stage C V&V negative |
| Spin | >20 qubits with all-pairs 2Q ≥99.5% on 300 mm; µs-class readout | Diraq's 2029 numbers revised down again |
| Topological | X-lifetime ≈ Z-lifetime; any two-qubit entanglement | none of the above by end-2027 |
| External | DARPA QBI Stage C selections (implied for late 2026 / early 2027; no official date); the DOE Quantum Genesis Q competition (launched 17 Sep 2026: up to $215 M for systems of at least 100 logical qubits running hundreds of millions of fault-tolerant operations, bonus pools at 150 and 200; applications due 19 Oct 2026) [241] — who enters, on what platform; Germany's Quantum Computing Competition (six consortia on superconducting, trapped-ion and neutral-atom platforms selected 22–23 Sep 2026, up to €640 M planned; working systems due 31 Mar 2027, a further selection after 30 months, at least two error-corrected machines by 2030) [127] — which platforms pass | — |
The forecast ledger of §8.5 dates each of these directions. One demote-trigger above is already partly met: Kookaburra is recorded in the register as announced but not delivered; and of the 65 roadmap shortfalls the register could evaluate, 49 quantify both deficits and in 48 of them the error deficit is the larger (§8.4, H6).
6Method, confidence, and where the sources disagree
- Method. Research in September 2026, brought to the announcements of 26 September 2026 — the data cut-off of the published edition 2026.09; the site carries the corrections and updates since then, to 15 October 2026, each listed in the changelog. Primary sources first: arXiv preprints, peer-reviewed journals, company newsrooms and roadmap pages, programme pages such as DARPA's; trade press served only to find them. When authors revise a result, the Atlas follows the latest version and dates it. Claims carry their standing: [D] demonstrated or published, [C] company claim without peer-reviewed data, [P] preprint, trade press or the author's own publication, [R] roadmap, [S] simulation or estimate, [G] established fact. Every number in §2–§3 carries a reference number into §9; the scores in §3.1 and the matrix in §4 are the author's judgment under the anchors of §1.2. What changed between editions is in the Editions table, not here.
- High confidence: numbers with a peer-reviewed paper behind them (physical and logical, for the groups named in §2–§3), programme rosters such as DARPA QBI's, and funding events taken from the primary release.
- Medium confidence: Alice & Bob hour-scale bit-flips (company-labelled preliminary, no paper); Nord Quantique tesseract result (press release only); Quantinuum's "near five-nines logical" claim (earnings call; the nearest public result is the Helix preprint — §6.1); IBM Heron r3 medians (dashboard snapshot); Origin Wukong-180 figures (company only); Infleqtion's 30 error-detected logical qubits (release and blog, paper pending, Sep 2026) [151].
- Quantum machines. The 184 quantum machines of §8 — gate-model processors, annealers, analogue simulators, boson samplers and testbeds, built, announced or planned — come from the Quantum Machines Register (data as of the cut-off), joined to the map technology by technology; each of the 2,006 joints carries its evidence — a paper, whitepaper or figure, or only a press page or an inference — and is verified (✅) when that source was opened and seen to show the technology in the machine, unverified (🔎) otherwise; every count in §8 states the verified share of the cells it rests on. Twenty-two machines have no verified cell and enter at that level.
- How to read an advantage or logical-qubit claim. The "advantage" claims of 2026 are all candidate claims explicitly open to classical challenge; certified randomness, cross-platform cross-checks (Qedma on Heron + Helios) and layer-fidelity-class metrics under full load are what separates a result from a press release. For logical qubits, Troyer and Nayak (Microsoft) with Martinis (QOLAB) propose four conditions of a scalable one: sustained by repeated error correction during computation; a fault-tolerant universal gate set with low-latency real-time decoding and feedback; a code family whose logical error falls predictably as qubits are added; a credible path to hundreds–thousands of copies (preprint, Sep 2026) [242] — by §3.2 no platform meets all four yet.
- The interactive map. What the map lights for any combination of architecture, technology, lens value and machine follows written rules; each build is checked against an independent implementation of those rules before it is published, and the rules are published in the repository.
- Known conflictsWhere two sources give two figures the paper prevails, and the blog or press figure is listed while it circulates: Helios SPAM 4.8×10-4 (arXiv) vs 3.3×10-4 (Nature); Ocelot d=3 1.72% (blog) vs 1.75% (paper); Google surface-code Λ 2.14 (paper) vs 2.31 (blog); Harvard 448-atom "2.14× below threshold" (Nature abstract) vs an early press summary of the arXiv version; Majorana 2 parity time "20 s mean" (Microsoft) vs "characteristic ~20 s" (paper) vs 22 ± 1 s (analysis); Diraq "thousands by 2029" (July 2026) vs "150 k by 2029" (August 2026); Magne's commissioning date — end-2026 in the 2025 announcements, "early 2027" on QuNorth's page and in the Sep-2026 facility news [164]; Quantinuum IPO valuation $14–17.6 B across sources.
6.1 What the sources did not confirm (as of 26 September 2026)
table
| Expectation | What the primary sources show | Standing |
|---|---|---|
| Google successor to Willow / multi-chip result | None published as of 26 September 2026: Google's Oct-2025 and Mar-2026 posts still describe Willow (105 q) as the current chip; the July-2026 QEC paper runs on Willow; no inter-fridge or multi-chip result [2], [9] | not found |
| Λ for the July-2026 record (7.72×10⁻⁴ at d=7) | Not reported: the paper (arXiv:2511.08493 → Nature 655, 879) gives the d=7 logical error rate (LER) with AlphaQubit 2, the d=5 colour-code LER 8.19×10⁻³, ~20% RL gain and 3.5× drift robustness, but no numeric Λ and no d=3/d=5 surface-code LERs [2], [9] | value not published |
| Kookaburra / Loon hardware in 2026 | Kookaburra not delivered; roadmap page still lists it for 2026; Loon 'demonstrates all key components' with no performance numbers; Nighthawk r2 expected at 25× Heron throughput (future tense); no gross-code hardware result [72]–[74] | not delivered yet |
| Fujitsu 1,000-qubit launch | Scheduled for fiscal 2026 (Apr 2026–Mar 2027) at Fujitsu Technology Park; no architecture or fidelity disclosed; not launched [75], [76] | not delivered yet |
| IQM / OQC in DARPA QBI | Neither appears on any DARPA Stage A/B roster nor in the 2026 selections of DARPA's follow-on programme QBIT [243]–[245] | not found |
| IonQ laser-gate durations, Tempo fidelities | Forte: MS gates 550–883 µs (median 672 µs), 1Q 110 µs, SPAM 0.5% [100], [101]; Tempo: '99.9% fidelity', #AQ 64 on a 64-qubit register in one chain (development system), no gate times; Oxford Ionics electronic gate 225.8 µs (2025), ≈120 µs (2024) [102] | answered |
| planqc 2025–26 metrics | No hardware-metric release since the Oct-2024 1,200-atom register; DLR 100-qubit system targeted spring 2027, LRZ 1,000-qubit (2×500) 'circa 2027' — a 1,000-qubit demonstrator reached TRL 5 and the first MAQCS hardware arrived at LRZ on 9 Sep 2026, operation by end-2027 [C] [161]; €2.3 M grant Mar 2026, no equity round [246], [247]; LOGIQC (ytterbium atoms) selected for Germany's Quantum Computing Competition, 22 Sep 2026 [G] [160] | slipped; hardware now arriving |
| Intel posture | Program alive without a roadmap: 12-qubit Tunnel Falls deployed at Argonne (Jan 2026), 'scale to hundreds of dots'; quantum page unchanged since Aug 2025; no successor chip, no exit statement [207] | answered |
| 18th QBI Stage-A company | DARPA's page still reads '17 of the 18 companies have been announced; one is still in negotiation'; the 18th has never been named. Stage A roster: 15 on 3 Apr 2025 + QuEra (29 Apr) + Google (9 Sep 2025); DARPA counts '20 companies evaluated' incl. Microsoft and PsiQuantum (US2QC) [243]–[245] | never named |
| Gidney RSA-2048 update in 2026 | No revision by Gidney/Ekerå; four other 2026 estimates: Pinnacle (qLDPC) < 100 k physical qubits [29]; Google ECDLP-256 < 0.5 M qubits in minutes [28]; neutral-atom Shor with ~10⁴–2.6×10⁴ reconfigurable atoms (P-256 in days, RSA-2048 1–2 orders longer) [30], [31]; IonQ trapped-ion secp256k1 (256-bit elliptic curve): 19,397 ions, ~1,450 logical, 25.7 days per attempt (Sep 2026) [112] | superseded by four papers |
| DARPA QBI Stage C selections | None as of 26 September 2026 beyond the two US2QC performers (PsiQuantum, Microsoft). Stage B is 'yearlong' from Nov 2025; DARPA's 2025 Q&A gives Stage B ≈ 12 months and Stage C ≈ 36 months, implying decisions in late 2026 / early 2027; no official date [243]–[245] | not delivered yet |
| Quantinuum 'near five-nines logical' paper | No preprint is named as its basis; the Q2-2026 release restates the claim and gives Helios 2Q 99.921% [123], [124]; the nearest public result is Helix (preprint, Sep 2026): 4.6×10-5 per logical qubit per QEC cycle (≈99.995%) in the new [[20,2,6]] C₄-Helix code, logical two-qubit Clifford 2.8×10-4 [5] | company claim; a matching preprint, link unconfirmed |
7The technology graph — nodes, attributes, edges, and what the graph says on its own
7.1 Construction rules
Nodes are technologies, not platforms. A technology enters the graph if it is self-contained (replaceable without touching the rest of the stack) and principled (its replacement shifts at least one of the four outputs — error channel, clock, count-with-quality, scaling path — by an order of magnitude). A platform is an architecture: one technology per layer through the ten layers — the stack, read from the qubit up: carrier → encoding → gate mechanism → connectivity/transport → control → readout → code → decoder → interconnect → manufacturing. Where an architecture uses more than one technology in a layer, the one it is defined by — its typical choice — is the primary and is drawn on its line; the others are its alternates (§7.3).
Seven attributes per node (design space, stable):
- (a) carrier-nature affinity on the natural ↔ fabricated spectrum (photon = natural particle in engineered modes; donor/defect = intermediate; carrier-agnostic = neutral);
- (b) the characteristic time the node imposes (log-scale) with the entangling flag deterministic / probabilistic-heralded;
- (c) measurement mechanism with time bound, destructiveness and mid-circuit capability;
- (d) mobility/connectivity mechanism;
- (e) control modality and placement (temperature stage: room temperature / 4 K / millikelvin; a node may carry several, the first being primary);
- (f) dominant error structure as the code sees it;
- (g) manufacturing technology.
An attribute is a property that does not move as records improve; anything that moves with records (fidelity, Λ, counts, cycle times, QBI stage, funding) is an evaluation-space attribute — dated, sourced, attached to the node, never used for position. Actors and goals are annotations on architectures.
Four edge types: requires/provides (a dependency, read in the supply direction — B is needed by A — with the arrowhead at A, the technology that needs B; a dependency is hard (A cannot exist without B) or soft (B is the usual route), and B may be one of a group of technologies any of which would do; each dependency has a kind — acts on the carrier, fabrication route, signal delivery, readout apparatus, measurement or heralding, the code's connectivity need, decoder ↔ code, a particular encoding, built from other operations, part of or a refinement — see §7.8), alternatives (two technologies that can fill the same slot of a layer; the relation is symmetric and does not mean exclusion — a platform may combine both across modules or hierarchy levels, e.g. surface-code processing with gross-code memory), conflicts (the two work together only with a mitigating element or a change in a third layer; every conflict edge carries the mechanism, the measured price, the mitigation, a status — open / mitigated / bypassed — and a dated source, see §7.8), defines (node → one of the four outputs, each carrying a source, a date and a number).
Clock is not an attribute. Per architecture it is derived as the length of one syndrome-extraction round, t_round = d₂·(t_2Q + t_move) + d₁·t_1Q + t_meas + t_reset, where d₂ and d₁ are the two- and one-qubit gate layers of the architecture's code (from the code node), t_2Q and t_meas come from the gate and readout attributes, t_1Q, t_move (transport between gate layers, mobile platforms only) and t_reset from standard records; the measured QEC cycle is shown next to it as a check. Two further clocks are derived from the same records: the reaction time (measurement → conditioned operation; the published loop where one exists, else readout + decode latency as a floor) and operations per coherence T2/t_2Q, with the idle exposure per round t_round/T2 compared against the measured idle error.
Crossing test (the map's own term). Along the natural–fabricated axis, attributes correlate: natural carriers default to optical room-temperature control, transport connectivity, loss-type errors, slow fluorescence readout, optical/MEMS assembly; fabricated carriers default to microwave/electrical room-temperature control, static nearest-neighbour wiring, Pauli/leakage errors, fast dispersive/charge readout, lithography. A technology is a crossing technology — hatched on the map — when, in the architecture that uses it, it breaks that correlation: natural carrier + microwave control; fabricated + far connectivity; fabricated + erasure; fabricated + cold-stage control or decoding; solid-state carrier + photonic interconnect; natural + sub-µs gate; natural + ≤ 30 µs readout; natural + semiconductor/photonic-chip fabrication. Empty slots are nodes with no demonstrated technology, or architecture slots with nothing in them.
7.2 Node table (110 technologies × 7 attributes)
Show table
| # | Layer | Technology | (a) carrier affinity | (b) time · entangling | (c) readout | (d) mobility | (e) control · placement | (f) error structure | (g) manufacturing | status · since |
|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 1 Qubit carrier | Bosonic cavity mode cavity |
fabricated | 316 ns; deterministic | dispersive microwave; 1 µs; destructive=no; mid-circuit=yes | shared bus (motional / cavity) | microwave @ room temperature | loss (erasure), biased | 3D machined cavities | demonstrated · 2013 |
| 2 | 1 Qubit carrier | Fluxonium fluxonium |
fabricated | 50.1 ns; deterministic | dispersive microwave; 316 ns; destructive=no; mid-circuit=yes | static nearest-neighbour wiring | low-frequency electrical @ room temperature | stochastic Pauli, coherent / calibration | superconducting lithography | demonstrated · 2009 |
| 3 | 1 Qubit carrier | rf-SQUID flux qubit (annealer) fluxq |
fabricated | 3.16 ns; n/a | dispersive microwave; 1 µs; destructive=no; mid-circuit=no | long-range static couplers | low-frequency electrical @ millikelvin stage | stochastic Pauli, coherent / calibration | superconducting lithography | demonstrated · 2011 |
| 4 | 1 Qubit carrier | Majorana parity (InAs–Pb tetron) majorana |
fabricated | 1 µs; deterministic | rf quantum capacitance (parity); 100 µs; destructive=no; mid-circuit=yes | static nearest-neighbour wiring | low-frequency electrical @ room temperature | unknown / contested | III-V MBE heterostructures | emerging · 2025 |
| 5 | 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) qd_spin |
fabricated | 50.1 ns; deterministic | spin-to-charge + rf reflectometry; 6.31 µs; destructive=no; mid-circuit=yes | static nearest-neighbour wiring | low-frequency electrical @ room temperature | coherent / calibration, stochastic Pauli, leakage | CMOS foundry 300 mm | demonstrated · 2012 |
| 6 | 1 Qubit carrier | Transmon transmon |
fabricated | 10 ns; deterministic | dispersive microwave; 316 ns; destructive=no; mid-circuit=yes | static nearest-neighbour wiring | microwave @ room temperature | leakage, stochastic Pauli, correlated bursts, coherent / calibration | superconducting lithography | demonstrated · 2007 |
| 7 | 1 Qubit carrier | Colour-centre / defect spin (NV, SiV, SnV, T centre) defect |
intermediate / carrier-agnostic | 1 µs; deterministic | fluorescence (PMT/SNSPD); 100 µs; destructive=no; mid-circuit=yes | flying qubits (photons) | optical @ room temperature | stochastic Pauli, loss (erasure) | diamond growth / implantation | demonstrated · 2004 |
| 8 | 1 Qubit carrier | Donor spin (P in ²⁸Si) donor |
intermediate / carrier-agnostic | 1 µs; deterministic | spin-to-charge + rf reflectometry; 10 µs; destructive=no; mid-circuit=yes | static nearest-neighbour wiring | low-frequency electrical @ room temperature | stochastic Pauli | STM hydrogen-resist lithography | demonstrated · 2012 |
| 9 | 1 Qubit carrier | Single photon (discrete variable) photon |
photon (natural particle, engineered modes) | 100 ns; probabilistic / heralded | single-photon detection; 10 ns; destructive=yes; mid-circuit=no | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | demonstrated · 2001 |
| 10 | 1 Qubit carrier | Squeezed light mode (CV) squeezed |
photon (natural particle, engineered modes) | 1 µs; probabilistic / heralded | single-photon detection; 10 ns; destructive=yes; mid-circuit=no | flying qubits (photons) | electro-optic @ room temperature | Gaussian (small-shift), loss (erasure) | photonic IC foundry | demonstrated · 2012 |
| 11 | 1 Qubit carrier | Alkaline-earth(-like) atom (Yb/Sr) — erasure-native ae_atom |
natural | 251 ns; deterministic | fluorescence imaging (camera); 501 µs; destructive=no; mid-circuit=yes | physical transport | optical @ room temperature | erasure-convertible, loss (erasure) | optical / mechanical assembly | demonstrated · 2019 |
| 12 | 1 Qubit carrier | Alkali atom (Rb/Cs) in optical tweezers alkali |
natural | 251 ns; deterministic | fluorescence imaging (camera); 501 µs; destructive=no; mid-circuit=yes | physical transport | optical @ room temperature | loss (erasure), leakage, coherent / calibration | optical / mechanical assembly | demonstrated · 2016 |
| 13 | 1 Qubit carrier | Trapped atomic ion ion |
natural | 63.1 µs; deterministic | fluorescence (PMT/SNSPD); 10 µs; destructive=no; mid-circuit=yes | physical transport | optical @ room temperature | coherent / calibration, leakage, stochastic Pauli | MEMS / surface-electrode traps | demonstrated · 1995 |
| 14 | 2 Encoding | Bare physical qubit (no encoding) enc_bare |
fabricated | — | — | — | — | leakage | — | demonstrated · 2007 |
| 15 | 2 Encoding | Cat-code encoding (biased noise) enc_cat |
fabricated | — | — | — | — | biased | — | demonstrated · 2020 |
| 16 | 2 Encoding | Exchange-only / singlet–triplet spin encoding enc_eo |
fabricated | — | — | — | — | leakage, coherent / calibration | — | demonstrated · 2013 |
| 17 | 2 Encoding | Fermion-parity encoding (tetron) enc_parity |
fabricated | — | — | — | — | unknown / contested | — | theory / design only · 2025 |
| 18 | 2 Encoding | GKP grid encoding enc_gkp |
hybrid (fabricated host) | — | — | — | — | Gaussian (small-shift) | — | emerging · 2020 |
| 19 | 2 Encoding | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding enc_spin_ld |
hybrid (fabricated host) | — | — | — | — | coherent / calibration, stochastic Pauli | — | demonstrated · 1998 |
| 20 | 2 Encoding | Dual-rail (erasure) encoding enc_dualrail |
photon (natural particle, engineered modes) | — | — | — | — | erasure-convertible | — | demonstrated · 2023 |
| 21 | 2 Encoding | Time-bin / path photonic encoding enc_timebin |
photon (natural particle, engineered modes) | — | — | — | — | loss (erasure) | — | demonstrated · 1999 |
| 22 | 2 Encoding | Ground–Rydberg analogue qubit enc_gr |
natural | — | — | — | — | loss (erasure), coherent / calibration | — | demonstrated · 2017 |
| 23 | 2 Encoding | Hyperfine / clock-state qubit enc_hf |
natural | — | — | — | — | stochastic Pauli, leakage | — | demonstrated · 1995 |
| 24 | 2 Encoding | Metastable ('omg') erasure encoding enc_omg |
natural | — | — | — | — | erasure-convertible | — | emerging · 2023 |
| 25 | 2 Encoding | Optical narrow-line qubit (ion S–D, atom clock) enc_opt |
natural | — | — | — | — | stochastic Pauli, leakage | — | demonstrated · 2003 |
| 26 | 3 Gate mechanism | Quantum annealing (analogue evolution) g_anneal |
fabricated | 3.98 ns; n/a | — | long-range static couplers | low-frequency electrical @ millikelvin stage | coherent / calibration, stochastic Pauli | superconducting lithography | demonstrated · 2011 |
| 27 | 3 Gate mechanism | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) g_bos |
fabricated | 501 ns; deterministic | — | shared bus (motional / cavity) | microwave @ room temperature | erasure-convertible, biased, stochastic Pauli | 3D machined cavities | demonstrated · 2018 |
| 28 | 3 Gate mechanism | Bias-preserving cat–cat CNOT g_catcnot |
fabricated | —; deterministic | — | shared bus (motional / cavity) | microwave @ room temperature | biased | superconducting lithography | empty slot — no technology yet · |
| 29 | 3 Gate mechanism | Cross-resonance (fixed-frequency, all-microwave) g_cr |
fabricated | 316 ns; deterministic | — | static nearest-neighbour wiring | microwave @ room temperature | coherent / calibration, stochastic Pauli | superconducting lithography | demonstrated · 2011 |
| 30 | 3 Gate mechanism | Electronic microwave gate (ions, laser-free: near-field or static gradient) g_elec |
fabricated | 200 µs; deterministic | — | shared bus (motional / cavity) | microwave @ room temperature | stochastic Pauli, coherent / calibration | MEMS / surface-electrode traps | demonstrated · 2024 |
| 31 | 3 Gate mechanism | Exchange gate (spins; incl. shuttled-spin CZ) g_exch |
fabricated | 100 ns; deterministic | — | static nearest-neighbour wiring | low-frequency electrical @ room temperature | coherent / calibration, stochastic Pauli, leakage | CMOS foundry 300 mm | demonstrated · 2018 |
| 32 | 3 Gate mechanism | Measurement-based Majorana gate g_mbq |
fabricated | —; deterministic | — | static nearest-neighbour wiring | low-frequency electrical @ room temperature | unknown / contested | III-V MBE heterostructures | empty slot — no technology yet · |
| 33 | 3 Gate mechanism | Tunable-coupler CZ / iSWAP g_tc |
fabricated | 39.8 ns; deterministic | — | static nearest-neighbour wiring | microwave @ room temperature | coherent / calibration, leakage, stochastic Pauli | superconducting lithography | demonstrated · 2014 |
| 34 | 3 Gate mechanism | Microwave / optical spin gates (defect centres, 1Q spins) g_mwspin |
intermediate / carrier-agnostic | 1 µs; deterministic | — | static nearest-neighbour wiring | microwave @ room temperature | stochastic Pauli, coherent / calibration | diamond growth / implantation | demonstrated · 2004 |
| 35 | 3 Gate mechanism | CV Gaussian gates + GKP-assisted non-Gaussian operations g_cv |
photon (natural particle, engineered modes) | 1 µs; deterministic | — | flying qubits (photons) | electro-optic @ room temperature | Gaussian (small-shift), loss (erasure) | photonic IC foundry | demonstrated · 2020 |
| 36 | 3 Gate mechanism | Linear-optical fusion (heralded) g_fusion |
photon (natural particle, engineered modes) | 100 ns; probabilistic / heralded | — | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | demonstrated · 2005 |
| 37 | 3 Gate mechanism | Programmable linear-optical interferometer (no entangling primitive) g_lointer |
photon (natural particle, engineered modes) | — | — | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | optical / mechanical assembly | demonstrated · 2020 |
| 38 | 3 Gate mechanism | Multi-photon resource-state generator (RSG; 6-ring etc.) src_resource |
photon (natural particle, engineered modes) | —; probabilistic / heralded | — | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | empty slot — no technology yet · |
| 39 | 3 Gate mechanism | Mølmer–Sørensen / light-shift laser gate g_ms |
natural | 63.1 µs; deterministic | — | shared bus (motional / cavity) | optical @ room temperature | coherent / calibration, leakage, stochastic Pauli | optical / mechanical assembly | demonstrated · 2003 |
| 40 | 3 Gate mechanism | Rydberg-blockade CZ g_ryd |
natural | 251 ns; deterministic | — | physical transport | optical @ room temperature | loss (erasure), leakage, coherent / calibration | optical / mechanical assembly | demonstrated · 2010 |
| 41 | 3 Gate mechanism | Analogue Rydberg Hamiltonian evolution g_rydanalog |
natural | — | — | — | optical @ room temperature | coherent / calibration, loss (erasure) | optical / mechanical assembly | demonstrated · 2017 |
| 42 | 4 Connectivity / transport | Crossbar shared-line control (spins) cx_crossbar |
fabricated | — | — | shared-line crossbar | low-frequency electrical @ room temperature | coherent / calibration | CMOS foundry 300 mm | emerging · 2023 |
| 43 | 4 Connectivity / transport | Long-range on-chip couplers (c-couplers, mm-scale) cx_lr |
fabricated | — | — | long-range static couplers | — | coherent / calibration | superconducting lithography | emerging · 2023 |
| 44 | 4 Connectivity / transport | Static nearest-neighbour lattice cx_nn |
fabricated | — | — | static nearest-neighbour wiring | — | coherent / calibration | superconducting lithography | demonstrated · 2014 |
| 45 | 4 Connectivity / transport | Spin shuttling (conveyor mode) cx_shuttle |
fabricated | 200 ns; n/a | — | physical transport | — | coherent / calibration | CMOS foundry 300 mm | emerging · 2025 |
| 46 | 4 Connectivity / transport | Photonic switching / routing (electro-optic, feed-forward) cx_switch |
photon (natural particle, engineered modes) | 1 µs; n/a | — | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | demonstrated · 2015 |
| 47 | 4 Connectivity / transport | Atom transport by AOD tweezers (zoned architecture) cx_aod |
natural | 1 ms; n/a | — | physical transport | — | loss (erasure) | optical / mechanical assembly | demonstrated · 2022 |
| 48 | 4 Connectivity / transport | Ion-chain motional bus (all-to-all in chain) cx_bus |
natural | — | — | shared bus (motional / cavity) | — | coherent / calibration | MEMS / surface-electrode traps | demonstrated · 2003 |
| 49 | 4 Connectivity / transport | Ion shuttling (QCCD, junctions, grid traps) cx_qccd |
natural | 2 ms; n/a | — | physical transport | — | coherent / calibration | MEMS / surface-electrode traps | demonstrated · 2002 |
| 50 | 4 Connectivity / transport | Continuous atom reloading (reservoir + optical conveyor belt) cx_reload |
natural | 79.4 ms; n/a | — | physical transport | optical @ room temperature | loss (erasure) | optical / mechanical assembly | demonstrated · 2024 |
| 51 | 5 Control | Baseband electrical control (spins, Majorana) ct_base |
fabricated | — | — | — | low-frequency electrical @ room temperature | coherent / calibration | CMOS foundry 300 mm | demonstrated · 2012 |
| 52 | 5 Control | Cryo-CMOS controller (4 K / mK) ct_cryocmos |
fabricated | — | — | — | microwave @ 4 K stage / millikelvin stage | coherent / calibration | CMOS foundry 300 mm | demonstrated · 2024 |
| 53 | 5 Control | On-chip flux-DAC multiplexing ct_fluxdac |
fabricated | — | — | — | low-frequency electrical @ millikelvin stage | coherent / calibration | superconducting lithography | demonstrated · 2026 |
| 54 | 5 Control | Chip-integrated microwave control (ions) ct_ionmw |
fabricated | — | — | — | microwave @ room temperature | stochastic Pauli | MEMS / surface-electrode traps | demonstrated · 2024 |
| 55 | 5 Control | Room-temperature electronics + per-qubit coax/flex ct_rt |
fabricated | — | — | — | microwave @ room temperature | coherent / calibration | superconducting lithography | demonstrated · 2007 |
| 56 | 5 Control | SFQ digital control (4 K / mK) ct_sfq |
fabricated | — | — | — | microwave @ 4 K stage / millikelvin stage | stochastic Pauli | superconducting lithography | emerging · 2026 |
| 57 | 5 Control | Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring ct_vio |
fabricated | — | — | — | microwave @ room temperature | coherent / calibration | superconducting lithography | demonstrated · 2016 |
| 58 | 5 Control | Electro-optic drive + feed-forward electronics (room temperature) ct_eo |
photon (natural particle, engineered modes) | — | — | — | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | demonstrated · 2020 |
| 59 | 5 Control | PIC-generated tweezers / integrated optics for atoms ct_pic_trap |
photon (natural particle, engineered modes) | — | — | — | optical @ room temperature | coherent / calibration | photonic IC foundry | emerging · 2026 |
| 60 | 5 Control | Free-space laser addressing of ions (AOM/AOD beams) ct_ionaod |
natural | — | — | — | optical @ room temperature | coherent / calibration | optical / mechanical assembly | demonstrated · 2016 |
| 61 | 5 Control | Laser control with integrated photonics (ions) ct_ionlaser |
natural | — | — | — | optical @ room temperature | coherent / calibration | photonic IC foundry | demonstrated · 2020 |
| 62 | 5 Control | Laser + AOD/SLM optical control (atoms) ct_laser |
natural | — | — | — | optical @ room temperature | coherent / calibration | optical / mechanical assembly | demonstrated · 2016 |
| 63 | 6 Readout | Dispersive microwave readout (+TWPA, Purcell) ro_disp |
fabricated | — | dispersive microwave; 282 ns; destructive=no; mid-circuit=yes | — | microwave @ room temperature | leakage | superconducting lithography | demonstrated · 2005 |
| 64 | 6 Readout | Flux readout via QFP / SQUID shift registers (annealers) ro_fluxro |
fabricated | — | flux latch (QFP/SQUID); 100 µs; destructive=yes; mid-circuit=no | — | low-frequency electrical @ millikelvin stage | stochastic Pauli | superconducting lithography | demonstrated · 2011 |
| 65 | 6 Readout | rf quantum-capacitance parity readout ro_qcap |
fabricated | — | rf quantum capacitance (parity); 100 µs; destructive=no; mid-circuit=yes | — | low-frequency electrical @ room temperature | unknown / contested | III-V MBE heterostructures | emerging · 2025 |
| 66 | 6 Readout | Fast unconditional / dissipative qubit reset ro_reset |
fabricated | — | — | — | microwave @ room temperature | leakage | superconducting lithography | demonstrated · 2018 |
| 67 | 6 Readout | Spin-to-charge conversion + rf reflectometry ro_s2c |
fabricated | — | spin-to-charge + rf reflectometry; 6.31 µs; destructive=no; mid-circuit=yes | — | low-frequency electrical @ room temperature | coherent / calibration | CMOS foundry 300 mm | demonstrated · 2004 |
| 68 | 6 Readout | Mid-circuit erasure check ro_erasure |
intermediate / carrier-agnostic | — | ancilla erasure check; 398 ns; destructive=no; mid-circuit=yes | — | microwave @ room temperature | erasure-convertible | — | demonstrated · 2023 |
| 69 | 6 Readout | Homodyne quadrature detection (CV) ro_homodyne |
photon (natural particle, engineered modes) | — | homodyne detection (quadrature); 1 µs; destructive=yes; mid-circuit=yes | — | electro-optic @ room temperature | Gaussian (small-shift) | photonic IC foundry | demonstrated · 2012 |
| 70 | 6 Readout | Single-photon detection (SNSPD / TES) ro_spd |
photon (natural particle, engineered modes) | — | single-photon detection; 10 ns; destructive=yes; mid-circuit=no | — | electro-optic @ 4 K stage | loss (erasure) | photonic IC foundry | demonstrated · 2001 |
| 71 | 6 Readout | Fluorescence state detection (ions, defects) ro_fluor |
natural | — | fluorescence (PMT/SNSPD); 100 µs; destructive=no; mid-circuit=yes | — | optical @ room temperature | stochastic Pauli | optical / mechanical assembly | demonstrated · 1995 |
| 72 | 6 Readout | Fluorescence imaging of atom arrays ro_img |
natural | — | fluorescence imaging (camera); 501 µs; destructive=no; mid-circuit=yes | — | optical @ room temperature | loss (erasure) | optical / mechanical assembly | demonstrated · 2016 |
| 73 | 7 Code | Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) code_bosonic |
hybrid (fabricated host) | — | — | static nearest-neighbour wiring | — | biased, Gaussian (small-shift) | — | emerging · 2024 |
| 74 | 7 Code | Colour code (transversal Cliffords) code_color |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | stochastic Pauli | — | demonstrated · 2024 |
| 75 | 7 Code | Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) code_detect |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | stochastic Pauli | — | demonstrated · 2017 |
| 76 | 7 Code | Erasure-adapted codes code_erasure |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | erasure-convertible | — | emerging · 2025 |
| 77 | 7 Code | Magic-state factory (cultivation / distillation / code switching) code_magic |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | stochastic Pauli | — | demonstrated · 2025 |
| 78 | 7 Code | Error mitigation in the code slot (ZNE, PEC) — not a code code_mitig |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | stochastic Pauli | — | demonstrated · 2017 |
| 79 | 7 Code | Non-local qLDPC codes (bivariate bicycle, 'gross') code_qldpc |
intermediate / carrier-agnostic | — | — | long-range static couplers | — | stochastic Pauli | — | emerging · 2025 |
| 80 | 7 Code | Rotated surface code (+ yoked variants) code_surface |
intermediate / carrier-agnostic | — | — | static nearest-neighbour wiring | — | stochastic Pauli | — | demonstrated · 2023 |
| 81 | 7 Code | Fusion-based fault tolerance code_fusion |
photon (natural particle, engineered modes) | — | — | flying qubits (photons) | — | loss (erasure) | — | theory / design only · |
| 82 | 7 Code | Algorithmic FT / transversal architectures code_aft |
natural | — | — | physical transport | — | stochastic Pauli | — | emerging · 2025 |
| 83 | 7 Code | High-rate concatenated codes with transversal gates code_highrate |
natural | — | — | physical transport | — | stochastic Pauli | — | demonstrated · 2024 |
| 84 | 8 Decoder | Cryogenic / on-chip decoder (cryo-CMOS, SFQ) dec_cryo |
fabricated | — | — | — | microwave @ millikelvin stage | stochastic Pauli | superconducting lithography | empty slot — no technology yet · |
| 85 | 8 Decoder | In-loop RL calibration / control steering dec_rl |
fabricated | — | — | — | — | coherent / calibration | — | demonstrated · 2026 |
| 86 | 8 Decoder | FPGA real-time decoders (LCD, Deltaflow) dec_fpga |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | — | demonstrated · 2025 |
| 87 | 8 Decoder | GPU decoding via NVQLink dec_gpu |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | — | demonstrated · 2025 |
| 88 | 8 Decoder | MWPM / Sparse Blossom (+ correlated matching) dec_mwpm |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | — | demonstrated · 2015 |
| 89 | 8 Decoder | Neural decoders (AlphaQubit 2, CNN, transformers) dec_nn |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | — | demonstrated · 2024 |
| 90 | 8 Decoder | Relay-BP for qLDPC (FPGA) dec_relaybp |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | — | demonstrated · 2025 |
| 91 | 8 Decoder | Correlated / loss-aware decoding (transversal, atom loss) dec_corr |
natural | — | — | — | — | loss (erasure), erasure-convertible | — | demonstrated · 2025 |
| 92 | 9 Interconnect | Cryogenic microwave link between refrigerators ic_cryolink |
fabricated | — | — | long-range static couplers | microwave @ millikelvin stage | loss (erasure), coherent / calibration | superconducting lithography | emerging · 2020 |
| 93 | 9 Interconnect | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) ic_fanout |
fabricated | — | — | static nearest-neighbour wiring | low-frequency electrical @ 4 K stage / millikelvin stage | coherent / calibration | CMOS foundry 300 mm | emerging · 2025 |
| 94 | 9 Interconnect | Multi-chip modules / l-couplers (same cryostat) ic_mcm |
fabricated | — | — | long-range static couplers | microwave @ millikelvin stage | coherent / calibration | superconducting lithography | emerging · 2025 |
| 95 | 9 Interconnect | Multi-die packaging in one module (flip-chip, bump-bonded control die) ic_multidie |
fabricated | — | — | static nearest-neighbour wiring | microwave @ millikelvin stage | coherent / calibration | superconducting lithography | demonstrated · 2017 |
| 96 | 9 Interconnect | Microwave–optical transducer (useful efficiency) ic_transducer |
fabricated | — | — | flying qubits (photons) | electro-optic @ millikelvin stage | loss (erasure) | photonic IC foundry | empty slot — no technology yet · |
| 97 | 9 Interconnect | Spin–photon solid-state link (SiV, NV, T centre) ic_spinphoton |
intermediate / carrier-agnostic | — | — | flying qubits (photons) | optical @ room temperature | loss (erasure) | diamond growth / implantation | demonstrated · 2013 |
| 98 | 9 Interconnect | Fibre links between photonic modules ic_fibre |
photon (natural particle, engineered modes) | — | — | flying qubits (photons) | electro-optic @ room temperature | loss (erasure) | photonic IC foundry | demonstrated · 2025 |
| 99 | 9 Interconnect | Atom–photon cavity interface ic_atomcavity |
natural | — | — | flying qubits (photons) | optical @ room temperature | loss (erasure) | optical / mechanical assembly | emerging · 2024 |
| 100 | 9 Interconnect | Ion–photon link ic_ionphoton |
natural | — | — | flying qubits (photons) | optical @ room temperature | loss (erasure) | optical / mechanical assembly | demonstrated · 2007 |
| 101 | 10 Manufacturing | 3D machined superconducting cavities fab_3d |
fabricated | — | — | — | — | loss (erasure) | 3D machined cavities | demonstrated · 2013 |
| 102 | 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) fab_cmos |
fabricated | — | — | — | — | coherent / calibration | CMOS foundry 300 mm | demonstrated · 2022 |
| 103 | 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) fab_sc |
fabricated | — | — | — | — | coherent / calibration | superconducting lithography | demonstrated · 2007 |
| 104 | 10 Manufacturing | III-V MBE heterostructures (InAs–Pb wires, QD sources) fab_mbe |
hybrid (fabricated host) | — | — | — | — | unknown / contested | III-V MBE heterostructures | demonstrated · 2015 |
| 105 | 10 Manufacturing | Diamond growth / implantation (NV, SiV, SnV) fab_diamond |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | diamond growth / implantation | demonstrated · 2010 |
| 106 | 10 Manufacturing | STM hydrogen-resist lithography (donors) fab_stm |
intermediate / carrier-agnostic | — | — | — | — | stochastic Pauli | STM hydrogen-resist lithography | demonstrated · 2012 |
| 107 | 10 Manufacturing | Bulk-optics and fibre assembly (photonic samplers) fab_bulk |
photon (natural particle, engineered modes) | — | — | — | — | loss (erasure) | optical / mechanical assembly | demonstrated · 2020 |
| 108 | 10 Manufacturing | Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) fab_pic |
photon (natural particle, engineered modes) | — | — | — | — | loss (erasure) | photonic IC foundry | demonstrated · 2015 |
| 109 | 10 Manufacturing | Optical / mechanical assembly (lasers, vacuum, objectives) fab_optics |
natural | — | — | — | — | coherent / calibration | optical / mechanical assembly | demonstrated · 2016 |
| 110 | 10 Manufacturing | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) fab_trap |
natural | — | — | — | — | coherent / calibration | MEMS / surface-electrode traps | demonstrated · 2006 |
7.3 Architectures layer by layer — the technology each one uses in each of the ten layers (alternates in brackets)
Each row is an architecture, each column one of the ten layers of §7.1. The cell names the technology the architecture's line passes through on the map — its primary technology for that layer, the typical choice the architecture is defined by — and, in brackets, its alternates: technologies the same architecture also uses, or has used, in that layer (the half-tone squares of the map). ∅ is a layer the architecture has no technology for (§7.6 lists these empty slots); ✗ marks a technology that is itself an empty slot — a name for something no one has built yet.
table
| Architecture | 1 Qubit carrier | 2 Encoding | 3 Gate mechanism | 4 Connectivity / transport | 5 Control | 6 Readout | 7 Code | 8 Decoder | 9 Interconnect | 10 Manufacturing |
|---|---|---|---|---|---|---|---|---|---|---|
| Transmon lattice with tunable couplers — IBM (Heron, Nighthawk), Google (Willow), Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu/RIKEN, QuantWare | Transmon (Fluxonium) | Bare physical qubit (no encoding) | Tunable-coupler CZ / iSWAP (Cross-resonance (fixed-frequency, all-microwave)) | Static nearest-neighbour lattice (Long-range on-chip couplers (c-couplers, mm-scale)) | Room-temperature electronics + per-qubit coax/flex (Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring; Cryo-CMOS controller (4 K / mK); SFQ digital control (4 K / mK)) | Dispersive microwave readout (+TWPA, Purcell) (Fast unconditional / dissipative qubit reset) | Rotated surface code (+ yoked variants) (Colour code (transversal Cliffords); Non-local qLDPC codes (bivariate bicycle, 'gross'); Magic-state factory (cultivation / distillation / code switching); Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime); Error mitigation in the code slot (ZNE, PEC) — not a code) | Neural decoders (AlphaQubit 2, CNN, transformers) (MWPM / Sparse Blossom (+ correlated matching); FPGA real-time decoders (LCD, Deltaflow); Relay-BP for qLDPC (FPGA); In-loop RL calibration / control steering; GPU decoding via NVQLink; Cryogenic / on-chip decoder (cryo-CMOS, SFQ)) | Multi-chip modules / l-couplers (same cryostat) (Multi-die packaging in one module (flip-chip, bump-bonded control die); Cryogenic microwave link between refrigerators; Microwave–optical transducer (useful efficiency)) | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) (300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)) |
| Bosonic cavity qubits — cat and GKP — Alice & Bob, AWS, Nord Quantique | Bosonic cavity mode | Cat-code encoding (biased noise) (GKP grid encoding) | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) (Bias-preserving cat–cat CNOT) | Static nearest-neighbour lattice | Room-temperature electronics + per-qubit coax/flex | Dispersive microwave readout (+TWPA, Purcell) | Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) | MWPM / Sparse Blossom (+ correlated matching) | Multi-chip modules / l-couplers (same cryostat) (Multi-die packaging in one module (flip-chip, bump-bonded control die)) | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) (3D machined superconducting cavities) |
| Dual-rail erasure qubits — D-Wave/QCI, AWS, SUSTech | Bosonic cavity mode (Transmon) | Dual-rail (erasure) encoding | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) | Static nearest-neighbour lattice | Room-temperature electronics + per-qubit coax/flex (Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring; On-chip flux-DAC multiplexing) | Mid-circuit erasure check (Dispersive microwave readout (+TWPA, Purcell)) | Erasure-adapted codes | MWPM / Sparse Blossom (+ correlated matching) | Multi-chip modules / l-couplers (same cryostat) (Multi-die packaging in one module (flip-chip, bump-bonded control die)) | 3D machined superconducting cavities (Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm)) |
| Trapped ions — QCCD (transport between zones) — Quantinuum (H1, H2, Helios, Sol), Universal Quantum | Trapped atomic ion | Hyperfine / clock-state qubit | Mølmer–Sørensen / light-shift laser gate (Electronic microwave gate (ions, laser-free: near-field or static gradient)) | Ion shuttling (QCCD, junctions, grid traps) | Free-space laser addressing of ions (AOM/AOD beams) (Laser control with integrated photonics (ions); Chip-integrated microwave control (ions)) | Fluorescence state detection (ions, defects) | High-rate concatenated codes with transversal gates (Colour code (transversal Cliffords); Magic-state factory (cultivation / distillation / code switching); Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime)) | GPU decoding via NVQLink (MWPM / Sparse Blossom (+ correlated matching)) | Ion–photon link | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) (Optical / mechanical assembly (lasers, vacuum, objectives); 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring); Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)) |
| Trapped ions — linear Paul trap with individual laser addressing — IonQ (Aria, Forte, Tempo), AQT, Qudoor, Maryland/Duke (EURIQA), Innsbruck | Trapped atomic ion | Hyperfine / clock-state qubit (Optical narrow-line qubit (ion S–D, atom clock); Metastable ('omg') erasure encoding) | Mølmer–Sørensen / light-shift laser gate | Ion-chain motional bus (all-to-all in chain) | Free-space laser addressing of ions (AOM/AOD beams) (Laser control with integrated photonics (ions)) | Fluorescence state detection (ions, defects) | Non-local qLDPC codes (bivariate bicycle, 'gross') (High-rate concatenated codes with transversal gates; Colour code (transversal Cliffords); Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime); Magic-state factory (cultivation / distillation / code switching)) | MWPM / Sparse Blossom (+ correlated matching) (Relay-BP for qLDPC (FPGA)) | Ion–photon link | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) (Optical / mechanical assembly (lasers, vacuum, objectives); Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)) |
| Trapped ions — electronic qubit control (laser-free, microwave-driven gates) — Oxford Ionics (IonQ), eleQtron, QUDORA, Universal Quantum | Trapped atomic ion | Hyperfine / clock-state qubit (Metastable ('omg') erasure encoding) | Electronic microwave gate (ions, laser-free: near-field or static gradient) | Ion-chain motional bus (all-to-all in chain) (Ion shuttling (QCCD, junctions, grid traps)) | Chip-integrated microwave control (ions) | Fluorescence state detection (ions, defects) | Non-local qLDPC codes (bivariate bicycle, 'gross') (High-rate concatenated codes with transversal gates) | Relay-BP for qLDPC (FPGA) (MWPM / Sparse Blossom (+ correlated matching)) | Ion–photon link | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) (300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring); Optical / mechanical assembly (lasers, vacuum, objectives)) |
| Rydberg tweezer array — alkali (Rb/Cs) — Harvard/MIT, QuEra (Gemini), Pasqal (Orion), Infleqtion, Google (2026; species not stated) | Alkali atom (Rb/Cs) in optical tweezers | Hyperfine / clock-state qubit | Rydberg-blockade CZ | Atom transport by AOD tweezers (zoned architecture) (Continuous atom reloading (reservoir + optical conveyor belt)) | Laser + AOD/SLM optical control (atoms) (PIC-generated tweezers / integrated optics for atoms) | Fluorescence imaging of atom arrays | High-rate concatenated codes with transversal gates (Rotated surface code (+ yoked variants); Colour code (transversal Cliffords); Algorithmic FT / transversal architectures; Magic-state factory (cultivation / distillation / code switching)) | Correlated / loss-aware decoding (transversal, atom loss) (Neural decoders (AlphaQubit 2, CNN, transformers); GPU decoding via NVQLink; MWPM / Sparse Blossom (+ correlated matching)) | Atom–photon cavity interface | Optical / mechanical assembly (lasers, vacuum, objectives) (Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)) |
| Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native — Atom Computing/Microsoft, Princeton, Caltech, planqc, Yaqumo | Alkaline-earth(-like) atom (Yb/Sr) — erasure-native | Metastable ('omg') erasure encoding (Hyperfine / clock-state qubit; Optical narrow-line qubit (ion S–D, atom clock)) | Rydberg-blockade CZ | Atom transport by AOD tweezers (zoned architecture) (Continuous atom reloading (reservoir + optical conveyor belt)) | Laser + AOD/SLM optical control (atoms) | Fluorescence imaging of atom arrays (Mid-circuit erasure check) | Erasure-adapted codes (Rotated surface code (+ yoked variants)) | Correlated / loss-aware decoding (transversal, atom loss) (MWPM / Sparse Blossom (+ correlated matching)) | Atom–photon cavity interface | Optical / mechanical assembly (lasers, vacuum, objectives) |
| Neutral-atom analogue simulator (Rydberg arrays, lattice gases) — QuEra (Aquila), Pasqal (Fresnel; Orion in analogue mode), ICFO (QUIONE) | Alkali atom (Rb/Cs) in optical tweezers (Alkaline-earth(-like) atom (Yb/Sr) — erasure-native) | Ground–Rydberg analogue qubit | Analogue Rydberg Hamiltonian evolution | Atom transport by AOD tweezers (zoned architecture) | Laser + AOD/SLM optical control (atoms) | Fluorescence imaging of atom arrays | ∅ | ∅ | ∅ | Optical / mechanical assembly (lasers, vacuum, objectives) |
| Fusion-based photonic (FBQC) — PsiQuantum (Omega), Quandela, QuiX | Single photon (discrete variable) | Time-bin / path photonic encoding (Dual-rail (erasure) encoding) | Linear-optical fusion (heralded) (Multi-photon resource-state generator (RSG; 6-ring etc.)) | Photonic switching / routing (electro-optic, feed-forward) | Electro-optic drive + feed-forward electronics (room temperature) | Single-photon detection (SNSPD / TES) | Fusion-based fault tolerance | MWPM / Sparse Blossom (+ correlated matching) | Fibre links between photonic modules | Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) (III-V MBE heterostructures (InAs–Pb wires, QD sources)) |
| Continuous-variable photonic — GKP — Xanadu (Aurora) | Squeezed light mode (CV) | GKP grid encoding | CV Gaussian gates + GKP-assisted non-Gaussian operations (Linear-optical fusion (heralded)) | Photonic switching / routing (electro-optic, feed-forward) | Electro-optic drive + feed-forward electronics (room temperature) | Homodyne quadrature detection (CV) (Single-photon detection (SNSPD / TES)) | Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) (Non-local qLDPC codes (bivariate bicycle, 'gross')) | Relay-BP for qLDPC (FPGA) (MWPM / Sparse Blossom (+ correlated matching)) | Fibre links between photonic modules | Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
| Boson sampler — USTC (Jiuzhang), Xanadu (Borealis), ORCA | Squeezed light mode (CV) (Single photon (discrete variable)) | ∅ | Programmable linear-optical interferometer (no entangling primitive) | Photonic switching / routing (electro-optic, feed-forward) | Electro-optic drive + feed-forward electronics (room temperature) | Single-photon detection (SNSPD / TES) | ∅ | ∅ | ∅ | Bulk-optics and fibre assembly (photonic samplers) (Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)) |
| Silicon / germanium quantum-dot spins — Intel, Diraq, Quantum Motion, HRL→IBM, QuTech/Groove, Quobly, Equal1 | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding (Exchange-only / singlet–triplet spin encoding) | Exchange gate (spins; incl. shuttled-spin CZ) (Microwave / optical spin gates (defect centres, 1Q spins)) | Static nearest-neighbour lattice (Spin shuttling (conveyor mode); Crossbar shared-line control (spins)) | Baseband electrical control (spins, Majorana) (Cryo-CMOS controller (4 K / mK); Room-temperature electronics + per-qubit coax/flex) | Spin-to-charge conversion + rf reflectometry | Rotated surface code (+ yoked variants) (Non-local qLDPC codes (bivariate bicycle, 'gross')) | MWPM / Sparse Blossom (+ correlated matching) | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
| Donor spins in silicon — SQC | Donor spin (P in ²⁸Si) | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding | Exchange gate (spins; incl. shuttled-spin CZ) (Microwave / optical spin gates (defect centres, 1Q spins)) | Static nearest-neighbour lattice | Baseband electrical control (spins, Majorana) (Room-temperature electronics + per-qubit coax/flex) | Spin-to-charge conversion + rf reflectometry | Rotated surface code (+ yoked variants) | MWPM / Sparse Blossom (+ correlated matching) | ∅ | STM hydrogen-resist lithography (donors) |
| Colour-centre spins — network nodes (NV/SiV/T) — QuTech/Fujitsu, Harvard, Photonic Inc, Quantum Brilliance | Colour-centre / defect spin (NV, SiV, SnV, T centre) | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding | Microwave / optical spin gates (defect centres, 1Q spins) | Static nearest-neighbour lattice | Baseband electrical control (spins, Majorana) (Room-temperature electronics + per-qubit coax/flex) | Fluorescence state detection (ions, defects) | Non-local qLDPC codes (bivariate bicycle, 'gross') | ∅ | Spin–photon solid-state link (SiV, NV, T centre) | Diamond growth / implantation (NV, SiV, SnV) (Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)) |
| Topological — tetron (Majorana) — Microsoft | Majorana parity (InAs–Pb tetron) | Fermion-parity encoding (tetron) | Measurement-based Majorana gate ✗ | Static nearest-neighbour lattice | Baseband electrical control (spins, Majorana) | rf quantum-capacitance parity readout | ∅ | ∅ | ∅ | III-V MBE heterostructures (InAs–Pb wires, QD sources) |
| Quantum annealer — flux qubits — D-Wave | rf-SQUID flux qubit (annealer) | ∅ | Quantum annealing (analogue evolution) | Long-range on-chip couplers (c-couplers, mm-scale) | On-chip flux-DAC multiplexing | Flux readout via QFP / SQUID shift registers (annealers) (Dispersive microwave readout (+TWPA, Purcell)) | ∅ | ∅ | ∅ | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
7.4 Derived clocks per architecture — syndrome round, reaction time, operations per coherence
table
| Architecture | round of | d₂ | gates | transport | 1Q | readout | reset | t_round | limiter | measured cycle | reaction time (loop / floor) | T2 | ops per coherence | idle exposure t_round/T2 | idle measured |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Transmon lattice with tunable couplers | code_surface | 4 | 159 ns | 0 | 50 ns | 282 ns | 160 ns | 651 ns | readout | 1.1 µs (Willow QEC cycle) | 63 µs / 406 ns | 89 µs | 2.2×10³ | 7.3×10⁻³ | 9.0×10⁻³ |
| Bosonic cavity qubits — cat and GKP | code_bosonic | 2 | 1 µs | 0 | 0 | 282 ns | 160 ns | 1.44 µs | gates | 2.8 µs (Ocelot cycle) | 63 µs / 1.28 µs | 34 ms (best) | 6.8×10⁴ | 4.2×10⁻⁵ | — |
| Dual-rail erasure qubits | code_surface | 4 | 2 µs | 0 | 400 ns | 398 ns | unpublished | ≥ 2.8 µs | gates | ~2 µs (CZ 500 ns + 384 ns check) | 63 µs / 1.4 µs | 34 ms (best) | 6.8×10⁴ | 8.2×10⁻⁵ | — |
| Trapped ions — QCCD (transport between zones) | code_color | 8 | 505 µs | 9.04 ms | 0 | 100 µs | 20 µs | 9.66 ms | transport | ~1–5 ms syndrome cycle; 55 ms per full layer (Helios) | — / 167 µs | 4.24×10³ s (best) | 6.7×10⁷ | 2.3×10⁻⁶ | 5.0×10⁻⁴ |
| Trapped ions — linear Paul trap with individual laser addressing | code_qldpc | 7 | 442 µs | 0 | 0 | 100 µs | 20 µs | ≥ 562 µs | gates | ~ms (IonQ decoder assumption); 1–5 ms cycles in QCCD-class experiments | — / 101 µs | 4.24×10³ s (best) | 6.7×10⁷ | 1.3×10⁻⁷ | 5.0×10⁻⁴ |
| Trapped ions — electronic qubit control (laser-free, microwave-driven gates) | code_qldpc | 7 | 1.4 ms | 0 | 0 | 100 µs | 20 µs | ≥ 1.52 ms | gates | ~1–5 ms (IonQ decoder assumption) | — / 101 µs | 4.24×10³ s (best) | 2.1×10⁷ | 3.6×10⁻⁷ | 5.0×10⁻⁴ |
| Rydberg tweezer array — alkali (Rb/Cs) | code_surface | 4 | 1 µs | 800 µs | 10 µs | 501 µs | 0 | 1.31 ms | transport | ~1–4.5 ms per QEC round | 5 µs / 502 µs | 12.6 s (best) | 5.0×10⁷ | 1.0×10⁻⁴ | — |
| Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native | code_surface | 4 | 1 µs | 800 µs | 340 ns | 501 µs | 0 | 1.3 ms | transport | ~1–4 ms | 5 µs / 502 µs | 7.9 s (best) | 3.1×10⁷ | 1.6×10⁻⁴ | — |
| Neutral-atom analogue simulator (Rydberg arrays, lattice gases) | — | — | — | — | — | — | — | — | — | n/a — analogue evolution, µs-class; no cycle | 5 µs / | 11.4 µs | — | — | — |
| Fusion-based photonic (FBQC) | — | — | — | — | — | — | — | — | — | MHz–GHz by design; no logical cycle | 1 µs / 1.01 µs | — | — | — | — |
| Continuous-variable photonic — GKP | — | — | — | — | — | — | — | — | — | 1 MHz clock (Aurora); no logical cycle | 1 µs / 2 µs | — | — | — | — |
| Boson sampler | — | — | — | — | — | — | — | — | — | n/a — sampling; MHz-class clock, no cycle | 1 µs / | — | — | — | — |
| Silicon / germanium quantum-dot spins | code_surface | 4 | 400 ns | 0 | 800 ns | 6.31 µs | 1 µs | 8.51 µs | readout | ~100 µs – 300 µs (readout-limited) | — / 7.31 µs | 1.9 ms | 1.9×10⁴ | 4.5×10⁻³ | — |
| Donor spins in silicon | code_surface | 4 | 400 ns | 0 | unpublished | 6.31 µs | 1 µs | ≥ 7.71 µs | readout | ~ms (nuclear-spin gates µs, readout 100 µs) | — / 7.31 µs | 44.5 ms | 4.4×10⁵ | 1.7×10⁻⁴ | — |
| Colour-centre spins — network nodes (NV/SiV/T) | — | — | — | — | — | — | — | — | — | n/a (network node) | — / | 600 ms (best) | 6.0×10⁵ | — | — |
| Topological — tetron (Majorana) | — | — | — | — | — | — | — | — | — | n/a (no qubit) | — / | — | — | — | — |
| Quantum annealer — flux qubits | — | — | — | — | — | — | — | — | — | µs–ms anneal; 3.6–27 ns quenches | — / | — | — | — | — |
Reading. The round is a sum, not a maximum, so the limiter is the largest term, not the only one: on the superconducting architecture readout and reset together are two-thirds of the round, on the atom architectures transport between gate layers is, on the QCCD ion architecture transport plus recooling is ~90%. Where the derived round sits below the measured cycle the difference is the gap between the attribute (best published time for the mechanism) and the device (the cycle actually run) — on the superconducting architecture 0.65 µs against 1.1 µs, on the spin architecture the best 6 µs readout against the ~100 µs typically run. The idle exposure t_round/T2 is a second check: on the superconducting architecture it predicts 0.7% per round against the 0.9% idle term in Google's measured error budget; on ions and atoms it is 10⁻⁴–10⁻⁷, so a millisecond clock costs those platforms mostly time — idle error is small per round, though the terms the idle exposure omits (heating during transport, loss during imaging, drift between calibrations) are exactly the ones those platforms report. A total printed with ≥ is a partial sum: a term the architecture needs (transport, 1Q, reset) that no record publishes enters as zero and is named in the column, so the round is a lower bound, not an estimate. On the QCCD ion architecture the transport-plus-recooling primitives are the published H1 table (2020) — 9.7 ms derived against the 1–5 ms cycles reported for H2-class experiments, because the primitives have not been republished for H2/Helios and the derived value uses the colour code's eight layers. Reaction time is the quantity resource estimates assume (10 µs in the RSA-2048 estimate) and the one the map most often cannot fill: only the superconducting, atom and photonic architectures have a published measurement-to-operation loop.
Notes: Dual-rail erasure qubits — round of the host code (code_surface); reset time unpublished for ro_erasure; Trapped ions — QCCD (transport between zones) — round of code_color (code_highrate has no published syndrome circuit); Trapped ions — linear Paul trap with individual laser addressing — on one chain the gates of a layer run largely one at a time: d₂ layers assume parallel gates, so the total is a lower bound; Trapped ions — electronic qubit control (laser-free, microwave-driven gates) — on one chain the gates of a layer run largely one at a time: d₂ layers assume parallel gates, so the total is a lower bound; Rydberg tweezer array — alkali (Rb/Cs) — round of code_surface (code_highrate has no published syndrome circuit); reset by optical pumping (unpublished); reload amortised; Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native — round of the host code (code_surface); reset by optical pumping (unpublished); reload amortised; Neutral-atom analogue simulator (Rydberg arrays, lattice gases) — reset by optical pumping (unpublished); reload amortised; no code on this architecture; Fusion-based photonic (FBQC) — no published syndrome round for code_fusion; measurement-driven photonic architecture: no syndrome round; native clock in the measured column; no code on this architecture; Continuous-variable photonic — GKP — measurement-driven photonic architecture: no syndrome round; native clock in the measured column; reset time unpublished for ro_homodyne; no code on this architecture; Boson sampler — measurement-driven photonic architecture: no syndrome round; native clock in the measured column; no code on this architecture; Colour-centre spins — network nodes (NV/SiV/T) — network-node architecture: the code's checks run over the ic_spinphoton link, whose rate (see its records) sets the round — no derived round; Topological — tetron (Majorana) — reset time unpublished for ro_qcap; no code on this architecture; Quantum annealer — flux qubits — reset time unpublished for ro_fluxro; no code on this architecture.
7.5 Crossing technologies — where a technology takes a trait from across the natural/fabricated divide
The divide on paper. Rows are the carrier class of the architecture a technology serves, columns the side its traits come from. Natural-side traits: optical control, µs–ms gates and readout, no semiconductor/photonic-chip fabrication, local connectivity. Fabricated-side traits: microwave control, sub-µs gates, ≤ 10 µs readout, cold electronics at 4 K/mK, transport/long-range connectivity, erasure conversion, photonic interconnect. The two cells where the row and the column agree hold the stereotype — 90 of 110 technologies; the two crossing cells hold the 20 hatched technologies (8 in the natural row, 13 in the fabricated row; 1 of them carries a flag on each side and appears in both rows) with their flags from the OFFDIAG vocabulary.
table
| Carrier class of the architecture | Natural-side traits | Fabricated-side traits |
|---|---|---|
| natural (trapped ions, neutral atoms, photonics, defect spins) | the stereotype — most technologies | Rydberg-blockade CZ g_ryd (NAT_FAST_GATE); Electronic microwave gate (ions, laser-free: near-field or static gradient) g_elec (NAT_MW); PIC-generated tweezers / integrated optics for atoms ct_pic_trap (NAT_FAB); Laser control with integrated photonics (ions) ct_ionlaser (NAT_FAB); Chip-integrated microwave control (ions) ct_ionmw (NAT_MW); Mid-circuit erasure check ro_erasure (NAT_FAST_READ); 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) fab_cmos (NAT_FAB); Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) fab_pic (NAT_FAB) |
| fabricated (superconducting circuits, semiconductor spins, topological, quantum annealers) | Dual-rail (erasure) encoding enc_dualrail (FAB_ERASURE); Long-range on-chip couplers (c-couplers, mm-scale) cx_lr (FAB_FAR); Spin shuttling (conveyor mode) cx_shuttle (FAB_FAR); Cryo-CMOS controller (4 K / mK) ct_cryocmos (FAB_COLD); SFQ digital control (4 K / mK) ct_sfq (FAB_COLD); On-chip flux-DAC multiplexing ct_fluxdac (FAB_COLD); Mid-circuit erasure check ro_erasure (FAB_ERASURE); Erasure-adapted codes code_erasure (FAB_ERASURE); Cryogenic / on-chip decoder (cryo-CMOS, SFQ) dec_cryo (FAB_COLD); Multi-chip modules / l-couplers (same cryostat) ic_mcm (FAB_FAR); Cryogenic microwave link between refrigerators ic_cryolink (FAB_FAR); Spin–photon solid-state link (SiV, NV, T centre) ic_spinphoton (FAB_PHOTONIC); Microwave–optical transducer (useful efficiency) ic_transducer (FAB_PHOTONIC) |
the stereotype — most technologies |
table
| Node | Layer | Pattern | In architectures | Why it matters |
|---|---|---|---|---|
Dual-rail (erasure) encoding enc_dualrail |
2 | fabricated carrier + erasure error structure | Dual-rail erasure qubits | erasure — a natural-world error class — engineered into a fabricated carrier; threshold ×4 |
Rydberg-blockade CZ g_ryd |
3 | natural carrier + sub-microsecond gate | Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native, Rydberg tweezer array — alkali (Rb/Cs) | a natural carrier with a 270 ns gate: the reason atoms compete at all |
Electronic microwave gate (ions, laser-free: near-field or static gradient) g_elec |
3 | natural carrier + microwave/electronic control | Trapped ions — electronic qubit control (laser-free, microwave-driven gates), Trapped ions — QCCD (transport between zones) | removes lasers, the historic scaling blocker of ions; 8.4×10⁻⁵ |
Long-range on-chip couplers (c-couplers, mm-scale) cx_lr |
4 | fabricated carrier + far connectivity (transport / long-range) | Quantum annealer — flux qubits, Transmon lattice with tunable couplers | gives 2D lattices the degree-6 connectivity qLDPC needs |
Spin shuttling (conveyor mode) cx_shuttle |
4 | fabricated carrier + far connectivity (transport / long-range) | Silicon / germanium quantum-dot spins | transport connectivity for a fabricated carrier — the spin route to non-local codes |
Cryo-CMOS controller (4 K / mK) ct_cryocmos |
5 | fabricated carrier + control/decoding in the cold stage | Transmon lattice with tunable couplers, Silicon / germanium quantum-dot spins | control moves into the fridge: wiring and heat are one of the four limits on the count |
SFQ digital control (4 K / mK) ct_sfq |
5 | fabricated carrier + control/decoding in the cold stage | Transmon lattice with tunable couplers | the second cold route: nW per qubit at millikelvin; quasiparticle poisoning is the open risk |
On-chip flux-DAC multiplexing ct_fluxdac |
5 | fabricated carrier + control/decoding in the cold stage | Quantum annealer — flux qubits, Dual-rail erasure qubits | annealer heritage: 10⁴ qubits on 200–300 lines (D-Wave's own figures disagree) |
PIC-generated tweezers / integrated optics for atoms ct_pic_trap |
5 | natural carrier + semiconductor / photonic-chip fabrication | Rydberg tweezer array — alkali (Rb/Cs) | optics of the fabricated world for a natural carrier; footprint ÷50 claimed |
Laser control with integrated photonics (ions) ct_ionlaser |
5 | natural carrier + semiconductor / photonic-chip fabrication | Trapped ions — linear Paul trap with individual laser addressing, Trapped ions — QCCD (transport between zones) | integrated photonics in the trap — the ion analogue of the same move |
Chip-integrated microwave control (ions) ct_ionmw |
5 | natural carrier + microwave/electronic control | Trapped ions — electronic qubit control (laser-free, microwave-driven gates), Trapped ions — QCCD (transport between zones) | ~200 electronic sources for 1,000 ions instead of laser beams |
Mid-circuit erasure check ro_erasure |
6 | fabricated carrier + erasure error structure; natural carrier + ≤ 10 µs readout | Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native, Dual-rail erasure qubits | the readout primitive behind every erasure code; 384 ns on transmons |
Erasure-adapted codes code_erasure |
7 | fabricated carrier + erasure error structure | Dual-rail erasure qubits | threshold 0.94% → 4.15%; the largest single lever on overhead |
Cryogenic / on-chip decoder (cryo-CMOS, SFQ) dec_cryo |
8 | fabricated carrier + control/decoding in the cold stage | Transmon lattice with tunable couplers | |
Multi-chip modules / l-couplers (same cryostat) ic_mcm |
9 | fabricated carrier + far connectivity (transport / long-range) | Bosonic cavity qubits — cat and GKP, Dual-rail erasure qubits, Transmon lattice with tunable couplers | fabricated carriers reaching beyond one chip (chiplets, l-couplers) |
Cryogenic microwave link between refrigerators ic_cryolink |
9 | fabricated carrier + far connectivity (transport / long-range) | Transmon lattice with tunable couplers | 30 m between fridges at 80% Bell — the microwave route to modularity |
Spin–photon solid-state link (SiV, NV, T centre) ic_spinphoton |
9 | fabricated/solid-state carrier + photonic interconnect | Colour-centre spins — network nodes (NV/SiV/T) | solid-state spins reaching the network via photons |
Microwave–optical transducer (useful efficiency) ic_transducer |
9 | fabricated/solid-state carrier + photonic interconnect | Transmon lattice with tunable couplers | the missing link for optical modularity of superconducting machines — empty |
300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) fab_cmos |
10 | natural carrier + semiconductor / photonic-chip fabrication | Trapped ions — electronic qubit control (laser-free, microwave-driven gates), Trapped ions — QCCD (transport between zones) | ion traps from standard semiconductor fabs (Oxford Ionics, SkyWater) |
Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) fab_pic |
10 | natural carrier + semiconductor / photonic-chip fabrication | Rydberg tweezer array — alkali (Rb/Cs), Trapped ions — linear Paul trap with individual laser addressing, Trapped ions — QCCD (transport between zones) |
7.6 Empty slots — where a technology does not exist yet
table
| Slot | Status | What would fill it | Best today vs needed |
|---|---|---|---|
Microwave–optical transducer (useful efficiency) ic_transducer (9) |
empty slot — no technology yet | Best: η_tot 15%, N_add 0.16 (EO); useful regime needs η > 1/2 and N_add ≪ 1; ~3 orders of magnitude short (IBM analysis). | η_tot 15%, N_add 0.16 vs η > 1/2, N_add ≪ 1; ~3 orders of magnitude (IBM) |
Cryogenic / on-chip decoder (cryo-CMOS, SFQ) dec_cryo (8) |
empty slot — no technology yet | Designs only: NISQ+ (≤ 20 ns, SFQ), QECOOL (2.8 µW), Pinball/CryoZip (4 K predecoders) — no fabricated decoder chip. | designs only (NISQ+ 20 ns, QECOOL 2.8 µW); no fabricated decoder chip |
Bias-preserving cat–cat CNOT g_catcnot (3) |
empty slot — no technology yet | Required by every cat-qubit resource estimate; proposed since 2019 (Guillaud–Mirrahimi) and 2020 (Puri et al.), the first unitary scheme in July 2026; no demonstration. | theory proposal Jul 2026; every cat resource estimate assumes it |
Multi-photon resource-state generator (RSG; 6-ring etc.) src_resource (3) |
empty slot — no technology yet | Fusion-based FT needs 24–168-photon encoded resource states at high rate; largest fused deterministic-emitter graph states are 8 photons at < 1 Hz. | 8-photon states at < 1 Hz vs 24–168-photon encoded resource states at MHz |
Measurement-based Majorana gate g_mbq (3) |
empty slot — no technology yet | Braiding by sequences of parity measurements — nothing demonstrated; single-wire readout only. | single-wire parity readout only; no X-lifetime ≈ Z, no two-qubit operation |
| Donor spins in silicon — Interconnect | ∅ | interconnect for donor spins | — |
| Colour-centre spins — network nodes (NV/SiV/T) — Decoder | ∅ | — | — |
| Topological — tetron (Majorana) — Code | ∅ | Floquet / measurement-based codes on a demonstrated qubit | — |
| Topological — tetron (Majorana) — Decoder | ∅ | — | — |
| Topological — tetron (Majorana) — Interconnect | ∅ | — | — |
Numeric gaps on existing nodes (attribute-level, not empty slots): ion–photon links at 10–250 s⁻¹ vs ≥ 10⁴ s⁻¹ needed; photonic switch loss 100–190 mdB vs ~7 mdB; optical GKP effective squeezing 0.62 dB vs 9.75 dB; cat phase-flip ~10⁻¹ per CX vs 10⁻³ assumed; spin readout 6 µs at 99.2% vs sub-µs at 99.9% for a µs-class cycle; atom imaging 0.5–1 ms typical vs 17.6 µs emerging.
7.7 How the map shows a graph of 7 attributes and 4 edge types — and why it is dynamic
The map is a layered map: the ten layers of §7.1 are its columns, left to right from the carrier to the application; inside a column a technology's vertical position is its carrier-nature affinity, so the natural half sits above and the fabricated half below, and a crossing technology (§7.5) is the one drawn in the other half, hatched. Each architecture is a coloured line through its primary technology in every layer it has one for; its alternates are half-tone squares of the same colour beside the line; a layer the architecture skips shows a dotted circle where the line jumps the column; an empty slot (§7.6) is a hollow dashed technology. Seven attributes cannot all be painted at once — a reader has one hue channel — so the map carries a lens that recolours every technology by one attribute at a time and a card that keeps the three spaces apart: design attributes, dated evaluation attributes, actors and goals. Edges of type requires / alternatives / conflicts are drawn only for the focused technology, because 110 technologies × 270 edges of those three types drawn together are a hairball; defines edges live in the card as dated rows, not lines. Dynamic is necessary, static is mandatory: the resting frame is a complete readable map (all architectures, all technologies) that prints and thumbnails; the interaction adds lenses, focus, the machine selector and Find, without which four edge types and 110 technologies cannot be read. The tables of §7.2–7.9 are the same graph on paper.
7.8 Edge list
dependencies — B is needed by A (the table lists A, then B)
dependencies — B is needed by A (the table lists A, then B)
| Technology | Needs | Kind | Strength | Note |
|---|---|---|---|---|
g_tc Tunable-coupler CZ / iSWAP |
transmon Transmon |
acts on the carrier | one carrier of several | flux-tunable coupler between transmons |
g_cr Cross-resonance (fixed-frequency, all-microwave) |
transmon Transmon |
acts on the carrier | hard | fixed-frequency transmons |
g_ryd Rydberg-blockade CZ |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | Rydberg excitation of the atom |
g_ryd Rydberg-blockade CZ |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | Rydberg excitation of the atom |
g_ryd Rydberg-blockade CZ |
ct_laser Laser + AOD/SLM optical control (atoms) |
signal delivery | hard | Rydberg lasers, global pulses |
g_ms Mølmer–Sørensen / light-shift laser gate |
ion Trapped atomic ion |
acts on the carrier | hard | spin–motion coupling |
g_ms Mølmer–Sørensen / light-shift laser gate |
ct_ionlaser Laser control with integrated photonics (ions) |
signal delivery | one control route of several | laser fields (integrated delivery) |
g_elec Electronic microwave gate (ions, laser-free: near-field or static gradient) |
ion Trapped atomic ion |
acts on the carrier | hard | chip currents act on the ion |
g_elec Electronic microwave gate (ions, laser-free: near-field or static gradient) |
ct_ionmw Chip-integrated microwave control (ions) |
signal delivery | hard | electronic signal sources |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | one carrier of several | exchange between dots |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
donor Donor spin (P in ²⁸Si) |
acts on the carrier | one carrier of several | exchange between donors |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
ct_base Baseband electrical control (spins, Majorana) |
signal delivery | one control route of several | voltage pulses on gates |
g_fusion Linear-optical fusion (heralded) |
photon Single photon (discrete variable) |
acts on the carrier | one carrier of several | photons to fuse |
g_fusion Linear-optical fusion (heralded) |
ro_spd Single-photon detection (SNSPD / TES) |
measurement or heralding | hard | heralding detection |
g_fusion Linear-optical fusion (heralded) |
cx_switch Photonic switching / routing (electro-optic, feed-forward) |
built from other operations | hard | feed-forward routing |
g_cv CV Gaussian gates + GKP-assisted non-Gaussian operations |
squeezed Squeezed light mode (CV) |
acts on the carrier | hard | squeezed modes |
g_cv CV Gaussian gates + GKP-assisted non-Gaussian operations |
ct_eo Electro-optic drive + feed-forward electronics (room temperature) |
signal delivery | hard | homodyne feed-forward |
g_bos Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) |
cavity Bosonic cavity mode |
acts on the carrier | hard | bosonic modes |
g_bos Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) |
transmon Transmon |
acts on the carrier | soft | ancilla transmon |
g_catcnot Bias-preserving cat–cat CNOT |
enc_cat Cat-code encoding (biased noise) |
needs a particular encoding | hard | two cat qubits |
g_mbq Measurement-based Majorana gate |
majorana Majorana parity (InAs–Pb tetron) |
acts on the carrier | hard | Majorana wires |
g_mbq Measurement-based Majorana gate |
ro_qcap rf quantum-capacitance parity readout |
measurement or heralding | hard | measurement-based |
g_mwspin Microwave / optical spin gates (defect centres, 1Q spins) |
defect Colour-centre / defect spin (NV, SiV, SnV, T centre) |
acts on the carrier | one carrier of several | spin register |
src_resource Multi-photon resource-state generator (RSG; 6-ring etc.) |
g_fusion Linear-optical fusion (heralded) |
part of, or a refinement | hard | fusions build the resource state |
src_resource Multi-photon resource-state generator (RSG; 6-ring etc.) |
photon Single photon (discrete variable) |
acts on the carrier | hard | deterministic or multiplexed photons |
enc_cat Cat-code encoding (biased noise) |
cavity Bosonic cavity mode |
acts on the carrier | hard | two-photon dissipation on a mode |
enc_gkp GKP grid encoding |
cavity Bosonic cavity mode |
acts on the carrier | one carrier of several | microwave GKP |
enc_gkp GKP grid encoding |
squeezed Squeezed light mode (CV) |
acts on the carrier | one carrier of several | optical GKP needs ~10 dB squeezing |
enc_dualrail Dual-rail (erasure) encoding |
ro_erasure Mid-circuit erasure check |
measurement or heralding | one readout of several | erasure check |
enc_omg Metastable ('omg') erasure encoding |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | metastable manifold |
enc_omg Metastable ('omg') erasure encoding |
ion Trapped atomic ion |
acts on the carrier | one carrier of several | metastable ion levels |
enc_opt Optical narrow-line qubit (ion S–D, atom clock) |
ion Trapped atomic ion |
acts on the carrier | one carrier of several | S–D quadrupole transition of an alkaline-earth ion |
enc_opt Optical narrow-line qubit (ion S–D, atom clock) |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | ¹S₀–³P₀ clock transition of Sr/Yb |
enc_eo Exchange-only / singlet–triplet spin encoding |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | hard | three-dot encoded qubit |
enc_timebin Time-bin / path photonic encoding |
photon Single photon (discrete variable) |
acts on the carrier | hard | photonic modes |
enc_parity Fermion-parity encoding (tetron) |
majorana Majorana parity (InAs–Pb tetron) |
acts on the carrier | hard | two wires per tetron |
enc_bare Bare physical qubit (no encoding) |
transmon Transmon |
acts on the carrier | one carrier of several | anharmonic subspace |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
ion Trapped atomic ion |
acts on the carrier | hard | ions to move |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
fab_trap Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) |
fabrication route | hard | junction / grid traps |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
ct_laser Laser + AOD/SLM optical control (atoms) |
signal delivery | hard | AOD deflectors |
cx_shuttle Spin shuttling (conveyor mode) |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | hard | spins to move |
cx_shuttle Spin shuttling (conveyor mode) |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
fabrication route | hard | uniform conveyor gates |
cx_lr Long-range on-chip couplers (c-couplers, mm-scale) |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | multilayer routing |
cx_switch Photonic switching / routing (electro-optic, feed-forward) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | hard | low-loss switches |
cx_crossbar Crossbar shared-line control (spins) |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | hard | dot array |
ct_sfq SFQ digital control (4 K / mK) |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | flip-chip SFQ MCM |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
fabrication route | hard | cryo ASIC |
ct_fluxdac On-chip flux-DAC multiplexing |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | on-chip SFQ DACs |
ct_pic_trap PIC-generated tweezers / integrated optics for atoms |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | hard | photonic chip |
ct_ionlaser Laser control with integrated photonics (ions) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | hard | integrated waveguides |
ct_ionmw Chip-integrated microwave control (ions) |
fab_trap Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) |
fabrication route | hard | current traces in the trap |
ct_eo Electro-optic drive + feed-forward electronics (room temperature) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | one manufacturing route of several | modulators |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
transmon Transmon |
acts on the carrier | one carrier of several | dispersive shift |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
cavity Bosonic cavity mode |
acts on the carrier | one carrier of several | ancilla-mediated readout |
ro_fluor Fluorescence state detection (ions, defects) |
ion Trapped atomic ion |
acts on the carrier | one carrier of several | cycling transition |
ro_fluor Fluorescence state detection (ions, defects) |
defect Colour-centre / defect spin (NV, SiV, SnV, T centre) |
acts on the carrier | one carrier of several | optical readout of the spin |
ro_img Fluorescence imaging of atom arrays |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | imaging transition |
ro_img Fluorescence imaging of atom arrays |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | imaging transition |
ro_s2c Spin-to-charge conversion + rf reflectometry |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | one carrier of several | charge sensor |
ro_s2c Spin-to-charge conversion + rf reflectometry |
donor Donor spin (P in ²⁸Si) |
acts on the carrier | one carrier of several | charge sensor |
ro_spd Single-photon detection (SNSPD / TES) |
photon Single photon (discrete variable) |
acts on the carrier | one carrier of several | detection |
ro_qcap rf quantum-capacitance parity readout |
majorana Majorana parity (InAs–Pb tetron) |
acts on the carrier | hard | quantum capacitance |
ro_erasure Mid-circuit erasure check |
enc_dualrail Dual-rail (erasure) encoding |
readout apparatus | one encoding of several | erasure-detectable encoding |
ro_erasure Mid-circuit erasure check |
enc_omg Metastable ('omg') erasure encoding |
readout apparatus | one encoding of several | erasure-detectable encoding |
code_surface Rotated surface code (+ yoked variants) |
cx_nn Static nearest-neighbour lattice |
the code's connectivity need | one connectivity of several | 2D nearest-neighbour checks |
code_color Colour code (transversal Cliffords) |
cx_nn Static nearest-neighbour lattice |
the code's connectivity need | one connectivity of several | 2D checks |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_lr Long-range on-chip couplers (c-couplers, mm-scale) |
the code's connectivity need | one connectivity of several | degree-6 long-range checks |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
the code's connectivity need | one connectivity of several | long-range via transport |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_bus Ion-chain motional bus (all-to-all in chain) |
the code's connectivity need | one connectivity of several | all-to-all in chain |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
the code's connectivity need | one connectivity of several | long-range via transport |
code_highrate High-rate concatenated codes with transversal gates |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
the code's connectivity need | one connectivity of several | transversal blocks by transport |
code_highrate High-rate concatenated codes with transversal gates |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
the code's connectivity need | one connectivity of several | all-to-all via QCCD |
code_highrate High-rate concatenated codes with transversal gates |
cx_bus Ion-chain motional bus (all-to-all in chain) |
the code's connectivity need | one connectivity of several | all-to-all in chain |
code_erasure Erasure-adapted codes |
ro_erasure Mid-circuit erasure check |
measurement or heralding | hard | erasure flags |
code_erasure Erasure-adapted codes |
dec_corr Correlated / loss-aware decoding (transversal, atom loss) |
decoder ↔ code | one decoder of several | erasure-/loss-aware decoding (flags are useless to a plain matcher) |
code_bosonic Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) |
enc_cat Cat-code encoding (biased noise) |
needs a particular encoding | one encoding of several | biased inner qubit |
code_bosonic Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) |
enc_gkp GKP grid encoding |
needs a particular encoding | one encoding of several | GKP inner qubit |
code_fusion Fusion-based fault tolerance |
g_fusion Linear-optical fusion (heralded) |
built from other operations | hard | fusion measurements |
code_fusion Fusion-based fault tolerance |
src_resource Multi-photon resource-state generator (RSG; 6-ring etc.) |
built from other operations | hard | resource states |
code_aft Algorithmic FT / transversal architectures |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
the code's connectivity need | one connectivity of several | transversal gates by transport |
code_aft Algorithmic FT / transversal architectures |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
the code's connectivity need | one connectivity of several | transversal gates by ion shuttling (Quantinuum tesseract on ions) |
code_aft Algorithmic FT / transversal architectures |
dec_corr Correlated / loss-aware decoding (transversal, atom loss) |
decoder ↔ code | hard | correlated decoding |
code_magic Magic-state factory (cultivation / distillation / code switching) |
code_surface Rotated surface code (+ yoked variants) |
part of, or a refinement | one code of several | host code |
code_magic Magic-state factory (cultivation / distillation / code switching) |
code_color Colour code (transversal Cliffords) |
part of, or a refinement | one code of several | host code |
dec_fpga FPGA real-time decoders (LCD, Deltaflow) |
code_surface Rotated surface code (+ yoked variants) |
decoder ↔ code | soft | matching/clustering on surface syndromes |
dec_nn Neural decoders (AlphaQubit 2, CNN, transformers) |
code_surface Rotated surface code (+ yoked variants) |
decoder ↔ code | soft | trained on surface-code syndromes |
dec_relaybp Relay-BP for qLDPC (FPGA) |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
decoder ↔ code | hard | qLDPC syndromes |
dec_corr Correlated / loss-aware decoding (transversal, atom loss) |
code_highrate High-rate concatenated codes with transversal gates |
decoder ↔ code | one code of several | transversal circuits |
dec_rl In-loop RL calibration / control steering |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
part of, or a refinement | soft | decoder steering reweights the matching graph |
dec_cryo Cryogenic / on-chip decoder (cryo-CMOS, SFQ) |
ct_sfq SFQ digital control (4 K / mK) |
signal delivery | one control route of several | cold digital logic |
dec_cryo Cryogenic / on-chip decoder (cryo-CMOS, SFQ) |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
signal delivery | one control route of several | cold digital logic |
ic_mcm Multi-chip modules / l-couplers (same cryostat) |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | chiplets, couplers |
ic_cryolink Cryogenic microwave link between refrigerators |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | superconducting waveguide |
ic_ionphoton Ion–photon link |
ion Trapped atomic ion |
acts on the carrier | hard | ion–photon entanglement |
ic_ionphoton Ion–photon link |
ro_spd Single-photon detection (SNSPD / TES) |
measurement or heralding | hard | photon detection |
ic_atomcavity Atom–photon cavity interface |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | cavity-coupled atoms |
ic_atomcavity Atom–photon cavity interface |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | cavity-coupled atoms |
ic_atomcavity Atom–photon cavity interface |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | cavities |
ic_spinphoton Spin–photon solid-state link (SiV, NV, T centre) |
defect Colour-centre / defect spin (NV, SiV, SnV, T centre) |
acts on the carrier | hard | spin–photon interface |
ic_spinphoton Spin–photon solid-state link (SiV, NV, T centre) |
ro_spd Single-photon detection (SNSPD / TES) |
measurement or heralding | hard | photon detection |
ic_transducer Microwave–optical transducer (useful efficiency) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | hard | electro-optic / optomechanical chip |
ic_transducer Microwave–optical transducer (useful efficiency) |
ro_spd Single-photon detection (SNSPD / TES) |
measurement or heralding | hard | heralded entanglement through the transducer needs single-photon detection |
ic_transducer Microwave–optical transducer (useful efficiency) |
transmon Transmon |
acts on the carrier | hard | microwave qubit |
ic_fibre Fibre links between photonic modules |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | hard | chip-to-fibre coupling |
transmon Transmon |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | JJ lithography |
fluxonium Fluxonium |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | JJ arrays |
cavity Bosonic cavity mode |
fab_3d 3D machined superconducting cavities |
fabrication route | one manufacturing route of several | machined cavities |
fluxq rf-SQUID flux qubit (annealer) |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | annealer fab |
ion Trapped atomic ion |
fab_trap Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) |
fabrication route | hard | surface-electrode or 3D blade trap |
ion Trapped atomic ion |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | lasers, vacuum |
alkali Alkali atom (Rb/Cs) in optical tweezers |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | tweezers, vacuum |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | tweezers, clock lasers |
photon Single photon (discrete variable) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | one manufacturing route of several | sources, waveguides |
squeezed Squeezed light mode (CV) |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fabrication route | one manufacturing route of several | squeezers |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
fabrication route | soft | 300 mm dots |
donor Donor spin (P in ²⁸Si) |
fab_stm STM hydrogen-resist lithography (donors) |
fabrication route | soft | STM placement |
defect Colour-centre / defect spin (NV, SiV, SnV, T centre) |
fab_diamond Diamond growth / implantation (NV, SiV, SnV) |
fabrication route | soft | host crystal |
majorana Majorana parity (InAs–Pb tetron) |
fab_mbe III-V MBE heterostructures (InAs–Pb wires, QD sources) |
fabrication route | hard | InAs–Pb stack |
g_rydanalog Analogue Rydberg Hamiltonian evolution |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | Rydberg excitation of the atom |
g_rydanalog Analogue Rydberg Hamiltonian evolution |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | Rydberg excitation of an alkaline-earth atom (Sr) |
g_rydanalog Analogue Rydberg Hamiltonian evolution |
enc_gr Ground–Rydberg analogue qubit |
needs a particular encoding | hard | ground–Rydberg computational states |
g_rydanalog Analogue Rydberg Hamiltonian evolution |
ct_laser Laser + AOD/SLM optical control (atoms) |
signal delivery | hard | global Rydberg lasers |
enc_gr Ground–Rydberg analogue qubit |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | an atom with a Rydberg level |
enc_gr Ground–Rydberg analogue qubit |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | an alkaline-earth(-like) atom with a Rydberg level |
g_lointer Programmable linear-optical interferometer (no entangling primitive) |
photon Single photon (discrete variable) |
acts on the carrier | one carrier of several | single photons in the mesh |
g_lointer Programmable linear-optical interferometer (no entangling primitive) |
squeezed Squeezed light mode (CV) |
acts on the carrier | one carrier of several | squeezed light in the mesh |
g_lointer Programmable linear-optical interferometer (no entangling primitive) |
ct_eo Electro-optic drive + feed-forward electronics (room temperature) |
signal delivery | soft | phase shifters and switches |
cx_reload Continuous atom reloading (reservoir + optical conveyor belt) |
ct_laser Laser + AOD/SLM optical control (atoms) |
signal delivery | hard | lattice and tweezer light |
cx_reload Continuous atom reloading (reservoir + optical conveyor belt) |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | second MOT region, conveyor optics, vacuum |
ct_ionaod Free-space laser addressing of ions (AOM/AOD beams) |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | bulk optics above the trap |
g_ms Mølmer–Sørensen / light-shift laser gate |
ct_ionaod Free-space laser addressing of ions (AOM/AOD beams) |
signal delivery | one control route of several | laser fields delivered from free space |
ct_vio Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | through-substrate vias, coaxial pins, interposers |
ro_reset Fast unconditional / dissipative qubit reset |
transmon Transmon |
acts on the carrier | hard | the qubit to be reset |
ro_reset Fast unconditional / dissipative qubit reset |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
part of, or a refinement | hard | the readout resonator used as the loss channel |
ro_fluxro Flux readout via QFP / SQUID shift registers (annealers) |
fluxq rf-SQUID flux qubit (annealer) |
acts on the carrier | hard | flux qubits latched by QFPs |
ro_fluxro Flux readout via QFP / SQUID shift registers (annealers) |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
part of, or a refinement | hard | frequency-multiplexed microresonators read the latched flux at the chip edge |
ro_fluxro Flux readout via QFP / SQUID shift registers (annealers) |
ct_fluxdac On-chip flux-DAC multiplexing |
signal delivery | hard | on-chip shift registers and DACs |
ro_homodyne Homodyne quadrature detection (CV) |
squeezed Squeezed light mode (CV) |
acts on the carrier | hard | a field quadrature to measure |
ro_homodyne Homodyne quadrature detection (CV) |
ct_eo Electro-optic drive + feed-forward electronics (room temperature) |
signal delivery | hard | local-oscillator phase control |
ic_multidie Multi-die packaging in one module (flip-chip, bump-bonded control die) |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | hard | bump-bonded superconducting dies |
ic_fanout Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
fabrication route | hard | a CMOS router die at cryogenic temperature |
ic_fanout Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
signal delivery | hard | cryogenic electronics behind the fan-out |
enc_hf Hyperfine / clock-state qubit |
ion Trapped atomic ion |
acts on the carrier | one carrier of several | hyperfine ground levels of the ion |
enc_hf Hyperfine / clock-state qubit |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | hyperfine ground levels of the atom |
enc_hf Hyperfine / clock-state qubit |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | nuclear-spin ground levels (¹⁷¹Yb, ⁸⁷Sr) |
enc_spin_ld Single-spin (Loss–DiVincenzo) / nuclear-spin encoding |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | one carrier of several | a single electron spin in a dot |
enc_spin_ld Single-spin (Loss–DiVincenzo) / nuclear-spin encoding |
donor Donor spin (P in ²⁸Si) |
acts on the carrier | one carrier of several | the donor's electron or nuclear spin |
enc_spin_ld Single-spin (Loss–DiVincenzo) / nuclear-spin encoding |
defect Colour-centre / defect spin (NV, SiV, SnV, T centre) |
acts on the carrier | one carrier of several | the defect's electron or nuclear spin |
enc_dualrail Dual-rail (erasure) encoding |
cavity Bosonic cavity mode |
acts on the carrier | one carrier of several | two cavity modes, one excitation |
enc_dualrail Dual-rail (erasure) encoding |
transmon Transmon |
acts on the carrier | one carrier of several | two transmons, one excitation |
enc_dualrail Dual-rail (erasure) encoding |
photon Single photon (discrete variable) |
acts on the carrier | one carrier of several | two optical modes, one photon |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
code_surface Rotated surface code (+ yoked variants) |
decoder ↔ code | one code of several | graph-like syndromes |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
code_bosonic Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) |
decoder ↔ code | one code of several | repetition-cat syndromes |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
code_fusion Fusion-based fault tolerance |
decoder ↔ code | one code of several | fusion-network syndrome graph |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
code_erasure Erasure-adapted codes |
decoder ↔ code | one code of several | erasure-weighted matching |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
alkali Alkali atom (Rb/Cs) in optical tweezers |
acts on the carrier | one carrier of several | atoms to move |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
acts on the carrier | one carrier of several | atoms to move |
cx_bus Ion-chain motional bus (all-to-all in chain) |
ion Trapped atomic ion |
acts on the carrier | hard | collective motional modes of the chain |
g_anneal Quantum annealing (analogue evolution) |
fluxq rf-SQUID flux qubit (annealer) |
acts on the carrier | hard | Ising Hamiltonian of coupled flux qubits |
g_anneal Quantum annealing (analogue evolution) |
ct_fluxdac On-chip flux-DAC multiplexing |
signal delivery | hard | h and J programmed by flux DACs |
enc_eo Exchange-only / singlet–triplet spin encoding |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
built from other operations | hard | all operations by exchange pulses |
g_mbq Measurement-based Majorana gate |
enc_parity Fermion-parity encoding (tetron) |
needs a particular encoding | hard | acts on the tetron parity qubit |
g_tc Tunable-coupler CZ / iSWAP |
ct_rt Room-temperature electronics + per-qubit coax/flex |
signal delivery | one control route of several | flux pulses and microwave drive |
g_tc Tunable-coupler CZ / iSWAP |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
signal delivery | one control route of several | flux pulses and microwave drive |
g_cr Cross-resonance (fixed-frequency, all-microwave) |
ct_rt Room-temperature electronics + per-qubit coax/flex |
signal delivery | one control route of several | microwave drive at the target qubit's frequency |
g_cr Cross-resonance (fixed-frequency, all-microwave) |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
signal delivery | one control route of several | microwave drive at the target qubit's frequency |
g_bos Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) |
ct_rt Room-temperature electronics + per-qubit coax/flex |
signal delivery | hard | microwave pump tones |
g_mwspin Microwave / optical spin gates (defect centres, 1Q spins) |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
acts on the carrier | one carrier of several | ESR/EDSR single-spin rotations |
g_mwspin Microwave / optical spin gates (defect centres, 1Q spins) |
donor Donor spin (P in ²⁸Si) |
acts on the carrier | one carrier of several | ESR/NMR rotations |
g_tc Tunable-coupler CZ / iSWAP |
fluxonium Fluxonium |
acts on the carrier | one carrier of several | fluxonium CZ via a transmon coupler |
enc_bare Bare physical qubit (no encoding) |
fluxonium Fluxonium |
acts on the carrier | one carrier of several | two lowest fluxonium levels |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
fluxonium Fluxonium |
acts on the carrier | one carrier of several | dispersive shift of a fluxonium |
code_surface Rotated surface code (+ yoked variants) |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
the code's connectivity need | one connectivity of several | degree-4 checks by moving atoms |
code_color Colour code (transversal Cliffords) |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
the code's connectivity need | one connectivity of several | weight-6 checks by ion transport |
code_color Colour code (transversal Cliffords) |
cx_bus Ion-chain motional bus (all-to-all in chain) |
the code's connectivity need | one connectivity of several | all-to-all in the chain |
code_color Colour code (transversal Cliffords) |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
the code's connectivity need | one connectivity of several | checks by moving atoms |
dec_corr Correlated / loss-aware decoding (transversal, atom loss) |
code_aft Algorithmic FT / transversal architectures |
decoder ↔ code | one code of several | correlated decoding of transversal circuits |
dec_corr Correlated / loss-aware decoding (transversal, atom loss) |
code_erasure Erasure-adapted codes |
decoder ↔ code | one code of several | loss- and erasure-aware decoding |
code_erasure Erasure-adapted codes |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
decoder ↔ code | one decoder of several | erasure-weighted matching |
ro_spd Single-photon detection (SNSPD / TES) |
squeezed Squeezed light mode (CV) |
acts on the carrier | one carrier of several | photon-number-resolving detection of squeezed light |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
signal delivery | one control route of several | exchange pulses from cryo-CMOS |
ct_laser Laser + AOD/SLM optical control (atoms) |
fab_optics Optical / mechanical assembly (lasers, vacuum, objectives) |
fabrication route | hard | lasers, AOD/SLM, objectives |
cavity Bosonic cavity mode |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fabrication route | one manufacturing route of several | planar or on-chip bosonic modes |
photon Single photon (discrete variable) |
fab_mbe III-V MBE heterostructures (InAs–Pb wires, QD sources) |
fabrication route | one manufacturing route of several | quantum-dot single-photon sources |
squeezed Squeezed light mode (CV) |
fab_bulk Bulk-optics and fibre assembly (photonic samplers) |
fabrication route | one manufacturing route of several | bulk-optics OPO squeezers |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
ic_spinphoton Spin–photon solid-state link (SiV, NV, T centre) |
built from other operations | one connectivity of several | non-local checks over spin–photon links between nodes |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_shuttle Spin shuttling (conveyor mode) |
the code's connectivity need | one connectivity of several | non-local checks by spin shuttling |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_switch Photonic switching / routing (electro-optic, feed-forward) |
the code's connectivity need | one connectivity of several | non-local checks by photonic switching |
enc_dualrail Dual-rail (erasure) encoding |
ro_spd Single-photon detection (SNSPD / TES) |
measurement or heralding | one readout of several | photon loss heralded at detection |
g_fusion Linear-optical fusion (heralded) |
squeezed Squeezed light mode (CV) |
acts on the carrier | one carrier of several | fusion of GKP-encoded modes by beamsplitters and homodyne readout |
ro_disp Dispersive microwave readout (+TWPA, Purcell) |
fluxq rf-SQUID flux qubit (annealer) |
acts on the carrier | one carrier of several | dispersive shift of a resonator by the latched flux state (via a QFP) |
g_mwspin Microwave / optical spin gates (defect centres, 1Q spins) |
ct_base Baseband electrical control (spins, Majorana) |
signal delivery | one control route of several | microwave and baseband pulses on the spin |
g_mwspin Microwave / optical spin gates (defect centres, 1Q spins) |
ct_rt Room-temperature electronics + per-qubit coax/flex |
signal delivery | one control route of several | microwave drive from room temperature |
g_mbq Measurement-based Majorana gate |
ct_base Baseband electrical control (spins, Majorana) |
signal delivery | hard | gate voltages that set the measurement |
g_catcnot Bias-preserving cat–cat CNOT |
ct_rt Room-temperature electronics + per-qubit coax/flex |
signal delivery | hard | microwave drives of the cat modes |
ct_eo Electro-optic drive + feed-forward electronics (room temperature) |
fab_bulk Bulk-optics and fibre assembly (photonic samplers) |
fabrication route | one manufacturing route of several | fibre-coupled modulators and free-space optics |
alternatives (within layer)
alternatives (within layer)
| From | To | Note |
|---|---|---|
transmon Transmon |
fluxonium Fluxonium |
alternative superconducting carriers |
alkali Alkali atom (Rb/Cs) in optical tweezers |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
alternative atomic species |
photon Single photon (discrete variable) |
squeezed Squeezed light mode (CV) |
DV vs CV photonics |
qd_spin Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) |
donor Donor spin (P in ²⁸Si) |
dot vs donor spins |
enc_bare Bare physical qubit (no encoding) |
enc_dualrail Dual-rail (erasure) encoding |
bare vs erasure encoding |
enc_bare Bare physical qubit (no encoding) |
enc_cat Cat-code encoding (biased noise) |
bare vs cat |
enc_cat Cat-code encoding (biased noise) |
enc_gkp GKP grid encoding |
cat vs GKP |
enc_hf Hyperfine / clock-state qubit |
enc_omg Metastable ('omg') erasure encoding |
ground vs metastable manifold |
enc_hf Hyperfine / clock-state qubit |
enc_opt Optical narrow-line qubit (ion S–D, atom clock) |
hyperfine ground levels vs optical S–D qubit |
enc_eo Exchange-only / singlet–triplet spin encoding |
enc_spin_ld Single-spin (Loss–DiVincenzo) / nuclear-spin encoding |
encoded vs bare spin |
g_tc Tunable-coupler CZ / iSWAP |
g_cr Cross-resonance (fixed-frequency, all-microwave) |
tunable vs fixed-frequency |
g_ms Mølmer–Sørensen / light-shift laser gate |
g_elec Electronic microwave gate (ions, laser-free: near-field or static gradient) |
laser vs electronic gates |
g_fusion Linear-optical fusion (heralded) |
g_cv CV Gaussian gates + GKP-assisted non-Gaussian operations |
DV fusion vs CV Gaussian |
g_bos Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) |
g_catcnot Bias-preserving cat–cat CNOT |
ancilla-mediated vs direct cat CNOT |
cx_nn Static nearest-neighbour lattice |
cx_lr Long-range on-chip couplers (c-couplers, mm-scale) |
NN vs long-range couplers |
cx_qccd Ion shuttling (QCCD, junctions, grid traps) |
cx_bus Ion-chain motional bus (all-to-all in chain) |
shuttling vs chain bus |
cx_nn Static nearest-neighbour lattice |
cx_shuttle Spin shuttling (conveyor mode) |
static vs shuttled spins |
cx_nn Static nearest-neighbour lattice |
cx_crossbar Crossbar shared-line control (spins) |
individual vs shared lines |
ct_rt Room-temperature electronics + per-qubit coax/flex |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
RT vs 4 K control |
ct_rt Room-temperature electronics + per-qubit coax/flex |
ct_sfq SFQ digital control (4 K / mK) |
RT vs mK SFQ |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
ct_sfq SFQ digital control (4 K / mK) |
cryo-CMOS vs SFQ |
ct_rt Room-temperature electronics + per-qubit coax/flex |
ct_fluxdac On-chip flux-DAC multiplexing |
RT lines vs on-chip DACs |
ct_laser Laser + AOD/SLM optical control (atoms) |
ct_pic_trap PIC-generated tweezers / integrated optics for atoms |
free-space vs PIC optics |
ct_ionlaser Laser control with integrated photonics (ions) |
ct_ionmw Chip-integrated microwave control (ions) |
laser vs microwave ion control |
code_surface Rotated surface code (+ yoked variants) |
code_color Colour code (transversal Cliffords) |
surface vs colour |
code_surface Rotated surface code (+ yoked variants) |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
local (surface) vs non-local constant-rate qLDPC — alternatives for the same slot, combinable hierarchically (surface/LPU processing + gross memory) |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
code_highrate High-rate concatenated codes with transversal gates |
non-local BB memory (gross) vs high-rate transversal blocks ([[16,6,4]] tesseract, [[16,4,2,4]]) |
code_surface Rotated surface code (+ yoked variants) |
code_highrate High-rate concatenated codes with transversal gates |
2D vs high-rate transversal |
code_surface Rotated surface code (+ yoked variants) |
code_erasure Erasure-adapted codes |
Pauli vs erasure-adapted |
code_fusion Fusion-based fault tolerance |
code_bosonic Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) |
DV fusion FT vs GKP concatenation |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
dec_nn Neural decoders (AlphaQubit 2, CNN, transformers) |
matching vs neural |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
dec_relaybp Relay-BP for qLDPC (FPGA) |
matching vs BP |
dec_fpga FPGA real-time decoders (LCD, Deltaflow) |
dec_gpu GPU decoding via NVQLink |
FPGA vs GPU |
dec_fpga FPGA real-time decoders (LCD, Deltaflow) |
dec_cryo Cryogenic / on-chip decoder (cryo-CMOS, SFQ) |
RT FPGA vs cryo decoder |
ic_mcm Multi-chip modules / l-couplers (same cryostat) |
ic_cryolink Cryogenic microwave link between refrigerators |
same-fridge vs inter-fridge |
ic_cryolink Cryogenic microwave link between refrigerators |
ic_transducer Microwave–optical transducer (useful efficiency) |
microwave link vs optical link |
fab_sc Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) |
fab_3d 3D machined superconducting cavities |
planar vs 3D |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
fab_stm STM hydrogen-resist lithography (donors) |
foundry vs STM |
fab_trap Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) |
fab_cmos 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) |
MEMS vs standard CMOS fab for traps |
enc_hf Hyperfine / clock-state qubit |
enc_gr Ground–Rydberg analogue qubit |
hyperfine vs ground–Rydberg encoding |
g_ryd Rydberg-blockade CZ |
g_rydanalog Analogue Rydberg Hamiltonian evolution |
gate vs analogue Rydberg operation |
g_fusion Linear-optical fusion (heralded) |
g_lointer Programmable linear-optical interferometer (no entangling primitive) |
fusion vs sampling interferometer |
cx_aod Atom transport by AOD tweezers (zoned architecture) |
cx_reload Continuous atom reloading (reservoir + optical conveyor belt) |
one-shot loading vs continuous reload |
ct_ionlaser Laser control with integrated photonics (ions) |
ct_ionaod Free-space laser addressing of ions (AOM/AOD beams) |
integrated vs free-space laser delivery |
ct_ionmw Chip-integrated microwave control (ions) |
ct_ionaod Free-space laser addressing of ions (AOM/AOD beams) |
electronic vs free-space laser addressing |
ct_rt Room-temperature electronics + per-qubit coax/flex |
ct_vio Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring |
edge-routed vs vertical signal delivery |
ro_spd Single-photon detection (SNSPD / TES) |
ro_homodyne Homodyne quadrature detection (CV) |
photon counting vs homodyne detection |
code_surface Rotated surface code (+ yoked variants) |
code_detect Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) |
correcting vs detecting code |
code_surface Rotated surface code (+ yoked variants) |
code_mitig Error mitigation in the code slot (ZNE, PEC) — not a code |
a code vs error mitigation |
ic_mcm Multi-chip modules / l-couplers (same cryostat) |
ic_multidie Multi-die packaging in one module (flip-chip, bump-bonded control die) |
module-to-module vs die-to-die |
ic_mcm Multi-chip modules / l-couplers (same cryostat) |
ic_fanout Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) |
coupled modules vs signal fan-out |
fab_pic Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
fab_bulk Bulk-optics and fibre assembly (photonic samplers) |
photonic foundry vs bulk-optics assembly |
conflicts
conflicts
| From | To | Mechanism | Measured price | Mitigation | Status · source |
|---|---|---|---|---|---|
code_highrate High-rate concatenated codes with transversal gates |
cx_nn Static nearest-neighbour lattice |
needs all-to-all connectivity | no nearest-neighbour device has run a high-rate code beyond the four-qubit [[4,2,2]] detection code; on a static lattice the non-local checks need SWAP networks whose depth grows with the check span, and errors accumulate with it | long-range on-chip couplers (IBM c-couplers, Loon 2025-11) or physical transport (atoms, ions) | open — no mitigation shown at scale · 2025-06 |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
cx_nn Static nearest-neighbour lattice |
needs degree ≥ 6; heavy-hex insufficient without c-couplers | bivariate bicycle codes need a degree-6 Tanner graph — two long-range connections per qubit — which heavy-hex (degree 2–3) cannot provide; without c-couplers no gross code runs | c-couplers (Loon), then Kookaburra module; measured coupler fidelity and length not yet published | open — no mitigation shown at scale · 2024-03 |
code_aft Algorithmic FT / transversal architectures |
cx_nn Static nearest-neighbour lattice |
transversal permutations need transport | transversal gates between logical blocks need block-to-block qubit permutations; on a static lattice that is O(d) SWAP depth per logical gate, which erases the constant-depth advantage | physical transport (AOD tweezers, ion shuttling) — the reason the architecture is atom/ion-native | bypassed by choosing another technology in place of one of the two · 2025-09 |
enc_cat Cat-code encoding (biased noise) |
code_surface Rotated surface code (+ yoked variants) |
unbiased code wastes the bias — needs repetition/XZZX/elevator codes | a CSS surface code corrects X and Z symmetrically, so a bias > 25 (Ocelot, 2025) buys nothing; the ~10× qubit saving of cat architectures exists only with bias-tailored codes | repetition (Ocelot), XZZX, elevator or LDPC-cat codes instead of the plain surface code | bypassed by choosing another technology in place of one of the two · 2025-02 |
enc_dualrail Dual-rail (erasure) encoding |
code_surface Rotated surface code (+ yoked variants) |
a surface code decoded without its erasure flags wastes the encoding — the flags must reach an erasure-aware decoder | a matching decoder that ignores erasure flags sees a threshold of 0.937% instead of 4.15% — the erasure advantage is lost entirely | erasure-aware decoding (heralded-loss matching) — a decoder change, not a hardware change | mitigated at small scale · 2022-01 |
ro_spd Single-photon detection (SNSPD / TES) |
code_surface Rotated surface code (+ yoked variants) |
destructive detection precludes repeated syndrome extraction on the same photon | a detected photon is gone: no repeated syndrome extraction on the same carrier, so a surface-code memory cycle cannot be run on flying qubits | fusion-based / measurement-based fault tolerance, where every photon is measured exactly once by design | bypassed by choosing another technology in place of one of the two · 2023-02 |
g_ms Mølmer–Sørensen / light-shift laser gate |
cx_bus Ion-chain motional bus (all-to-all in chain) |
gate time grows with chain length (median 672 µs on Forte's 30-ion chain) | spectral crowding of the motional modes makes the gate slower and less faithful as the chain grows: median 672 µs on Forte's 30-ion chain vs ~10–30 µs on short chains | short chains in zoned QCCD traps (Quantinuum), amplitude/phase-modulated gates, or electronic gates on ≤ 4-ion segments | open — no mitigation shown at scale · 2025 |
fab_3d 3D machined superconducting cavities |
cx_nn Static nearest-neighbour lattice |
cm-scale cavities cannot tile dense 2D lattices | cm-scale machined cavities give ~1 mode per cm²; a dense 2D lattice of them is impossible, so 3D bosonic qubits stop at a few tens of modes per module | mm-scale coaxial λ/4 and double-post cavities, or planar bosonic modes; density still an order below transmon lattices | open — no mitigation shown at scale · 2026-07 |
cx_crossbar Crossbar shared-line control (spins) |
g_exch Exchange gate (spins; incl. shuttled-spin CZ) |
shared lines vs per-pair exchange calibration | one shared line drives many exchange gates at once, but J varies dot-to-dot with disorder; the 2024 16-dot crossbar showed no coherent qubit operation | 300 mm uniformity (~1% device-to-device), local floating-gate trims, or a semi-shared scheme with per-qubit correction lines | open — no mitigation shown at scale · 2024-07 |
ct_sfq SFQ digital control (4 K / mK) |
transmon Transmon |
SFQ switching photons cause quasiparticle poisoning unless shielded (0.96% error source in 2023 MCM) | photons emitted by switching junctions lie above the aluminium gap (2Δ ≈ 90 GHz) and break Cooper pairs in the qubit film: T1 decay plus correlated, non-Pauli bursts; 0.96(2)% of the 1.2(1)% error per Clifford in the 2023 multi-chip module | driver on a separate die, pulse-bandwidth limiting (projected 0.1%), quasiparticle traps / gap engineering, mm-wave shielding; SEEQC 2026 reports no detectable poisoning at 5 qubits (press, not independently measured) | open — no mitigation shown at scale · 2023-09 |
code_color Colour code (transversal Cliffords) |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
colour-code syndromes contain three-body (hyperedge) events that pairwise matching cannot decode | weight-6 checks produce detection events that fire in triples; a plain matcher is not applicable, and the decoders that are (restriction, Möbius, Chromobius) lose accuracy — Google's d=5 colour memory reached 8.19(14)×10⁻³ per cycle with the search-based Tesseract decoder, worse than its d=5 surface code | hyperedge-capable decoders: Chromobius / restriction decoders, Tesseract (search), neural decoders; hook-free one-ancilla circuits (2026) reduce the hyperedge burden | mitigated at small scale · 2026-07 |
dec_gpu GPU decoding via NVQLink |
transmon Transmon |
GPU decoding over NVQLink adds a ~4 µs round trip to a ~1 µs surface-code cycle | NVQLink's measured round trip is 3.84 µs mean / 3.96 µs max, i.e. 3–4 surface-code cycles of a Willow-class transmon (~1.1 µs): syndromes queue faster than any single-cycle reaction, so real-time feed-forward (non-Clifford, teleportation) must wait | windowed / streaming decoding with an FPGA predecoder at the fridge, deferring only the reaction-critical decisions; slower carriers (atoms, ions: ms cycles) do not see the conflict | open — no mitigation shown at scale · 2025-11 |
cx_reload Continuous atom reloading (reservoir + optical conveyor belt) |
alkali Alkali atom (Rb/Cs) in optical tweezers |
scattered cooling and MOT light reaching stored qubits | a separate MOT region 0.5 m away with conveyor transport, or a reservoir a few hundred µm away with molasses stopping | dynamical decoupling of the stored qubits; spatial separation | mitigated at small scale · 2025-09 |
cx_reload Continuous atom reloading (reservoir + optical conveyor belt) |
ae_atom Alkaline-earth(-like) atom (Yb/Sr) — erasure-native |
MOT light and repumper depleting stored atoms | the MOT run without the repumper; stored atoms shelved in ³P₀ (13 s lifetime) | shelving; separation | mitigated at small scale · 2024-02 |
code_qldpc Non-local qLDPC codes (bivariate bicycle, 'gross') |
dec_mwpm MWPM / Sparse Blossom (+ correlated matching) |
one fault of a bivariate bicycle code flips three checks (hyperedges); pairwise matching cannot decode it | no matching decoder has run a bivariate bicycle code: the syndrome graph has hyperedges, so the decoders that run it are BP+OSD (offline) and Relay-BP (real-time, FPGA) | Relay-BP (dec_relaybp) or BP+OSD; matching stays for the surface-like codes | bypassed by choosing another technology in place of one of the two · 2025-06 |
g_cr Cross-resonance (fixed-frequency, all-microwave) |
code_surface Rotated surface code (+ yoked variants) |
collision-free fixed frequencies force a sparse heavy-hex lattice; the degree-4 surface code then needs flag qubits and longer rounds | a cross-resonance lattice avoids frequency collisions by keeping the degree at 2–3 (heavy-hex); the surface code's weight-4 checks then need flag qubits, a longer syndrome circuit and a lower threshold than on a degree-4 lattice | tunable couplers (g_tc) — IBM's move from Eagle's cross-resonance to Heron's tunable couplers, still on heavy-hex; the degree-4 square lattice came with Nighthawk (2025); or heavy-hex codes on the cross-resonance lattice | bypassed by choosing another technology in place of one of the two · 2020-01 |
ro_img Fluorescence imaging of atom arrays |
enc_hf Hyperfine / clock-state qubit |
same-species imaging light scattered and re-absorbed dephases the hyperfine data atoms | a mid-circuit image of one atom scatters resonant light that the stored hyperfine qubits absorb; without separation or shelving the data qubits decohere during every measurement | a separate readout zone reached by transport (cx_aod), a second species, or shelving the data qubits in metastable levels (enc_omg) | mitigated at small scale · 2023-05 |
ro_fluor Fluorescence state detection (ions, defects) |
enc_hf Hyperfine / clock-state qubit |
fluorescence-detection light reaches spectator ions during mid-circuit readout | detection light on one ion reaches its neighbours in the same chain; mid-circuit measurement of a hyperfine qubit therefore needs distance or a hidden manifold | zoned QCCD traps that move the measured ion away (cx_qccd), a second species, or metastable shelving (enc_omg) | mitigated at small scale · 2021-04 |
ic_transducer Microwave–optical transducer (useful efficiency) |
transmon Transmon |
the transducer's optical pump at the millikelvin stage creates quasiparticles and heats the qubit chip | the optical pump light that drives the conversion reaches the mixing chamber: its stray light breaks Cooper pairs and heats the stage, so the first qubit-to-photon transduction ran the pump pulsed at a low duty cycle | pulsed, low-duty-cycle pumping; the transducer on a separate chip or module with filtered optical access | open — no mitigation shown at scale · 2020-12 |
ct_cryocmos Cryo-CMOS controller (4 K / mK) |
transmon Transmon |
milliwatt-class CMOS dissipation at the mixing chamber against a cooling budget of tens of microwatts | a full CMOS controller dissipates milliwatts; the mixing chamber of a dilution refrigerator offers tens of microwatts, so the controller sits at 3–4 K (< 2 mW per channel set, 2019) and only microwatt-class parts — multiplexers, switches — go beside the transmons | the controller at the 4 K stage with wiring down to the qubits; a millikelvin multiplexer that routes pulses without generating them; spin qubits operated at ~1 K do not see the conflict | mitigated at small scale · 2019-11 |
ct_sfq SFQ digital control (4 K / mK) |
fluxonium Fluxonium |
switching photons above 2Δ break Cooper pairs in the junction film — the transmon mechanism, not yet measured on a fluxonium | inferred from the transmon case: the same aluminium junctions, the same pair-breaking photons; no fluxonium driven by SFQ pulses has been reported, and a fluxonium biased at half flux is less sensitive to quasiparticle tunnelling than a transmon (Pop et al. 2014), so the price may be lower | as for the transmon: the driver on a separate die, bandwidth limiting, quasiparticle traps, shielding | open — no mitigation shown at scale · 2023-09 |
squeezed Squeezed light mode (CV) |
cx_switch Photonic switching / routing (electro-optic, feed-forward) |
loss adds vacuum noise: after a fraction 1−η of loss no more than −10·log₁₀(1−η) dB of squeezing survives, so the ~10 dB GKP needs put the switch's loss budget below 10 % | the fault-tolerance threshold of a GKP architecture is stated as ~10 dB of effective squeezing; a total loss of 1 dB on the route (η = 0.79) caps the reachable squeezing at 6.9 dB and 0.46 dB (η = 0.9) at 10 dB, so the switch budget is the tightest number of the architecture | loss budgets per mode and switch, the lowest-loss switch technologies (BTO, MEMS), or a discrete-variable encoding where loss is a heralded erasure | open — no mitigation shown at scale · 2021-02 |
defines (node → output; every row carries a source, a date and a number)
defines (node → output; every row carries a source, a date and a number)
| Node | Output | Metric | Value | Date | Source |
|---|---|---|---|---|---|
transmon |
error channel | Willow mean T1 / T2,CPMG | 68 µs / 89 µs (QEC chip) | 2024-12 | https://www.nature.com/articles/s41586-024-08449-y |
transmon |
error channel | Willow mean simultaneous CZ error | 0.33 ± 0.18% (spec sheet) | 2024-12 | https://quantumai.google/static/site-assets/downloads/willow-spec-sheet.pdf |
transmon |
error channel | correlated burst rate | ~1 per hour on the 72-qubit processor (d=29 repetition code, 3×10⁹ cycles); decay ~400 µs; 10⁻¹⁰ logical floor | 2024-12 | https://arxiv.org/abs/2408.13687 |
fluxonium |
error channel | record 2Q (CNOT, Manucharyan group) | 99.94% in 60 ns, > 99.9% over 24 days | 2024-07 | https://arxiv.org/abs/2407.15783 |
fluxonium |
error channel | MIT FTF CZ (RL-optimised mean) | 99.922% | 2023-09 | https://journals.aps.org/prx/abstract/10.1103/PhysRevX.13.031035 |
cavity |
error channel | cavity single-photon lifetime (Al, Yale) | 10 ms | 2013 | https://arxiv.org/abs/1302.4408 |
cavity |
error channel | cavity-qubit coherence (Weizmann) | T1 25.6 ms / T2 34 ms | 2023-09 | https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.030336 |
ion |
error channel | Helios (98 q) 2Q / SPAM | 7.9×10⁻⁴ / 4.8×10⁻⁴ | 2025-11 | https://arxiv.org/abs/2511.05465 |
ion |
error channel | memory | > 1 hour single-qubit coherence | 2021 | https://arxiv.org/abs/2008.00251 |
alkali |
count with quality | atoms with coherence | 6,100 Cs atoms, T2 12.6(1) s, 23-min trap lifetime (Caltech) | 2024-03 | https://arxiv.org/abs/2403.12021 |
alkali |
count with quality | continuous operation | > 3,000 qubits held > 2 h; 300,000 atoms/s reloaded into tweezers, 30,000 initialised qubits/s | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 |
alkali |
count with quality | trapped (no gates) | 11,022 Rb atoms in 18,225 metasurface tweezers | 2026-06 | https://arxiv.org/abs/2606.02715 |
ae_atom |
error channel | erasure conversion demonstrated | 56% of 1Q errors → erasures (¹⁷¹Yb) | 2023-05 | https://arxiv.org/abs/2305.05493 |
ae_atom |
error channel | Yb CZ | 99.72% post-selected / 99.40% raw | 2024-11 | https://arxiv.org/abs/2411.11708 |
photon |
error channel | source purity / HOM (Omega) | 99.5% / 99.5% | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
photon |
error channel | QD source system efficiency | 71.2% (first above 2/3 loss threshold) | 2023-11 | https://arxiv.org/abs/2311.08347 |
squeezed |
error channel | on-chip GKP effective squeezing (Xanadu) | 0.62 dB vs ~9.75 dB required | 2025-06 | https://www.nature.com/articles/s41586-025-09044-5 |
squeezed |
error channel | on-chip raw squeezing (poled TFLN) | 1.4 dB measured (> 10 dB loss-corrected) | 2025-08 | https://arxiv.org/abs/2508.08599 |
qd_spin |
error channel | 2Q on 300 mm foundry wafer | 99.04–99.56% (Diraq/imec) | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 |
qd_spin |
count with quality | largest arrays | 18 qubits (Groove/QuTech Ge; HRL EO) | 2026-04 | https://arxiv.org/abs/2604.01063 |
donor |
error channel | nuclear-spin gates (range reported) | 99.5–99.99%; Bell > 99% (single 99.90(4)% CZ not isolable in the abstract) | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w |
defect |
error channel | NV gate errors (GST) | < 0.1% [P] — press release only, no primary paper | 2025-03 | https://thequantuminsider.com/2025/03/28/fujitsu-and-qutech-realize-high-precision-quantum-gates/ |
majorana |
error channel | single-nanowire parity switching time | 22 ± 1 s Z-parity lifetime in one wire of one tetron (not a qubit lifetime); two-loop device Z 12.4 ms vs X 14.5 µs (2025) | 2026-06 | https://arxiv.org/abs/2606.03884 |
fluxq |
count with quality | Advantage2 | 4,400+ qubits, degree 20 | 2025-05 | https://thequantuminsider.com/2025/05/20/d-wave-announces-general-availability-of-advantage2-quantum-computer/ |
enc_bare |
error channel | leakage suppression | 72× (all-microwave reset), residual 6.4×10⁻⁴ after 40 cycles | 2025-12 | https://journals.aps.org/prl/abstract/10.1103/rqkg-dw31 |
enc_hf |
error channel | leakage per 1Q Clifford (Helios) | 1.1×10⁻⁵ | 2025-11 | https://arxiv.org/abs/2511.05465 |
enc_opt |
error channel | D₅/₂ lifetime (⁴⁰Ca⁺), the encoding's ceiling | τ = 1.17 s (AQT demonstrator, ⁴⁰Ca⁺ |4S₁/₂,m=−1/2⟩–|3D₅/₂,m=−1/2⟩ at 729 nm) | 2021-01 | https://arxiv.org/abs/2101.11390 |
enc_omg |
error channel | erasure fraction (theory) | 98% of errors convertible (¹⁷¹Yb) | 2022-01 | https://arxiv.org/abs/2201.03540 |
enc_omg |
error channel | [[4,2,2]] with erasure info | logical decay 1.9(4)× slower (unconditional decoding) | 2026-06 | https://arxiv.org/abs/2506.13724 |
enc_dualrail |
error channel | cavity dual-rail CZ | erasure 0.53%/gate, residual Pauli < 0.1%, 500 ns | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y |
enc_dualrail |
error channel | transmon dual-rail | erasure 2.5×10⁻²/check, residual 6×10⁻⁴, bias 42 | 2026-04 | https://arxiv.org/abs/2604.16292 |
enc_cat |
error channel | bit-flip time | 44 min mean (12-cat chip, preliminary); 22 s squeezed cat | 2025-09 | https://alice-bob.com/newsroom/alice-bob-surpasses-bit-flip-stability-record |
enc_cat |
error channel | phase-flip per CX (Ocelot) | 9.6(4)×10⁻² at n̄=2 (bit-flip 3.5(4)×10⁻³); bias > 25 under the gate, > 30 idle | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 |
enc_gkp |
error channel | single-mode GKP logical error | 8.1×10⁻³/round (survival 0.24×0.39) | 2026-07 | https://arxiv.org/abs/2607.06718 |
enc_gkp |
error channel | GKP qudit gain beyond break-even (UCSB + Google) | 1.82–1.87 | 2025-05 | https://www.nature.com/articles/s41586-025-08899-y |
enc_gkp |
error channel | best bosonic memory gain (GKP, Yale) | 2.27(7) | 2023-03 | https://www.nature.com/articles/s41586-023-05782-6 |
enc_eo |
error channel | EO 1Q error (18 qubits) | 2×10⁻⁴ mean | 2026-07 | https://arxiv.org/abs/2604.16216 |
enc_parity |
error channel | Z / X parity lifetimes | 12.4 ms / 14.5 µs in the quoted tuning (~9.3 ms / ~4 µs in others; the ~10³ ratio is robust, the point values are not) | 2025-07 | https://arxiv.org/abs/2507.08795 |
g_tc |
error channel | record CZ (tunable coupler, IQM) | 99.93% over 40 h | 2025-08 | https://arxiv.org/abs/2508.16437 |
g_tc |
error channel | record CZ (double-transmon coupler) | 99.90% in 48 ns | 2024-11 | https://journals.aps.org/prx/abstract/10.1103/PhysRevX.14.041050 |
g_tc |
clock (cycle time) | gate time (Willow) | ~30 ns CZ | 2024-12 | https://www.nature.com/articles/s41586-024-08449-y |
g_tc |
error channel | fleet EPLG (full width) | best 0.19% (ibm_boston), typical 0.37% | 2026-07 | https://www.ibm.com/quantum/blog/whats-new-q2-2026 |
g_cr |
error channel | CR CNOT with intrinsic static-ZZ suppression (Kandala) | 99.77(2)% in a single 180 ns pulse | 2021 | https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.127.130501 |
g_ryd |
error channel | record CZ | 99.854% raw / 99.941% loss-post-selected | 2026-04 | https://arxiv.org/abs/2604.25987 |
g_ryd |
clock (cycle time) | gate time | 270 ns | 2025-06 | https://arxiv.org/abs/2506.20661 |
g_ms |
error channel | Helios 2Q | 7.9×10⁻⁴ in ~70 µs | 2025-11 | https://arxiv.org/abs/2511.05465 |
g_ms |
clock (cycle time) | IonQ Forte MS duration (30-ion chain, all 435 pairs) | 550–883 µs (median 672 µs) | 2023-08 | https://arxiv.org/abs/2308.05071 |
g_ms |
clock (cycle time) | fastest laser gate (Schäfer et al., Oxford) | 99.8% at 1.6 µs | 2018 | https://arxiv.org/abs/1709.06952 |
g_elec |
error channel | record 2Q | 8.4×10⁻⁵ without ground-state cooling | 2025-10 | https://arxiv.org/abs/2510.17286 |
g_elec |
clock (cycle time) | gate duration | 225.8 µs (2025); ≈120 µs in 2024 (two 60 µs pulses, arXiv:2407.07694) | 2025-10 | https://arxiv.org/html/2510.17286 |
g_exch |
error channel | foundry CZ | 99.04–99.56% (300 mm) | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 |
g_exch |
error channel | EO CNOT best / mean | 9×10⁻⁴ / 3×10⁻³ | 2026-07 | https://arxiv.org/abs/2604.16216 |
g_exch |
clock (cycle time) | mobile-spin CZ | 98.86% in 58 ns | 2026-05 | https://www.nature.com/articles/s41586-026-10423-9 |
g_fusion |
error channel | fusion Bell fidelity | 99.22% | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
g_bos |
error channel | dual-rail cavity CZ | post-selected infidelity 0.029% (bound 0.12%), 500 ns | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y |
g_bos |
error channel | cavity beamsplitter (DC-SQUID coupler) | > 99.98%, ~100 ns swaps | 2023-03 | https://arxiv.org/abs/2303.00959 |
g_mbq |
error channel | status | no two-qubit operation, no entanglement | 2026-06 | https://arxiv.org/abs/2606.03884 |
g_anneal |
clock (cycle time) | coherent quench | 3.6–27 ns | 2025-03 | https://arxiv.org/abs/2403.00910 |
cx_nn |
count with quality | Nighthawk | 120 q, 218 couplers, 5,000 2Q gates/circuit | 2025-11 | https://newsroom.ibm.com/2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance |
cx_nn |
error channel | CZ crosstalk (fitted budget term, Willow d=7) | 5.5×10⁻⁴ | 2024-08 | https://arxiv.org/abs/2408.13687 |
cx_lr |
scaling path | long-range CZ | 99.81% over ≥ 2 mm | 2023 | https://arxiv.org/abs/2208.09460 |
cx_lr |
scaling path | IBM Loon | c-couplers + multilayer routing shown, no performance numbers | 2025-11 | https://newsroom.ibm.com/2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance |
cx_qccd |
clock (cycle time) | time per full-width layer (Helios) | ~55 ms | 2025-11 | https://arxiv.org/html/2511.05465v1 |
cx_qccd |
scaling path | junction transport | 4 m/s, 0.013–0.03 quanta/round trip | 2022 | https://arxiv.org/abs/2206.11888 |
cx_qccd |
scaling path | grid-trap ion exchange | 2.5 kHz | 2024-03 | https://arxiv.org/abs/2403.00756 |
cx_qccd |
scaling path | two-module matter link (Universal Quantum) | 2,424 transfers/s, loss infidelity < 7×10⁻⁸ | 2023-02 | https://www.nature.com/articles/s41467-022-35285-3 |
cx_bus |
count with quality | independently benchmarked chain (Forte) | 30 ions, all 435 pairs | 2023-08 | https://arxiv.org/abs/2308.05071 |
cx_bus |
count with quality | largest chain demonstrated (Tempo development system) | 64-qubit register, #AQ 64 [C] — IonQ's own benchmark, no per-pair data; the 100-qubit product is listed for late 2026 | 2025-09 | https://www.ionq.com/blog/ionq-hits-aq-64-milestone-ahead-of-schedule-and-sets-its-sights-even-higher |
cx_aod |
clock (cycle time) | move time | 610 µm in 1.6 ms at 99.95%; 270 µm in 400 µs at 99.8% | 2025-09 | https://arxiv.org/abs/2403.12021 |
cx_aod |
count with quality | zoned FT processor | 448 atoms, 256 in entangling zone | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 |
cx_reload |
clock (cycle time) | reload flux | ≈ 300,000 atoms/s into tweezers; > 30,000 initialised qubits/s (15,000/s sorted into defect-free batches) | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 |
cx_reload |
count with quality | continuous run | > 2 h, > 5 × 10⁷ atoms cycled through a 3,000-qubit array | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 |
cx_shuttle |
scaling path | conveyor shuttling | 10 µm, 99.54%, up to 64 m/s | 2025-06 | https://www.nature.com/articles/s41565-025-01920-5 |
cx_shuttle |
scaling path | weight-4 parity via shuttled ancilla | 97.7% per shuttle | 2026-07 | https://www.nature.com/articles/s41586-026-10766-3 |
cx_switch |
error channel | best in-line switch (PsiQuantum BTO) | 100 mdB insertion; 52(12) mdB fibre-to-chip | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
cx_switch |
error channel | system-scale switch loss (Aurora) | 0.19 dB/MZI; requirement ≈ 7 mdB | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 |
cx_switch |
error channel | BTO phase shifter | 0.33 dB·V | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
cx_crossbar |
scaling path | control lines vs dots (no coherent qubit operation) | 23 lines for 16 dots | 2024-01 | https://www.nature.com/articles/s41565-023-01491-3 |
ct_rt |
scaling path | I/O wall | > 4,000 high-density rf lines per fridge | 2026 | https://bluefors.com/ |
ct_rt |
count with quality | largest single-fridge chip | 1,121 qubits (Condor) | 2023-12 | https://www.ibm.com/quantum/blog/quantum-roadmap-2033 |
ct_cryocmos |
scaling path | HRL 4 K controller sequencing QEC | ≤ 3.5 W, 366 DACs; d=5 bit-flip-only repetition code Λ=4.7 without room-temperature real-time electronics (arXiv Apr–May 2026, Nature Jul 2026) | 2026-07 | https://arxiv.org/abs/2604.16216 |
ct_cryocmos |
scaling path | IBM 14 nm at 4 K | 23 mW/qubit; 1Q 8×10⁻⁴ | 2024-02 | https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.5.010326 |
ct_cryocmos |
scaling path | mK CMOS next to spin qubits | ~20 nW/MHz per cell; fidelity impact 0.07% | 2025-06 | https://www.nature.com/articles/s41586-025-09157-x |
ct_sfq |
scaling path | SEEQC mK SFQ control | 1Q > 99%, up to 99.9% (Nature Electronics) | 2026-03 | https://www.nature.com/articles/s41928-026-01576-6 |
ct_sfq |
scaling path | DigiQ: A Scalable Digital Controller for Quantum Computers Using SFQ Logic, HPCA 2022 | 4 K in-fridge SFQ controller; the largest designs fit the few-watt budget of the 4 K stage | 2022-02 | https://arxiv.org/abs/2202.01407 |
ct_sfq |
scaling path | QP-poisoning-limited SFQ MCM | 1.2% error/Clifford, 0.96% from photon-mediated QP | 2023-07 | https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.030310 |
ct_fluxdac |
scaling path | bias lines per qubits | ~300 bias lines into the QPU, of which ~200 multiplexed lines address ~10⁵ on-chip DACs (whitepaper 2026-01-23); fluxonium MCM at 10 mK | 2026-01 | https://www.dwavequantum.com/media/41upubz2/14-1090a-a_fluxonium-dac-control.pdf |
ct_laser |
count with quality | SLM array | ~12,000 sites, 6,100 atoms | 2025-09 | https://arxiv.org/abs/2403.12021 |
ct_laser |
scaling path | metasurface tweezers | 18,225 traps from 33 W | 2026-06 | https://arxiv.org/abs/2606.02715 |
ct_pic_trap |
scaling path | on-chip traps | 4 Rb atoms, 27.5 s lifetime | 2026-08 | https://www.pasqal.com/newsroom/pasqal-brings-qubit-control-on-chip/ |
ct_ionlaser |
scaling path | waveguide-delivered 2Q gate | > 99.3% | 2020-10 | https://www.nature.com/articles/s41586-020-2823-6 |
ct_ionmw |
error channel | chip-integrated microwave 1Q | 1.5×10⁻⁷ error per Clifford | 2024-12 | https://arxiv.org/abs/2412.04421 |
ct_ionmw |
scaling path | WISE architecture | 1,000 ions with ~200 signal sources (design) | 2023 | https://arxiv.org/abs/2305.12773 |
ct_base |
error channel | extrinsic control share of CNOT error | ~80% (HRL) | 2026-07 | https://arxiv.org/abs/2604.16216 |
ro_disp |
clock (cycle time) | readout pulse / fidelity (IQM) | 240 ns pulse (≈280 ns full window) / 99.94% simultaneous assignment; QNDness 99.3% | 2025-09 | https://arxiv.org/abs/2508.16437 |
ro_disp |
error channel | at-scale readout error | ~1×10⁻² (fleet) | 2025-08 | https://www.ibm.com/quantum/hardware |
ro_fluor |
clock (cycle time) | fastest ion readout | 11 µs at 99.931% (¹⁷¹Yb⁺, MoSi SNSPD) | 2019 | https://www.nature.com/articles/s42005-019-0195-8 |
ro_fluor |
error channel | Helios SPAM | 4.8×10⁻⁴ | 2025-11 | https://arxiv.org/abs/2511.05465 |
ro_img |
clock (cycle time) | typical mid-circuit readout | ~0.5–1 ms; 0.46% bit-flip, 0.24% loss | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 |
ro_img |
clock (cycle time) | fast imaging (emerging) | 17.6 µs, 99.89% discrimination, 98.8% survival — neutral ¹⁷⁴Yb, spinless (not qubit-state-resolved) | 2026-08 | https://arxiv.org/html/2605.24175 |
ro_s2c |
clock (cycle time) | fast readout (Oakes et al., Quantum Motion; rf single-electron box) | 99.2% in < 6 µs | 2023-02 | https://journals.aps.org/prx/abstract/10.1103/PhysRevX.13.011023 |
ro_s2c |
error channel | best SPAM | 99.9% (100 µs integration) | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 |
ro_spd |
error channel | wafer-scale median on-chip efficiency (PsiQuantum Omega, 300 mm) | 93.4% at ~2 K | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
ro_spd |
error channel | best on-chip efficiency (laboratory device) | 99.73% | 2025-10 | https://www.nature.com/articles/s41377-025-02031-5 |
ro_qcap |
clock (cycle time) | readout | 1% error; SNR 1 in 3.6 µs | 2025-02 | https://www.nature.com/articles/s41586-024-08445-2 |
ro_qcap |
clock (cycle time) | independent replication (QuTech, InSb Kitaev chain) | ~1.85 ms dwell, SNR ~1.93 | 2026-02 | https://www.nature.com/articles/s41586-025-09927-7 |
ro_erasure |
clock (cycle time) | transmon dual-rail check | 384 ns; FP/FN ≈ separation error 0.8% (SNR 11.6) | 2026-04 | https://arxiv.org/abs/2604.16292 |
ro_erasure |
clock (cycle time) | cavity dual-rail check | 1.8 µs, FP 0.51% / FN 3.7% | 2025-01 | https://www.nature.com/articles/s41534-024-00944-4 |
ro_erasure |
clock (cycle time) | Yb erasure detection | 20 µs (1Q) / 420 µs (2Q) | 2023-05 | https://arxiv.org/abs/2305.05493 |
code_surface |
error channel | Λ (Willow, d=3→7) | 2.14 ± 0.02; d=7 record 7.72×10⁻⁴/cycle (Jul 2026) | 2026-07 | https://www.nature.com/articles/s41586-026-10759-2 |
code_surface |
error channel | Λ (USTC 107 q, d=7) | 1.40(6) | 2025-12 | https://journals.aps.org/prl/abstract/10.1103/rqkg-dw31 |
code_surface |
error channel | neutral-atom d=3→5 | 2.14(13)× in 4-round circuit | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 |
code_surface |
count with quality | teraquop footprint, plain patches (p=10⁻³) | ~1,500 physical/logical (800 with 1D yokes, 600 with 2D yokes) | 2023-12 | https://arxiv.org/abs/2312.04522 |
code_surface |
count with quality | teraquop footprint with correlated matching (p=10⁻³) | ~650 physical/logical | 2023-12 | https://arxiv.org/abs/2312.08813 |
code_color |
error channel | Λ₃/₅ (Google) | 1.56(4); logical Clifford 0.0027 | 2025-05 | https://www.nature.com/articles/s41586-025-09061-4 |
code_color |
error channel | 5-to-1 distillation on logical qubits | d=3: 95.1%→99.4%; d=5: 92.5%→98.6% | 2025-07 | https://www.nature.com/articles/s41586-025-09367-3 |
code_qldpc |
count with quality | gross code overhead | 288 physical for 12 logical (~24/logical) vs ~3,000 surface | 2024-03 | https://arxiv.org/abs/2308.07915 |
code_qldpc |
error channel | IonQ memories on a 40-ion ¹³³Ba chain: eight codes, BB [[18,4,3]] (4 logical in 18 ions) to [[30,4,5]] | 3.95 ± 0.68 s in one code the paper does not identify vs 3.84 ± 0.48 s physical (= 3 T2*; the June version gave 3.3 ± 0.9 s); BB [[18,4,3]] 2.48 ± 0.40 s; logical runs leakage-post-selected — break-even within error bars (arXiv version of 14 Sep 2026) | 2026-09 | https://arxiv.org/abs/2606.06455 |
code_qldpc |
error channel | Zhejiang [[18,4,4]] on 32 SC qubits | 8.91%/logical/cycle (not break-even) | 2025-05 | https://arxiv.org/html/2505.09684 |
code_qldpc |
count with quality | RSA-2048 with qLDPC (Pinnacle) | < 100,000 physical qubits at 10⁻³, 1 µs cycle | 2026-02 | https://arxiv.org/abs/2602.11457 |
code_highrate |
count with quality | Helios [[80,48,4]] | 48 corrected logical qubits; logical gate error 1.0–1.2×10⁻⁴ | 2026-02 | https://arxiv.org/abs/2602.22211 |
code_highrate |
count with quality | Harvard tesseract [[16,6,4]] | up to 96 d=4 logical qubits active | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 |
code_highrate |
count with quality | Quantinuum tesseract [[16,6,4]] on ions | transversal logical Clifford group in depth-one circuits, 12 addressable logical CZ pairs | 2026-06 | https://www.nature.com/articles/s41586-026-10628-y |
code_erasure |
error channel | threshold with 98% erasure | 4.15% vs 0.937% | 2022-01 | https://arxiv.org/abs/2201.03540 |
code_erasure |
error channel | [[4,2,2]] erasure teleportation (atoms) | logical decay 1.9(4)× slower with erasure info in unconditional decoding | 2026-06 | https://arxiv.org/abs/2506.13724 |
code_bosonic |
error channel | repetition-cat (Ocelot) | d=3 1.75% at |α|²=1 → d=5 1.65% at |α|²=1.5 per 2.8 µs cycle — different n̄, not a distance scan | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 |
code_bosonic |
count with quality | LDPC-cat estimate | 758 cats → 100 logical at 10⁻⁸ (assumes 0.1% phase-flip) | 2024-01 | https://arxiv.org/abs/2401.09541 |
code_bosonic |
count with quality | repetition-cat estimate (Gouzien et al.) | 126,133 cats for a 256-bit elliptic-curve logarithm in 9 h | 2023-02 | https://arxiv.org/abs/2302.06639 |
code_fusion |
error channel | loss threshold | 2.7% per photon (boosted 6-ring); 17.4% ({7,4}-encoded resource state) | 2025-06 | https://arxiv.org/abs/2506.11975 |
code_aft |
clock (cycle time) | rounds per logical gate | O(d) → O(1) | 2024-06 | https://arxiv.org/abs/2406.17653 |
code_aft |
count with quality | Shor / P-256 on reconfigurable atoms | 10,000 atoms minimum (26,000 time-efficient); P-256 in days, RSA-2048 one to two orders longer | 2026-03 | https://arxiv.org/abs/2603.28627 |
code_aft |
count with quality | RSA-2048 on reconfigurable atoms (ISCA 2025) | 5.6 days on 19 M qubits at a 1 ms cycle | 2025-05 | https://arxiv.org/abs/2505.15907 |
code_magic |
error channel | cultivation (Google) | 0.9999(1), 8% acceptance, 40× error reduction | 2025-12 | https://arxiv.org/abs/2512.13908 |
code_magic |
error channel | code switching (Quantinuum) | ≤ 5.1×10⁻⁴ at 82.6% acceptance | 2025-06 | https://arxiv.org/abs/2506.14169 |
dec_mwpm |
clock (cycle time) | PyMatching v2 throughput | < 1 µs/round at d=17, p=0.1% | 2023-03 | https://arxiv.org/abs/2303.15933 |
dec_mwpm |
clock (cycle time) | Micro Blossom FPGA (ASPLOS 2025) | 0.8 µs average latency at d=13, p=0.1% | 2025-02 | https://arxiv.org/abs/2502.14787 |
dec_nn |
error channel | Willow d=7 with AlphaQubit 2 | 7.72×10⁻⁴/cycle | 2026-07 | https://www.nature.com/articles/s41586-026-10759-2 |
dec_nn |
clock (cycle time) | FPGA NN decoder | 124 ns decode, 550 ns closed loop (d=3) | 2026-05 | https://arxiv.org/abs/2605.04892 |
dec_relaybp |
clock (cycle time) | FPGA Relay-BP | average < 1 µs per cycle at p < 3×10⁻³ (simulated syndromes) | 2025-10 | https://arxiv.org/abs/2510.21600 |
dec_fpga |
clock (cycle time) | Riverlane LCD | < 1 µs/round to d=17 | 2025-12 | https://www.nature.com/articles/s41467-025-66773-x |
dec_fpga |
clock (cycle time) | Google real-time at d=5 | 63 µs latency, Λ=2.0 | 2024-08 | https://arxiv.org/abs/2408.13687 |
dec_gpu |
clock (cycle time) | NVQLink RoCE round trip | 3.84 µs mean | 2025-10 | https://developer.nvidia.com/blog/nvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ |
dec_corr |
error channel | loss-aware ML decoding gain | 1.73(13)× | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 |
dec_rl |
error channel | RL-steered QEC | 20% LER cut, 3.5× stability vs drift; the same Willow d=7 run that yields 7.72(9)×10⁻⁴/cycle (see dec_nn) | 2025-11 | https://arxiv.org/abs/2511.08493 |
dec_cryo |
scaling path | QECOOL on-line SFQ decoder (simulation) | 2.78 µW at 2 GHz; latency not published | 2021-03 | https://arxiv.org/abs/2103.14209 |
dec_cryo |
clock (cycle time) | NISQ+ approximate SFQ decoder (design) | ≤ 20 ns latency | 2020-04 | https://arxiv.org/abs/2004.04794 |
dec_cryo |
scaling path | cryo-CMOS predecoder (design) | 3,780× syndrome-bandwidth reduction at < 0.56 mW | 2025-12 | https://arxiv.org/abs/2512.09807 |
ic_mcm |
count with quality | chiplet tiling | 108 q from 12 chiplets, median 2Q 99.1% (vs 99.5% at 36 q) | 2026-04 | https://investors.rigetti.com/news-releases/news-release-details/rigetti-announces-general-availability-108-qubit-system |
ic_mcm |
scaling path | coupled cryogenic cells | two cells coupled; 0.53 m² wiring area each | 2026-08 | https://www.ibm.com/quantum/blog/modular-cryogenics |
ic_cryolink |
error channel | 30 m link Bell fidelity / rate | 80.4% / 12.5 kHz | 2023-05 | https://www.nature.com/articles/s41586-023-05885-0 |
ic_cryolink |
scaling path | 2026 modular link | waveguide loss < 0.03 dB/30 m; end-to-end transfer loss 0.55–0.65 dB, i.e. 86–88% transmission | 2026-04 | https://arxiv.org/html/2604.15971v1 |
ic_ionphoton |
error channel | distributed CZ (Oxford) | remote Bell 96.9% at 9.7 s⁻¹; teleported CZ 86.2% | 2025-02 | https://www.nature.com/articles/s41586-024-08404-x |
ic_ionphoton |
clock (cycle time) | entanglement rate record | 250 s⁻¹ at F > 94% | 2024 | https://arxiv.org/abs/2404.16167 |
ic_atomcavity |
error channel | atom–photon efficiency (MPQ, Science 385, 179) | ~90% generation-to-detection | 2024-07 | https://arxiv.org/abs/2407.09109 |
ic_spinphoton |
error channel | SiV over 35 km | F = 0.69, ≤ 1 Hz | 2024-05 | https://www.nature.com/articles/s41586-024-07252-z |
ic_spinphoton |
error channel | NV Delft–The Hague 25 km | F = 0.534, 0.022 s⁻¹ | 2024-04 | https://arxiv.org/html/2404.03723 |
ic_spinphoton |
error channel | T-centre inter-cryostat link (Photonic Inc.) | Bell F = 0.60(8) at 7.5 mHz; teleported-CNOT sequence post-selected, no gate fidelity | 2024-06 | https://arxiv.org/html/2406.01704v1 |
ic_spinphoton |
error channel | NV unconditional teleported CNOT (QuTech) | 63(4)% (4-qubit GHZ 64(4)%), real-time feed-forward, no post-selection | 2026-05 | https://www.nature.com/articles/s41467-026-72818-6 |
ic_transducer |
error channel | state of the art (review) | η_int 99.5%, η_tot 15%, N_add 0.16 (EO, 60 mK) | 2026-05 | https://arxiv.org/html/2605.26976 |
ic_transducer |
scaling path | gap to useful | 3 orders of magnitude (noise, η, rate) for 99.7% remote gates at MHz | 2025-03 | https://arxiv.org/abs/2503.10842 |
ic_fibre |
error channel | chip-to-chip Bell fidelity | 99.72% over 42 m, conditional on heralded events (channel loss excluded) | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
fab_cmos |
scaling path | wafer-scale statistics | > 24,000 devices/wafer, CD < 0.5 nm | 2024-10 | https://arxiv.org/abs/2410.16583 |
fab_cmos |
scaling path | wafer-level yield (cryo-prober, 1.6 K) | 96% of 232 twelve-dot devices tuned to single-electron occupancy; 99.8% of dots | 2024-05 | https://www.nature.com/articles/s41586-024-07275-6 |
fab_cmos |
scaling path | multi-modality foundry LOI | GlobalFoundries $375 M (SC, ion, photonic, topological, spin) | 2026-05 | https://www.nist.gov/news-events/news/2026/05/department-commerce-announces-letters-intent-9-companies-2-billion |
fab_sc |
scaling path | junction frequency targeting (ABAA) | 97.4% success, 0.9 ± 2.4% of prediction | 2024-08 | https://www.nature.com/articles/s43246-024-00596-z |
fab_sc |
count with quality | wafer-scale package (OQC) | > 500 qubits on one 3-inch sapphire die; T1 ~97 µs, T2e ~129 µs; no per-qubit control lines in the measured configuration | 2026-02 | https://arxiv.org/abs/2602.12773 |
fab_sc |
scaling path | Anderon foundry | $1 B CHIPS + $1 B IBM; SC wiring/TSV/bump; 30× device output vs 200 mm | 2026-05 | https://www.tomshardware.com/tech-industry/quantum-computing/ibm-spins-off-americas-first-quantum-chip-foundry-with-2-billion-in-federal-and-private-funding |
fab_3d |
error channel | cavity Q (Al, Yale) | > 0.5×10⁹, single-photon lifetime 10 ms | 2013 | https://arxiv.org/abs/1302.4408 |
fab_trap |
scaling path | Helios trap | 1,228 electrodes, 273 independent signals (2.8 per qubit) | 2025-11 | https://arxiv.org/html/2511.05465 |
fab_trap |
scaling path | standard-fab traps | 99.99% 2Q on chips from standard semiconductor fabs | 2025-10 | https://www.ionq.com/news/ionq-achieves-landmark-result-setting-new-world-record-in-quantum-computing |
fab_pic |
error channel | SiN waveguide loss (multimode) | 0.5 dB/m | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
fab_pic |
error channel | SiN waveguide loss (single-mode) | 1.8(2) dB/m | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
fab_pic |
error channel | wafer-scale median on-chip SNSPD efficiency | 93.4% at ~2 K, 300 mm | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 |
fab_optics |
scaling path | system power / mass | 3 kW avg, 2,500 kg (Orion Gamma) | 2025-11 | https://www.pasqal.com/wp-content/uploads/2025/11/2509_Pasqal_Quantum-Computing-Processor_Brochure-RVB-V8.pdf |
fab_optics |
scaling path | continuous reload hardware | 300,000 atoms/s reloaded into tweezers; 30,000 initialised qubits/s | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 |
fab_mbe |
scaling path | replication | no independent replication of the InAs–Pb stack | 2026-06 | https://www.nature.com/articles/s41586-026-10567-8 |
fab_stm |
count with quality | register size | 11 qubits | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w |
fab_diamond |
scaling path | device yield | 327 cavities resonance-characterised at room temperature (mean Q 1.1(4)×10⁴); coherent cooperativity > 1 shown on 2 | 2026-06 | https://journals.aps.org/prx/abstract/10.1103/z514-v4n6 |
g_cv |
clock (cycle time) | Aurora clock | 1 MHz, 12 modes per cycle | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 |
g_mwspin |
error channel | NV 1Q/2Q (GST) | < 0.1% [P] — press release only, no primary paper | 2025-03 | https://thequantuminsider.com/2025/03/28/fujitsu-and-qutech-realize-high-precision-quantum-gates/ |
g_catcnot |
error channel | status | no experimental bias-preserving cat–cat CNOT | 2026-07 | https://arxiv.org/abs/2607.22852 |
src_resource |
count with quality | largest emitter-fused graph state | 8 qubits, 0.4–2.3 coincidences/min | 2024-05 | https://www.nature.com/articles/s41586-024-07357-5 |
src_resource |
count with quality | independent emitter graph states (C2N Paris-Saclay) | reconfigurable 4-photon graph states from one quantum dot, ~0.5 Hz | 2025-05 | https://www.nature.com/articles/s41467-025-59693-3 |
ct_eo |
clock (cycle time) | single-clock-cycle feed-forward | 1 MHz (Aurora) | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 |
7.9 Standard records — the dated numbers behind the derived clocks (nulls are honest: not published)
table
| Node | Quantity | Value | Scope | Date | Source · tag |
|---|---|---|---|---|---|
transmon |
T1 relaxation | 68 µs — Willow 105-qubit QEC chip: mean operating T1 = 68 µs (spec sheet: 68 +/- 13 µs; RCS chip 98 +/- 32 µs) | typical | 2024-12 | https://www.nature.com/articles/s41586-024-08449-y · [D] |
transmon |
T1 relaxation | 1.68 ms — Princeton Ta-on-Si 2D transmons: T1 up to 1.68 ms; median time-averaged Q_avg 9.7×10⁶ across 45 qubits | best | 2025-11 | https://www.nature.com/articles/s41586-025-09687-4 · [D] |
transmon |
T2 coherence (echo/DD) | 89 µs — Willow 105-qubit QEC chip: mean T2,CPMG = 89 µs | typical | 2024-12 | https://www.nature.com/articles/s41586-024-08449-y · [D] |
transmon |
1Q gate time | 25 ns — Willow 105 q: all XY single-qubit rotations 25 ns (72-q processor: pi 35 ns, pi/2 18 ns) | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
transmon |
idle / memory error per round | 0.009 — Google 72-q surface-code error budget: data-qubit idle error 0.9×10⁻² per cycle, weight 10, 20% of 1/Lambda | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
transmon |
leakage per gate | 0.0002 — Google error budget: CZ leakage 2.0×10⁻⁴ per gate; a separate 'leakage (heating)' term is 2.5×10⁻⁴ | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
transmon |
correlated-burst rate | 0.00028 Hz — 72-q processor, distance-29 repetition code: correlated error bursts approx. once an hour (3×10⁹ cycles), decay ~400 µs | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
fluxonium |
T1 relaxation | 1 ms — Somoroff et al. fluxonium: T1 stable around 1 ms over several months of operation | best | 2021-03 | https://arxiv.org/pdf/2103.08578 · [D] |
fluxonium |
T2 coherence (echo/DD) | 1.48 ms — Somoroff et al. fluxonium: Ramsey T2* = 1.48 +/- 0.13 ms; no spin-echo T2 is reported | best | 2021-03 | https://arxiv.org/pdf/2103.08578 · [D] |
fluxonium |
1Q gate time | 80 ns — Somoroff fluxonium X/2 and Y/2: Gaussian-edged square pulses, 60 ns plateau + 2x5 ns edges = 80 ns, >0.9999 avg fidelity | best | 2021-03 | https://arxiv.org/pdf/2103.08578 · [D] |
fluxonium |
idle / memory error per round | not published — fluxonium work reports coherence and gate fidelity only, no syndrome-extraction cycle. — No fluxonium QEC round has been run; no idle/memory error per round is published | typical | 2021-03 | https://arxiv.org/pdf/2103.08578 · [D] |
cavity |
T1 relaxation | 25.6 ms — Weizmann long-lived superconducting cavity: single-photon T1 = 25.6 ms | best | 2023-09 | https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.030336 · [D] |
cavity |
T2 coherence (echo/DD) | 34 ms — Weizmann: single-photon-encoded cavity qubit coherence T2 = 34 ms | best | 2023-09 | https://journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.030336 · [D] |
cavity |
1Q gate time | not published — Null to avoid duplicating g_bos: the mechanism, not the carrier, defines the single-qubit gate. — A bosonic mode has no intrinsic 1Q gate; the gate is ancilla- or beam-splitter-mediated and is recorded on g_bos (~200 ns) | typical | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y · [D] |
cavity |
idle / memory error per round | not published — bosonic results are quoted per gate (erasure, Pauli), never per syndrome round. — No cavity-qubit QEC round with a published per-round idle error; dual-rail 1Q gate erasure is ~0.1% | typical | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y · [D] |
ion |
T1 relaxation | 1.19×10⁴ s — Single 171Yb+ memory: T1 = 11,902 +/- 2,209 s from the process-matrix fit | best | 2020-08 | https://arxiv.org/pdf/2008.00251 · [D] |
ion |
T2 coherence (echo/DD) | 4.24×10³ s — Single 171Yb+ with KDDxy DD (0.4 s interpulse): T2 = 4,235 +/- 576 s; |0>,|1> coherence 15,943 +/- 3,190 s | best | 2020-08 | https://arxiv.org/pdf/2008.00251 · [D] |
ion |
1Q gate time | not published — Null on the carrier by design - the mechanism defines it; see g_ms and g_elec t1q records. — Ion 1Q gate time is set by the drive mechanism: laser Raman 110 µs (g_ms, IonQ Forte); near-field microwave 8 µs (g_elec) | typical | 2023-08 | https://arxiv.org/pdf/2308.05071 · [D] |
ion |
idle / memory error per round | 0.0005 — Quantinuum Helios (98 q): linear memory error rate 5(1)e-4 per qubit per transport-idle step; quadratic term 0.7(2)e-4 | typical | 2025-11 | https://arxiv.org/html/2511.05465v1 · [D] |
ion |
leakage per gate | 1.12×10⁻⁵ — Helios: single-qubit gate leakage 1.12(6)e-5 per Clifford; ternary readout shows 4.2(7)e-3 leakage population after prep | typical | 2025-11 | https://arxiv.org/html/2511.05465v1 · [D] |
alkali |
T1 relaxation | 1.38×10³ s — Caltech 6,100-atom Cs tweezer array: room-temperature trapping lifetime 23 minutes | best | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
alkali |
T2 coherence (echo/DD) | 12.6 s — Caltech 6,100 Cs atoms in ~12,000 tweezers: hyperfine qubit coherence T2 = 12.6(1) s | best | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
alkali |
1Q gate time | 5 µs — Harvard/QuEra 448-atom processor: global Raman path at ~0.5 MHz Rabi gives ~5 µs rotations (composite pulses) | typical | 2025-06 | https://arxiv.org/html/2506.20661v1 · [D] |
alkali |
idle / memory error per round | not published — idle/transport dephasing is folded into the logical per-round figure, not decomposed. — Not separately quantified: the 448-atom paper reports only combined logical error 0.62(3)% per round (d=5) and a 4 ms cycle | typical | 2025-06 | https://arxiv.org/html/2506.20661v1 · [D] |
alkali |
leakage per gate | 8×10⁻⁵ — 87Rb CZ: leakage to F=1 0.008(1)% per atom per gate (Rydberg T1 decay + intermediate-state scattering) | best | 2026-04 | https://arxiv.org/html/2604.25987v1 · [D] |
ae_atom |
T1 relaxation | 6.42 s — 171Yb nuclear-spin qubit: tweezer lifetime 6.42(3) s (parametric heating); spin depolarization tens of s, ~100 s with a few G | typical | 2021-12 | https://arxiv.org/pdf/2112.06732 · [D] |
ae_atom |
T2 coherence (echo/DD) | 7.9 s — 171Yb nuclear-spin qubit in tweezers: spin-echo T2 = 7.9(4) s; Ramsey T2* = 3.7(4) s | best | 2021-12 | https://arxiv.org/pdf/2112.06732 · [D] |
ae_atom |
1Q gate time | 170 ns — 171Yb nuclear-spin qubit: 170 ns pi/2 pulses (submicrosecond rotations), 5.2(5)e-3 error per Clifford | best | 2021-12 | https://arxiv.org/pdf/2112.06732 · [D] |
ae_atom |
idle / memory error per round | not published — Yb results are reported per gate (99.72% post-selected CZ) and as erasure fraction. — No alkaline-earth erasure-qubit QEC round with a published per-round idle/memory error | typical | 2024-11 | https://arxiv.org/abs/2411.11708 · [D] |
photon |
T1 relaxation | 0.0228 — PsiQuantum Omega: BTO electro-optic phase shifter insertion loss ~100 mdB (2 mm); SiN waveguide 0.5+/-0.3 dB/m multimode | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
photon |
T2 coherence (echo/DD) | not published — dephasing has no photonic counterpart; distinguishability plays that role. — No T2 for photons; the analogue is indistinguishability - HOM visibility 99.50(25)%, source spectral purity 99.5(1)% | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
photon |
1Q gate time | not published — the paper gives component losses and a loss-voltage product, not switching times. — 1Q gates on dual-rail photons are passive phase shifters and beam splitters; no gate duration is stated in the Omega paper | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
photon |
idle / memory error per round | not published — photonic FT is measurement-driven, so idle error is replaced by delay-line loss. — No photonic QEC round has been demonstrated; a fusion network has no idling syndrome cycle | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
squeezed |
T1 relaxation | 0.615 — Xanadu Aurora: refinery-chip insertion loss 4.15 dB average; heralded optical paths >95% total loss; sources chip 1.82 dB | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
squeezed |
T2 coherence (echo/DD) | not published — CV dephasing shows up as squeezing degradation (dB), not as a decay time. — No T2 for CV modes; Aurora reports nullifier variances held below vacuum noise over 2 h continuous acquisition | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
squeezed |
1Q gate time | not published — Null on the carrier by design to avoid duplicating the g_cv t1q record (1 µs per cycle). — 1Q Gaussian operations are clocked, not pulse-timed; the 1 MHz Aurora cycle is recorded on g_cv | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
squeezed |
idle / memory error per round | not published — Aurora needs a 20-30x (in dB) component-loss improvement before rounds exist. — No CV QEC round with a published per-round idle error; loss per round is the equivalent quantity and is unstated | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
qd_spin |
T1 relaxation | 9.5 s — 300 mm foundry Si/SiGe (Diraq/imec), device A: spin relaxation T1 = 9.5 s | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
qd_spin |
T2 coherence (echo/DD) | 1.9 ms — 300 mm foundry Si/SiGe device A: Hahn-echo T2 = 1.9 ms; Ramsey T2* = 40.6 µs. No CPMG reported | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
qd_spin |
1Q gate time | 400 ns — 300 mm foundry Si/SiGe: single-qubit (EDSR) gates ~400 ns at 99.45-99.97% fidelity; CZ 100-500 ns | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
qd_spin |
idle / memory error per round | not published — largest arrays are 18 qubits, below any syndrome-extraction demonstration. — No spin-qubit QEC round has been run; no idle/memory error per round is published | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
qd_spin |
leakage per gate | not published — the ERR attribute lists 'leak' for qd_spin but no primary source quantifies it. — Leakage to valley or triplet states per gate is not reported in the 300 mm foundry paper or its device tables | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
donor |
T1 relaxation | not published — those lifetimes are mean times between spontaneous flips during readout, not T1. — No T1 reported for the P donor electron or nuclear spin; the supplementary gives only readout-limited nuclear lifetimes 2,900 s / 7,900 s | best | 2014-02 | https://arxiv.org/pdf/1402.7140 · [D] |
donor |
T2 coherence (echo/DD) | 35.6 s — 28Si:P ionised 31P+ nuclear qubit: T2(DD) = 35.6 s, Hahn 1.75 s, T2* 0.6 s; electron T2(DD) = 0.56 s | best | 2014-02 | https://arxiv.org/pdf/1402.7140 · [D] |
donor |
T2 coherence (echo/DD) | 44.5 ms — SQC 11-qubit donor register: nuclear T2(Hahn) 3-660 ms (T2 1-46 ms); electron T2(Hahn) ~350 µs, T2 ~20 µs | typical | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w · [D] |
donor |
1Q gate time | not published — donor papers report control fidelity (99.10-99.99% 1Q) without gate times. — No pi-pulse duration in ns or us is stated in Muhonen 2014 or in the SQC 11-qubit paper; only fidelities are given | typical | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w · [D] |
donor |
idle / memory error per round | not published — the largest donor register is 11 qubits (9 nuclear data + 2 ancilla electrons). — No donor QEC round has been run; no idle/memory error per round is published | typical | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w · [D] |
defect |
T1 relaxation | 3.6×10³ s — NV electron spin in a 10-qubit diamond register (4 K): T1 = 3.6(3)e3 s, i.e. > 1 hour | best | 2019-05 | https://arxiv.org/pdf/1905.02094 · [D] |
defect |
T2 coherence (echo/DD) | 600 ms — NV electron spin: T2 ~ 0.6 s (580 ms) with 8192-pulse CPMG at 77 K in isotopically pure diamond | best | 2013-04 | https://www.nature.com/articles/ncomms2771 · [D] |
defect |
1Q gate time | 997 µs — Delft NV register: nuclear-spin 1Q gates via electron-controlled DD take 419-2,371 µs; electron MW Rabi is 14 MHz | typical | 2019-05 | https://arxiv.org/pdf/1905.02094 · [D] |
defect |
idle / memory error per round | not published — defect centres are used as network nodes; the logical-qubit work reports per-gate only. — No NV/SiV QEC round with a published per-round idle error | typical | 2019-05 | https://arxiv.org/pdf/1905.02094 · [D] |
majorana |
parity lifetime (single wire, not a qubit T1) | 22 s — InAs-Pb tetron, single wire: Z-parity lifetime 22 +/- 1 s (Poissonian fit, 200 ms integration, 324 dwell intervals) | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
majorana |
T2 coherence (echo/DD) | not published — The node's 'X loop 14.5 µs (2025)' figure was not found in the sources consulted. — No coherent superposition of a Majorana qubit has been prepared, so no T2 exists; only Z-basis parity switching is measured | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
majorana |
1Q gate time | not published — Parity readout takes 3.6 µs for SNR 1 (InAs-Al, 2025) but is not a gate. — No Majorana single-qubit gate has been demonstrated; gates would be sequences of parity measurements (g_mbq) | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
majorana |
idle / memory error per round | not published — no two-qubit operation and no Bell test exist for this carrier. — No QEC round; no logical or idle error per round has been measured on any Majorana device | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
fluxq |
T1 relaxation | not published — relative claims only; the ICE chapter refers users to D-Wave support for per-system data. — D-Wave publishes no absolute T1 for Advantage2 flux qubits - only '2x longer coherence time' and '4x lower noise' vs Advantage | typical | 2025-05 | https://www.dwavequantum.com/media/wakjcpsf/adv2_4400q_whitepaper-1.pdf · [C] |
fluxq |
T2 coherence (echo/DD) | not published — beyond ~30 ns the data diverge from coherent theory because of thermal noise. — No T2 published; the operational proxy is the coherent-annealing window, quoted as anneal times below 30 ns | typical | 2025-05 | https://www.dwavequantum.com/media/x3blg5bk/14-1074a-a_fast_anneals_and_coherent_quantum_annealing.pdf · [C] |
fluxq |
1Q gate time | not published — by construction: fluxq is an analog-Hamiltonian carrier, not a gate-model qubit. — An annealer has no gates; the closest quantity is the 5 ns minimum fast-anneal time (vs 0.5-1 µs previously) | typical | 2025-05 | https://www.dwavequantum.com/media/x3blg5bk/14-1074a-a_fast_anneals_and_coherent_quantum_annealing.pdf · [C] |
fluxq |
idle / memory error per round | not published — by construction. — No QEC rounds exist in an annealer, so there is no idle error per round | typical | 2025-05 | https://www.dwavequantum.com/media/wakjcpsf/adv2_4400q_whitepaper-1.pdf · [C] |
enc_gr |
T2 coherence (echo/DD) | 11.4 µs — Aquila (QuEra): T2* 5.8 µs, T2 with echo 11.4 µs on the ground–Rydberg qubit; analog programs capped at 4 µs | typical | 2023-06 | https://arxiv.org/abs/2306.11727 · [C] |
enc_gr |
T2 coherence (echo/DD) | 32 µs — Harvard/MIT (2018): T2* 4.5(1) µs, spin-echo T2 32(6) µs on a ground–Rydberg atom qubit | best | 2018-09 | https://arxiv.org/abs/1806.04682 · [D] |
g_tc |
2Q error under full-width parallel operation | 0.0033 — Willow 105 q QEC chip: two-qubit gate error 0.33% +/- 0.18% (CZ), stated as 'mean, simultaneous' in the spec sheet | typical | 2024-12 | https://quantumai.google/static/site-assets/downloads/willow-spec-sheet.pdf · [C] |
g_tc |
2Q error under full-width parallel operation | 0.0019 — IBM fleet, Q2 2026: best EPLG 0.19% (ibm_boston); 2,210 qubits across 15 QPUs, best CLOPS 330K+ | best | 2026-07 | https://www.ibm.com/quantum/blog/whats-new-q2-2026 · [C] |
g_tc |
crosstalk | 0.00055 — Google 72-q error budget: CZ crosstalk 5.5×10⁻⁴ per gate, weight 91, 11% of 1/Lambda - separate from the 2.8×10⁻³ CZ term | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
g_cr |
2Q error under full-width parallel operation | 0.017 — ibm_sherbrooke (Eagle r3, 127 q, fixed-coupling CR): EPLG 1.7×10⁻² at chain length 100 (layer fidelity 0.19); 0.26 at N=80 | typical | 2023-11 | https://arxiv.org/abs/2311.05933 · [D] |
g_cr |
crosstalk | not published — EPLG folds CR crosstalk in but does not separate it. — No simultaneous-minus-isolated crosstalk figure is published for cross-resonance; Kandala 2021 reports static-ZZ suppression, not a rate | typical | 2021-09 | https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.127.130501 · [D] |
g_ryd |
2Q error under full-width parallel operation | 0.005 — Harvard/Lukin: CZ at 99.5% fidelity on up to 60 atoms entangled in parallel by a global Rydberg pulse | typical | 2023-04 | https://arxiv.org/abs/2304.05420 · [D] |
g_ryd |
2Q error under full-width parallel operation | 0.00146 — 87Rb CZ 99.854(4)% raw / 99.941(3)% loss-postselected, benchmarked on 8 simultaneous gate sites, stable 10 h | best | 2026-04 | https://arxiv.org/html/2604.25987v1 · [D] |
g_ryd |
crosstalk | not published — neither the 60-atom nor the 8-site benchmark separates a crosstalk term. — No simultaneous-minus-isolated crosstalk figure is published; with a global Rydberg pulse crosstalk is inside the parallel number | typical | 2026-04 | https://arxiv.org/html/2604.25987v1 · [D] |
g_ms |
1Q gate time | 110 µs — IonQ Forte, 30-ion chain: total duration of each single-qubit Raman gate is 110 µs; median 1Q error 2.0×10⁻⁴ | typical | 2023-08 | https://arxiv.org/pdf/2308.05071 · [D] |
g_ms |
2Q error under full-width parallel operation | 0.00079 — Quantinuum Helios (98 q): 2QRB infidelity 7.9(2)e-4 averaged over all operational zones; cycle benchmarking 8.1(2)e-4 | typical | 2025-11 | https://arxiv.org/html/2511.05465v1 · [D] |
g_ms |
crosstalk | 1×10⁻⁵ — Quantinuum H2 datasheet: crosstalk error typical 1×10⁻⁵, range 1×10⁻⁶ to 2×10⁻⁴ | typical | 2024-06 | https://assets.website-files.com/62b9d45fb3f64842a96c9686/665f5f21ce5b0435bcd32917_Quantinuum%20H2%20Product%20Data%20Sheet%20v1.4%204Jun24.pdf · [C] |
g_elec |
1Q gate time | 8 µs — Oxford Ionics near-field microwave 1Q gate: 8 µs total (7.5 µs coherent + 0.5 µs dead), 8.4(7)e-6 error per Clifford | best | 2024-07 | https://arxiv.org/pdf/2407.07694 · [D] |
g_elec |
2Q error under full-width parallel operation | not published — no multi-zone simultaneous 2Q benchmark has been published for this mechanism. — The 8.4(7)e-5 smooth gate and the 3(1)e-4 / 4.7(7)e-4 12 h and 60 h figures are two-ion measurements, not full-width parallel | best | 2025-10 | https://arxiv.org/html/2510.17286v1 · [D] |
g_elec |
crosstalk | 1.6×10⁻⁶ — Oxford Ionics: residual interaction with hidden spectator qubits 1.6(8)e-6 per Clifford; between zones <= ~1×10⁻⁶ | best | 2024-07 | https://arxiv.org/pdf/2407.07694 · [D] |
g_exch |
2Q error under full-width parallel operation | not published — largest exchange-coupled arrays are 18 qubits, and are benchmarked pairwise. — The 99.04-99.56% 300 mm CZ fidelities are isolated two-qubit RB; no simultaneous or full-width spin-qubit measurement exists | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
g_exch |
crosstalk | not published — electrostatic crosstalk in dense dot arrays is cited as a known issue, not quantified. — Not reported: the 300 mm paper gives only Stark-shift coefficients (e.g. 31.3(3) MHz/V/T on the J gate), not a crosstalk error | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
g_fusion |
2Q error under full-width parallel operation | not published — Related Omega numbers: SPAM 99.98(1)%, chip-to-chip interconnect 99.72(4)%. — Fusion Bell-state fidelity 99.22(12)% is a single-fusion measurement; no parallel or network-scale fusion figure is published | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
g_fusion |
crosstalk | not published — by construction - linear optics has no static coupling between qubits to leak. — No crosstalk figure: fusion failure is heralded and enters the loss budget, not a coherent-error budget | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
g_bos |
1Q gate time | 200 ns — Yale dual-rail cavity qubit: beam-splitter single-qubit gate ~200 ns, post-selected RB error ~0.01%, erasure ~0.1% | best | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y · [D] |
g_bos |
2Q error under full-width parallel operation | not published — no multi-pair simultaneous operation of ancilla-mediated bosonic gates is published. — Dual-rail CZ 0.029(6)% post-selected (0.53(2)% erasure per CZ, Pauli <0.1%) is a two-qubit measurement, not a parallel one | best | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y · [D] |
g_bos |
crosstalk | not published — SPAM ~0.02% and bit-flip errors at the 1×10⁻⁶ level are given, but no crosstalk term. — No crosstalk figure published for ancilla-mediated bosonic gates or for the DC-SQUID beam-splitter coupler | best | 2026-08 | https://www.nature.com/articles/s41586-026-10822-y · [D] |
g_mbq |
2Q error under full-width parallel operation | not published — nothing to measure - no braiding, no entanglement, no Bell test. — No two-qubit Majorana operation exists, in parallel or otherwise; only single-wire parity readout has been demonstrated | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
g_mbq |
crosstalk | not published — by construction. — No measurement-based Majorana gate has been demonstrated, so no crosstalk figure can exist | best | 2026-06 | https://arxiv.org/html/2606.03884v1 · [D] |
g_anneal |
2Q error under full-width parallel operation | not published — by construction: performance is quoted as anneal time and solution quality. — Annealing evolution is not a gate; no two-qubit error rate is defined or published for D-Wave hardware | typical | 2025-05 | https://www.dwavequantum.com/media/x3blg5bk/14-1074a-a_fast_anneals_and_coherent_quantum_annealing.pdf · [C] |
g_anneal |
crosstalk | 0.0121 — D-Wave ICE: delta-J std ~0.0095-0.0155 and delta-h std ~0.010-0.026 through the anneal; background susceptibility chi -0.04 to -0.015 | typical | 2026-09 | https://docs.dwavequantum.com/en/latest/quantum_research/errors.html · [C] |
cx_nn |
connectivity degree | 3.63 — IBM Nighthawk: '120 qubits linked together with 218 next-generation tunable couplers' in a square lattice -> mean degree 2x218/120 = 3.63 | typical | 2025-11 | https://newsroom.ibm.com/2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance · [C] |
cx_nn |
transport per round | 0 — Zero by construction: a static coupler lattice moves no qubits; the whole 1.1 µs Willow / 921 ns Sycamore cycle is gates, measure, reset | typical | 2023-02 | https://arxiv.org/abs/2302.02192 · [G] |
cx_lr |
connectivity degree | 6 — Design target, not a measured device: gross-code layouts need 'a degree-6 graph that consists of two edge-disjoint planar subgraphs' | theory | 2023-08 | https://arxiv.org/abs/2308.07915 · [S] |
cx_lr |
transport per round | 0 — Zero: c-couplers and mm-scale resonator links are static wiring, not transport; the gross-code cycle is 7 CNOT layers with no move step | theory | 2023-08 | https://arxiv.org/abs/2308.07915 · [S] |
cx_qccd |
connectivity degree | 97 — Helios: 98-qubit ion processor with 'all-to-all connectivity enabled by a rotatable ion storage ring' joining two operation regions | typical | 2025-11 | https://arxiv.org/html/2511.05465v1 · [D] |
cx_qccd |
transport per round | 55 ms — Helios: 'an average of 55 ms per layer' for a full-width depth-1 layer (transport + ground-state cooling + gates); 2Q gate itself is ~70 µs | typical | 2025-11 | https://arxiv.org/html/2511.05465v1 · [D] |
cx_qccd |
transport per gate layer | 1.13 ms — H1 QCCD primitives: interzone shift 283 µs, intrazone shift 58 µs, split/combine 128 µs, swap 200 µs; sideband cooling 850 µs and 650 µs | typical | 2020-03 | https://arxiv.org/pdf/2003.01293 · [D] |
cx_qccd |
transport per gate layer | 33 ms — Full-width upper bound: transport is '60% on average' of H2 circuit time; on Helios's 55 ms 98-qubit layer that is ~33 ms of transport | best | 2023-05 | https://arxiv.org/pdf/2305.03828 · [D] |
cx_bus |
connectivity degree | 29 — IonQ Forte: 'single-chain 30-qubit trapped-ion quantum computer with all-to-all operations', benchmarked over all 30-choose-2 = 435 pairs | typical | 2023-08 | https://arxiv.org/abs/2308.05071 · [D] |
cx_bus |
transport per round | not published — Ion transport time belongs to cx_qccd (55 ms per full-width Helios layer). — Not applicable: a single motional-bus chain performs no transport between zones; all 435 Forte pairs are addressed in place | typical | 2023-08 | https://arxiv.org/abs/2308.05071 · [D] |
cx_aod |
connectivity degree | 447 — 448-atom zoned processor: 'atoms are rearranged with the AOD traps to enable arbitrary connectivity': all-to-all, degree N-1 | typical | 2025-06 | https://arxiv.org/abs/2506.20661 · [D] |
cx_aod |
transport per round | 1.6 ms — Caltech 6,100-atom array: 'atoms transported by 610 um in 1.6 ms' with ~99.95% fidelity; 270 um moves take 0.35-1 ms at 99.85-99.94% | typical | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
cx_aod |
transport per gate layer | 200 µs — Harvard/QuEra logical processor: 'characteristic free-space movement time between gates is roughly 200 µs'; SLM-AOD transfer adds 150-300 µs | typical | 2023-12 | https://arxiv.org/pdf/2312.03982 · [D] |
cx_reload |
initialised qubits delivered to the array per second, sustained | 3×10⁴ — Harvard/MIT 3,000-qubit system: 'more than 30,000 qubits per second' initialised without rearrangement; 15,000/s sorted into defect-free batches of 600; ~300,000 atoms/s into tweezers | best | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 · [D] |
cx_reload |
initialised qubits delivered to the array per second, sustained | 7.3×10⁴ — Princeton: 7.3 × 10⁴ atoms/s extracted from a continuously fed reservoir; a 256-site array reloaded 500 times/s; complete new qubit arrays 30 times/s | best | 2025-06 | https://arxiv.org/abs/2506.15633 · [D] |
cx_reload |
initialised qubits delivered to the array per second, sustained | 52 — MPQ: ~130 atoms reloaded per 2.5 s cycle into a > 1,000-atom ⁸⁸Sr lattice array; continuous operation > 1.5 h | typical | 2024-02 | https://arxiv.org/abs/2402.04994 · [D] |
cx_reload |
reset / initialisation time | 1 ms — Princeton: tweezer load time 1 ms for a replacement atom (90 ms in earlier work) | best | 2025-06 | https://arxiv.org/abs/2506.15633 · [D] |
cx_reload |
reset / initialisation time | 80 ms — Harvard/MIT: one of six subarrays ejected and refilled every 80 ms; the full storage array assembled in ~500 ms | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 · [D] |
cx_reload |
T2 coherence (echo/DD) | 5.4 s — Princeton: Hahn-echo T2 = 5.4(9) s while reloading vs 7(1) s without; T2* 0.73(2) vs 0.69(2) s | best | 2025-06 | https://arxiv.org/abs/2506.15633 · [D] |
cx_reload |
trap lifetime of a stored atom, vacuum- or tweezer-limited | 60 s — Harvard/MIT: tweezer-limited lifetime about 60 s in the storage array | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09596-6 · [D] |
cx_reload |
trap lifetime of a stored atom, vacuum- or tweezer-limited | 1.37×10³ s — Caltech 6,100-atom Cs array: vacuum-limited lifetime 22.9(1) min at room temperature (~7 × 10⁻¹² mbar) | best | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
cx_reload |
trap lifetime of a stored atom, vacuum- or tweezer-limited | 6×10³ s — Institut d'Optique: single-atom lifetimes in excess of ~6,000 s in tweezer arrays at ~4 K (unbaked vacuum) | best | 2021-06 | https://arxiv.org/abs/2106.07414 · [D] |
cx_shuttle |
connectivity degree | 4 — Ge/Si array: one mobile shuttled ancilla reaches the 4 data qubits of a weight-four parity check; no mean coupler degree is published | best | 2026-07 | https://www.nature.com/articles/s41586-026-10766-3 · [D] |
cx_shuttle |
transport per round | 4.84 µs — Ge/Si spin array: 'the shortest weight-four parity-check circuit has a duration of 4.84 µs'; 1.2 um round-trip shuttle path at 1.8 m/s | best | 2026-07 | https://www.nature.com/articles/s41586-026-10766-3 · [D] |
cx_shuttle |
transport per gate layer | 670 ns — Ge/Si spin bus: '1.2-um round-trip shuttling path' at 'a speed of 1.8 m s-1' = ~670 ns per round trip; a DCZ 'uses two rounds of shuttling' | best | 2026-07 | https://www.nature.com/articles/s41586-026-10766-3 · [D] |
cx_switch |
connectivity degree | not published — The meaningful cost is loss per switch: 100 mdB in-line (BTO), 0.19 dB/MZI at system scale. — Undefined for a switch fabric: connectivity is reprogrammed each clock cycle, and no mean degree is published for Omega or Aurora | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
cx_switch |
transport per round | not published — Feed-forward latency (1 µs single-clock-cycle on Aurora) is recorded on the control layer. — No transport and no syndrome round: photons propagate at c through the switch network and are consumed by fusion, not idled between rounds | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
cx_crossbar |
connectivity degree | 3 — Ge crossbar: 'two-dimensional 16-quantum-dot system' on a 4x4 grid with 23 gates; 24 nearest-neighbour bonds / 16 dots gives mean degree 3.0 | best | 2024-01 | https://www.nature.com/articles/s41565-023-01491-3 · [D] |
cx_crossbar |
transport per round | not published — without coherent operation there is no round to time. — No syndrome round: the crossbar showed charge control only (tunnel coupling 3-20 GHz), no coherent qubit operation and no shuttling schedule | best | 2024-01 | https://www.nature.com/articles/s41565-023-01491-3 · [D] |
ct_rt |
feed-forward latency | 63 µs — Google Willow d=5: 'average decoder latency of 63 µs ... with a cycle time of 1.1 µs'; Fig. 4c gives 63 +/- 17 µs | typical | 2024-08 | https://arxiv.org/pdf/2408.13687v1 · [D] |
ct_rt |
feed-forward latency | 9.6 µs — Rigetti Ankaa-2 + FPGA decoder: '9.6 µs' total response over 9 rounds = 6.5 µs decoding + 3.1 µs communication and control | best | 2024-10 | https://arxiv.org/html/2410.05202v1 · [D] |
ct_rt |
control lines per qubit | 4 — Bluefors KIDE: 'over 4 000 RF lines' and 'supports more than 1000 qubits', i.e. ~4 RF lines per qubit at rated capacity | typical | 2026-09 | https://bluefors.com/products/kide/ · [C] |
ct_rt |
recalibration interval | 4.32×10⁴ s — VTT/IQM superconducting QPUs are calibrated 'twice a day at 00:45 UTC and 14:15 UTC' (frequency, amplitude, readout, CZ, RB) | typical | 2026-09 | https://qx.vtt.fi/docs/calibration.html · [C] |
ct_cryocmos |
feed-forward latency | not published — a custom instruction set is described, but no measurement-to-gate latency. — No feed-forward latency stated: HRL's d=5 repetition code ran from the on-chip sequencer without room-temperature real-time electronics | typical | 2026-04 | https://arxiv.org/pdf/2604.16216 · [D] |
ct_cryocmos |
control lines per qubit | 8.7 — HRL 4 K cryo-CMOS: '156 output channels, 366 DACs' driving '54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits' | typical | 2026-04 | https://arxiv.org/pdf/2604.16216 · [D] |
ct_cryocmos |
recalibration interval | not published — No recalibration interval or drift figure is given for the 4 K controller | typical | 2026-04 | https://arxiv.org/pdf/2604.16216 · [D] |
ct_sfq |
control lines per qubit | not published — the demux factor is asserted qualitatively; the quantitative claim is 1Q >99%, up to 99.9%. — SEEQC mK SFQ uses 'digital demultiplexing to distribute control pulses to several qubits, thus breaking the linear scaling' | typical | 2026-03 | https://www.nature.com/articles/s41928-026-01576-6 · [D] |
ct_fluxdac |
control lines per qubit | 0.109 — D-Wave 512 q: '512 single-, 3520 two- and 512 three-stage flux-DACs are controlled with an XYZ addressing scheme requiring 56 wires' | typical | 2014-01 | https://arxiv.org/abs/1401.5504 · [D] |
ct_laser |
feed-forward latency | 5 µs — 87Rb cavity MCM: 'a 5 µs wait time after each 40 µs detection window is used to process measurement information' | best | 2026-06 | https://arxiv.org/html/2606.24869 · [D] |
ct_laser |
control lines per qubit | not published — channels scale with AOD tones (rows+columns), not atom number; no per-atom figure published. — Global optics: 'a global Raman path illuminating the entire array is used for global rotations'; traps come from one SLM plus crossed AODs | typical | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 · [D] |
ct_laser |
recalibration interval | not published — a cycle rate, not a cadence. — No recalibration interval published; the paper only notes 'Rabi calibrations with a 4-ms cycle time' | typical | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 · [D] |
ct_pic_trap |
control lines per qubit | 1 — Pasqal on-chip tweezers: 'four optical traps through a single photonic chip ... to hold four individual rubidium atoms', ~27.5 s lifetimes | best | 2026-08 | https://www.pasqal.com/newsroom/pasqal-brings-qubit-control-on-chip/ · [C] |
ct_ionlaser |
recalibration interval | 5 s — Quantinuum Helios: 'magnetic field calibrations (every ~5 s)'; field drift ~200 uG over 24 h | typical | 2025-11 | https://arxiv.org/pdf/2511.05465 · [D] |
ct_ionlaser |
feed-forward latency | not published — timing is dominated by ~70 µs 2Q gates and ~300 µs post-transport cooling. — No measurement-to-conditioned-operation latency is published for H2/Helios mid-circuit conditional operations | typical | 2025-11 | https://arxiv.org/pdf/2511.05465 · [D] |
ct_ionmw |
control lines per qubit | 0.2 — WISE: 'operate a fully connected 1000-qubit trapped ion quantum computer using ~200 signal sources' (integrated switching) | theory | 2023-05 | https://arxiv.org/abs/2305.12773 · [S] |
ct_base |
control lines per qubit | 0.18 — Si quantum-dot crossbar: 'combined control reduces the total number of gate lines to N_wires ~ 4*sqrt(2N)+1' - ~180 lines for 1,000 qubits | theory | 2017-11 | https://arxiv.org/pdf/1711.03807 · [S] |
ct_base |
feed-forward latency | not published — that is calibration feedback, not measurement-conditioned gating. — Real-time feedback tracks the SET operating point and Larmor/Rabi frequencies, but no latency is quoted | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ct_base |
recalibration interval | not published — the qualitative statement is itself the state of the art for spin qubits. — 'The consistent calibration of qubits at the level demonstrated here remains an intensive manual process' - no interval given | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ro_disp |
reset / initialisation time | 160 ns — Google surface code: 'Cycle duration is 921 ns, including 500 ns measurement and 160 ns reset' (measure-qubit multi-level reset) | typical | 2022-07 | https://arxiv.org/pdf/2207.06431 · [D] |
ro_disp |
reset / initialisation time | 25 ns — IBM Nighthawk r2: activating the reset coupler pulls effective T1 from ~200 µs median 'down to roughly 25 nanoseconds' | best | 2026-08 | https://www.ibm.com/quantum/blog/nighthawk-r2 · [C] |
ro_disp |
reset error | 0.002 — Unconditional all-microwave reset via |f0>-|g1> transfer to the resonator: <500 ns, 0.2% residual excitation | best | 2018-01 | https://arxiv.org/abs/1801.07689 · [D] |
ro_disp |
SPAM error | 0.0077 — Willow 105-q QEC chip: measurement error 0.77% +/- 0.21% (repetitive, measure qubits); RCS chip 0.67% +/- 0.51% (terminal) | typical | 2024-12 | https://quantumai.google/static/site-assets/downloads/willow-spec-sheet.pdf · [C] |
ro_disp |
SPAM error | 0.0006 — IQM, 240 ns readout pulse with |f>-shelving + TWPA: simultaneous assignment fidelity 'above 99.94%' for both qubits | best | 2025-08 | https://arxiv.org/html/2508.16437v1 · [D] |
ro_disp |
QND fidelity / survival | 0.993 — IQM: 'QNDness 99.3% for both qubits', measured without the shelving gate | best | 2025-08 | https://arxiv.org/html/2508.16437v1 · [D] |
ro_fluor |
reset / initialisation time | 20 µs — 137Ba+: 'Population initialization is performed by turning on pi-polarized 493 nm light ... for 20 µs' (optical pumping) | best | 2024-09 | https://arxiv.org/html/2409.05805 · [D] |
ro_fluor |
reset error | not published — Helios reports SPAM 4.8(6)e-4 as one number, not split into prep and measure. — No separate initialisation/reset error is published for H2 or Helios; both quote a combined SPAM figure only | typical | 2025-11 | https://arxiv.org/pdf/2511.05465 · [D] |
ro_fluor |
SPAM error | 0.00048 — Quantinuum Helios: 'average infidelities of ... 4.8(6) x 10-4 for state preparation and measurement' | typical | 2025-11 | https://arxiv.org/pdf/2511.05465 · [D] |
ro_fluor |
SPAM error | 5×10⁻⁶ — 137Ba+ heralded SPAM: 7(4)e-6 optical qubit, 5(4)e-6 metastable, 8(4)e-6 ground-level; 400 µs camera exposure | best | 2024-09 | https://arxiv.org/html/2409.05805 · [D] |
ro_fluor |
QND fidelity / survival | not published — Detection is QND for the surviving ion by construction; only leakage/crosstalk are quantified. — No QND fidelity or measurement-survival number is quoted for H2/Helios ion readout | typical | 2025-11 | https://arxiv.org/pdf/2511.05465 · [D] |
ro_img |
reset / initialisation time | 90 ms — Atom Computing: atom reload cycle '~90 ms, which includes the software processing time and a sequence buffer time of ~20 ms' | typical | 2026-06 | https://arxiv.org/html/2606.04079v1 · [D] |
ro_img |
reset / initialisation time | 80 ms — Continuous 3,000-atom system: an array segment is ejected and refilled 'every ~80 ms'; 300,000 atoms/s trapped, 30,000 qubits/s initialised | best | 2025-06 | https://www.arxiv.org/pdf/2506.20660 · [D] |
ro_img |
reset error | 0.0095 — Atom Computing: mid-circuit-measurement reset loss 9.5(4.6)e-3 per MCM cycle; initial load loss 6.8(6.8)e-3 | typical | 2026-06 | https://arxiv.org/html/2606.04079v1 · [D] |
ro_img |
SPAM error | 0.0046 — Harvard/QuEra 448-atom: '0.46(4)% bit-flip error and 0.24(2)% loss' per non-destructive spin-to-position readout | typical | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 · [D] |
ro_img |
QND fidelity / survival | 0.998 — Harvard/QuEra 448-atom: non-destructive readout with 0.24(2)% atom loss, i.e. 99.76% survival per mid-circuit image | typical | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 · [D] |
ro_img |
SPAM error | 0.009 — Cavity MCM, 87Rb: 40 µs windows (9.5 µs mean bright detection); infidelity 0.9(+0.4/-0.3)% bright, 0.2(+0.4/-0.2)% dark | typical | 2026-06 | https://arxiv.org/html/2606.24869 · [D] |
ro_img |
SPAM error | 0.0011 — Kyoto fast imaging of neutral 174Yb: 17.6 µs exposure (1000 pulses), discrimination fidelity 99.89(5)% | best | 2026-05 | https://arxiv.org/html/2605.24175 · [D] |
ro_img |
QND fidelity / survival | 0.92 — Cavity MCM, 87Rb: adaptive gating 'decreases the atom loss rate from 95% to an average of 8%'; 45 µs measure-and-feedforward cycle | typical | 2026-06 | https://arxiv.org/html/2606.24869 · [D] |
ro_img |
QND fidelity / survival | 0.988 — Kyoto fast 174Yb imaging: survival probability 98.80(44)% after the 17.6 µs image | best | 2026-05 | https://arxiv.org/html/2605.24175 · [D] |
ro_s2c |
reset / initialisation time | 1 µs — Si spins: 'heralded initialization protocol ... repeated the initialization if unsuccessful', with a t_ramp = 1 µs ramp at V_J = 1.12 V | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ro_s2c |
reset error | not published — Heralding discards failed initialisations, so a bare init error is not defined for this protocol. — Initialisation error is not reported separately from the 99.9% SPAM figure | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ro_s2c |
SPAM error | 0.001 — Si spins, Pauli spin blockade + d.c. single-island SET: 'SPAM fidelities reach up to 99.9%' at t_int = 100 µs; best device 99.95(8)% | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ro_s2c |
QND fidelity / survival | not published — Spin-to-charge conversion destroys the spin state on a singlet outcome, so QND is not claimed. — No QND or repeated-readout fidelity is reported for the PSB/SET spin readout | typical | 2025-09 | https://www.nature.com/articles/s41586-025-09531-9 · [D] |
ro_spd |
reset / initialisation time | 20.3 ns — SNSPD dead time, not a qubit reset: 'recovery time tau_rec,exp is suppressed from 20.3 ns at Ih = 0 uA to 7.1 ns'; 120 Mcps | typical | 2025-08 | https://arxiv.org/abs/2508.11832 · [D] |
ro_spd |
reset error | not published — Not defined for a photon detector; the analogue is latching/afterpulsing, unquantified in the Omega paper | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
ro_spd |
SPAM error | 0.066 — PsiQuantum Omega 300 mm: SNSPD 'median on-chip efficiency of 93.4% and average value of 88.9% +/- 3.5%'; PNRDs 98.9% median | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
ro_spd |
QND fidelity / survival | not published — a photon-number-resolving TES is equally destructive. — QND survival is undefined: SNSPD/TES detection absorbs the photon (the node's own coordinate marks it destructive) | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
ro_qcap |
reset / initialisation time | not published — the paper demonstrates parity measurement only, with no state-preparation protocol. — No initialisation or reset procedure is described for the tetron parity readout | typical | 2025-02 | https://www.nature.com/articles/s41586-024-08445-2 · [D] |
ro_qcap |
reset error | not published — No reset error published, because no reset is demonstrated | typical | 2025-02 | https://www.nature.com/articles/s41586-024-08445-2 · [D] |
ro_qcap |
SPAM error | 0.01 — Microsoft tetron: 'a parity measurement with an assignment error probability of 1%'; SNR 1 in 3.6 µs | typical | 2025-02 | https://www.nature.com/articles/s41586-024-08445-2 · [D] |
ro_qcap |
QND fidelity / survival | not published — The 2 ms poisoning time bounds repeated parity checks, but no survival fidelity is given. — QND-ness is not quantified; the paper gives parity dwell times >1 ms and tau_RTS ~ 2 ms (quasiparticle poisoning) | typical | 2025-02 | https://www.nature.com/articles/s41586-024-08445-2 · [D] |
ro_erasure |
reset / initialisation time | not published — passive resonator reset, no measured value published. — Transmon dual-rail check: 'The SRO intrinsically resets on a timescale set by its linewidth kappa (tens to hundreds of ns)' | typical | 2026-04 | https://arxiv.org/html/2604.16292v1 · [D] |
ro_erasure |
reset error | not published — No reset error quoted; the budget is given as separation, dephasing and residual error per check | typical | 2026-04 | https://arxiv.org/html/2604.16292v1 · [D] |
ro_erasure |
SPAM error | 0.008 — Transmon dual-rail erasure check: 384 ns pulse, separation error eps_sep = 0.8% at SNR 11.6(5); FP/FN limited by the same 0.8% | typical | 2026-04 | https://arxiv.org/html/2604.16292v1 · [D] |
ro_erasure |
QND fidelity / survival | 1 — Symmetric readout resonator: induced dephasing 8(3)e-5 per erasure check; total residual error 6.0(2)e-4 per check | best | 2026-04 | https://arxiv.org/html/2604.16292v1 · [D] |
code_surface |
2Q layers per syndrome round | 4 — Rotated surface code: 'a cycle depth of only four layers of CNOT or CZ gates'; Google runs this ZXXZ variant at 1.1 µs/cycle | typical | 2023-02 | https://arxiv.org/abs/2302.02192 · [G] |
code_surface |
1Q layers per round | 2 — Standard round: Hadamards on the measure qubit 'at the start and end of each round', bracketing the 4 CZ layers | theory | 2023-02 | https://arxiv.org/abs/2302.02192 · [G] |
code_surface |
code rate k/n | 0.0204 — Willow d=7 patch [[49,1,7]]: '49 data qubits, 48 measure qubits, and 4 additional leakage removal qubits'; k/n = 1/49 | typical | 2024-08 | https://arxiv.org/abs/2408.13687 · [D] |
code_surface |
acceptance fraction | not published — surface-code memory is decoded unconditionally; post-selection appears only in injection. — No acceptance fraction: Google's d=3/5/7 memory results (2.14x per distance step) are unconditional, with no post-selection | typical | 2024-08 | https://arxiv.org/abs/2408.13687 · [D] |
code_color |
2Q layers per syndrome round | 8 — Superdense colour-code round = 'a reset step, 8 CNOT steps, and a measurement step' (midout circuit: 6 CNOT steps) | typical | 2025-10 | https://arxiv.org/html/2510.00370 · [D] |
code_color |
1Q layers per round | not published — only the total round duration (~1.3 µs after decomposition) is given. — Not published: Google decomposes the superdense CNOTs into CZ + Hadamards but states no single-qubit layer count per round | typical | 2024-12 | https://arxiv.org/abs/2412.14256 · [D] |
code_color |
code rate k/n | 0.0526 — Google d=5 triangular colour code [[19,1,5]]: '19 data qubits and 18 auxiliary qubits'; total 3d^2/2 - 1/2 = 37 qubits | typical | 2024-12 | https://arxiv.org/abs/2412.14256 · [D] |
code_color |
acceptance fraction | 0.75 — Google colour-code magic-state injection: 'fidelities exceeding 99% with post-selection (retaining about 75% of the data)' | best | 2024-12 | https://arxiv.org/abs/2412.14256 · [D] |
code_qldpc |
2Q layers per syndrome round | 7 — Gross code: 'The full syndrome measurement cycle ... requires n ancillary qubits and a depth-7 circuit ... of nearest-neighbor CNOT gates' | theory | 2023-08 | https://arxiv.org/abs/2308.07915 · [S] |
code_qldpc |
1Q layers per round | not published — X-check ancillas need basis-change layers, but the paper does not count them. — Not stated: the depth-7 gross-code cycle is specified only as CNOT layers plus ancilla prep/measure; no 1Q layer count is given | theory | 2023-08 | https://arxiv.org/abs/2308.07915 · [S] |
code_qldpc |
code rate k/n | 0.0833 — [[144,12,12]] gross code: 12 logical in 144 data qubits, k/n = 1/12; net rate 1/24 with the 144 ancillas ('288 physical in total') | theory | 2023-08 | https://arxiv.org/abs/2308.07915 · [S] |
code_highrate |
code rate k/n | 0.6 — Helios two-level concatenated Iceberg [[80,48,4]] (I8 o I6): 48 logical qubits in 80 physical ions; k/n = 0.6 | best | 2026-02 | https://arxiv.org/abs/2602.22211 · [D] |
code_highrate |
code rate k/n | 0.375 — Tesseract colour code [[16,6,4]]: 6 logical in 16 physical; Quantinuum runs the subsystem variant with 4 logical, i.e. 0.25 | typical | 2024-09 | https://arxiv.org/abs/2409.04628 · [D] |
code_highrate |
acceptance fraction | 0.5 — Helios [[80,48,4]] QEC cycle: leakage acceptance 0.775, pre-acceptance 0.654(8), post-acceptance 0.987(2) -> ~0.50 combined | typical | 2026-02 | https://arxiv.org/abs/2602.22211 · [D] |
code_highrate |
acceptance fraction | 0.5 — Quantinuum tesseract: acceptance 90(1)% (path-4), 71-75% (cube-8), 73-75% (cat-12), 82% (5 rounds/4 q), 50(2)% (5 rounds/8 q) | best | 2024-09 | https://arxiv.org/abs/2409.04628 · [D] |
code_highrate |
2Q layers per syndrome round | not published — the paper counts CNOTs per stabiliser pair, not two-qubit layers per round. — Not given as layers: tesseract EC measures X^4 and Z^4 'across four rows, then down four columns', with 8 CNOTs per paired measurement | typical | 2024-09 | https://arxiv.org/abs/2409.04628 · [D] |
code_erasure |
code rate k/n | 0.5 — Erasure demo runs the [[4,2,2]] code: 2 logical in 4 atoms, k/n = 0.5; erasure conversion does not change the host code's rate | best | 2025-06 | https://arxiv.org/abs/2506.13724 · [D] |
code_erasure |
2Q layers per syndrome round | not published — the cost of erasure conversion is measurement time, not extra two-qubit layers. — No separate count: erasure codes reuse the host round (4 CZ layers for the surface code); erasure checks are extra mid-circuit readouts | theory | 2025-06 | https://arxiv.org/abs/2506.13724 · [D] |
code_erasure |
acceptance fraction | not published — ~31% of the entangling-gate error and ~half the idle loss are flagged as erasures. — No stated acceptance: the [[4,2,2]] paper shows it only in Fig. 3d; unconditional gain 1.9(4)x, post-selected hold 3.6(1)x slower decay | best | 2025-06 | https://arxiv.org/abs/2506.13724 · [D] |
code_bosonic |
2Q layers per syndrome round | 2 — Ocelot repetition-cat round: 'two CX gates between Ai and its adjacent data qubits Si and Si+1' per ancilla; cycle 2.8 µs | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 · [D] |
code_bosonic |
1Q layers per round | not published — cat-qubit phase-flip correction needs no basis-change layers on the data modes. — Not stated: the Ocelot cycle is described as ancilla initialisation, two CX gates, measurement and reset, with no single-qubit layer count | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 · [D] |
code_bosonic |
code rate k/n | 0.2 — Ocelot d=5 repetition-cat: 5 cat data modes + 4 transmon ancillas, k/n = 1/5; protects phase flips only (bit flips suppressed by the cat) | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 · [D] |
code_bosonic |
acceptance fraction | not published — unlike the ion/atom detection codes, the repetition-cat result is unconditional. — No acceptance fraction: Ocelot's 1.65(3)% per-cycle logical error is raw, with no post-selection applied | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08642-7 · [D] |
code_fusion |
2Q layers per syndrome round | not published — by construction; the cost metric is photons and fusions per logical cell, not gate layers. — No syndrome round exists in FBQC: destructive fusion measurements on small resource states replace the repeated stabiliser circuit | theory | 2025-06 | https://arxiv.org/abs/2506.11975 · [S] |
code_fusion |
code rate k/n | not published — The 17.4% threshold variant uses a {7,4}-encoded resource state of ~168 photons. — No k/n for the headline instance: the 2.7%-loss-threshold construction is a boosted 6-ring resource state, not an [[n,k,d]] block code | theory | 2025-06 | https://arxiv.org/abs/2506.11975 · [S] |
code_aft |
2Q layers per syndrome round | 1 — Transversal round: one depth-1 layer of physical CNOTs between blocks; then 'only a constant number of extraction rounds' is needed, vs O(d) | theory | 2024-06 | https://arxiv.org/abs/2406.17653 · [G] |
code_aft |
acceptance fraction | 0.5 — Harvard/QuEra 448-atom transversal results are post-selected: 'an acceptance fraction of 50% is used'; deep circuits vary the fraction | typical | 2025-06 | https://arxiv.org/abs/2506.20661 · [D] |
code_magic |
acceptance fraction | 0.08 — Google cultivation on Willow: 'reduces the error by a factor of 40, with a state fidelity of 0.9999(1) (retaining 8% of attempts)' | best | 2025-12 | https://arxiv.org/abs/2512.13908 · [D] |
code_magic |
qubit·rounds per magic state | 14600 — Litinski (15-to-1)_{7,3,3} at p=1×10⁻⁴: 810 qubits x 18.1 code cycles = 14,600 qubit-cycles per T state (p_out 4.4×10⁻⁸); 20,700 for 9.3×10⁻¹⁰ | theory | 2019-05 | https://arxiv.org/abs/1905.06903 · [S] |
code_magic |
magic states per round per factory | 0.0552 — Litinski single-level 15-to-1 factory: one T state per 18.1 code cycles; two-level (20-to-4)x(15-to-1): 90.3 cycles, 16,400 qubits | theory | 2019-05 | https://arxiv.org/abs/1905.06903 · [S] |
dec_mwpm |
decode latency per round | 1 µs — PyMatching v2 / sparse blossom: 'less than one microsecond per round of syndrome extraction on a single core', d=17, p=0.1% | typical | 2023-03 | https://arxiv.org/abs/2303.15933 · [D] |
dec_mwpm |
decode latency per round | 800 ns — Micro Blossom FPGA: 'average decoding latency of 0.8 µs at a moderate clock frequency of 62 MHz', d=13, p=0.1% | best | 2025-02 | https://arxiv.org/abs/2502.14787 · [D] |
dec_nn |
decode latency per round | 124 ns — FPGA neural decoder: '124 ns for NN decoding' with a 'deterministic closed-loop latency of 550 ns' inside a 1.25 µs QEC cycle, d=3 | best | 2026-05 | https://arxiv.org/abs/2605.04892 · [D] |
dec_relaybp |
decode latency per round | 1 µs — Relay-BP FPGA on [[144,12,12]]: 'belief propagation iteration time of 24ns', 'average per cycle decoding time under 1 µs' at p<3×10⁻³ | typical | 2025-10 | https://arxiv.org/abs/2510.21600 · [D] |
dec_fpga |
decode latency per round | 1 µs — Riverlane LCD: 'We decode in under 1 µs per round ... up to at least distance d = 17' on a Virtex UltraScale+ VU19P at 285 MHz | typical | 2025-12 | https://www.nature.com/articles/s41467-025-66773-x · [D] |
dec_fpga |
decode latency per round | 590 ns — Collision clustering on Rigetti Ankaa-2 (QPU data): '0.44 µs when decoding 5 rounds to 0.79 µs when decoding 25 rounds' | best | 2024-10 | https://arxiv.org/html/2410.05202v1 · [D] |
dec_gpu |
decode latency per round | 67 µs — Quantinuum Helios + GH200 over NVQLink: BP+OSD 'ran with a 67 microsecond median decoding time'; link round trip 3.84 µs mean | typical | 2025-10 | https://developer.nvidia.com/blog/nvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ · [C] |
dec_corr |
decode latency per round | 1 µs — Harvard/QuEra 448-atom loss-aware maximum-likelihood decoding: 'fast (about 1 µs per shot, batched on a GPU)' | typical | 2025-11 | https://www.nature.com/articles/s41586-025-09848-5 · [D] |
dec_rl |
decode latency per round | not published — Reports 7.72(9)e-4 logical error/cycle (surface code) and 3.5-fold stability against drift. — No decode latency or inference time is reported: the RL agent steers control parameters, it is not a per-round decoder | typical | 2025-11 | https://arxiv.org/abs/2511.08493 · [D] |
dec_cryo |
decode latency per round | 20 ns — NISQ+ approximate SFQ decoder: latency a 'maximum of ~20 nanoseconds on the largest code distances studied' | theory | 2020-04 | https://arxiv.org/abs/2004.04794 · [S] |
fab_cmos |
device yield | 0.96 — Intel 300 mm Si/SiGe wafer statistics: 'Full 12QD device yield: 96%', quantum-dot yield 99.8%, ohmic and gate yield 100% | typical | 2024-04 | https://www.nature.com/articles/s41586-024-07275-6 · [D] |
fab_cmos |
parameter spread | 0.059 — 300 mm Si/SiGe: matched-pair gate threshold-voltage sigma = 59 mV; 1e-voltage random variation 61 mV (30 nm) and 63 mV (50 nm SiGe barrier) | typical | 2024-04 | https://www.nature.com/articles/s41586-024-07275-6 · [D] |
fab_sc |
device yield | 0.983 — imec 300 mm transmons: 'Out of 400 qubits, 393 (yield 98.25%) ... were functional and fully characterized' (varied designs and sizes) | typical | 2024-09 | https://www.nature.com/articles/s41586-024-07941-9 · [D] |
fab_sc |
parameter spread | 0.059 — imec 300 mm: 'RSD of the measured qubit frequencies ... ranged between 5% and 7%'; junction normal-resistance RSD 4.47% at single-die level | typical | 2024-09 | https://www.nature.com/articles/s41586-024-07941-9 · [D] |
fab_3d |
device yield | not published — no cavity-per-batch pass fraction exists anywhere in the 3D-cavity literature. — No yield published: the Al 3D cavity result (Q > 0.5×10⁹, 10 ms single-photon lifetime) is a single machined device, not a batch | best | 2013-02 | https://arxiv.org/abs/1302.4408 · [D] |
fab_3d |
parameter spread | not published — Serial machining means each cavity is characterised alone, not as a population. — No cavity-to-cavity spread is reported for machined 3D superconducting cavities; only individual best-device Q values are published | best | 2013-02 | https://arxiv.org/abs/1302.4408 · [D] |
fab_trap |
device yield | not published — no ion-trap foundry (Sandia, Infineon, SkyWater/IonQ, Oxford Ionics) publishes a die or electrode yield. — No trap-chip yield published: Helios gives 1,228 electrodes and 273 independent signals but no fraction of chips or electrodes in spec | typical | 2025-11 | https://arxiv.org/html/2511.05465 · [D] |
fab_trap |
parameter spread | not published — Zone-to-zone variation is folded into the 7.9(2)e-4 2QRB average over all operational zones. — No electrode or trap-parameter spread published for microfabricated surface traps; Helios quotes only aggregate gate and memory performance | typical | 2025-11 | https://arxiv.org/html/2511.05465 · [D] |
fab_pic |
device yield | not published — 'screened' implies a selection step whose pass fraction is the missing number. — No wafer-level yield: Omega gives 'Testing of screened SNSPDs yielded a median on-chip efficiency of 93.4%', not the screening pass rate | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
fab_pic |
parameter spread | 0.039 — Omega 300 mm: SNSPD efficiency 88.9% +/- 3.5% mean (93.4% median) = 3.9% relative sigma; BTO 3-sigma thickness uniformity < 3% wafer-wide | typical | 2025-02 | https://www.nature.com/articles/s41586-025-08820-7 · [D] |
fab_optics |
device yield | 0.512 — Caltech 6,100-atom array: '51.2% of the array on average' filled across 11,998 tweezer sites, with 'a relative standard deviation of 1.13%' | typical | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
fab_optics |
parameter spread | 0.114 — Caltech tweezer array: 'average trap depth of kB x 0.18(2) mK, with a standard deviation of 11.4% across all sites' | typical | 2024-03 | https://arxiv.org/abs/2403.12021 · [D] |
fab_mbe |
device yield | not published — neither the number measured nor the pass fraction is given, and no group has replicated the InAs-Pb stack. — No device yield: Microsoft says only that 'several devices, fabricated according to the design's engineering specifications, have passed' | typical | 2022-07 | https://arxiv.org/abs/2207.02472 · [D] |
fab_mbe |
parameter spread | not published — Growth is in-house and unreplicated, so no cross-lab distribution exists either. — No wafer-level parameter spread published for the InAs-Al or InAs-Pb heterostructures; only per-device topological gaps are quoted: maxima of 20–60 µeV for InAs-Al, a top-quintile ~70 µeV for InAs-Pb (against ~30 µeV for InAs-Al on that measure; tetron preprint arXiv:2606.03884, 2026) | typical | 2022-07 | https://arxiv.org/abs/2207.02472 · [D] |
fab_stm |
device yield | not published — STM hydrogen lithography is serial and bespoke, so a per-wafer yield is not defined. — No placement yield: the 11-qubit donor register gives engineered geometry but not the fraction of sites with the intended donor count | best | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w · [D] |
fab_stm |
parameter spread | 0.077 — SQC donor register: inter-register spacing 'atomically engineered' to 13(1) nm, i.e. ~8% placement spread; 1Q fidelities span 99.10-99.99% | best | 2025-12 | https://www.nature.com/articles/s41586-025-09827-w · [D] |
fab_diamond |
device yield | not published — 327 is the number characterised at room temperature, not the number meeting the C > 1 spec. — No pass fraction: 'Across two samples ... measuring resonances for 327 cavities'; only the 2 devices analysed in detail show C > 1 | typical | 2026-06 | https://journals.aps.org/prx/abstract/10.1103/z514-v4n6 · [D] |
fab_diamond |
parameter spread | 0.36 — SnV photonic-crystal cavities: average Q across all 327 devices 1.1(4)e4 -> ~36% relative spread; the best devices reach 25.4(4)e3 | typical | 2026-06 | https://journals.aps.org/prx/abstract/10.1103/z514-v4n6 · [D] |
g_cv |
1Q gate time | 1 µs — Xanadu Aurora: 1 MHz clock with 12 physical qubit modes per cycle - 1 µs per Gaussian-gate cycle; 7.2×10⁹ temporal modes | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
g_cv |
2Q error under full-width parallel operation | not published — Fault tolerance needs a 20-30x (in dB) improvement in per-component insertion loss. — No error-per-gate is defined for CV two-mode operations; Aurora is characterised by loss (>95% on heralded paths) and squeezing | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
g_cv |
crosstalk | not published — by construction. — No crosstalk figure: mode mixing in a CV interferometer is the programmed operation, not an error channel | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
g_mwspin |
1Q gate time | not published — Null to avoid duplication; no NV microwave pi-pulse duration in ns is stated in the opened sources. — 1Q durations are recorded on the carriers instead: qd_spin ~400 ns EDSR, defect 419-2,371 µs nuclear gates | typical | 2019-05 | https://arxiv.org/pdf/1905.02094 · [D] |
g_mwspin |
2Q error under full-width parallel operation | not published — The '<0.1%' NV gate figure (QuTech/Fujitsu, March 2025) is a press-release number for single gates; no parallel or simultaneous multi-qubit measurement is published | typical | 2025-03 | https://thequantuminsider.com/2025/03/28/fujitsu-and-qutech-realize-high-precision-quantum-gates/ · [P] |
g_mwspin |
crosstalk | not published — Delft reports gate fidelities and coherence, not simultaneous-minus-isolated error. — No crosstalk figure for NV or spin microwave gates in any primary source opened | typical | 2019-05 | https://arxiv.org/pdf/1905.02094 · [D] |
g_catcnot |
2Q error under full-width parallel operation | not published — this is the single missing experiment behind every cat-qubit resource estimate. — No experimental bias-preserving cat-cat CNOT exists - only a July-2026 theory proposal - so no parallel error can be quoted | theory | 2026-07 | https://arxiv.org/abs/2607.22852 · [S] |
g_catcnot |
crosstalk | not published — by construction. — No experimental bias-preserving cat-cat CNOT exists, so no crosstalk figure can exist | theory | 2026-07 | https://arxiv.org/abs/2607.22852 · [S] |
src_resource |
2Q error under full-width parallel operation | not published — by construction: the relevant metric is state rate and size, not gate error. — A resource-state factory emits states; no two-qubit gate error is defined. Largest emitter-fused graph state is 8 photons at 0.4-2.3/min | typical | 2024-05 | https://www.nature.com/articles/s41586-024-07357-5 · [D] |
src_resource |
crosstalk | not published — by construction. — No crosstalk metric is defined for photonic resource-state generation from a single emitter | typical | 2024-05 | https://www.nature.com/articles/s41586-024-07357-5 · [D] |
ct_eo |
feed-forward latency | 1 µs — Xanadu Aurora: 'real-time single-clock-cycle feedforward' at a 1 MHz clock, so the detect-to-modulator loop closes within 1 µs | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
ct_eo |
control lines per qubit | not published — 3 detectors per mode is a detector ratio, not a control line per qubit. — Aurora: '36 photon-number-resolving detectors' and '12 physical qubit modes at each clock cycle'; modulator count per mode is not given | typical | 2025-01 | https://www.nature.com/articles/s41586-024-08406-9 · [D] |
7.10 Machines as instances of the architectures — the register joined to the map
A machine is an instance of its architecture on the map: one technology per layer, primary or alternate, taken from the technologies the map already has — and its measured numbers (§7) are what the architecture, on paper, could only promise. A layer without a technology holds one of three values, which the register keeps apart: none — the machine has nothing in this layer (no code, no decoder, no interconnect; for analogue and sampling machines no encoding layer or no entangling gate); undisclosed — something is there and nothing is published (a gate mechanism, a control stack, an inter-core link); a gap (∅G-…) — the machine runs what the map has no technology for, each an entry in the register's gap ledger and a candidate technology for a later edition. The 184 machines of the Quantum Machines Register (edition 2026.09; its input files are in the repository, data/register, and every machine has its own page, machine/) are joined to the graph by node id; every cell carries its evidence (verified or inferred) and the machine's own dated records sit beside the standard records of §7.9, never replacing them. Table A condenses the Technology × Machine matrix to one row per layer; Table B puts each machine's published clock numbers against the derived clock of its architecture (§7.4).
On the map the Machine selector is one more term in the intersection isolate ∩ focus ∩ lens: choosing a machine keeps its technologies along its family's architecture, dims the rest and marks the layers where the machine has no technology (none, undisclosed or a gap); with a lens the reader sees which attribute the machine's choices share with the architecture, with focus which of its technologies other architectures share. The register's numbers are evaluation-space attributes — dated, sourced, never used for position.
Table A — the Technology × Machine matrix by layer
| Layer | Technologies used / on the map | Most-used technologies (machines, primary) | Primary none · undisclosed | Primary is an Atlas gap: machines · gap ids |
|---|---|---|---|---|
| 1 Qubit carrier | 12 / 13 | Transmon transmon (84); Trapped atomic ion ion (30); Alkali atom (Rb/Cs) in optical tweezers alkali (18) |
0 · 0 | 0 · |
| 2 Encoding | 12 / 12 | Bare physical qubit (no encoding) enc_bare (78); Hyperfine / clock-state qubit enc_hf (44); Single-spin (Loss–DiVincenzo) / nuclear-spin encoding enc_spin_ld (14) |
12 · 0 | 1 · ∅G-fock02 (1) |
| 3 Gate mechanism | 16 / 16 | Tunable-coupler CZ / iSWAP g_tc (61); Mølmer–Sørensen / light-shift laser gate g_ms (20); Rydberg-blockade CZ g_ryd (20) |
3 · 16 | 2 · ∅G-isinganalog (2) |
| 4 Connectivity / transport | 8 / 9 | Static nearest-neighbour lattice cx_nn (96); Atom transport by AOD tweezers (zoned architecture) cx_aod (22); Ion-chain motional bus (all-to-all in chain) cx_bus (18) |
3 · 9 | 9 · ∅G-bus (4), ∅G-crystal (2), ∅G-lattice (2), ∅G-optlink (1) |
| 5 Control | 12 / 12 | Room-temperature electronics + per-qubit coax/flex ct_rt (82); Laser + AOD/SLM optical control (atoms) ct_laser (25); Free-space laser addressing of ions (AOM/AOD beams) ct_ionaod (16) |
0 · 6 | 4 · ∅G-nvroom (4) |
| 6 Readout | 10 / 10 | Dispersive microwave readout (+TWPA, Purcell) ro_disp (80); Fluorescence state detection (ions, defects) ro_fluor (35); Fluorescence imaging of atom arrays ro_img (24) |
0 · 1 | 2 · ∅G-lru (2) |
| 7 Code | 11 / 11 | Rotated surface code (+ yoked variants) code_surface (15); Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) code_bosonic (8); Erasure-adapted codes code_erasure (8) |
109 · 8 | 6 · ∅G-qac (2), ∅G-analogrot (1), ∅G-pathcode (1), ∅G-subsystem (1), ∅G-toric (1) |
| 8 Decoder | 8 / 8 | MWPM / Sparse Blossom (+ correlated matching) dec_mwpm (11); Correlated / loss-aware decoding (transversal, atom loss) dec_corr (6); Neural decoders (AlphaQubit 2, CNN, transformers) dec_nn (4) |
138 · 9 | 8 · ∅G-auton (2), ∅G-lut (2), ∅G-beam (1), ∅G-coherent (1), ∅G-frontier (1), ∅G-parity (1) |
| 9 Interconnect | 6 / 9 | Multi-chip modules / l-couplers (same cryostat) ic_mcm (12); Multi-die packaging in one module (flip-chip, bump-bonded control die) ic_multidie (12); Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) ic_fanout (4) |
139 · 10 | 1 · ∅G-ionmatter (1) |
| 10 Manufacturing | 10 / 10 | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) fab_sc (93); Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) fab_trap (26); Optical / mechanical assembly (lasers, vacuum, objectives) fab_optics (25) |
0 · 0 | 4 · ∅G-twofab (3), ∅G-sicolour (1) |
Table B — machines against the derived clock of their architecture
| Machine | Architecture | Architecture t_round | T1 (date; ×architecture) | T2 (date; ×architecture) | 1Q gate (date) | Feed-forward (date) | SPAM (date) | Clock term ×architecture | Verdict |
|---|---|---|---|---|---|---|---|---|---|
| 6,100-qubit tweezer array (Caltech (Endres group)) | Rydberg tweezer array — alkali (Rb/Cs) | 1.31 ms | — | 12.6 s (Sep 2025; ×1.0) | — | — | — | — | — |
| Gemini-class (QuEra) | Rydberg tweezer array — alkali (Rb/Cs) | 1.31 ms | — | — | — | — | 0.003 (2025) | — | — |
| MAQCS (planqc) | Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native | 1.3 ms | — | 100 ms (2026; ×1.3×10⁻²) | — | — | — | — | — |
| Phoenix (Gen-1) and Gen-2 (Atom Computing) | Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native | 1.3 ms | — | 40 s (2021; ×5.1) | — | — | — | — | — |
| 40-ion Ba-133 qLDPC testbed (IonQ: a Tempo engineering test system) (IonQ) | Trapped ions — linear Paul trap with individual laser addressing | ≥ 562 µs | — | 3.95 s (Sep 2026; ×9.3×10⁻⁴) | — | — | — | — | — |
| Forte / Forte Enterprise (IonQ) | Trapped ions — linear Paul trap with individual laser addressing | ≥ 562 µs | 10 s (2024; ×8.4×10⁻⁴) | 1 s (2024; ×2.4×10⁻⁴) | — | — | — | — | — |
| Helios (Quantinuum) | Trapped ions — QCCD (transport between zones) | 9.66 ms | — | — | — | — | 0.00033 (Jun 2026) | — | — |
| Maryland / Duke Quantum Center (EURIQA lineage) (University of Maryland / Duke University) | Trapped ions — linear Paul trap with individual laser addressing | ≥ 562 µs | — | — | — | — | 0.006 (Oct 2021) | — | — |
| System Model H1 (H1-1) (Quantinuum) | Trapped ions — QCCD (transport between zones) | 9.66 ms | — | — | — | — | 0.003 (Feb 2026) | — | — |
| Aurora (Xanadu) | Continuous-variable photonic — GKP | — | — | — | — | 1 µs (Jan 2025) | — | reaction ×1.0 | on its clock |
| Omega chipset (Moreton Bay / Chicago systems unnamed) (PsiQuantum) | Fusion-based photonic (FBQC) | — | — | — | — | — | 0.0002 (Feb 2025) | — | — |
| AWS Ocelot (AWS Center for Quantum Computing) | Bosonic cavity qubits — cat and GKP | 1.44 µs | 1 ms (Feb 2025; ×3.9×10⁻²) | 27 µs (Feb 2025; ×7.9×10⁻⁴) | — | — | — | — | — |
| Academia Sinica 20-qubit superconducting quantum computer (Academia Sinica) | Transmon lattice with tunable couplers | 651 ns | 530 µs (Jan 2026; ×7.8) | — | — | — | — | — | — |
| Alice & Bob Boson 4 (Alice & Bob) | Bosonic cavity qubits — cat and GKP | 1.44 µs | 430 s (May 2024; ×1.7×10⁴) | — | — | — | — | — | — |
| Alice & Bob Helium 2 ("Galvanic Cat") (Alice & Bob) | Bosonic cavity qubits — cat and GKP | 1.44 µs | — | — | 26.5 ns (Sep 2025) | — | — | — | — |
| Aqumen Seeker (Quantum Circuits Inc. (acquired by D-Wave, Jan 2026)) | Dual-rail erasure qubits | ≥ 2.8 µs | 1 ms (2024; ×3.9×10⁻²) | — | — | — | — | — | — |
| IBM Quantum Heron r3 (ibm_pittsburgh) (IBM) | Transmon lattice with tunable couplers | 651 ns | — | 350 µs (2025; ×3.9) | — | — | 0.013 (Jul 2025) | — | — |
| IBM Quantum Nighthawk r2 (IBM) | Transmon lattice with tunable couplers | 651 ns | — | 27 µs (Mar 2026; ×0.3) | — | — | — | — | — |
| IQM Emerald (IQM Crystal 54) (IQM Quantum Computers) | Transmon lattice with tunable couplers | 651 ns | — | — | — | 4 µs (Mar 2026) | 0.0006 (Aug 2025) | reaction ×6.3×10⁻² | faster |
| Nord Quantique single-mode GKP (Nord Quantique) | Bosonic cavity qubits — cat and GKP | 1.44 µs | 360 µs (Jul 2026; ×1.4×10⁻²) | 640 µs (Jul 2026; ×1.9×10⁻²) | — | — | 0.0007 (Jul 2026) | — | — |
| OQC GENESIS (Oxford Quantum Circuits) | Dual-rail erasure qubits | ≥ 2.8 µs | 1 ms (Jun 2025; ×3.9×10⁻²) | — | — | — | — | — | — |
| Origin Wukong (3rd gen) (Origin Quantum) | Transmon lattice with tunable couplers | 651 ns | 15 µs (2024; ×0.2) | 2.2 µs (2024; ×2.5×10⁻²) | — | — | — | — | — |
| QpiAI Kaveri (QpiAI) | Transmon lattice with tunable couplers | 651 ns | 100 µs (Feb 2026; ×1.5) | — | — | — | — | — | — |
| Rigetti Ankaa-2 (Rigetti Computing) | Transmon lattice with tunable couplers | 651 ns | — | — | — | 9.6 µs (Jun 2026) | — | reaction ×0.2 | faster |
| SUSTech biased-erasure cavity qubit (Southern University of Science and Technology) | Dual-rail erasure qubits | ≥ 2.8 µs | 6.2 ms (Jan 2026; ×0.2) | 3.1 ms (Jan 2026; ×9.1×10⁻²) | — | — | — | — | — |
| Sycamore (Google Quantum AI) | Transmon lattice with tunable couplers | 651 ns | — | — | 25 ns (Oct 2019) | — | — | 1Q ×1.0 | on its clock |
| Tianyan-287 (China Telecom Quantum Group / QuantumCTek / CAS) | Transmon lattice with tunable couplers | 651 ns | — | — | — | — | 0.013 (Dec 2025) | — | — |
| Toshiba double-transmon coupler (Toshiba + RIKEN RQC + University of Tokyo) | Transmon lattice with tunable couplers | 651 ns | 230 µs (Nov 2024; ×3.4) | 360 µs (Nov 2024; ×4.0) | — | — | — | — | — |
| Willow (Google Quantum AI) | Transmon lattice with tunable couplers | 651 ns | 68 µs (Dec 2024; ×1.0) | 89 µs (Dec 2024; ×1.0) | 25 ns (Dec 2024) | — | 0.008 (Dec 2024) | 1Q ×1.0 | on its clock |
| Zhejiang University 125-qubit surface-code processor (Zhejiang University + Graduate School of China Academy of Engineering Physics (Beijing)) | Transmon lattice with tunable couplers | 651 ns | — | — | — | — | 0.025 (Jun 2026) | — | — |
| Zuchongzhi 3.0 (USTC / Hefei National Laboratory) | Transmon lattice with tunable couplers | 651 ns | 72 µs (Mar 2025; ×1.1) | 58 µs (Mar 2025; ×0.7) | 28 ns (Mar 2025) | — | 0.0082 (Mar 2025) | 1Q ×1.1 | on its clock |
| Zuchongzhi 3.2 (USTC / Hefei National Laboratory) | Transmon lattice with tunable couplers | 651 ns | — | — | — | — | 0.0095 (Dec 2025) | — | — |
| 11-qubit donor processor (Silicon Quantum Computing) | Donor spins in silicon | ≥ 7.71 µs | — | 660 ms (Feb 2026; ×14.8) | — | — | — | — | — |
| foundry 8-qubit array (Diraq) | Silicon / germanium quantum-dot spins | 8.51 µs | — | 1.31 ms (Jul 2026; ×0.7) | 2.4 µs (Jul 2026) | — | — | 1Q ×6.0 | slower |
| Majorana 1 (Microsoft) | Topological — tetron (Majorana) | — | — | — | — | — | 0.01 (Feb 2025) | — | — |
149 machines publish none of these numbers.
What the comparison shows. 35 machines publish at least one of the seven numbers; only 7 of them publish a clock term the architecture can be checked against (1Q gate time or feed-forward latency), and 29 publish a coherence time. Verdicts per family, faster / on its clock / slower / no join: superconducting circuits 2/3/0/16; trapped ions 0/0/0/5; neutral atoms 0/0/0/4; photonics 0/1/0/1; semiconductor spins 0/0/1/1; topological 0/0/0/1. Coherence against the architecture's T1 or T2 (above ×1.25 / within / below ×0.8): superconducting circuits 6/3/12; trapped ions 0/0/3; neutral atoms 1/1/1; semiconductor spins 1/0/1. The extremes are honest about what is being compared: the largest clock ratio is foundry 8-qubit array (Diraq) (1Q 2.4 µs against 400 ns on its architecture, ×6.0); the smallest is IQM Emerald (IQM Crystal 54) (IQM Quantum Computers) (reaction 4 µs against 63 µs, ×6.3×10⁻²); on coherence Alice & Bob Boson 4 (Alice & Bob) sits at ×1.7×10⁴ of its architecture's T1 and Forte / Forte Enterprise (IonQ) at ×2.4×10⁻⁴. A ratio of ×1.0 is often the architecture's own record seen from the machine side (Willow's T1/T2 and 25 ns gate, Aurora's 1 µs loop), not an independent confirmation. Nulls: no machine in the register publishes t2q, t_meas — so the two largest terms of the superconducting and spin rounds, the 2Q gate and the readout, cannot be checked against any machine; published records that did not join: 1 — Alice & Bob Helium 2 ("Galvanic Cat") (1Q) — because their architecture has no derived round (photonic, defect, topological, annealing) or no 1Q layer in its code (cat); the ratios are per gate layer (parts ÷ d₂, d₁), so a machine's single-gate time is compared with a single gate of its architecture, not with the layer sum.
8Quantum machines — 184 attempts, 17 architectures, and where they are going
The map's technologies are what can be built; the machines register says what has been built, announced or planned, one row per machine, each joined to the map as an architecture instance (§7.10). This chapter reads the register as a population: how large it is, which technologies it is built from, what idea justifies each attempt, and what the population's trends say about where the architecture is heading. Every count below is computed from the Quantum Machines Register as of 26 September 2026 (the register and its evidence file are published with the Atlas's data); a claim is tested against the register, not asserted, and its evidence grade is carried along — the share of the cells behind it whose cited source was opened and found to support them (✅) rather than left unverified or inferred (🔎).
Terms used in this chapter. A quantum machine — machine for short in this chapter — is one row of the register: a named system an organisation has built, announced or planned. Its family is its qubit platform (superconducting circuits, trapped ions, neutral atoms, photonics, semiconductor spins, defect spins, topological, quantum annealers); its architecture is the map architecture it instantiates — one of the 17 architectures of §7.3, i.e. the family plus the choice of encoding, gate and control that defines it (cat qubits and dual-rail erasure are architectures of the superconducting family). An evidence cell is one machine × one technology it uses in a layer of the stack, with the document that shows it (a layer may hold a primary technology and an alternate, so a machine has about a dozen cells, not ten) and the register holds 2,006. A cell is verified (✅) when its cited source — a paper, a whitepaper, a product page or a technical press release; the card shows which by its glyph — was opened and seen to show that technology in that machine, and unverified (🔎) when the source was not re-opened or the cell is an inference; the evidence grade of a count is the verified share of the cells it rests on — it says how much of a claim rests on sources that were actually checked, not how many of them are papers. A device is a machine whose status is deployed, demonstrated or retired and that is not flagged as a target or a component; a gate-capable device additionally runs an entangling gate (analogue simulators, tweezer arrays without a gate and single-qubit testbeds are devices but not processors); a benchmarked device is a gate-capable device with a published figure for that gate — a benchmark paper, calibration data on a cloud platform, a vendor's datasheet or a vendor's stated number (the register records which) — and the frontier tables count only these, by the qubits the builder made usable (Osprey: 413 of 433). A chip whose gate is only described is a scale demonstrator (Condor: "comparable to Osprey", never offered to users); a machine operated for users as a technical demonstration is exploratory (Osprey). A cohort is the year of the register's status date. Integrated control means the qubits are driven by electronics on the chip or inside the cryostat (on-chip microwave electrodes, cryo-CMOS, SFQ, flux DACs) rather than by room-temperature racks or free-space optics; closed-loop decoding means the error-correction decoder acts within the cycle. A link technology is an interconnect-layer technology that joins modules — a photonic, microwave or long-range coupler link; multi-die packaging inside one module and cryogenic signal fan-out are interconnect technologies but not links. A layer in which a machine uses no technology holds one of three values: none (nothing in this layer — no code, no decoder, no interconnect; for analogue and sampling machines no encoding layer or no entangling gate), undisclosed (something is there, nothing is published) or an Atlas gap (∅G-…: the machine runs what the map has no technology for; each is an entry of the register's gap ledger). A roadmap verdict is the register's feasibility check of a published roadmap against its target algorithm (FEASIBLE, SHORT with a deficit, or NOT EVALUABLE).
8.1 The population
184 quantum machines, 8 families, 17 architectures. 131 of them exist as hardware — devices, in this chapter's word: 73 deployed, 48 demonstrated, 10 retired, not counting the rows flagged as a target or a component — and of the other 53, 45 are announcements or plans, 5 carry a deployed or demonstrated status but are flagged as a component or a target, and 3 have a status the register could not reduce to one word. Every count in this chapter is computed from the register when the page is built; none is typed in. Access, among the devices: 53 reachable through a cloud service, 26 sold on-premises, 49 laboratory-only. By country of the operating organisation: USA 50, China 29, France 13, Germany 9, USA/UK 9, Japan 8. By cohort (the year of the status date): 2018 — 1, 2019 — 2, 2020 — 3, 2021 — 7, 2022 — 8, 2023 — 17, 2024 — 26, 2025 — 52, 2026 — 53, 2027 — 4, 2028 — 3, 2029 — 4, 2030 — 1, 2031 — 1, 2033 — 1, 2034 — 1.
Table 8.1 — families × status (machines); devices; cloud access; evidence cells and how many of them are documented
| Family | Machines | Deployed | Demonstrated | Announced | Planned | Retired | Other | Devices | Devices with cloud access | Evidence cells | Verified cells (✅) | Verified, % |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| superconducting circuits | 94 | 42 | 26 | 9 | 9 | 7 | 1 | 72 | 40 | 1018 | 425 | 42 % |
| trapped ions | 30 | 12 | 9 | 5 | 4 | 0 | 0 | 20 | 6 | 330 | 175 | 53 % |
| neutral atoms | 25 | 7 | 6 | 7 | 5 | 0 | 0 | 13 | 2 | 277 | 115 | 42 % |
| photonics | 14 | 5 | 4 | 2 | 0 | 3 | 0 | 11 | 2 | 156 | 75 | 48 % |
| semiconductor spins | 10 | 2 | 5 | 2 | 1 | 0 | 0 | 7 | 0 | 110 | 45 | 41 % |
| defect spins | 5 | 2 | 3 | 0 | 0 | 0 | 0 | 5 | 1 | 53 | 25 | 47 % |
| topological | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 20 | 12 | 60 % |
| quantum annealers | 4 | 3 | 0 | 0 | 1 | 0 | 0 | 3 | 2 | 42 | 18 | 43 % |
| all | 184 | 73 | 53 | 25 | 20 | 10 | 3 | 131 | 53 | 2006 | 890 | 44 % |
Reading the table: the superconducting family is the largest by far and also the only one with retirements; the spin family is small and mostly at the demonstration stage, the photonic one small and split between deployed and demonstrated machines; the 3 rows in other are statuses the register could not reduce to one word (component testbeds, disputed reachability). The last three columns are the chapter's evidence grade: of the evidence cells behind a family's rows, how many the cited source was opened and found to support. It matters because every count in this chapter inherits it — the family at 41 % rests mostly on press claims and inferences, the family at 60 % mostly on papers — and it differs by family because the families publish differently: architecture papers with device figures are the norm for the academic superconducting, ion and atom machines and the exception for commercial photonic and spin announcements.
Announcements by cohort. The share of announced or planned rows in each cohort, 2023–2026: 2023 0 % (0/17), 2024 0 % (0/26), 2025 19 % (10/52), 2026 38 % (20/53); retired machines by family: superconducting circuits 7, photonics 3. The newest cohort is a partial year, and some of its announcements will become devices before it closes.
Technologies shared between families. 98 technologies are in use as some machine's primary technology in a layer; 22 of them by two families or more, 5 by three or more (Static nearest-neighbour lattice cx_nn — 4, MWPM / Sparse Blossom (+ correlated matching) dec_mwpm — 4, Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) code_detect — 3, Non-local qLDPC codes (bivariate bicycle, 'gross') code_qldpc — 3, Baseband electrical control (spins, Majorana) ct_base — 3). The 22 shared technologies fall into four groups: 6 shared among the fabricated solid-state families only (Static nearest-neighbour lattice, Baseband electrical control (spins, Majorana), Long-range on-chip couplers (c-couplers, mm-scale), Single-spin (Loss–DiVincenzo) / nuclear-spin encoding, …), 2 between the two atomic families only (Hyperfine / clock-state qubit, Optical narrow-line qubit (ion S–D, atom clock)), 5 across that divide (Dual-rail (erasure) encoding, GKP grid encoding, 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring), Mid-circuit erasure check, …), and 9 of the 15 codes and decoders in use (MWPM / Sparse Blossom (+ correlated matching), Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime), Non-local qLDPC codes (bivariate bicycle, 'gross'), Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC), …). Sharing follows the kinship of the physics, the platform-independence of the mathematics, and one real crossing of ideas — the photonic encodings and erasure checks that superconducting circuits adopted.
8.2 What the machines are built from
Per layer of the map, the technologies the machines actually occupy (primary role), the three ways a machine can occupy none — none (nothing in this layer), undisclosed (published nothing) and Atlas gap (the map has no technology for what it runs) — and the families that share the most-used technology. The none column is the register's maturity profile: near zero for the carrier, small for gates, connectivity and fabrication, and large for exactly the layers where the field's claims run ahead of its machines — code, decoder, interconnect. The undisclosed column is its disclosure profile, and the gap column is the map's own to-do list: what the machines run that the map does not yet name.
Table 8.2 — layers: none, undisclosed and gap cells, and the most-used technologies
| Layer | none | undisclosed | Atlas gap | Most-used technologies (machines) | Families on the first |
|---|---|---|---|---|---|
| 1 Qubit carrier | — | — | — | Transmon transmon (84); Trapped atomic ion ion (30); Alkali atom (Rb/Cs) in optical tweezers alkali (18) |
superconducting circuits |
| 2 Encoding | 12 (7 %) | — | 1 (1 %) | Bare physical qubit (no encoding) enc_bare (78); Hyperfine / clock-state qubit enc_hf (44); Single-spin (Loss–DiVincenzo) / nuclear-spin encoding enc_spin_ld (14) |
superconducting circuits |
| 3 Gate mechanism | 3 (2 %) | 16 (9 %) | 2 (1 %) | Tunable-coupler CZ / iSWAP g_tc (61); Mølmer–Sørensen / light-shift laser gate g_ms (20); Rydberg-blockade CZ g_ryd (20) |
superconducting circuits |
| 4 Connectivity / transport | 3 (2 %) | 9 (5 %) | 9 (5 %) | Static nearest-neighbour lattice cx_nn (96); Atom transport by AOD tweezers (zoned architecture) cx_aod (22); Ion-chain motional bus (all-to-all in chain) cx_bus (18) |
superconducting circuits, semiconductor spins, defect spins, topological |
| 5 Control | — | 6 (3 %) | 4 (2 %) | Room-temperature electronics + per-qubit coax/flex ct_rt (82); Laser + AOD/SLM optical control (atoms) ct_laser (25); Free-space laser addressing of ions (AOM/AOD beams) ct_ionaod (16) |
superconducting circuits |
| 6 Readout | — | 1 (1 %) | 2 (1 %) | Dispersive microwave readout (+TWPA, Purcell) ro_disp (80); Fluorescence state detection (ions, defects) ro_fluor (35); Fluorescence imaging of atom arrays ro_img (24) |
superconducting circuits |
| 7 Code | 109 (59 %) | 8 (4 %) | 6 (3 %) | Rotated surface code (+ yoked variants) code_surface (15); Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) code_bosonic (8); Erasure-adapted codes code_erasure (8) |
superconducting circuits, neutral atoms |
| 8 Decoder | 138 (75 %) | 9 (5 %) | 8 (4 %) | MWPM / Sparse Blossom (+ correlated matching) dec_mwpm (11); Correlated / loss-aware decoding (transversal, atom loss) dec_corr (6); Neural decoders (AlphaQubit 2, CNN, transformers) dec_nn (4) |
superconducting circuits, trapped ions, neutral atoms, photonics |
| 9 Interconnect | 139 (76 %) | 10 (5 %) | 1 (1 %) | Multi-chip modules / l-couplers (same cryostat) ic_mcm (12); Multi-die packaging in one module (flip-chip, bump-bonded control die) ic_multidie (12); Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) ic_fanout (4) |
superconducting circuits, quantum annealers |
| 10 Manufacturing | — | — | 4 (2 %) | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) fab_sc (93); Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) fab_trap (26); Optical / mechanical assembly (lasers, vacuum, objectives) fab_optics (25) |
superconducting circuits, quantum annealers |
8.3 The idea behind each architecture
A machine is an argument: this combination of technologies will reach the goal before the others. The argument is made per architecture (an architecture of the map), not per machine, so the register is read here by architecture — the bet in one line, the count of machines and devices that make it, the largest benchmarked device the register holds for it — a device with a published figure for its entangling gate, counted by the qubits its builder made usable (analogue simulators, arrays without an entangling gate, single-qubit testbeds and chips whose gate is only described, such as Condor, excluded), and the best two-qubit error among its devices (hero pairs, targets and component demonstrations excluded).
Table 8.3 — architectures: the bet, the population, the best numbers
| Architecture (map architecture) | Machines | Devices | Largest benchmarked device (usable physical qubits) | Best 2Q error among devices | The bet |
|---|---|---|---|---|---|
Transmon lattice with tunable couplers sc |
78 | 62 | IBM Quantum Osprey — 413 | 1.0×10⁻³ (Origin Wukong-180 (4th gen)) (claimed) | fast microwave gates on a lithographic lattice; scale by fabrication and, later, by links between chips |
Bosonic cavity qubits — cat and GKP cat |
7 | 6 | AWS Ocelot — 9 | — | bias the noise so that one error type dominates, then correct only that type with a cheap code |
Dual-rail erasure qubits dualrail |
9 | 4 | Aqumen Seeker — 8 | — | turn photon loss into a flagged erasure; erasures cost far fewer qubits to correct than Pauli errors |
Trapped ions — QCCD (transport between zones) ion_qccd |
7 | 4 | Helios — 98 | 7.9×10⁻⁴ (Helios) | move the ions, not the information: transport between trap zones gives all-to-all connectivity at the highest gate fidelities |
Trapped ions — linear Paul trap with individual laser addressing ion_chain |
16 | 13 | Forte / Forte Enterprise — 30 | 4.0×10⁻³ (Forte / Forte Enterprise) | one static chain, every pair coupled through the shared motion, each ion addressed by its own laser beam; scale by more chains and photonic links |
Trapped ions — electronic qubit control (laser-free, microwave-driven gates) ion_elec |
7 | 3 | — | — | gates driven by microwaves and currents in the trap chip, no laser at the gate: control that scales like electronics |
Rydberg tweezer array — alkali (Rb/Cs) atom_rb |
16 | 7 | 448-atom fault-tolerant processor — 448 | 5.0×10⁻³ (448-atom fault-tolerant processor) | reconfigurable tweezers make the code geometry programmable and the qubit count cheap; the clock is slow |
Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native atom_ae |
6 | 3 | Phoenix (Gen-1) and Gen-2 — 1,180 | — | a two-electron atom whose metastable qubit flags its own decay as an erasure, paid for with a worse CZ; the clock qubit and continuous reloading come with the carrier |
Neutral-atom analogue simulator (Rydberg arrays, lattice gases) atom_analog |
3 | 3 | — | — | no gates at all: programme the Hamiltonian of a Rydberg array or a lattice gas and let it evolve — simulation and optimisation now, at hundreds of atoms |
Fusion-based photonic (FBQC) ph_fusion |
6 | 3 | — | — | make entanglement by measurement: room-temperature photonic fabrication and networking, loss is the enemy |
Continuous-variable photonic — GKP ph_cv |
1 | 1 | — | — | continuous-variable states and GKP encoding on the same photonic chips |
Boson sampler ph_sampler |
7 | 7 | — | — | sample from a linear-optical network of squeezed or single photons: a quantum-advantage experiment, not a programmable computer |
Silicon / germanium quantum-dot spins spin_qd |
9 | 6 | HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots) — 18 | 3.0×10⁻³ (HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots)) | the foundry: quantum dots in CMOS, density and cold electronics from the semiconductor industry |
Donor spins in silicon spin_donor |
1 | 1 | 11-qubit donor processor — 11 | — | donor spins in isotopically pure silicon: the longest coherence in a solid |
Colour-centre spins — network nodes (NV/SiV/T) defect |
5 | 5 | — | — | defect spins as network nodes: few-qubit registers joined by heralded photons |
Topological — tetron (Majorana) topo |
2 | 0 | — | — | protection in the hardware: a topological gap instead of a code |
Quantum annealer — flux qubits anneal |
4 | 3 | — | — | special-purpose scale now: thousands of analogue qubits for optimisation and simulation |
Two readings. First, the bets are not symmetric in what they need to prove: the superconducting and tweezer bets are already made by dozens of devices and argue about rates (error per gate, qubits per year); the bosonic, topological and donor bets are made by one to seven machines and still argue about existence (does the protection hold at the second qubit, at the second module). Second, the best numbers sit on different architectures for different quantities — the largest device is a tweezer array, the best two-qubit error is an ion trap, the fastest clock (§7.4) is a transmon lattice — which is the empirical form of the Atlas's claim that no architecture dominates on all axes.
The seventeen architectures, one by one. Each subsection below is the argument of one architecture in six parts — the idea, what it needs, where it stands in the register, its exceptions and borrowings, the next test, and what the builders themselves say about it, in their own dated words — followed by the register's own block: the machines on the architecture grouped by organisation, and every cell that falls outside the architecture's slots (an alternate borrowed from another architecture, an Atlas gap, or undisclosed where the architecture expects a technology). The short name in the heading is the nickname the map's chips use.
8.3.1 Transmon lattice — Transmon lattice with tunable couplers (sc)
The idea. A transmon (transmon) is a capacitively shunted Josephson junction whose two lowest levels serve bare as the qubit (enc_bare). The architecture tiles transmons in a lithographic lattice (cx_nn), switches neighbour exchange with flux-tuned couplers (g_tc), drives them from room-temperature racks (ct_rt), reads them dispersively (ro_disp) and corrects with the rotated surface code, whose weight-4 checks are the lattice's own neighbourhoods. A circuit atom is drawn, not found: gates take tens of nanoseconds [G] and the QEC cycle 1.1 µs [D][1], the map's fastest clock (§7.4). The price is coherence (T1 68 µs on Willow [D][32]), identical qubits and any coupling beyond the neighbour. The bet: speed and wafer fabrication outrun the error budget; links between chips come later.
What it needs. Everything rests on fab_sc: the transmon requires junction lithography, so its frequency spread is fixed at fabrication; the trimming that repairs it has no technology yet. The surface code requires only neighbour checks. Bivariate bicycle codes keep 12 logical qubits in 288 physical where the surface code needs nearly 3,000, but need a degree-6 graph [S][248]: code_qldpc requires long-range couplers (cx_lr) and conflicts with cx_nn, open since 2024-03. Readout and reset are two-thirds of the 651 ns derived round [S] (§7.4). Four control technologies replace one another per signal, not per machine — a Heron r2 ran cryo-CMOS flux ASICs in hybrid with room-temperature rf (Mar 2026) [C]. Both cold routes conflict with the transmon: cryo-CMOS (ct_cryocmos) on the mixing chamber's heat budget, SFQ (ct_sfq) on quasiparticles — its switching photons break Cooper pairs, 0.96(2)% of a 1.2(1)% error per Clifford in 2023 [D][249], mitigation projected, not yet independently measured. Encoding has one option; the microwave–optical transducer slot is empty.
Where it stands. 78 of the register's 184 machines and 62 devices (Table 8.3): 39 deployed, 18 demonstrated, 7 retired, 13 announced or planned, 1 other; IBM supplies 16 rows, China 18. The largest benchmarked device is IBM Quantum Osprey — 413 of its 433 qubits usable on the cloud for four months of 2023 as an exploratory technical demonstration, with performance IBM called consistent with Eagle r1 and no published gate figure beyond the platform's calibration [C][292]; the largest chip, IBM Quantum Condor (1,121 qubits), unveiled in December 2023 as an innovation milestone and never offered to users, is a scale demonstrator whose gate IBM only described as comparable to Osprey [C][292]. The best 2Q error, 1.0×10⁻³ on Origin Wukong-180 (4th gen), is a company figure [C] (Table 8.3); Willow's device mean is 99.88% [D][32]. Willow ran d=7 at Λ = 2.14 [D][1], then 7.72×10⁻⁴ per cycle (Jul 2026) [D][2]; Zuchongzhi 3.2 d=7 at Λ = 1.40 [D][3]. Code, decoder and interconnect slots are empty on 54, 66 and 59 machines; 12 rows publish no gate mechanism; 327 of 843 evidence cells are documented.
Exceptions and borrowings. No machine falls off the slots or fits another architecture better; alternates carry the direction. Wiring leaves the chip edge (ct_vio) on RIKEN 64, RIKEN–Fujitsu 256, OQC Toshiko and QuantWare Bass-A10K (VIO-40K), racks still warm; control goes cold only in part or at small scale: cryo-CMOS flux ASICs in hybrid with room-temperature rf on Heron r2 and as alternate on Starling and Blue Jay, SFQ on SEEQC's five-qubit system (single-qubit gates only); QuamCore's SFQ-controlled design stays unlisted until the company dates a first device. Sycamore and Zuchongzhi stack dies (ic_multidie); modules (ic_mcm) ship only on Rigetti Cepheus, at 99.6%→99.1% [C][36]. IBM's utility line sits in mitigation (code_mitig: Eagle, Heron r3, Nighthawk r2) and detection (code_detect: Falcon, Heron r2/r3, Origin Wukong 3rd gen); qLDPC runs only on Kunlun. Nominal members: Osprey, Eagle, Condor, Falcon and LBNL AQT use cross-resonance (g_cr), not tunable couplers; targets (Amaravati, CSCS, KRISS 50); plans (Kookaburra to Blue Jay, Fujitsu 10,000); component testbeds (Toshiba coupler, Loon); undisclosed stacks (Tianyan-504, RIKEN–Fujitsu 256, Toshiko). Gap cells show the architecture drawn too narrowly: a central-resonator bus (IQM Star 24, VLQ, DRDO–TIFR), leakage-removal units (Willow, Zuchongzhi 3.2), post-fabrication frequency trimming (Willow, Cepheus, Academia Sinica). Dual-rail borrows transmon, ct_vio and ic_mcm; cat ic_multidie; spins ct_cryocmos.
The next test. Expectations to 31 Mar 2028 (§5.2). A bivariate bicycle memory on c-couplers, Kookaburra or a Kunlun successor, reports a logical error per cycle below its physical idle error; Kunlun's 8.91% [P][72]–[74] is the baseline. If Kookaburra is undelivered again by end-2027, the qLDPC branch is demoted and the architecture stays a surface-code machine at >10³ physical qubits per logical at 10⁻⁶ [S] (§2.1). And a gate-capable device above 433 qubits with published two-qubit errors, plus cryo-CMOS or SFQ control of ≥50 qubits; if neither appears and readout stays near 10⁻², scale by fabrication is demoted to scale by modules.
What the builders say. Google argues that superconducting processors scale in circuit depth, with microsecond cycles, while neutral atoms scale in qubit count [C][2], [9], and expects commercially relevant superconducting machines by the end of this decade, naming no qubit count [R][2], [9]. Rigetti targets about 1,000 qubits at 99.9% two-qubit fidelity in roughly three years, built from chiplets [R][61]. Fujitsu is building a machine of more than 10,000 physical and 250 logical qubits for fiscal 2030 [R][75], [76]. IBM chose a qLDPC code (a low-density parity-check code whose checks join distant qubits) because it corrects as well as the surface code with ten times fewer qubits [D][481]; it plans Kookaburra, the first qLDPC module, for 2026 and Starling, 100 million gates on 200 logical qubits, for 2029 [R][481].
Machines of this architecture (register: 78, of them 62 devices, 52 gate-capable). IBM — IBM Quantum Starling (planned, 22,000), IBM Quantum Condor (demonstrated, 1,121), IBM Quantum Osprey (retired, 433), IBM Quantum Heron r2 (deployed, 156), IBM Quantum Heron r3 (ibm_pittsburgh) (deployed, 156), IBM Quantum Heron r1 (retired, 133), IBM Quantum Eagle r1-r3 (retired, 127), IBM Quantum Nighthawk r1 (deployed, 120), IBM Quantum Nighthawk r2 (deployed, 120), IBM Quantum Loon (demonstrated, 112), IBM Quantum Egret (retired, 33), IBM Quantum Falcon r5.11 (retired, 27), IBM Quantum Blue Jay (planned), IBM Quantum Cockatoo (planned), IBM Quantum Flamingo (l-coupler proof of concept) (demonstrated), IBM Quantum Kookaburra (planned); Beijing Academy of Quantum Information Sciences — Baihua (Quafu platform) (deployed, 156), ScQ-136 "Baiwang" (deployed, 136), Dongling (Quafu platform) (deployed, 130), Haituo (Quafu platform) (deployed, 117), Shenglian (BAQIS) (demonstrated, 84); IQM Quantum Computers — IQM Halocene (announced, 150), IQM Emerald (IQM Crystal 54) (deployed, 54), IQM Star 24 (deployed, 24), IQM Garnet (IQM Crystal 20) (deployed, 20), IQM six-qubit star QPU (Deneb-class) (demonstrated, 6); Rigetti Computing — Rigetti Cepheus-1-108Q (deployed, 108), Rigetti Ankaa-2 (deployed, 84), Rigetti Ankaa-3 (deployed, 84), Rigetti Cepheus-1-36Q (deployed, 36), Rigetti Novera (deployed, 9); Google Quantum AI — Willow (demonstrated, 105), Sycamore-class 72-qubit processor (demonstrated, 72), Sycamore (retired, 53); Origin Quantum — Origin Wukong-180 (4th gen) (deployed, 180), Origin Wukong 102 (deployed, 102), Origin Wukong (3rd gen) (deployed, 72); QuantWare — QuantWare Bass-A10K (VIO-40K) (announced, 10,000), QuantWare Tenor-D64 (other, 64), QuantWare Contralto-A17 (deployed, 17); USTC / Hefei National Laboratory — Zuchongzhi 3.2 (demonstrated, 107), Zuchongzhi 3.0 (demonstrated, 105), Zuchongzhi 2.1 (retired, 66); Korea Research Institute of Standards and Science — KRISS 50-qubit-class superconducting system (announced, 50), KRISS domestic superconducting QPU (deployed, 20); QpiAI — QpiAI Kaveri (announced, 64), QpiAI Indus (deployed, 25); RIKEN RQC + Fujitsu — RIKEN-Fujitsu 256-qubit superconducting quantum computer (deployed, 256), RIKEN RQC-Fujitsu 64-qubit superconducting quantum computer (deployed, 64); Academia Sinica — Academia Sinica 20-qubit superconducting quantum computer (demonstrated, 20); Anyon Systems — Anyon MonarQ (deployed, 24); Barcelona Supercomputing Center (Quantum Spain; installed by Qilimanjaro-GMV) — Quantum Spain quantum computer at BSC (deployed, 35); Basque Government (BasQ) - IBM-Euskadi Quantum Computational Center — IBM Quantum System Two, Donostia-San Sebastian (deployed, 156); CAS / Peking University — Zhuangzi 2.0 (Chuang-tzu 2.0) (demonstrated, 78); Chalmers University of Technology (WACQT) — WACQT quantum computer (Chalmers 25-qubit flip-chip processor) (demonstrated, 25); China Telecom Quantum Group + CAS + QuantumCTek — Tianyan-504 / "Xiaohong" chip (deployed, 504); China Telecom Quantum Group + QuantumCTek — Tianyan-176 / Tianyan-176 II (and Tianyan-24 sibling) (deployed, 66); China Telecom Quantum Group / QuantumCTek / CAS — Tianyan-287 (deployed, 105); DRDO DYSL-QT with TIFR and TCS — 6-qubit superconducting quantum processor (demonstrated, 6); ETH Zurich (Quantum Device Lab) — Surface-17 (demonstrated, 17); Fraunhofer-Gesellschaft — IBM Quantum System One, Ehningen (deployed, 27); Fujitsu (+ RIKEN) — Fujitsu 1,000-qubit machine (planned, 1,000); Fujitsu + AIST + RIKEN — Fujitsu >10,000 physical / ~250 logical (STAR) (announced, 10,000); IBM with ETH Zurich (CSCS) and Lockheed Martin — IBM Quantum System Two at CSCS (Swiss Quantum Innovation Hub) (announced, 120); IBM with TCS and the Government of Andhra Pradesh — IBM Quantum System Two at Amaravati Quantum Valley Tech Park (announced, 156); IQM Quantum Computers with Instituto de Pesquisas Eldorado — IQM Spark at Eldorado Research Institute (announced, 5); IT4Innovations National Supercomputing Center (VSB - Technical University of Ostrava) — VLQ (deployed, 24); Israeli Quantum Computing Center (Quantum Machines + QuantWare + Qolab + ORCA) — IQCC superconducting facility (deployed, 25); Lawrence Berkeley National Laboratory — Advanced Quantum Testbed (AQT) (deployed, 8); Oxford Quantum Circuits — OQC Toshiko (deployed, 32); Qolab — Qolab devices at the IQCC (deployed); RIKEN with AIST, NICT, Osaka University, Fujitsu, NTT — RIKEN 64-qubit superconducting processor (deployed, 64); SEEQC — SEEQC SFQ-controlled 5-qubit system (demonstrated, 5); SpinQ Technology — SpinQ Ursa Major (25 q / 103 q) (deployed, 25); Toshiba + RIKEN RQC + University of Tokyo — Toshiba double-transmon coupler (demonstrated, 2); Tsinghua University IIIS (D.-L. Deng) with Zhejiang University (H. Wang, C. Song groups) — Kunlun (demonstrated, 32); VTT Technical Research Centre of Finland — VTT Q50 (deployed, 50); Zhejiang University + Graduate School of China Academy of Engineering Physics (Beijing) — Zhejiang University 125-qubit surface-code processor (demonstrated, 125).
Cells outside the architecture's slots (25). Academia Sinica 20-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; Academia Sinica 20-qubit superconducting quantum computer: L10 ∅G-calib (Atlas gap — post-fabrication laser trimming tunes qubit frequencies (same slot as Rigetti ABAA / IQM P); Quantum Spain quantum computer at BSC: L3 undisclosed where the architecture expects a technology; Tianyan-504 / "Xiaohong" chip: L3 undisclosed where the architecture expects a technology; 6-qubit superconducting quantum processor: L3 undisclosed where the architecture expects a technology; 6-qubit superconducting quantum processor: L4 ∅G-bus (Atlas gap — ring-resonator design invented at TIFR: qubits sit around one shared ring resonator used a); Fujitsu >10,000 physical / ~250 logical (STAR): L5 undisclosed where the architecture expects a technology; Fujitsu >10,000 physical / ~250 logical (STAR): L7 ∅G-analogrot (Atlas gap — STAR: arbitrary-angle rotations by direct state injection, no distillation; 10⁴ q at p=1e-); Fujitsu 1,000-qubit machine: L3 undisclosed where the architecture expects a technology; Willow: L6 ∅G-lru (Atlas gap — DQLR + 4 dedicated leakage-removal qubits in the 101-qubit d=7 patch; leakage rate not pub); Willow: L10 ∅G-calib (Atlas gap — Snake optimiser splits ~3N-dim frequency problem; ~3.7× cycle-error suppression, mean cycl); IQM Halocene: L4 ∅G-bus (Atlas gap — Constellation option: Star cells, each a central computational resonator giving all-to-all); IQM Star 24: L4 ∅G-bus (Atlas gap — Star topology: central computational resonator bus giving all-to-all within the cell (degr); IQM six-qubit star QPU (Deneb-class): L4 ∅G-bus (Atlas gap — star topology: all six qubits coupled only to the central computational resonator, effecti); VLQ: L3 undisclosed where the architecture expects a technology; VLQ: L4 ∅G-bus (Atlas gap — star topology: 24 qubits connected to one central resonator, all-to-all through it); KRISS 50-qubit-class superconducting system: L3 undisclosed where the architecture expects a technology; OQC Toshiko: L3 undisclosed where the architecture expects a technology; Rigetti Cepheus-1-108Q: L10 ∅G-calib (Atlas gap — ABAA (alternating-bias assisted annealing) post-fab JJ frequency targeting, 97.4% success ); Rigetti Cepheus-1-36Q: L10 ∅G-calib (Atlas gap — ABAA (alternating-bias assisted annealing) post-fab JJ frequency targeting, 97.4% success ); RIKEN 64-qubit superconducting processor: L3 undisclosed where the architecture expects a technology; RIKEN-Fujitsu 256-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; RIKEN RQC-Fujitsu 64-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; SEEQC SFQ-controlled 5-qubit system: L3 undisclosed where the architecture expects a technology; Zuchongzhi 3.2: L6 ∅G-lru (Atlas gap — all-microwave leakage-reduction units on data qubits; leakage population suppressed 72× to).
8.3.2 Cat & GKP cavities — Bosonic cavity qubits — cat and GKP (cat)
The idea. The qubit is a microwave resonator mode, the Bosonic cavity mode (cavity), whose dominant error is photon loss. In the Cat-code encoding (biased noise) two-photon dissipation holds two coherent states apart: bit-flips fall exponentially with mean photon number n̄, phase-flips rise linearly, so a line of d cats, not a d × d patch, corrects the rest; lattice density is the price. The bet: photons buy the distance a lattice buys with qubits, if the bias survives the entangling gate. The alternate GKP grid encoding shares the hardware, not the bet: it corrects small displacements and passes up an analogue syndrome.
What it needs. The encoding requires two-photon dissipation on a mode, and Bosonic concatenation a biased or GKP inner qubit: the architecture rests on the phase-flip rate during a two-qubit gate. Every measured entangling gate is ancilla-mediated (g_bos), through a transmon that does not preserve the bias; the Bias-preserving cat–cat CNOT that would replace it is an empty slot with one simulated proposal (Jul 2026) [S][81]. Six layers offer one technology each. Lithographed modes replace 3D machined cavities, and the 3D branch conflicts with the lattice: centimetre-scale bodies cannot tile a dense 2D array (open [82]).
Where it stands. Seven machines, six devices (Table 8.3): Alice & Bob Boson 4, Helium 2 ("Galvanic Cat"), Helium (on-premise system) and the planned Graphene (2030) [R][828], [873] — the undated Lithium (48 cats) and Beryllium (250) chips stay unlisted until Alice & Bob dates them; AWS Ocelot; Nord Quantique single-mode GKP and Tesseract. The largest, Helium (18 cats), deployed June 2026 without logical data [C][87], [88]. Bit-flip times reach 430 s (Boson 4) and a preliminary 44-min mean (Helium 2) [C][77]; only Ocelot ran an outer code: repetition at 1.75% (d=3, n̄=1) and 1.65% (d=5, n̄=1.5) per 2.8 µs cycle, distance and photon number moving together, with CX phase-flip 9.6(4)×10⁻² against bit-flip 3.5(4)×10⁻³ [D][80]. Helium 2's 5.8×10⁻² is a single-qubit Z gate, not a two-qubit error, and Ocelot's 9.6×10⁻² is a phase-flip rate per error-correction cycle, not a gate error, so Table 8.3 shows no two-qubit error for the architecture [C][77]. Nord Quantique single-mode GKP: 8.1×10⁻³ logical error per round, SPAM below 10⁻³ at survival 0.24 × 0.39 [D][82].
Exceptions and borrowings. No off-slot cell, no better-fitting architecture; the shared absences, real-time decoder and interconnect, mark an early stage. The Nord Quantique pair: its decoder cell is an Atlas gap, ∅G-auton (stabilisation without classical feed-forward), so layer 8 is drawn too narrowly; its code cell reads Bosonic concatenation though neither runs an outer code, like Boson 4, a single cat with zero logical qubits on its roadmap [C][92]. GKP joins by hardware, not by the bias bet: for its idea the architecture is drawn too widely. Borrowers: Aurora (continuous-variable photonics) takes the GKP and code technologies; the dual-rail architecture's Aqumen Seeker, SUSTech biased-erasure cavity qubit and D-Wave gate-model dual-rail system take cavity and gates.
The next test. Two expectations to March 2028 (§5.2). First, Helium's roadmap rung, one logical qubit at 10⁻² [R][92]: phase-flip ≤ 10⁻² per cycle at n̄ ≈ 10 confirms; Helium still without logical data at end-2027 demotes. Second, a measured two-cat gate holding bit-flip time within 10× of idle; if 2028 opens with ancilla-mediated gates only, the 126,133- and 758-cat estimates, which assume 10⁻³ phase-flip per cycle, lose their premise [S][95], [96]. GKP owes a published GKP–GKP gate.
What the builders say. AWS chose cat qubits because they suppress bit flips in the hardware itself, as its Ocelot chip showed [D][827], and estimates that the approach cuts the cost of error correction by up to 90% [C][827]. Alice & Bob plans Graphene, 100 logical qubits for early industrial quantum advantage, by 2030 [R][828]; it reported bit-flip times above one hour, four times what that machine needs, before peer review [C][77], and built its on-premise Helium system to encode a first logical qubit in as few as 18 cat qubits [C][87], [88]. Nord Quantique builds the correction into each qubit, one cavity per logical qubit [C][829], and expects its first machines with more than 100 logical qubits by 2029 [R][830].
Machines of this architecture (register: 7, of them 6 devices, 6 gate-capable). Alice & Bob — Alice & Bob Graphene (planned, 2,000), Alice & Bob Helium (on-premise system) (deployed, 18), Alice & Bob Helium 2 ("Galvanic Cat") (demonstrated, 12), Alice & Bob Boson 4 (demonstrated, 1); Nord Quantique — Nord Quantique Tesseract (demonstrated, 2), Nord Quantique single-mode GKP (demonstrated, 1); AWS Center for Quantum Computing — AWS Ocelot (demonstrated, 9).
Cells outside the architecture's slots (2). Nord Quantique single-mode GKP: L8 ∅G-auton (Atlas gap — no classical decoder: autonomous, feed-forward-free stabilisation with analog closest-vect); Nord Quantique Tesseract: L8 ∅G-auton (Atlas gap — no classical decoder: autonomous stabilisation with heralded discard; no real-time decoder).
8.3.3 Dual-rail erasure — Dual-rail erasure qubits (dualrail)
The idea. One excitation shared between two modes, cavity modes or transmons, is the Dual-rail (erasure) encoding (enc_dualrail): logical |10⟩ and |01⟩; loss on either rail lands in |00⟩, outside the code space. A Mid-circuit erasure check sees that exit without reading the logical state: the dominant error arrives located, cheaper to correct than an unknown Pauli error. The price: two modes per qubit and a check every cycle. The bet: fail more often, but visibly; with 98% of errors converted, the surface-code threshold rises from 0.94% to 4.15% [S][8].
What it needs. The chain is hard: the encoding requires the check, and Erasure-adapted codes require its flags; without the check the qubit is merely lossier, without a flag-using decoder the heralds are wasted. The check's tax: 384 ns on transmons, residual 6.0(2)×10⁻⁴ against 2.54(1)×10⁻² erasure per check [D][85], inside a gate-limited round of at least 2.8 µs [S] (§7.4). Six layers (2–4, 7–9) hold one technology each; the gate technology requires the modes plus a transmon ancilla. Alternates: vertical delivery and on-chip flux-DAC multiplexing replace room-temperature lines, lithography replaces 3D machining, and transmon rails escape the cavities' conflict with a dense lattice.
Where it stands. Nine machines, four devices (Table 8.3): Aqumen Seeker, eight dual-rail cavity qubits (Quantum Circuits Inc., now D-Wave, 2024) [C][14], [86]; OQC GENESIS, 16 sites, deployed September 2025, and OQC's roadmap names TITAN (2,000 sites, 2028), ATHENA (75,000) and ATLAS (1,000,000) [R][874]; the SUSTech four-dual-rail-qubit processor (Nature Physics, 2026) [D][406] and the SUSTech biased-erasure cavity qubit; the AWS dual-rail transmon erasure line, a component; the D-Wave gate-model dual-rail system, 17 qubits due in 2026 [R][94]. The Yale/Quantum Circuits cavity CZ: ~500 ns, 0.53% erasure per gate, post-selected Pauli error below 0.1%, about 80% of its error flagged [D][84]. Seeker's 1.0×10⁻³ is post-selected on no heralded erasure (0.53% per gate), so Table 8.3 shows no unconditioned two-qubit error for the architecture [C][86]. GENESIS publishes no entangling gate — its gate cell reads undisclosed, not none — so Table 8.3 does not count it gate-capable; the table's largest gate-capable device is the SUSTech four-dual-rail-qubit processor, 8 qubits, whose logical CNOT (98.1 % process fidelity at a 13 % erasure rate) is post-selected [D][406]. No machine has run an erasure-decoded code.
Exceptions and borrowings. One off-slot cell and no better-fitting architecture: the SUSTech four-dual-rail-qubit processor entangles its transmon rails through tunable couplers (g_tc), a gate the architecture's slot does not hold — it expects ancilla-mediated bosonic gates [D][406]. Two more sit loosely. GENESIS's carrier alternate is an Atlas gap, ∅G-dimon: one fixed-frequency multimode transmon, three islands and two junctions, two transmon-like modes [C][250], beyond the transmon technology (layer 1 too narrow); its gate is undisclosed (a data gap), its code cell none: error detection by post-selection. The SUSTech qubit is not dual-rail: it encodes in the vacuum and two-photon Fock states of one cavity, with erasure bias above 265 [D][251]; its encoding cell is mislabelled, or the architecture too narrow, its idea being loss-to-erasure, not two rails. The D-Wave system is a hybrid: annealer flux-DAC control. Other architectures borrow the check (Phoenix (Gen-1) and Gen-2, Magne; alkaline-earth Rydberg) and the encoding (Lucy, Belenos; fusion-based photonic), as alternates.
The next test. Two expectations to March 2028 (§5.2). First, the D-Wave 17-qubit system publishes a logical error 2× below physical by mid-2027; if end-2027 passes with no dual-rail machine reporting logical error falling more than 2× per distance step on unconditioned data, the architecture is demoted. Second, the first dual-rail memory of at least ten rounds at distance 3, erasure flags in the decoder, survival reported; the CHIPS-backed design at 100 physical qubits per logical [R][91] presumes it.
What the builders say. D-Wave designs its dual-rail qubits to flag about 90% of errors as they occur, so that correction needs fewer physical qubits [C][831]; its entangling gate runs in about 500 ns, with about 0.5% erasure and under 0.1% residual error per gate [D][84]. It plans 17 physical qubits in 2026 and 100 logical qubits running more than a million operations by 2032 [R][831]. OQC says its dual-rail Dimon needs ten times fewer physical qubits per logical qubit than today's leading approaches [C][832], installed its GENESIS machine in a New York City data centre in September 2025 [C][833], and plans 200 logical qubits by 2028 and 50,000 by 2034 [R][832].
Machines of this architecture (register: 9, of them 4 devices, 3 gate-capable). Oxford Quantum Circuits — OQC ATLAS (planned, 1,000,000), OQC ATHENA (planned, 75,000), OQC TITAN (planned, 2,000), OQC GENESIS (deployed, 16); AWS Center for Quantum Computing (named Amazon Center for Quantum Computing in the Apr 2026 paper) — AWS dual-rail transmon erasure line (demonstrated, 2); D-Wave Quantum — D-Wave gate-model dual-rail system (announced, 17); Quantum Circuits Inc. (acquired by D-Wave, Jan 2026) — Aqumen Seeker (deployed, 8); Southern University of Science and Technology — SUSTech biased-erasure cavity qubit (demonstrated, 1); Southern University of Science and Technology (Huang et al.) — SUSTech four-dual-rail-qubit processor (demonstrated, 8).
Cells outside the architecture's slots (22). OQC ATHENA: L1 ∅G-dimon (Atlas gap — roadmap names 'next-generation multimode qubits' for ATHENA — the Dimon's multimode single); OQC ATHENA: L3 undisclosed where the architecture expects a technology; OQC ATHENA: L4 undisclosed where the architecture expects a technology; OQC ATHENA: L7 undisclosed where the architecture expects a technology; OQC ATHENA: L8 undisclosed where the architecture expects a technology; OQC ATHENA: L9 undisclosed where the architecture expects a technology; OQC ATLAS: L1 ∅G-dimon (Atlas gap — roadmap names an 'advanced multi-mode qubit' for ATLAS — the Dimon's multimode single-devi); OQC ATLAS: L3 undisclosed where the architecture expects a technology; OQC ATLAS: L4 undisclosed where the architecture expects a technology; OQC ATLAS: L7 undisclosed where the architecture expects a technology; OQC ATLAS: L8 undisclosed where the architecture expects a technology; OQC ATLAS: L9 undisclosed where the architecture expects a technology; OQC GENESIS: L1 ∅G-dimon (Atlas gap — Dimon: three islands, two junctions, one dual-rail qubit per device; the transmon node doe); OQC GENESIS: L3 undisclosed where the architecture expects a technology; OQC TITAN: L1 ∅G-dimon (Atlas gap — roadmap names 'multi-mode qubits' for TITAN — the Dimon's multimode single-device dual rai); OQC TITAN: L3 undisclosed where the architecture expects a technology; OQC TITAN: L4 undisclosed where the architecture expects a technology; OQC TITAN: L7 undisclosed where the architecture expects a technology; OQC TITAN: L8 undisclosed where the architecture expects a technology; OQC TITAN: L9 undisclosed where the architecture expects a technology; SUSTech biased-erasure cavity qubit: L2 ∅G-fock02 (Atlas gap — qubit in |0⟩/|2⟩ Fock states of one cavity; photon loss flagged as erasure); SUSTech four-dual-rail-qubit processor: L3 Tunable-coupler CZ / iSWAP (g_tc, primary off the architecture's slots).
8.3.4 QCCD ions — Trapped ions — QCCD (transport between zones) (ion_qccd)
The idea. The quantum charge-coupled device (QCCD) keeps every gate in a small, cold crystal and moves the ions instead: electrode voltages carry hyperfine clock qubits through junctions or grid sites (cx_qccd) into zones where a Mølmer–Sørensen laser gate acts on two ions [D][97]. The qubit survives the ride; the motion does not, so every move costs splitting, merging and re-cooling. The bet: trade clock for fidelity and connectivity (any pair meets, at an error no static layout matches), then cut transport time faster than rivals close the fidelity gap. On Helios a two-qubit gate takes ~70 µs, a full-width layer ~55 ms [D][97].
What it needs. Ion shuttling requires junction or grid traps, whose electrodes grow with the register: 1,228 on Helios, driven by 273 voltages [D][97]. High-rate concatenated codes require the all-to-all that transport buys; on Helix, moving an ion relabels a qubit, so automorphism gates are free [P][5]. Carrier, encoding, connectivity, readout and interconnect hold one technology each; at gate, control and fabrication the laser and electronic branches are replaces pairs, so transport alone defines the architecture. The colour-code alternate conflicts with matching. The derived syndrome round: 9.66 ms, 9.04 ms of it transport [S] (§7.4).
Where it stands. Seven machines, four counted as devices: Quantinuum's H1-1, H2-1 and Helios and Universal Quantum's iQPU (Helix, a code on Helios, is a component); Sol (2027, 192 qubits) and Apollo are plans [R][118]. Helios, the largest, holds the best median two-qubit error, 7.9×10⁻⁴ across all pairs, with SPAM 3.3×10⁻⁴ [D][97]; on it ran 48 error-corrected logical qubits at ~1×10⁻⁴ logical gate error [D][105] and a Helix memory at 4.6×10⁻⁵ per logical qubit per cycle, not post-selected [P][5]. The iQPU publishes no gate error; no built machine has an interconnect technology.
Exceptions and borrowings. Integrated photonic delivery, the architecture's stated direction, is in no built machine: Helios drives each operation with focused free-space beams parallel to the chip surface [D][97] — so the free-space technology is the architecture's primary since 26 September 2026 and integrated photonics its alternate; the H1-1 and H2-1 cells are press-level. Quantinuum's decoders fall outside layer 8: real-time lookup tables on H1-1 and H2-1 (∅G-lut), Helix's offline block decoder (∅G-frontier). Helix is a code on Helios, not a second trap, and is counted as a component. The iQPU is a hybrid: microwave gate, chip control and foundry fabrication from the electronic-control architecture, transport from this one; it fits both with seven technologies each. Its interconnect is the gap ∅G-ionmatter: ions carried between two chip modules at 2,424 transfers s⁻¹, transport infidelity below 7×10⁻⁸ [D][117], the architecture's one demonstrated module link, credited in the family's scaling score (§2.3), absent from the map. Transport crosses the module edge; layer 9, photonic only, is drawn too narrowly. The iQPU's fabrication cell reads trap microfabrication on a commercial 200 mm line, the CMOS-foundry technology a press-level alternate. Innsbruck and QUARTET borrow ion shuttling as an alternate.
The next test. Sol decides it (§5.2): confirm if it ships in 2027 with ≥99.9% two-qubit gates on the 2D grid and a full-width layer below 10 ms, 5× faster than Helios; demote if it slips past 2027 or its layer stays within 2× of 55 ms: a code demonstrator, not an algorithm runner. The builder's own bar is lower — Quantinuum promised Sol "about twice as fast as Helios" — and meeting it would confirm the promise, not the architecture's claim to run algorithms, which needs the 5×. Second signal: a third transport-linked module.
What the builders say. Quantinuum's case for transport is connectivity: moving ions lets any qubit entangle with any other, enabling, it says, codes that fixed layouts cannot run [C][834]; its Helix code concatenates codes in a way it calls extremely difficult without mobile qubits [C][835]. In 2024 it promised Sol with hundreds of physical qubits below 2×10⁻⁴ two-qubit error, about twice as fast as Helios, and Apollo with hundreds of logical qubits at logical error below 10⁻⁶ [R][836]; since June 2025 Apollo is dated 2029 [R][837]. In August 2026 Sol's trap chip was back from fabrication for a 2027 launch, and Apollo was on schedule for 2029 [R][123], [124]. Universal Quantum links trap chips by carrying ions between them, a route it says scales to millions of qubits [C][838].
Machines of this architecture (register: 7, of them 4 devices, 4 gate-capable). Quantinuum — Helios (deployed, 98), System Model H2 (H2-1, H2-2) (deployed, 56), Helix architecture on Helios (demonstrated, 20), System Model H1 (H1-1) (deployed, 20), Apollo (planned), Sol (planned); Universal Quantum — iQPU / UQConnect (demonstrated, 64).
Cells outside the architecture's slots (4). System Model H1 (H1-1): L8 ∅G-lut (Atlas gap — real-time lookup-table decoding of Steane [[7,1,3]] in-loop since 2021; no LUT node among ); System Model H2 (H2-1, H2-2): L8 ∅G-lut (Atlas gap — real-time lookup-table decoder); Helix architecture on Helios: L8 ∅G-frontier (Atlas gap — Frontier: block-specific offline decoder for concatenated high-rate codes, neither matchin); iQPU / UQConnect: L9 ∅G-ionmatter (Atlas gap — chip-to-chip matter link: UQConnect physically transfers ions between trap modules, 2,424 ).
8.3.5 Laser-addressed chain — Trapped ions — linear Paul trap with individual laser addressing (ion_chain)
The idea. One static chain in a linear Paul trap: its collective motional modes (cx_bus) couple every pair, so a Mølmer–Sørensen gate entangles any two ions without moving them, and each ion gets its own acousto-optically steered beam (ct_ionaod). The qubit is hyperfine (Yb⁺, Ba⁺) or the optical S–D qubit of ⁴⁰Ca⁺ (enc_opt: AQT, Innsbruck, PIAST-Q). It gives up length: N ions share N modes in a fixed bandwidth, so gates slow as the chain grows, to a median 672 µs on Forte's 30 ions [D][100], [101]. The bet: connectivity is free inside a chain of tens of ions; scale is bought at its edge with photonic links between chains, the modular architecture of Monroe et al. [S][252].
What it needs. The gate requires spin–motion coupling and free-space laser fields, which require bulk optics. The two defining technologies conflict (open): mode crowding makes the gate slower and less faithful with each ion; the mitigations (zoned short chains, electronic gates on ≤4-ion segments) belong to other ion architectures. qLDPC and high-rate codes require the chain's all-to-all: four logical qubits in 18 ions [D][109]. Encoding offers three mutually replacing technologies (hyperfine, optical, metastable); carrier, gate, connectivity, readout and interconnect have one technology each; the interconnect, Ion–photon photonic link, carries the scaling bet at a best 250 s⁻¹ [D][116] against ~10⁴ s⁻¹ needed [S] (§2.3). Layer 10 is drawn too narrowly: planar surface-electrode chips only, while IBEX Q1 runs in a machined blade trap [D][253] and the 512-ion crystal in a monolithic 3D trap [D][121].
Where it stands. Sixteen machines, thirteen devices: IonQ's Aria, Forte and 40-ion Ba-133 qLDPC testbed; AQT's IBEX Q1 and LYNX (15 qubits, quantum volume 32,768 in May 2026 [C][128]); PIAST-Q; Sandia's QSCOUT; Qudoor's AbaQ; the Innsbruck and Maryland/Duke traps; Tsinghua's analogue 512-ion simulator [D][121]. Tempo counts as a 64-qubit demonstration (IonQ's #AQ 64 run on a development system) without a published gate error; the 100-qubit product with its "99.9% fidelity" is listed for late 2026 [C][100], [101]. Quantum Art's Perspective (a 1,000-qubit multi-core system) [C][125] and the FIAN / Rosatom 70-qubit machine (35 ions as qudits) are announcements. The largest gate-capable device is Tempo's 64-qubit development register, which has no published gate error; the largest with published gate errors, the 40-ion testbed, reached memory break-even within error bars, 3.95(68) s logical against 3.84(48) s physical, with leakage post-selection [D][109]. Maryland/Duke's 3.0×10⁻³ is a logical Clifford error after correction, not a physical figure, and is no longer counted [D][254]; Table 8.3's best error is therefore the vendor's 4.0×10⁻³ on Aria and Forte [C][99]. IonQ, the largest vendor, has put its successor, Superion 256, on electronic gates [C][119].
Exceptions and borrowings. Maryland/Duke carries three: that logical figure; a Bacon–Shor subsystem code with no technology (∅G-subsystem; its high-rate alternate encodes one qubit); a link cell merging a separate experiment, the 250 s⁻¹ record [D][116], with Oxford's 9.7 s⁻¹ link [D][115]: a lineage, not a machine. Innsbruck borrows ion shuttling (segmented traps) and the magic-state technology [D][255]: a lineage spanning both laser architectures, and a code layer drawn too narrowly; its measurement-free feedback is a gap (∅G-coherent). IBEX Q1's shuttling alternate describes AQT's research traps, not the product: mislabelled. Forte's CMOS-foundry alternate projects IonQ's SkyWater route, first used for the 256-qubit chips of 2026 [C][119], onto a 2022 machine. The testbed and Tempo decode by offline beam search (∅G-beam), outside layer 8; Tempo's code cell repeats the testbed's run. Tsinghua's crystal is analogue under global beams (∅G-isinganalog, ∅G-crystal): the architecture is drawn too widely, and ions lack an analogue architecture. Quantum Art's link is filed as undisclosed, yet its paper segments one crystal into cells with reconfigurable optical potentials [S][256]: neither bus nor transport, a gap. Qudoor's control and all Rosatom cells: data gaps. Borrowers: the electronic-control architecture takes the motional bus (JION, QUARTET, Superion 256); planqc's MAQCS the optical qubit.
The next test. The link decides: confirm if an ion–photon link exceeds 10³ s⁻¹ by end-2027; demote if none passes ~10× the 250 s⁻¹ record by end-2028. At chain scale, confirm if per-pair errors and gate times appear for Tempo or any chain above 40 ions by end-2027; if disclosure stays at headline level while IonQ ships electronic gates, the architecture narrows to racks and laboratories, leaving early fault tolerance to other ion architectures.
What the builders say. IonQ reached #AQ 64 (its algorithmic-qubit benchmark) on a Tempo development system in a single ion chain with all-to-all connectivity [C][839]; in April 2026 it linked two commercial machines by photons, calling scaling beyond one chip essential [C][589]. AQT claims quantum volume 32,768 for LYNX, its rack-mounted series, first units due in Q4 2026 [C][128], [129]. Quantum Art cuts long chains into cores with laser-defined boundaries and promises 1,000 physical and up to 100 logical qubits in 2027, a million physical by 2033 [R][840]. FIAN reached 50 qubits with qudits, ions using more than two levels, doubling the count cheaply [C][841]; in August 2026 it and the Russian Quantum Center moved to planar traps, where ions shuttle between small arrays instead of one chain [C][842].
Machines of this architecture (register: 16, of them 13 devices, 11 gate-capable). IonQ — Tempo (demonstrated, 64), 40-ion Ba-133 qLDPC testbed (IonQ: a Tempo engineering test system) (demonstrated, 40), Aria (deployed, 32), Forte / Forte Enterprise (deployed, 30); Alpine Quantum Technologies — AQT LYNX (demonstrated, 15), IBEX Q1 (Marmot / PINE) (deployed, 12); Quantum Art — Montage (first-generation QaaS system, up to 50 qubits) (announced, 50), Perspective (1,000-qubit multi-core system) (announced); IQOQI Innsbruck (Austrian Academy of Sciences) with the University of Innsbruck (M. Joshi, C. Roos) — Innsbruck trapped-ion analog quantum simulator (up to 51 ions) (demonstrated, 51); Lebedev Physical Institute (FIAN) and the Russian Quantum Center, Rosatom roadmap — 70-qubit ion quantum computer (FIAN / Rosatom roadmap) (announced, 70); Poznan Supercomputing and Networking Center (PCSS) — PIAST-Q (deployed, 20); Qudoor (Guokaike) — Aba|Qu 1.0 (Tiansuan-1, 天算1号) (deployed); Sandia National Laboratories — QSCOUT (Quantum Scientific Computing Open User Testbed) (deployed, 6); Tsinghua University (Duan group) — 2-D site-resolved ion simulator (demonstrated, 512); University of Innsbruck — University of Innsbruck trapped-ion demonstrator (Institut für Experimentalphysik) (demonstrated, 20); University of Maryland / Duke University — Maryland / Duke Quantum Center (EURIQA lineage) (demonstrated, 13).
Cells outside the architecture's slots (13). 40-ion Ba-133 qLDPC testbed (IonQ: a Tempo engineering test system): L8 ∅G-beam (Atlas gap — beam-search decoder (Delfosse) for the qLDPC codes, run offline; no Atlas node for search ); Montage (first-generation QaaS system, up to 50 qubits): L5 undisclosed where the architecture expects a technology; Montage (first-generation QaaS system, up to 50 qubits): L9 undisclosed where the architecture expects a technology; Perspective (1,000-qubit multi-core system): L5 undisclosed where the architecture expects a technology; Perspective (1,000-qubit multi-core system): L9 undisclosed where the architecture expects a technology; Aba|Qu 1.0 (Tiansuan-1, 天算1号): L5 undisclosed where the architecture expects a technology; 2-D site-resolved ion simulator: L3 ∅G-isinganalog (Atlas gap — global laser-driven spin–spin coupling; analog Ising simulator in a 2-D ion crystal, not a); 2-D site-resolved ion simulator: L4 ∅G-crystal (Atlas gap — static 2-D Coulomb crystal, power-law all-to-all coupling (511 neighbours), no transport); University of Innsbruck trapped-ion demonstrator (Institut für Experimentalphysik): L4 Ion shuttling (QCCD, junctions, grid traps) (cx_qccd, alternate borrowed from another architecture); University of Innsbruck trapped-ion demonstrator (Institut für Experimentalphysik): L8 ∅G-coherent (Atlas gap — measurement-free: syndromes mapped into an auxiliary register, coherent feedback unitary r); Innsbruck trapped-ion analog quantum simulator (up to 51 ions): L3 ∅G-isinganalog (Atlas gap — analog long-range Ising / XY interaction from a bichromatic beam coupling all transverse m); Innsbruck trapped-ion analog quantum simulator (up to 51 ions): L4 ∅G-crystal (Atlas gap — static linear Coulomb chain, long-range (J0 = 185 rad/s, alpha = 0.97 at 51 ions), no tran); Maryland / Duke Quantum Center (EURIQA lineage): L7 ∅G-subsystem (Atlas gap — Bacon–Shor [[9,1,3]] subsystem code on 13 ions: FT prep, FT measurement, logical rotation,).
8.3.6 Electronic ion gates — Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (ion_elec)
The idea. Take the laser out of the entangling gate: currents in the trap chip's electrodes make a microwave field whose gradient couples a hyperfine ion qubit to the shared motion (g_elec); drive traces are shared and local tuning electrodes select the ions [D][257]. A microwave photon reaches no excited state, so laser gates' scattering floor vanishes: 8.4×10⁻⁵ on two ions, without ground-state cooling [D][102]. Speed is the price, since a stronger gradient puts the ion nearer heating surfaces: 225.8 µs per gate [D][102] against ~70 µs on Helios [D][97]. The bet: control that scales like electronics, ~200 sources for 1,000 ions [S] (§7.5).
What it needs. The gate requires chip-integrated microwave control (ct_ionmw), which requires current traces in the trap: the chip is the control system, with no fallback to laser gates. Lasers remain for cooling, state preparation and fluorescence readout. Carrier, gate, control, readout and interconnect have one technology each; elsewhere the options replace each other: chain bus or shuttling, qLDPC or high-rate codes (both require all-to-all), Relay-BP or matching, trap microfabrication or a 300 mm CMOS line. Without transport the derived syndrome round is gate-limited: 1.52 ms, 1.4 ms of it in gates [S] (§7.4).
Where it stands. Seven machines, three devices, no code, decoder or link run. QUARTET (Oxford Ionics/IonQ), at the UK's National Quantum Computing Centre, is the largest at 32 qubits (Table 8.3), a count no primary source gives; its evidence paper shows a seven-zone chip for up to 10 qubits [D][257]. JION (eleQtron with Forschungszentrum Jülich), inaugurated on 3 Sep 2026, runs 30 ytterbium ions with no published fidelity [P][258]; its predecessor QSea I, eleQtron's 10-qubit demonstrator for the DLR Quantum Computing Initiative, has run in Hamburg since July 2024 [C][327]. Hence no best error in Table 8.3: the 99.99% is a two-ion record [D][102]. Superion 256 is orderable: SkyWater-made chips, ions trapped in prototypes, no 256-qubit fidelity [C][119]; IonQ Superion 10K (commercial 2028) [R][119] and NFQC-1k (≥1,000 physical, 50 logical qubits by 2030) [R][126] are plans; XAPHIRO (QUDORA NFQC) is under construction — a first ion trapped in June 2025, fifty qubits due by January 2027; only its emulator is reachable.
Exceptions and borrowings. No cell leaves the architecture's slots; the exceptions are in the evidence. Superion 256 alone fills all ten layers, from plans: a qLDPC code from a resource estimate [S][112], a claimed photonic link [C][119], a Relay-BP cell reading "algorithm not named" while IonQ's published decoder runs on one CPU [S][111] (mislabelled), a metastable-encoding alternate citing nothing. Layers 7–9 are IonQ's intentions. IonQ Superion 10K and NFQC-1k leave four layers undisclosed: early stage. JION's MAGIC (magnetic-gradient-induced coupling) addresses ions by frequency in a static gradient, a second mechanism inside a technology defined by the near-field one: drawn too widely. QUARTET's shuttling alternate has no timeline. Universal Quantum's iQPU (QCCD architecture) borrows the gate and control technologies and fits both architectures equally: a hybrid.
The next test. Superion 256 is due at NVIDIA's research centre and Florida International University in 2027 [C][130], [131]. Confirm if it is commissioned by end-2027 near 10⁻⁴ two-qubit error over the full register, publishing gate time, heating and crosstalk (§5.2). Demote if it slips beyond 2027, or if its error lands tenfold above the two-ion record once hundreds of microwave channels share a die: electronic control would then remain the single-qubit layer of laser-entangled machines.
What the builders say. Oxford Ionics argues that one high-fidelity qubit is worth hundreds of poor ones, projecting 13 physical qubits per logical qubit and, without dates, 10,000+ qubits by replicating its 256-qubit design [C][843]. IonQ, its owner since 2025, expects electronic control to cut the cost per qubit over 300-fold against lasers and takes orders for Superion 256, delivery in 2027 [C][119]; with CMOS on the chip it promises full fault tolerance in its laboratory in 2027 and commercially in 2028 [R][119]. eleQtron calls MAGIC, microwave control with a magnetic-field gradient, a clear path to scale [C][128], [129], and opened JION at Jülich in September 2026 [C][844]. QUDORA's consortium aims within five years at a demonstrator of 1,000 physical and 50 logical qubits below 10⁻⁴ logical gate error [R][126].
Machines of this architecture (register: 7, of them 3 devices, 3 gate-capable). IonQ — IonQ Superion 10K (planned, 10,000), Superion 256 (announced, 256); Oxford Ionics (IonQ) — QUARTET (deployed, 32); QUDORA Technologies — XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative) (announced); QUDORA Technologies-led consortium (TU Braunschweig, Leibniz University Hannover, PTB, Forschungszentrum Jülich, NXP Semiconductors Germany, AQT Germany) — NFQC-1k (planned, 1,000); eleQtron + Forschungszentrum Julich — JION (deployed, 30); eleQtron with NXP Semiconductors and ParityQC, for the DLR Quantum Computing Initiative — QSea I (DLR QCI ion-trap demonstrator) (deployed, 10).
Cells outside the architecture's slots (10). IonQ Superion 10K: L4 undisclosed where the architecture expects a technology; IonQ Superion 10K: L8 undisclosed where the architecture expects a technology; IonQ Superion 10K: L9 undisclosed where the architecture expects a technology; Superion 256: L7 undisclosed where the architecture expects a technology; Superion 256: L8 undisclosed where the architecture expects a technology; XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative): L4 undisclosed where the architecture expects a technology; NFQC-1k: L4 undisclosed where the architecture expects a technology; NFQC-1k: L7 undisclosed where the architecture expects a technology; NFQC-1k: L8 undisclosed where the architecture expects a technology; NFQC-1k: L9 undisclosed where the architecture expects a technology.
8.3.7 Alkali Rydberg gates — Rydberg tweezer array — alkali (Rb/Cs) (atom_rb)
The idea. A rubidium or caesium atom in an optical tweezer holds a hyperfine clock qubit, coherent for 12.6 s in a 6,100-atom caesium array [D][138], [139]. A global laser pulse drives neighbours toward a Rydberg state, where one excitation blocks the other: a CZ gate in ~270 ns [D][4]. Acousto-optic deflectors (AODs) move atoms or whole code blocks so any pair can meet: connectivity is a program. The price is the clock: transport and imaging, not the gate, set a derived QEC round of 1.31 ms [S] (§7.4), 1–4.5 ms measured [D][4], [31]. The bet: qubits that cost laser power, not fabrication, and transversal logic between moved blocks, with constant syndrome rounds per logical gate, buying back the transport time [S][152].
What it needs. The gate requires the alkali atom and global Rydberg pulses from free-space lasers (ct_laser). The high-rate and algorithmic-fault-tolerance codes require AOD transport: moving one block onto another pairs every qubit with its partner under one pulse. Algorithmic fault tolerance requires correlated, loss-aware decoding, which requires transversal circuits; its gain, 1.73(13)× over a loss-blind decoder, rests on four rounds of one run [D][4], none in real time. Continuous reload replaces one-shot loading and conflicts with the stored qubits, which see scattered cooling light; a reservoir carried 0.5 m by conveyors mitigates it [D][144]. Carrier, encoding, gate, interconnect and fabrication hold one technology each, code five, decoder four: the hardware is fixed, the code open. No atom–photon cavity link has joined two modules; AOD bandwidth runs out near 10⁴ atoms [S] (§2.4).
Where it stands. Sixteen machines, seven devices, five gate-capable. The largest, the 448-atom fault-tolerant processor (Harvard/MIT/QuEra), holds the best two-qubit error, 5.0×10⁻³ (CZ fidelity 99.3–99.6% by randomised benchmarking) [D] (Table 8.3), and ran surface codes d=3→5 with 2.14× suppression over four rounds and up to 96 logical qubits [D][4]. Gemini-class (QuEra; 99.2% global CZ, one shot per second [C][137]) ran logical magic-state distillation [D][147]; Sqale (Infleqtion) entangled 30 logical qubits in error-detecting blocks [C][151]; Orion Alpha/Beta/Gamma (Pasqal) publishes no gate error. The largest arrays have no gate: the 6,100-qubit tweezer array [D][138], [139] and the continuously reloaded 3,000-atom machine, run over 2 h [D][144]. Libra (QuEra, 2028: >256 logical qubits at 10⁻⁶) [R][162], [163] and Pasqal's Vela, Centaurus (500+ qubits, 2028) and Lyra (2029) are plans [R][166], [167], [875]; Google's 2026 track names no species [P][158]. Rows with no documented cell — 6: Hanyuan-1, Hanyuan-2, Qinghe-1, the Moscow State University prototype, the Quantum X Labs platform.
Exceptions and borrowings. The boundary with the analogue simulator architecture (atom_analog) runs through layers 2 and 3: carrier, transport, control, readout and fabrication are shared, but the analogue qubit is the ground–Rydberg pair and its computation continuous Hamiltonian evolution, with no code, decoder or link above. Pasqal crosses it both ways: Orion, filed here, lists the analogue encoding and evolution as alternates; Fresnel, filed there, lists the hyperfine qubit and blockade CZ. One apparatus runs either mode, so the line divides modes, and a machine is filed by its primary one: hybrids, not errors. Orion's chip-optics alternate cites nothing. Gemini-class and Libra list fast readout as an alternate neither machine shows: mislabelled. Libra's ten-layer fit rests on a cavity cell specifying no link. The reload machine is dated August 2026 from a review; its paper is from 2025 [D][144]. The Moscow prototype has no entangling gate yet a two-qubit error from a press statement; Quantum X Labs names no species; Hanyuan-2's inter-core link is undisclosed: data gaps. The alkaline-earth architecture shares gate, transport, reload, decoder and cavity; carrier and erasure encoding divide them.
The next test. Confirm by end-2027 (§5.2): a memory of ≥100 rounds with reloading at Λ>2 (error suppression per code-distance step) on an alkali array, and a gate-capable alkali processor above 1,180 qubits, the family frontier the alkaline-earth architecture has held since 2023 (§8.5, F1b). Demote if Libra slips past 2028, or two-qubit fidelity stalls at 99.9%, the ceiling a 2026 review sets for the standard CZ, with no new gate scheme [S][140].
What the builders say. Harvard's Mikhail Lukin says the 448-atom processor combined, for the first time, all essential elements of scalable error-corrected computation in one architecture [D][845]; Caltech says its 6,100-atom array has quantity and quality together [D][138], [139]. QuEra promises Libra on Amazon Braket in 2028, with over 256 logical qubits at a logical error of 10⁻⁶ [R][162], [163]. Infleqtion, after entangling 30 logical qubits in error-detecting blocks in September 2026, says it is on track for 100 in 2028 and 1,000 by 2030 [R][168]. Pasqal's 2025 roadmap runs from 2 logical qubits in 2025 to 20 in 2027, 100 in 2029 and 200 in 2030 [R][166], [167]; in January 2026 it moved Vela, over 256 qubits, from 2027 to 2026 [R][390].
Machines of this architecture (register: 16, of them 7 devices, 5 gate-capable). Pasqal — Pasqal Centaurus (planned, 500), Vela (announced, 256), Orion Alpha / Beta ("Ruby") / Gamma (deployed, 140), Pasqal Lyra (planned); Infleqtion — Sqale (deployed, 100), Infleqtion Illinois neutral-atom quantum computer (IQMP, Chicago) (announced); QuEra — Libra (planned, 10,000), Gemini-class (deployed, 260); Zhongke Kuyuan (Wuhan, CAS) — Hanyuan-2 (announced, 200), Hanyuan-1 (deployed, 100); Caltech (Endres group) — 6,100-qubit tweezer array (demonstrated, 6,100); Harvard / MIT — continuously reloaded 3,000-atom machine (demonstrated, 3,000); Harvard / MIT / QuEra — 448-atom fault-tolerant processor (demonstrated, 448); Lomonosov Moscow State University with the Russian Quantum Center — 72-qubit neutral-atom (Rb) quantum computer prototype (50 qubits in Dec 2024) (announced, 72); Quantum X Labs Inc. (Nasdaq: QXL) — Quantum X Labs neutral-atom platform (50+ qubits, claimed) (announced, 50); Zhongqi Wuliang (Shanghai, CAS SIOM spin-off) — Qinghe-1 (Qinghe No. 1, 清河一号) (announced).
Cells outside the architecture's slots (8). Hanyuan-2: L9 undisclosed where the architecture expects a technology; Pasqal Centaurus: L7 undisclosed where the architecture expects a technology; Pasqal Centaurus: L8 undisclosed where the architecture expects a technology; Pasqal Lyra: L7 undisclosed where the architecture expects a technology; Pasqal Lyra: L8 undisclosed where the architecture expects a technology; Orion Alpha / Beta ("Ruby") / Gamma: L2 Ground–Rydberg analogue qubit (enc_gr, alternate borrowed from another architecture); Orion Alpha / Beta ("Ruby") / Gamma: L3 Analogue Rydberg Hamiltonian evolution (g_rydanalog, alternate borrowed from another architecture); Libra: L9 undisclosed where the architecture expects a technology.
8.3.8 Alkaline-earth arrays — Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native (atom_ae)
The idea. Ytterbium and strontium have a metastable ³P₀ level one clock-line photon above the ground state. Store the qubit there (the Metastable ('omg') erasure encoding on the Alkaline-earth(-like) atom (Yb/Sr) — erasure-native), and ground-state imaging light, dark to the qubit, reveals atoms that decayed out of it: errors arrive located, as erasures. The bet: a worse gate for a cheaper code. At 98% conversion the surface-code threshold rises from 0.94% to 4.15% [S][8]; measured, a metastable CZ errs 0.016(1), 38(6)% flagged, against 0.0060 raw on the ground-state ¹⁷¹Yb qubit [D][135], [141], [142].
What it needs. A relay: the encoding requires the metastable manifold; the Mid-circuit erasure check requires the encoding, since only a qubit dark to imaging can be checked unread; Erasure-adapted codes require the flags and Correlated / loss-aware decoding, since a plain matcher cannot use them. Break a link and the machine is an alkali array with a heavier atom. Five layers have one option; replaces edges name the retreats: ground-state or optical encodings, surface code, millisecond imaging, one-shot loading. One conflict: reload light (a magneto-optical trap, MOT, and a repumper) depletes stored atoms; a repumper-free MOT and ³P₀ shelving, 13 s lifetime, mitigate it [P][259].
Where it stands. Six machines, three devices (Table 8.3). Phoenix (Gen-1) and Gen-2, 1,180 ¹⁷¹Yb atoms (Oct 2023), is the largest gate-capable device, with the only two-qubit figure, 4.0×10⁻³ [C][148]; its toric code ran 90 rounds, but suppression vanished with reloading included [D][148]. Magne, 1,225 physical for ~50 logical, is being installed for early 2027 [R][11], [12], [164], [165]. The metastable Yb-171 erasure array (Princeton, 20 atoms) slowed [[4,2,2]] decay 1.9(4)× with unconditional erasure decoding [D][141], [142]. MAQCS and DiNAQC: a 1,000-qubit demonstrator at TRL 5 [C][161]; the neutral-ytterbium QPU began hardware validation in August 2026 [C][260]. 31 of 67 cells documented.
Exceptions and borrowings. All five fit here best; only Princeton runs the bet's encoding, check, code and decoder as primaries. Phoenix and Magne encode in the ¹⁷¹Yb ground-state nuclear spin (Yaqumo by inference); their erasures are imaged atom losses, as on rubidium [D][4]. Phoenix's metastable-encoding cell is denied by its own note (mislabelled), its code is an Atlas gap, ∅G-toric (code technology too narrow), its row joins ⁸⁷Sr and ¹⁷¹Yb generations. MAQCS encodes on the Sr clock line, 10–100 ms coherence [P][246], [247], in an optical lattice (∅G-lattice, shared with QUIONE), no code, an undisclosed core link; planqc's error-corrected line, LOGIQC, is ytterbium [C][160]. Yaqumo's fast readout is inferred from 17.6 µs imaging of spinless ¹⁷⁴Yb [P][261]: early stage. No machine has the Atom–photon cavity interface. Borrowers: OQC GENESIS (check), Superion 256 (encoding), IBEX Q1 (optical qubit), QUIONE (carrier). The architecture is drawn by species; erasure-native rests on one laboratory.
The next test. Consistent with §5.2: by mid-2027 Magne crosses the 1,180-qubit frontier (§8.5, F1b) and delivers 50 logical qubits, decoded with erasure flags on unconditioned data; loss detection alone confirms the carrier, not the encoding. By end-2027 a group outside Princeton and Caltech converts over 70% of a metastable CZ's error with residual below 3×10⁻³; if none passes 50% and the next Yb memory again loses suppression under reloading, the architecture demotes to a species choice within the alkali bet.
What the builders say. Atom Computing credits its ytterbium nuclear-spin qubits with record coherence, needed for deep algorithms [C][846], and calls its June 2026 toric-code run practical error correction [C][846]. Microsoft expects Magne, more than 1,200 physical qubits from Atom Computing, online in early 2027 [R][847]. Princeton's argument for the metastable qubit is overhead: fewer errors, and the remaining ones shaped to be easier to correct [D][141], [142]. planqc plans MAQCS, its 1,000-qubit demonstrator, as a co-processor at LRZ by the end of 2027 [R][161], and Yaqumo a ytterbium system of several hundred qubits with error correction by fiscal 2027 [R][260].
Machines of this architecture (register: 6, of them 3 devices, 3 gate-capable). Atom Computing — Phoenix (Gen-1) and Gen-2 (deployed, 1,180); Atom Computing + Microsoft, for QuNorth — Magne (announced, 1,225); Princeton (Thompson group) — metastable Yb-171 erasure array (demonstrated, 20); Yaqumo (+ Fujitsu) — neutral-ytterbium QPU (demonstrated); planqc — MAQCS (planned, 1,000); planqc, for the DLR Quantum Computing Initiative — DiNAQC (planned, 100).
Cells outside the architecture's slots (5). Phoenix (Gen-1) and Gen-2: L7 ∅G-toric (Atlas gap — toric code d=4 and d=6, up to 90 syndrome-extraction rounds; lower logical error at larger); DiNAQC: L7 undisclosed where the architecture expects a technology; DiNAQC: L8 undisclosed where the architecture expects a technology; MAQCS: L4 ∅G-lattice (Atlas gap — no Atlas node: optical-lattice grid ('egg carton made of light'), no per-atom tweezer move); MAQCS: L9 undisclosed where the architecture expects a technology.
8.3.9 Analogue atom simulator — Neutral-atom analogue simulator (Rydberg arrays, lattice gases) (atom_analog)
The idea. Keep the alkali tweezer array with its lasers, transport and imaging; drop the gate: global Rydberg lasers drive the whole register under one Ising Hamiltonian, Analogue Rydberg Hamiltonian evolution (g_rydanalog) on the Ground–Rydberg analogue qubit (enc_gr). Waveforms Ω(t), Δ(t) and atom geometry are the program, a bit-string snapshot the output. The bet: for many-body physics (G1), native Hamiltonian evolution reaches hundreds of atoms now. It gives up memory, gates and any route to fault tolerance.
What it needs. The evolution requires the ground–Rydberg basis, a Rydberg level in the carrier and global Rydberg lasers; imaging, an imaging transition. Code, decoder and interconnect are empty by design (§7.6): here analogue simulation stops being a quantum computer in the register's sense. The encoding is a basis, not a memory: |r⟩ cannot be shelved; Aquila's T2 is 5.8 µs, programs stop at 4 µs [C][262]; errors integrate coherently with no instant for a syndrome, so no code attaches and no decoder has input. Without an entangling gate they are devices, not processors (Table 8.3 prints no gate-capable size, no two-qubit error). The one replaces* edge swaps the species.
Where it stands. Three machines, three devices, none gate-capable. Aquila (QuEra, 256 ⁸⁷Rb atoms, on Amazon Braket since November 2022) [C][262] carries the physics: (2+1)D string breaking in a gauge theory, no advantage claim [D][226]. Fresnel / Fresnel 2 (Pasqal, deployed 2023–2024) publishes no error rates. QUIONE (ICFO, April 2024) images an ⁸⁴Sr quantum gas site by site in an 813.4 nm lattice, fidelity above 94% [D][263]. §7.4's T2 for the architecture is the ground–Rydberg qubit's own 11.4 µs (Aquila, spin echo) [C][262] since 26 Sep 2026, no longer the carrier's 12.6-s caesium hyperfine record [138], [139], which a qubit with a Rydberg level cannot use. 25 of 33 cells documented. No machine postdates 2024; the vendors' later ones (Gemini-class, Libra, Orion, Vela) are gate-model.
Exceptions and borrowings. The dual-mode Pasqal machines mirror each other: Fresnel / Fresnel 2 runs analogue as primary, its digital mode (Hyperfine / clock-state qubit, Rydberg-blockade CZ) and PIC-generated tweezers as alternates; Orion Alpha / Beta ("Ruby") / Gamma, on the alkali architecture, swaps the modes; all else matches. Each fits its own architecture seven technologies to five: the boundary with atom_rb is a mode switch in layers 2–3 of one hardware (hybrid). The gate separates simulator from processor; the line fault tolerance needs, a code, neither has crossed. QUIONE lacks encoding, gate and Rydberg state: a Bose–Hubbard gas in a lattice (∅G-lattice, shared with MAQCS) under a carrier named for erasure-native tweezer qubits, here by elimination (four technologies in slot): the architecture is too narrow for lattice quantum-gas simulators. Caltech's erasure-excising Sr Rydberg simulator [143], which the new alkaline-earth edges describe, is not in the register.
The next test. Two expectations; §5.2 has no analogue row. Confirmation: by 31 December 2027 a commercial analogue machine publishes a many-body fidelity at 60 or more atoms or a T2* above 20 µs, or an analogue result survives a year of classical challenge (§2.8). Demotion: if Vela and QuEra's next systems ship without analogue specifications and no analogue-first machine is announced by mid-2027, analogue simulation is a mode, analogue alternates of layers 2–3 on atom_rb, not an architecture.
What the builders say. Pasqal runs analogue workloads today on hardware it designs to evolve toward fault tolerance [C][157]. In June 2025 it promised a 250-qubit processor built for quantum advantage on an industry problem, to be demonstrated in the first part of 2026 [R][166], [167]. In September 2026 it reported simulating materials beyond the practical reach of classical computing [C][157]: 256 atoms on Orion Beta reproduced the magnet TmMgGaO₄, checked against crystal measurements [P][848]. QuEra says real-time gauge-theory dynamics with dozens of qubits on Aquila reach the limits of classical simulation [C][849]. ICFO's case for QUIONE: quantum simulation can answer questions current computers cannot, such as why some materials conduct without loss at relatively high temperatures [C][850].
Machines of this architecture (register: 3, of them 3 devices, 0 gate-capable). ICFO - Institut de Ciencies Fotoniques — QUIONE (demonstrated); Pasqal — Fresnel / Fresnel 2 (deployed, 100); QuEra — Aquila (deployed, 256).
Cells outside the architecture's slots (4). QUIONE: L4 ∅G-lattice (Atlas gap — atoms held in a 2-D in-plane optical lattice plus light sheet at 813.4 nm; no per-atom mov); Fresnel / Fresnel 2: L2 Hyperfine / clock-state qubit (enc_hf, alternate borrowed from another architecture); Fresnel / Fresnel 2: L3 Rydberg-blockade CZ (g_ryd, alternate borrowed from another architecture); Fresnel / Fresnel 2: L5 PIC-generated tweezers / integrated optics for atoms (ct_pic_trap, alternate borrowed from another architecture).
8.3.10 Photon fusion — Fusion-based photonic (FBQC) (ph_fusion)
The idea. Single photons in path or time-bin encoding are never joined by a gate: Linear-optical fusion (g_fusion) measures two photons from small pre-made resource states in the Bell basis, destroying both, and Fusion-based fault tolerance reads the logical state from the pattern of outcomes. The fact exploited: a photon does not decohere, loss is its dominant error, and a failed fusion announces itself: it erases one of its two measured outcomes, at a known place. The price is determinism. The bet: a foundry can build fault tolerance if each photon loses under 2.7% end to end, the threshold with 6-ring resource states [S][179].
What it needs. Fusion requires number-resolving detection to herald and switching with feed-forward to route the next photon within its flight time; the switches require the Photonic IC foundry, where each costs 0.1–0.2 dB of a ~0.5 dB per-photon budget [D][169]. The code requires the Multi-photon resource-state generator (src_resource), an empty slot: fused states reach 8 photons at under 1 Hz against 24–168 photons at MHz [D] (§7.6). A 2026 re-analysis adds a logical-error floor set by fusion failure alone [S][264]. Seven layers hold one technology each, and nothing inside the architecture replaces or conflicts; fusion itself forecloses the continuous-variable branch, replacing Gaussian gates as counting replaces homodyne detection.
Where it stands. Six machines, three devices (Table 8.3), no logical qubit. Omega chipset (PsiQuantum, February 2025), all ten technologies in slot, is a component set and is counted as such, not as a device: fusion Bell fidelity 99.22%, chip-to-chip Bell 99.72% over 42 m [D][169]; its 7.8×10⁻³ is that single fusion, and its code and decoder cells are flagged no-QEC-cycle. Belenos and Lucy (Quandela, 12 qubits each; Lucy at CEA, 2025 [176]) are the largest gate-capable devices; their 6.2×10⁻² is Ascella's 2023 figure [D][265], and Lucy has 0 of 14 cells documented. The ETRI 8-photon silicon-photonic qubit chip publishes no error rate; Carina (QuiX Quantum, 8 qubits) awaits commissioning at DLR [177]; Quandela's Canopus (24 qubits) is announced for its cloud in 2026 [C][876].
Exceptions and borrowings. No cell falls off the architecture, yet it is drawn wider than its bet. Belenos, Lucy and the ETRI chip occupy the fusion technology with post-selected or probabilistic gates in a reconfigurable mesh, circuit-model linear optics that the register's own cells call "not FBQC fusion"; only Omega and Carina fuse. Quandela's fault-tolerance design is a hybrid of quantum emitters and linear-optical gates [266]. Both Quandela machines carry an Atlas gap, ∅G-twofab: a III-V quantum-dot source and a SiN/silica mesh, two fabrication technologies where the map allows one (layer 10 too narrow). Omega and Belenos list the resource-state generator, an empty slot, as an alternate technology; Belenos's own cell calls the route undemonstrated (mislabelled). The other four have no code, decoder or interconnect: early stage. On other architectures, Aurora, Jiuzhang 4.0 and Borealis use its detector technology.
The next test. By March 2028 (§5.2), a chain of three or more fusions, or a resource state beyond Bell pairs fused into a network, published with an end-to-end success rate, would show that the architecture's real clock, resource-state supply, exists. Demoted in October 2026: PsiQuantum's 2027 target moved — its June 2026 release dates only the cryoplant (second half of 2027) and names no operating date. Promoted back by a dated first system or a fusion-based logical qubit; demoted further if only single-fusion figures remain, fused states stay at eight photons, or PsiQuantum's Stage C validation [181] comes back negative.
What the builders say. PsiQuantum's co-founder, Jeremy O'Brien, argues that a useful quantum computer must fully leverage the semiconductor industry [C][851]. In 2024 PsiQuantum planned its Brisbane site operational by the end of 2027, its first system near a million physical qubits [R][852]; in June 2026, breaking ground at a new site in Moreton Bay, it set cryoplant delivery for the second half of 2027, with commissioning and chip cabinets to follow, naming no operating date [R][853]. Quandela plans 100+ logical qubits in 2030–31 [R][854] and says hundreds of logical qubits will draw under 500 kW [C][854]. QuiX promised a universal machine in 2026 and error correction in 2027 [R][340]; Carina's core hardware, designed for a universal gate set, reached DLR in July 2026 [C][855].
Machines of this architecture (register: 6, of them 3 devices, 3 gate-capable). Quandela — Quandela Canopus (announced, 24), Belenos (deployed, 12), Lucy (deployed, 12); ETRI (with KAIST and the University of Trento) — ETRI 8-photon silicon-photonic qubit chip (demonstrated, 8); PsiQuantum — Omega chipset (Moreton Bay / Chicago systems unnamed) (demonstrated); QuiX Quantum — Carina (announced, 8).
Cells outside the architecture's slots (3). Belenos: L10 ∅G-twofab (Atlas gap — needs two L10 nodes: SiN/silica interferometer meshes (fab_pic) plus GaAs quantum-dot sour); Quandela Canopus: L10 ∅G-twofab (Atlas gap — quantum-dot source (III-V MBE) plus photonic-chip interferometer — two L10 nodes as for Be); Lucy: L10 ∅G-twofab (Atlas gap — needs two L10 nodes: SiN/silica interferometer meshes (fab_pic) plus GaAs quantum-dot sour).
8.3.11 Optical GKP — Continuous-variable photonic — GKP (ph_cv)
The idea. Squeezed light modes (squeezed), not single photons, carry the computation: beamsplitters entangle them deterministically into a time-multiplexed cluster state, CV Gaussian gates (g_cv) compute on it by homodyne measurement and feed-forward, and GKP grid encoding (enc_gkp) supplies both the qubit and the non-Gaussian resource that Gaussian operations lack. Xanadu's blueprint builds "three-dimensional hybrid resource states comprising both bosonic qubits and squeezed vacuum states" [S][267]. Against fusion it trades probabilistic entangling for deterministic, and heralded erasures for analogue noise: loss acts as a random displacement that spends squeezing. The bet: photonic chips will make GKP states near the ~10 dB of squeezing the code needs before loss consumes them [S][174].
What it needs. Gaussian gates require squeezed modes and room-temperature feed-forward; homodyne readout requires a local oscillator phase-locked by the same electronics, so detection, decision and modulation must close inside the 1 µs clock [D][173]. Optical GKP requires that squeezing; the best on-chip GKP source reaches 0.62 dB effective [D][174]. The code, bosonic concatenation with GKP under an outer qLDPC code, requires the GKP inner qubit, so it waits on that gap. Seven layers hold one technology each. The replaces edges fix the architecture's identity: Gaussian gates against fusion, homodyne against photon counting, Relay-BP against matching.
Where it stands. One machine, one device: Aurora (Xanadu, January 2025), 35 chips, 12 modes per 1 MHz cycle, a 12×N cluster state generated for two hours at ~14 dB total loss, no error-corrected computation [D][173]. It runs the only in-loop decoder in photonics, within the 1 µs clock [D][173], and 11 of its 12 cells are documented, the best-evidenced photonic machine. Table 8.3 still credits the architecture with no gate-capable device and no two-qubit error; the register flags Aurora detection-only and loss-dominated. Xanadu puts its loss 24× above threshold in 2026 [C][178] and plans 1× in 2030, a fault-tolerance milestone in 2028–29 and 1,000+ logical qubits by 2031 [R][178]; it holds a DARPA QBI Stage B slot [65], [66].
Exceptions and borrowings. An architecture of one machine cannot show whether it is drawn well; it is drawn around one design. Aurora fits every slot, with no gap and no none, but its alternates amend the edges. Number-resolving detection heralds its GKP states, so the architecture needs both detector technologies its replaces edge treats as rivals: counting to make the qubit, homodyne to compute. Its decoder is matching, with Relay-BP, the architecture's primary for the qLDPC outer code, as alternate. The gate alternate, fusion, has no machine. Jiuzhang 4.0 and Borealis, Aurora's predecessor, share the squeezed carrier and hold the Gaussian-gate technology as an off-architecture alternate without feed-forward: a Gaussian sampler is this architecture minus feed-forward and GKP states. Encoding and code are shared with the microwave cat-and-GKP architecture.
The next test. By March 2028 (§5.2): an on-chip optical GKP state above 1 dB effective squeezing, and a published loss factor within 10× of threshold; Xanadu's own schedule, 24× in 2026 to 1× in 2030, needs a gain of ~2.2× a year [S]. Both would keep the 2028–29 milestone credible. Demote if effective squeezing stays below 1 dB through 2027, or the milestone moves.
What the builders say. Xanadu chose GKP qubits because their logic runs by deterministic, room-temperature techniques and the states travel between chips over standard fibre [C][856]. It says Aurora could in principle grow to thousands of server racks and millions of qubits [C][857], and names optical loss as the next hurdle [C][856]. Its August 2026 roadmap cuts a 'key loss technical indicator', which it does not define, from 24.1× in 2026 to 1.0× in 2030 [R][178]; its chief executive expects fault tolerance in 2028–29 [R][178]; and it promises up to 200 logical qubits by 2029, 500 by 2030 and over 1,000 by 2031 [R][178].
Machines of this architecture (register: 1, of them 1 devices, 0 gate-capable). Xanadu — Aurora (demonstrated, 12).
Cells outside the architecture's slots: none — every cell of every machine sits in a slot of the architecture.
8.3.12 Boson sampling — Boson sampler (ph_sampler)
The idea. Squeezed light or single photons enter a Programmable linear-optical interferometer (g_lointer) and are counted at its outputs; the output probabilities are hafnians of matrices built from the network (permanents for single photons), #P-hard to compute [G][268]. No entangling gate, no feed-forward, no qubit: the only claim is that no classical computer reproduces the samples (goal G1). Where the fusion architecture builds qubits from small resource states and the continuous-variable architecture encodes them in GKP grids, this architecture skips the qubit. The bet: at high photon number the statistics outrun classical samplers before loss hands the output back to them.
What it needs. The interferometer requires light in the mesh and room-temperature electro-optic phase shifters; Bulk-optics and fibre assembly (fab_bulk) requires fibre-coupled modulators and delay loops. The carriers replace each other, as do photon counting and homodyne detection, and bulk assembly and the photonic IC foundry. Everything else is transmission: noisy Gaussian boson sampling becomes efficiently simulable once squeezing, transmission and detector efficiency fall below a bound [S][269]. Code, decoder and interconnect are ∅ by design (§7.3): a sample has no logical state to protect, so loss is modelled rather than corrected, and classical challengers exploit it [175].
Where it stands. Seven machines, seven devices, none gate-capable (Table 8.3). Jiuzhang 4.0 (USTC, May 2026): 1,024 squeezed states in 8,176 modes, up to 3,050 detected photons, 51% system efficiency, one sample per 25.6 µs [D][175]. Borealis (Xanadu, 2022): 216 squeezed modes through three fibre loops, TES number-resolving detectors, up to 219 photons, one sample per 36 µs [D][270]; the register flags its claim eroded. PT-2 (ORCA, deployed 2024–26) samples photon-subtracted squeezed states in a two-loop time-bin interferometer with a number-resolving detector [P][271]; ORCA publishes no mode count, clock or loss; its earlier PT-1 (two systems at PSNC Poznań, 2023) [C][877] and the retired Jiuzhang 1.0, 2.0 and 3.0 [D][460], [462], [878] are rows of their own. For the register the ∅ layers mean three things: no sampler enters the gate, code or decoder counts; their 21 none cells in layers 7–9 are the architecture, not a delay, and inflate Table 8.2's maturity profile; seven of photonics' eleven devices (Table 8.1) are samplers, so the family's device count overstates its processors.
Exceptions and borrowings. Jiuzhang 4.0 and Borealis hold CV Gaussian gates, the continuous-variable architecture's technology, as an off-slot layer-3 alternate: a Gaussian interferometer without homodyne feed-forward. That is lineage, not mislabelling; Borealis's successor is Aurora. Both leave layer 2 none. The encoding technology, Time-bin / path photonic encoding, rests on PT-2 alone and fits badly: PT-2 fills every time bin, nominally one photon each [P][271], so its bins are modes, not the two-bin qubit the technology defines; and the technology requires a single-photon carrier, while PT-2's is squeezed light. No machine uses the single-photon or homodyne alternates either: in layers 1, 2 and 6 the architecture is drawn wider than its register.
The next test. By 31 December 2027: no published classical sampler matches Jiuzhang 4.0 on its own benchmarks, and ORCA publishes PT-3's modes, loops and loss with a classical comparison. Demote if a classical algorithm matches Jiuzhang 4.0, as one matched each earlier advantage claim, or if PT-3, due in 2026 and undelivered (§2.5), ships without those figures.
What the builders say. USTC presents Jiuzhang 4.0 as more than a sampler: Gaussian boson sampling can also generate bosonic error-correcting codes [D][175], and control of thousands of photons, it says, reaches far beyond classical tractability and opens a path to fault-tolerant photonic hardware [D][175]. ORCA's case is time multiplexing: fibre delays let each photon source be reused many times [C][858]. In May 2025 its chief executive expected quantum advantage within 24 months, from PT-3, then due in early 2026 [R][859]; in June 2026 ORCA installed a PT-2 at a Japanese enterprise and scheduled its upgrade to PT-3 for later in the year [R][860].
Machines of this architecture (register: 7, of them 7 devices, 0 gate-capable). USTC (Pan Jianwei group) — Jiuzhang (1.0) (retired), Jiuzhang 2.0 (retired), Jiuzhang 3.0 (retired), Jiuzhang 4.0 (demonstrated); ORCA Computing — PT-1 (deployed), PT-2 (deployed); Xanadu — Borealis (deployed).
Cells outside the architecture's slots (2). Jiuzhang 4.0: L3 CV Gaussian gates + GKP-assisted non-Gaussian operations (g_cv, alternate borrowed from another architecture); Borealis: L3 CV Gaussian gates + GKP-assisted non-Gaussian operations (g_cv, alternate borrowed from another architecture).
8.3.13 CMOS spin qubits — Silicon / germanium quantum-dot spins (spin_qd)
The idea. A Gate-defined quantum-dot spin (qd_spin) is a transistor-sized gate stack: printed by a 300 mm CMOS foundry (fab_cmos), entangled by a pulse on the barrier to its neighbour, the Exchange gate (g_exch), read by Spin-to-charge conversion (ro_s2c), and coherent 1.31 ms (Hahn echo) on foundry ²⁸Si [D][197]. The bet: dots uniform enough to share calibration, with control moved into the cryostat, scale like transistors. The price: a readout-limited clock, 8.5 µs derived [S] against ~100–300 µs as run [G] (§7.4), and reach only to neighbours unless spins move.
What it needs. Exchange requires the dots and baseband pulses: its strength depends exponentially on barrier voltage, and HRL puts ~80% of its CNOT error on control and calibration [D][190], [191]. Carrier, cryo-CMOS, conveyor and the Cryogenic signal fan-out all require the foundry; the fan-out also requires cryo-CMOS behind it: Intel's Pando Tree serves up to 64 qubit terminals at 10–20 mK from one signal and nine digital lines of Horse Ridge II, 0.156 lines per terminal [C][272]. The surface code requires a 2D nearest-neighbour lattice, which no register device shows; qLDPC conflicts with it (long-range checks), needing the conveyor that replaces it. Crossbar lines conflict with per-pair calibration. Five layers hold one technology; none links modules.
Where it stands. Nine machines, six devices (Table 8.3): demonstrated, the HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots — Table 8.3's largest gate-capable device, level at 18 with Groove's, added to the register on 26 Sep 2026 [D][190], [191]), Tunnel Falls (Intel; 12 qubits [D][199]), the foundry 8-qubit array (Diraq/imec, exchange in one of four pairs [D][197]) and Groove Quantum's 18-qubit germanium spin processor (April 2026, no fidelities or paper [P][879]); deployed, RacQ (Equal1; sold as Bell-1 until May 2026, the name ESA still uses [C][237], [881]), installed at ESA's Frascati centre in July 2026 [C][881], and QM-One (Quantum Motion, count unpublished [200]); announced, the Diraq 8-qubit silicon spin quantum computer at Equinix Sydney and the Hitachi x Intel 18A spin programme; planned, Alloy Pioneer (Quobly), cloud access by end-2026 [R][201]. The best two-qubit error among devices, 3.0×10⁻³, is HRL's [D][190], [191]; Equal1's product page claims 99.3% (7.0×10⁻³) [C][273] where a press survey prints 98.4% [P][274]; no other machine publishes one. Off-register bests: 99.04–99.56% on foundry two-qubit devices [D][189]. HRL's bit-flip repetition code, error falling 4.7× from distance 3 to 5, sequenced from 4 K, is the architecture's only error-correction run [D][190], [191].
Exceptions and borrowings. No better-fitting architecture; two technology cells sit off the slots, HRL's error-detection code (code_detect) and RacQ's cryogenic decoder (dec_cryo), an alternate not yet run. Until 26 Sep 2026 the primaries described an absent machine — all eight rows used Single-spin (Loss–DiVincenzo) encoding, none Exchange-only encoding; HRL's device, now IBM's [204], is now the ninth row and the architecture's only carrier of its primary encoding, with its repetition code and parity decoder as Atlas gaps (∅G-repetition, ∅G-parity). The foundry 8-qubit array holds the only in-slot code cell, a roadmap qLDPC with shuttling as alternate (early stage), and carries 1.1×10⁻² from other devices at 1 K [D][194]. The on-die control of RacQ and QM-One is an Atlas gap (∅G-qsoc). Tunnel Falls mixes cryo-CMOS and room-temperature drive (hybrid); Equinix control is undisclosed. Only Tunnel Falls documents its fan-out; the cells of QM-One, RacQ and the Hitachi programme are inferred. Four drive single spins by ESR or EDSR, the Microwave / optical spin gates (g_mwspin) that layer 3 lists as the alternate; their gate cells name only the exchange gate. Borrowers: cryo-CMOS on five superconducting machines; the foundry on thirteen, eight ion traps.
The next test. By March 2028 (§5.2): a 300 mm array above 20 qubits with all-pairs two-qubit fidelity ≥ 99.5% and µs-class readout confirms; Diraq's 2029 target (150 k physical, 1 k logical [R][211], [212]) cut again demotes. If the Equinix system (due October 2026 [C][206]) and Alloy Pioneer reach 2028 without their own two-qubit error, the best number stays a vendor's.
What the builders say. Diraq argues from the foundry: its qubits are made like the chips in phones and laptops, a path to millions of qubits on one chip [C][861]. Quobly, making its chips on STMicroelectronics' 300 mm line, targets one million qubits by 2032, after cloud access to its first machine, Alloy Pioneer, by end-2026 [R][201]. Hitachi, with Intel and AIST, plans error-corrected prototypes of 100 qubits in fiscal 2028 and 1,000 in fiscal 2030 on Intel's 18A process [R][862]. HRL answers the wiring problem with a cryogenic CMOS controller that ran error correction on 18-qubit devices without room-temperature control [D][190], [191]. Equal1 fits a silicon-spin computer cooled to 0.3 K into one 19-inch rack [C][237]; Quantum Motion's QM-One takes three [C][200].
Machines of this architecture (register: 9, of them 6 devices, 6 gate-capable). Diraq — foundry 8-qubit array (demonstrated, 8); Diraq (with Equinix) — Diraq 8-qubit silicon spin quantum computer at Equinix Sydney (announced, 8); Equal1 — RacQ (Bell-1) (deployed, 6); Groove Quantum — Groove Quantum 18-qubit germanium spin processor (demonstrated, 18); HRL Laboratories (IBM since 26 Aug 2026) — HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots) (demonstrated, 18); Hitachi + Intel K.K. + AIST (G-QuAT) — Hitachi x Intel 18A spin programme (announced, 100); Intel — Tunnel Falls (demonstrated, 12); Quantum Motion — QM-One (deployed); Quobly — Alloy Pioneer (Quobly) (planned, 15).
Cells outside the architecture's slots (7). Diraq 8-qubit silicon spin quantum computer at Equinix Sydney: L5 undisclosed where the architecture expects a technology; RacQ (Bell-1): L5 ∅G-qsoc (Atlas gap — quantum system-on-chip: qubits, control electronics and error-correction logic on one CMOS); RacQ (Bell-1): L8 Cryogenic / on-chip decoder (cryo-CMOS, SFQ) (dec_cryo, alternate borrowed from another architecture); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L7 Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) (code_detect, primary off the architecture's slots); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L7 ∅G-repetition (Atlas gap — d=5 bit-flip repetition code on 7 exchange-only qubits, Λ5/3 = 4.7 over up to 200 rounds, ); HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots): L8 ∅G-parity (Atlas gap — repetition-code syndromes interpreted after the run with a parity-check (majority) decoder); QM-One: L5 ∅G-qsoc (Atlas gap — cryo-CMOS integrated on the qubit die).
8.3.14 Donor spins — Donor spins in silicon (spin_donor)
The idea. A Donor spin (P in ²⁸Si) (donor), written atom by atom by STM hydrogen-resist lithography (fab_stm): the ³¹P nucleus is the data qubit, the bound electron its drive, coupler and readout probe. The fact exploited: a nucleus has no orbital degree of freedom, hence no first-order coupling to the charge noise that holds foundry dots at 99.04–99.56% [D][189]; every gate still passes through the electron, which has one. The bet (Table 8.3): the longest coherence in a solid is worth a write process with no foundry.
What it needs. Nine of ten layers filled, one primary technology each, alternates in layers 3 and 5. The donor requires STM placement because exchange between donor electrons falls exponentially with separation, so a donor a few nanometres off leaves a dead register [G]. Exchange requires baseband gate pulses; readout requires a charge sensor beside the electron; the surface code requires a 2D lattice, which two registers of four and five nuclei [D][192] do not form. Two replaces edges, dot vs donor and foundry vs STM, separate it from the quantum-dot architecture; every other technology is shared. Layer 9 is empty: the dot architecture's fan-out requires a CMOS router die and cryo-CMOS control, both absent here, so a large array would be a hybrid with the dot architecture.
Where it stands. One machine, one device: the 11-qubit donor processor (Silicon Quantum Computing), demonstrated: nine ³¹P nuclear qubits in two registers with two electron ancillas; an electron CROT (controlled rotation) at 99.64% in 1.25 µs, 3.6×10⁻³, the family's best among devices (§8.4, H2); single-qubit gates to 99.99%; GHZ states over eight nuclei [D][192]. Nuclear Hahn echo reaches 660 ms [P][275]. No code runs; readout is non-demolition through the electron; control sits at room temperature. Six of ten cells documented. SQC holds a QBI Stage B slot [65], [66]; its roadmap dates no intermediate milestone. Flag: no foundry route.
Exceptions and borrowings. A single machine cannot test the architecture's drawing; SQC, fitting no other architecture better, amends layer 4. Inside a register the nuclei couple all-to-all through the shared electron, a star rather than a lattice; nearest neighbour holds only between registers (layer 4 too narrow). The nuclear gates are hyperfine-conditional rotations driven by ESR and NMR (nuclear magnetic resonance), not exchange, which serves only the electron CROT; baseband control excludes that resonant drive, which the architecture carries as alternates — Microwave / optical spin gates (g_mwspin) in layer 3, room-temperature electronics (ct_rt) in layer 5 — while SQC's cells record only exchange and baseband control. The fan-out cell records the missing slot, not a component (data gap: none). The manufacturing cell's SkyWater partnership is no foundry route: SkyWater's stated role is superconducting resonators and packaging [C][276] and it has been IonQ's since 31 July 2026 [C][19]. No other architecture uses donor or STM; single-spin encoding and baseband control recur on colour-centre machines and on Majorana 1 (and Majorana 2).
The next test. By March 2028 (§5.2 names no donor milestone): a donor device beyond eleven qubits, or a placement-yield distribution for SQC's automated patterning, hours to minutes per 70-dot device and hundreds of thousands of dots patterned [C][277], confirms the write step scales; eleven qubits and no yield figure then demote it to a physics testbed. QBI Stage C would be the first independent check.
What the builders say. Silicon Quantum Computing argues from purity and precision: its processors contain only silicon and phosphorus atoms, which it says cuts bit-flip errors [C][863], and it places phosphorus atoms with 0.13 nm precision and claims qubit quality rises as qubits are added [C][864]. Its 11-qubit processor, two multi-atom registers, reached Bell-state fidelities up to 99.5% on local and non-local nuclear-spin pairs [D][192]. In November 2025 SQC entered Stage B of DARPA's Quantum Benchmarking Initiative, committing to a detailed research roadmap to 2033 [C][865], the year its site gives for universal, fault-tolerant quantum computers [R][863].
Machines of this architecture (register: 1, of them 1 devices, 1 gate-capable). Silicon Quantum Computing — 11-qubit donor processor (demonstrated, 11).
Cells outside the architecture's slots: none — every cell of every machine sits in a slot of the architecture.
8.3.15 Spin–photon nodes — Colour-centre spins — network nodes (NV/SiV/T) (defect)
The idea. A point defect in diamond (NV, SiV, SnV) or silicon (T centre) (defect) has a spin-selective optical transition: its electron spin emits a photon entangled with it, and nearby nuclear spins under hyperfine-conditional microwave gates (g_mwspin) keep a small memory. Heralded photons (ic_spinphoton), not on-chip wiring, join these few-qubit nodes. Table 8.3's bet fuses two on one carrier: a room-temperature NV accelerator and cryogenic network nodes. Both forgo a dense lattice; for the nodes, link rate, not gate error, is the clock.
What it needs. The own technologies require the carrier — gates its spin register, fluorescence readout its optical transition, the link its spin–photon interface — and the carrier requires a host crystal, whose only technology is diamond (fab_diamond). Five technologies are borrowed: encoding, readout, baseband control, nearest-neighbour lattice, qLDPC code. Two clash: the code conflicts with the lattice, needing degree-6 checks that here only the optical link supplies. No decoder (§7.6): a code named, none decoded.
Where it stands. Five machines, five devices, no two-qubit error (Table 8.3). The largest, QC2026 Dual Core (SaxonQ, 10 qubits on two five-qubit NV cores), ran under operating conditions at Hannover Messe in April 2026 — a mobile room-temperature system with no published error rates [P][364]; SaxonQ's four-qubit SXQ4 units are delivered (DLR, Fraunhofer IWU) [C][880]. Quoll / QB-QDK 2.0 (Quantum Brilliance) is deployed: 6 qubits in the register, room-temperature units at Oak Ridge, no gate fidelity [C][278]. Entanglement First modules (Photonic Inc, QBI Stage B [65], [66]) teleported a state into a remote matter node over 30 km of commercial fibre (February 2026), no rate or fidelity [P][279]. Fujitsu's Diamond-spin quantum computer prototype carries SnV centres on photonic circuits at −271.6 °C, no qubit count or fidelity, multi-module by 2027 [C][R][210]. Per-node figures: NV gate errors below 0.1% [P], SiV entanglement over 35 km at ~1 Hz [D], a post-selected T-centre teleported CNOT [P] [208], [209].
Exceptions and borrowings. All three fit here best; none fits whole. Photonic connects any-to-any through the optical link (∅G-optlink), which its SHYPS qLDPC code needs, claimed at 20× fewer physical qubits per logical [C][280]; its silicon host has no technology (∅G-sicolour): layers 4 and 10 are drawn too narrowly. Quoll lacks link, code and decoder, and its microwave-and-laser control has no technology (∅G-nvroom): a processor on a network architecture, drawn too widely. Fujitsu's prototype adds a photonic-IC foundry (fab_pic), states no connectivity and shares the control gap at 1.55 K: an early hybrid. Only Photonic uses the namesake link; the architecture's spin gates (g_mwspin) recur as the layer-3 alternate of the quantum-dot and donor architectures.
The next test. By the technology briefs (§5.2 has no defect row), confirmation by March 2028 is an unconditional inter-node gate above 90%, a heralded link above 1 kHz, or link rate and fidelity from Fujitsu's multi-module prototype. Demotion: Photonic's links still without rate and fidelity, and the SnV modules without a qubit count, at end-2027; then the network bet is repeater and sensing technology; Quoll needs its own architecture.
What the builders say. Fujitsu, with TU Delft and QuTech, built a working diamond-spin prototype with tin-vacancy centres on photonic chips [C][210], chose the route for its optical links between modules and plans a multi-module prototype by 2027 [R][210]. Photonic argues that T-centre spin qubits in silicon, linked by light, give high connectivity, efficient error correction and a fit with telecom networks [C][866]; in 2024 it ran a teleported CNOT between qubits in different cryostats [C][867]. Quantum Brilliance bets on nitrogen-vacancy qubits at room temperature and pressure, which its CEO says decides where the machines can go and who can use them [C][868]; Fraunhofer IAF bought its rack-mounted QB-QDK2.0 [C][869].
Machines of this architecture (register: 5, of them 5 devices, 5 gate-capable). SaxonQ — QC2026 Dual Core (demonstrated, 10), SXQ4 (deployed, 4); Fujitsu (with TU Delft and QuTech) — Diamond-spin quantum computer prototype (demonstrated); Photonic Inc. — Entanglement First modules (demonstrated); Quantum Brilliance — Quoll / QB-QDK 2.0 (deployed, 6).
Cells outside the architecture's slots (7). Diamond-spin quantum computer prototype: L4 undisclosed where the architecture expects a technology; Diamond-spin quantum computer prototype: L5 ∅G-nvroom (Atlas gap — light, microwave and RF control of SnV spins; module operated at -271.6 °C (1.55 K)); Entanglement First modules: L4 ∅G-optlink (Atlas gap — any-to-any optical link used as the connectivity layer, not only as interconnect; basis fo); Entanglement First modules: L10 ∅G-sicolour (Atlas gap — Si-28 T-centre + silicon-photonics co-fabrication; no foundry node published; fab_diamond ); Quoll / QB-QDK 2.0: L5 ∅G-nvroom (Atlas gap — room-temperature microwave drive + green-laser initialisation + optical readout; no cryoge); QC2026 Dual Core: L5 ∅G-nvroom (Atlas gap — room-temperature optical initialisation and microwave control from a standard wall outlet,); SXQ4: L5 ∅G-nvroom (Atlas gap — optical initialisation and microwave gates at room temperature (18–27 °C), mobile, no cryo).
8.3.16 Majorana parity — Topological — tetron (Majorana) (topo)
The idea. Four Majorana zero modes on two gate-defined InAs–superconductor wires (majorana) hold one qubit at fixed total fermion parity (enc_parity, the tetron): Z and X are parities of different mode pairs. Gates would be parity-measurement sequences read by rf quantum capacitance (g_mbq, ro_qcap). The claim is a topological gap: with the modes far apart, their splitting falls exponentially with wire length and only an arriving quasiparticle flips a parity. Table 8.3's bet, protection in hardware instead of a code, is an existence claim, at the price of Clifford-only gates and no fallback.
What it needs. One chain, no alternates: the gate requires the wires and the readout, every gate being a measurement; the encoding two wires per tetron; the readout the island's quantum capacitance; the wires an InAs–Pb stack from III-V MBE (fab_mbe), whose disorder can mimic Majorana signatures. No replaces or conflicts edge: with no rival at any layer, one failure strands the architecture. Code, decoder and interconnect are empty (§7.6); a Floquet or measurement-based code awaits a demonstrated qubit. The gate is an empty slot: specified since 2008, never operated.
Where it stands. Two machines, no device: Majorana 1 and Majorana 2 (Microsoft), both contested, 5/30 in §2.7 [D]. Measured: single-wire parity readout at 1% assignment error, not by itself proof of Majorana zero modes (MZMs), the editors noted [D][13], [214]; tetron Z- and X-loop parity lifetimes of 12.4 ms and 14.5 µs, the X–Z succession test deferred [P][20]; a ~20 s InAs–Pb parity switching time in one wire of one tetron, called a qubit lifetime by Microsoft's blog [P][21][C][215]. No braiding, X measurement on Majorana 2, or two-qubit operation. A Nature Matters Arising disputes the topological reading, answered without concession [D][22], [23]; QuTech's independent Kitaev-chain parity qubit has limited protection [P][217].
Exceptions and borrowings. None off-slot: the machine fills all seven technologies and fits no other architecture — weak evidence: the architecture was drawn around it; one machine cannot test its width. The code gap (∅G-pathcode) is telling: Microsoft's own geometric codes need all-to-all connectivity, which its neutral-atom product offers (§3.3) and the intended tetron lattice does not. Of its own technologies only MBE travels: Belenos and Lucy (Quandela), on the fusion architecture, grow quantum-dot photon sources with it.
The next test. Per §5.2, an X-parity lifetime near the Z lifetime, or any two-qubit entanglement, confirms; neither by end-2027 demotes. Since 22 September 2026 DARPA's evaluators have on-site access to a Majorana 2 system in Microsoft's Maryland research centre — access, not a result [C][219]. Expectation: by March 2028 an X/Z lifetime ratio below 10² (now ~10³ [20]) or a joint parity measurement across two tetrons, confirmed by DARPA; without either, the tetron is a materials result, not an architecture.
What the builders say. Microsoft argues that topological qubits suit error correction through inherently low error rates, small size and digital control [C][215], and presented Majorana 1 as eight qubits on a chip designed to scale to a million [C][870]. With lead replacing aluminium in its tetrons (qubits made of two superconducting nanowires with MZMs at their ends), it reports in a preprint parity lifetimes near 20 seconds, some reaching a minute [P][21]. On that basis it halved its timeline and now aims at a scalable, practical quantum computer by 2029, without a qubit count [R][215]. In September 2026 it gave DARPA full on-site access to its Majorana 2 system for independent testing [C][219].
Machines of this architecture (register: 2, of them 0 devices, 0 gate-capable). Microsoft — Majorana 1 (other), Majorana 2 (other).
Cells outside the architecture's slots (1). Majorana 1: L7 ∅G-pathcode (Atlas gap — empty L7 on topo architecture; MS 4D geometric codes [[96,6,8]] need all-to-all, not a tet).
8.3.17 Flux-qubit annealer — Quantum annealer — flux qubits (anneal)
The idea. Thousands of rf-SQUID flux qubits (fluxq) serve as programmable Ising spins: a loop's persistent current, one way or the other, is the spin; inductive couplers set the interactions; the chip evolves continuously (g_anneal) from a transverse-field ground state toward that of the programmed problem. The problem is static: biases are held on chip, the answer latched as bits. Table 8.3's bet, special-purpose scale now, is a trade: count and connectivity for gates, logical qubits and any route to fault tolerance.
What it needs. The qubits, the long couplers' multilayer routing (cx_lr) and the SFQ flux DACs (ct_fluxdac) all require one superconducting process (fab_sc). Readout (ro_fluxro) requires the qubits and the DACs: a quantum flux parametron latches each qubit's current, on-chip shift registers carry the bit out. Static biases let DACs control "tens of thousands of qubits and couplers with just 200 bias wires" [C][281]. The empty layers mean: no encoding, so a qubit is a Hamiltonian term, not a memory; no readout during the anneal, so no syndrome for a code or decoder. Errors are never detected, only averaged over samples: more qubits buy larger problems, not better answers.
Where it stands. Four machines, three devices, 18 of 42 cells documented (Table 8.1), no gate. Advantage2 (D-Wave, May 2025; 4,400+ qubits, Zephyr 20-way, 12.5 kW [C][220]) supersedes Advantage (2020); Advantage3, a 20,000-qubit system for 2029 on the way to 100,000 qubits by 2031, is D-Wave's named next annealer [R][15]. D-Wave's "beyond-classical" spin-glass result (Science, March 2025) was substantially eroded within weeks by tensor-network and variational methods [D][221]–[223]; D-Wave maintains its largest instances remain unmatched [P][224]. Qilimanjaro's AQPU, a 10-qubit analogue fluxonium annealer, was inaugurated at the Barcelona Supercomputing Center on 28 May 2026 with no published benchmark [C][872]. §2.8 scores only E 4 and F 2; H1-2026 revenue fell 67% [C][15]–[17]; a CHIPS agreement (up to $100 M, 8 September 2026) funds work toward a 100,000-qubit annealer and a gate-model system [C][R][91].
Exceptions and borrowings. No cell falls off the slots; all fit here best. Both Advantage machines list dispersive readout (ro_disp), which the map says replaces the flux latch, as an alternate: perimeter resonators read the shift-register bits after the latch, so the two sit in series: a hybrid, not rivals. Qilimanjaro's coupler and DAC cells are inferred, its readout undisclosed: a data gap. Borrowings run outward: the D-Wave gate-model dual-rail system takes the flux DACs as an alternate, and IBM Quantum Loon and its successors use the long couplers for qLDPC checks.
The next test. §5.2 has no annealing row; D-Wave's roadmap serves. Its 20,000-qubit system for 2029 and 100,000 qubits by 2031 [R][15]–[17] rest on "superconducting interconnect technologies" for "multi-chip fabrics" [C][15]–[17], the layer the architecture leaves empty. Confirmation by March 2028: a multi-chip anneal with couplers across chip boundaries, or a beyond-classical claim surviving a year of classical challenge. Demotion: neither by then, and Advantage3 moved or dropped.
What the builders say. D-Wave's Advantage2 has more than 4,400 qubits, each coupled to 20 others so that larger problems can be embedded [C][220]. D-Wave says an Advantage2 prototype simulated magnetic materials in minutes where a classical supercomputer would need nearly a million years, a result published in Science [D][871]. It plans a multi-chip Advantage3: 20,000 qubits in 2029 and 100,000 by 2031 [R][15], wired through a new input-output design needing at most 20% more lines than today's 4,500-qubit machine [C][15]. Qilimanjaro builds analogue processors from fluxonium qubits, which it calls error-resilient by design and usable before fault tolerance; the first, 10 qubits, runs at the Barcelona Supercomputing Center, with two more generations due in 2026 and 2027 [C][872].
Machines of this architecture (register: 4, of them 3 devices, 0 gate-capable). D-Wave Quantum — Advantage3 (planned, 20,000), Advantage (deployed, 5,000), Advantage2 (deployed, 4,500); Qilimanjaro Quantum Tech — Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC (deployed, 10).
Cells outside the architecture's slots (7). Advantage: L7 ∅G-qac (Atlas gap — quantum annealing correction (penalty-repetition encoding) on up to 1,322 logical qubits o); Advantage2: L7 ∅G-qac (Atlas gap — penalty-spin and stacked quantum annealing correction on Advantage2_system1.10 (sweep 7 Oc); Advantage3: L4 undisclosed where the architecture expects a technology; Advantage3: L9 Multi-chip modules / l-couplers (same cryostat) (ic_mcm, primary off the architecture's slots); Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L4 undisclosed where the architecture expects a technology; Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L5 undisclosed where the architecture expects a technology; Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L6 undisclosed where the architecture expects a technology.
8.4 Trends — six hypotheses tested on the register
Each hypothesis is a falsifiable statement about the population; the test is the computation named with it, run by the build on the register's current rows, under a rule printed with the test; the verdict is supported, partly supported or not supported, with the sample size. What each verdict rests on, and what would overturn it, is in §8.7. A hypothesis's wording and rule freeze when the edition is stamped as released; a changed claim takes a new number, and an old one is retired, never reworded — so that the verdict history at the end of this section, one row per edition with the register's size beside it, shows how a verdict drifts as the register grows.
H7 and H8 — the share of announcements by cohort and the technologies shared between families — are retired: §8.1 describes both as facts of the population, and their past verdicts stay in the verdict history at the end of this section.
H1 — Physical qubit count has moved to the atoms; superconducting quantum computers no longer compete on count.
Test. Median physical qubits per family over all devices and over gate-capable devices (102 of 131; analogue simulators, arrays without an entangling gate and single-qubit testbeds excluded); the largest benchmarked device per family (39 devices carry a published gate figure), by usable qubits; cohort medians for the two largest families.
table
| Family | Devices: median qubits (n) | Gate-capable: median qubits (n) | Largest benchmarked device (usable qubits) | Largest device of any kind |
|---|---|---|---|---|
| neutral atoms | 256 (11) | 140 (7) | Phoenix (Gen-1) and Gen-2 — 1,180 | 6,100-qubit tweezer array — 6,100 |
| superconducting circuits | 53 (71) | 60 (60) | IBM Quantum Osprey — 413 | IBM Quantum Condor — 1,121 |
| trapped ions | 30 (19) | 30 (17) | Helios — 98 | 2-D site-resolved ion simulator — 512 |
| photonics | 12 (4) | 12 (3) | — | Lucy — 12 |
| semiconductor spins | 11.5 (6) | 11.5 (6) | HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots) — 18 | HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots) — 18 |
Result. The atoms lead by ×4.8 on all devices and ×2.3 on gate-capable ones. Cohort medians (gate-capable; n in brackets) — superconducting circuits: 2021 40 (6), 2022 52.5 (4), 2023 75 (6), 2024 105 (13), 2025 36 (19), 2026 49 (12); neutral atoms: 2023 1,180 (1), 2024 140 (1), 2025 180 (4), 2026 20 (1). Verdict: supported. The atoms' lead in count is real among processors and much larger among trap arrays: the thousands-of-qubits machines are arrays that do not yet run an entangling gate, while the largest benchmarked tweezer processor and the largest transmon lattice are within a factor of a few of each other. The cohort medians move with who enters the register in a given year (small first chips from new entrants) more than with the leaders, and are too thin per cohort to carry a trend on their own.
H2 — Two-qubit error is converging across the three large families at the median, while the best single number stays with the ions.
Test. Median and best err_2q_median over devices per family, excluding hero-pair numbers, targets and component demonstrations. Result. superconducting circuits median 4.4×10⁻³, best 1.0×10⁻³ (Origin Wukong-180 (4th gen)) (claimed), n = 21; trapped ions median 2.5×10⁻³, best 7.9×10⁻⁴ (Helios), n = 6; neutral atoms median 8.0×10⁻³, best 5.0×10⁻³ (448-atom fault-tolerant processor), n = 3; semiconductor spins median 5.0×10⁻³, best 3.0×10⁻³ (HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots)), n = 2. The spread of the three large medians is ×3.2. Verdict: not supported. A convergence of medians with a persistent gap at the best is what one expects when the median is set by the many second-tier machines and the best by a few labs that have run the same platform for a decade. The verdict describes one snapshot of the register; whether the medians keep converging is a question for the next edition's cohorts, not for this one.
Comparability classes. Read in its own class — protocol, scope, statistic, conditioning (the register's class table) — a two-qubit figure compares only with figures of the same class. Devices with a class-consistent figure (a named protocol, measured simultaneously, in a layer or in a code cycle, unconditioned; in brackets: with isolated-pair figures admitted): superconducting circuits 8 (13); trapped ions 1 (4); neutral atoms 1 (1); photonics 0 (0); semiconductor spins 0 (1); defect spins 0 (0); topological 0 (0); quantum annealers 0 (0). 13 of the register's figures are surrogates — vendor dashboards, statements, Bell-state fidelities, post-selected or single-pair values — that no class admits. Only superconducting circuits reach five such devices, so the comparison this hypothesis makes is not testable at a class-consistent resolution; the verdict above rests on the register's mixed figures, as the frozen rule prescribes, and the class-restricted claim is the next edition's hypothesis.
H3 — Control stays external: integrated control is a minority confined to spins, annealers and a few traps; no superconducting device of 100 qubits or more generates its microwave drive inside the cryostat — 4 K cryo-CMOS flux bias has run in hybrid with room-temperature rf on 156 qubits (Heron r2, Mar 2026).
Test. The register's control_placement classified as room-temperature electronics, optics, integrated (on-chip microwave, cryo-CMOS, SFQ, flux DACs, 4 K) or undisclosed; the integrated class by family; superconducting devices ≥ 100 qubits with cryogenic control that is not a demo. Result. External 82 of the 110 machines of the cryogenic families (superconducting, spin, topological, annealing); integrated 20 (superconducting circuits 4, trapped ions 7, semiconductor spins 6, quantum annealers 3), of which cryogenic 13; superconducting devices ≥ 100 qubits with non-demo cryogenic control: 0. Verdict: supported. The attribute the map treats as the slow-moving one (§7.2: control placement) moves slowly in the register too: the integrated class is where the physics forces it — flux DACs on annealers, CMOS next to CMOS spins, microwave electrodes in surface traps — and a plan elsewhere.
H4 — Running a code on the hardware is becoming the entry ticket: the share of new machines that have done so rises by cohort, and closed-loop decoding follows.
Test. Machines with at least one code in the register's code table, by cohort 2023–2026; machines whose decoding is in the loop. Rule. Supported if the cohort share rises monotonically and ten or more machines decode in the loop; partly if the last cohort's share is above the first's, or five or more machines decode in the loop. Result. 68 of 184 machines list a code — 53 of them devices that have run it, 11 announced or planned machines whose roadmap names one, 4 component demonstrations or rows of status other (superconducting circuits 42, trapped ions 12, neutral atoms 6, photonics 2, semiconductor spins 2, defect spins 1, topological 1, quantum annealers 2); share by cohort 2023 29 % (5/17), 2024 27 % (7/26), 2025 40 % (21/52), 2026 30 % (16/53); decoding in the loop (the decoder's result acts inside the run): 4 (Aurora, Rigetti Ankaa-2, System Model H1 (H1-1), System Model H2 (H2-1, H2-2)); real-time throughput without feedback, not counted as a closed loop: 1 (Willow). Verdict: partly supported. The share rises but not monotonically, and the loop is closed on a handful of machines: the entry ticket is a code demonstration, not yet a decoder in the cycle.
H5 — Modularity is a roadmap, not a machine: a link between modules is the rarest thing in the register.
Test. Primary interconnect cells (Table 8.2): machines with no interconnect at all (none), with packaging or fan-out inside one module but no link, with an undisclosed link, with a link the map has no technology for, and with a link technology between modules. Result. No interconnect 139 of 184 (76 %); in-module packaging or fan-out only, 16; undisclosed, 10; an Atlas gap, 1; a link technology between modules on 18 machines (superconducting circuits 11, trapped ions 3, photonics 2, defect spins 1, quantum annealers 1) — 166 of 184 (90 %) have no link between modules. The layer with the most none cells is Interconnect (139). Verdict: supported. This is a snapshot of the register, not a trend: every roadmap that reaches thousands of qubits assumes a link between modules; the register holds one on 18 machines, 6 of them devices, 10 announced or planned, 2 component demonstrations or rows of status other. The layer where the architecture must go is the layer where it has least been.
H6 — Where a roadmap falls short of a target algorithm, its logical-error deficit exceeds its qubit deficit.
Test. The register's roadmap-feasibility table (16 roadmaps × the target algorithms): the verdicts, and for every SHORT verdict the size of its qubit deficit and of its error deficit (each a factor; a deficit given as a range counts by its geometric mean). Rule. Supported if in seven SHORT rows out of ten the error deficit is the larger one or the only one; partly at five out of ten. Result. FEASIBLE 23, NOT EVALUABLE 40, SHORT 65; of the 65 SHORT verdicts 49 quantify both deficits and in 48 of them the error deficit is the larger, 5 carry an error deficit only, 11 a qubit deficit only and 0 neither; median qubit deficit ×7, median error deficit ×1,000. Verdict: supported. Qubit counts are the roadmaps' own currency and they budget it generously, so the qubit deficit is a small factor; the logical error per operation and the gate count of the target algorithm are where the same roadmaps miss by one to eight orders of magnitude.
Verdict history — one row per edition
A row is written by the builds of its edition and frozen when the edition is stamped as released; a verdict that flips between editions is re-run on the old and the new rows apart, and the row's note names the cause — new machines, re-graded cells or a re-cut map. The row current register holds the verdicts on today's rows until the next edition takes its own row.
8.5 Forecasts — what the register predicts, and how the next edition will score them
A hypothesis says what the register shows; a forecast predicts what the next register will show. Each forecast below names its indicator, its value today, the value expected one year on (September 2027) and two years on (September 2028), the basis — the historical series, the register's own announcements, or both — and a confidence; the wording is frozen when this edition is stamped as released (data/forecast-ledger.json, kept under its edition), and the edition that reaches each date scores it against that frozen text; a new forecast takes a new number. Two limits govern the confidence: the series are short (five to eight yearly points) and dated by press releases, so the forecasts are directional with ranges rather than point estimates; and announcements are discounted — the register's rows marked as never or not (yet) delivered (IBM Quantum Condor, IBM Quantum Flamingo (l-coupler proof of concept), IBM Quantum Kookaburra, IQM Halocene) are the reminder that an announced machine is a forecast, not a device.
Table 8.5 — the forecast ledger (scored one and two years on)
| # | Indicator | Today (2026.09) | Expected at 2027.09 | Expected at 2028.09 | Basis | Confidence | Falsified if |
|---|---|---|---|---|---|---|---|
| F1a | largest benchmarked superconducting device (usable physical qubits) | 413 (flat since 2022) | ≤ 1,121 (no benchmarked device above 413 delivered; the 2026.09 edition's baseline was 1,121 — Condor, since filed as a scale demonstrator, and the 433-qubit Osprey counts its 413 usable qubits) | ≤ 1,500; the first multi-module lattice (Kookaburra-class) is the only route above it | frontier series 2019 53, 2021 127, 2022 413, 2023 413, 2024 413, 2025 413, 2026 413; announced above the frontier: Fujitsu >10,000 physical / ~250 logical (STAR) — 10,000 (2025); QuantWare Bass-A10K (VIO-40K) — 10,000 (2025); Fujitsu 1,000-qubit machine — 1,000 (2026); OQC TITAN — 2,000 (2028) | high | a superconducting device with a benchmarked entangling gate on more than 1,121 usable qubits in the 2027.09 register |
| F1b | largest benchmarked neutral-atom device (usable qubits) | 1,180 (flat since 2023) | 1,180–1,300: one announced candidate above the frontier within the year (see basis); even odds it lands | 1,300–3,000: the 10,000-qubit plans sit at 2028 and are discounted to a third of their count on the register's delivery record | frontier series 2023 1,180, 2025 1,180; announced above the frontier: Magne — 1,225 (2026); Libra — 10,000 (2028) | medium | a gate-capable tweezer processor above 3,000 qubits by 2028.09, or none above 1,180 by then |
| F1c | largest benchmarked trapped-ion device (usable qubits) | 98 (2025) | 180–260: the historical ×1.37/yr gives ≈185 by 2027; the first announced system above it caps the range at 260 | 200–400 | frontier series 2020 20, 2022 30, 2023 56, 2024 56, 2025 98 — the family whose frontier last grew (2023, 2025); announced: Superion 256 — 256 (2026); NFQC-1k — 1,000 (2026); IonQ Superion 10K — 10,000 (2026) | medium | a trapped-ion device with entangling gates on more than 260 qubits by 2027.09, or the frontier still at 98 |
| F2 | best two-qubit error per family (devices; hero pairs excluded) and the family median | superconducting circuits 1.0×10⁻³ / median 4.4×10⁻³; trapped ions 7.9×10⁻⁴ / median 2.5×10⁻³; neutral atoms 5.0×10⁻³ / median 8.0×10⁻³ | superconducting circuits ≈ 7.7×10⁻⁴; trapped ions ≈ 7.2×10⁻⁴; medians ≈ 2–3×10⁻³ for the three large families | superconducting circuits ≈ 6.0×10⁻⁴; trapped ions ≈ 6.9×10⁻⁴; the first family median below 2×10⁻³ | frontier series superconducting circuits: 2019 6.0×10⁻³, 2021 5.2×10⁻³, 2022 5.2×10⁻³, 2023 2.5×10⁻³, 2024 1.5×10⁻³, 2025 1.5×10⁻³, 2026 1.0×10⁻³ (×1.29/yr); trapped ions: 2020 1.0×10⁻³, 2022 1.0×10⁻³, 2023 1.0×10⁻³, 2024 1.0×10⁻³, 2025 7.9×10⁻⁴ (×1.05/yr); the median trails the frontier by superconducting circuits 3 yr, trapped ions 6 yr, neutral atoms 1 yr (the year the frontier first reached today's median) | medium | a family frontier that fails to improve for two editions, or a median that improves faster than the frontier did three years earlier |
| F3 | machines that list a code (run, or named in the roadmap); decoders in the loop | 68 / 4 | ≥ 55 machines with a code (cumulative series by cohort year 2022 13, 2023 18, 2024 25, 2025 46, 2026 62; 6 planned machines dated after 2026 lie outside it); 6–8 in the loop | ≥ 65 with a code; 8–12 in the loop (11 machines list real-time decoding as planned or intended: Apollo, IBM Quantum Blue Jay, IBM Quantum Cockatoo, IBM Quantum Kookaburra, IBM Quantum Starling, IQM Halocene, Libra, Magne, Sol, Superion 256, neutral-ytterbium QPU; half on time is the working assumption) | cumulative count of code-running machines by cohort (×3.4 from 2023 to 2026) and the register's planned-decoding rows | medium | fewer than 52 machines with a code, or fewer than 6 closed loops, in 2027.09 |
| F4 | devices with a demonstrated link technology (interconnect layer) | 6 (superconducting circuits 3, trapped ions 1, photonics 1, defect spins 1) | 9–12: of the 10 announced machines that name a link (Fujitsu >10,000 physical / ~250 logical (STAR) (2025), QuantWare Bass-A10K (VIO-40K) (2025), D-Wave gate-model dual-rail system (2026), IBM Quantum Kookaburra (2026), Superion 256 (2026), IBM Quantum Cockatoo (2027), Advantage3 (2029), Apollo (2029), IBM Quantum Starling (2029), IBM Quantum Blue Jay (2033)), the ones dated 2025–2026 are the candidates | 12–18; the interconnect gap share falls below 85 % only if the multi-module superconducting lattices arrive | the register's announced-link rows discounted by the delivery record; the historical series is too short to extrapolate | low | fewer than 9 devices with a link in 2027.09, or more than 12 |
| F5 | machines with integrated control; superconducting devices ≥ 100 qubits driven cryogenically | 20 / 0 | ≤ 25 / 0: the candidates are demos and claims (IBM Quantum Heron r2, OQC GENESIS, OQC Toshiko, QuantWare Bass-A10K (VIO-40K), foundry 8-qubit array); IBM's cryo-CMOS is scheduled with Starling (2029) | ≤ 30 / 0–1 | H3's mechanism: integration happens where physics forces it (spins, annealers, surface traps) and is a plan elsewhere; the register's control-placement field lists the plans | high | a ≥ 100-qubit superconducting device with production cryogenic control before 2028.09 |
| F6 | roadmap checkpoints the register can score by 2028 | 4 roadmaps dated 2025–2028: Nord Quantique — nordquantique-2029 (2028-2029), OQC — oqc-titan (2028), PsiQuantum — psiquantum-2033 (2028-2033), QuEra — quera-phase3 (2026-2028) | the checkpoints dated 2026–2027 are scored; on H6's distribution (53 of 65 SHORT verdicts on error or gates) the expectation is that they miss on the error budget, not on qubits | the 2028 checkpoints are scored; at least two of three miss on the logical error per operation | the register's roadmap-feasibility verdicts and their dates | medium | a dated checkpoint met on qubits, error and gate budget together |
Reading the ledger. The reliable part is the shape, not the digits: the count frontier of the two largest families has not moved for years while the announced frontier lies an order of magnitude above it (F1); the error frontier improves by ×1.05 (trapped ions) to ×1.29 (superconducting circuits) a year where the series has more than two points, and the medians reach the frontier's value with a lag of years (superconducting circuits 3, trapped ions 6, neutral atoms 1) (F2); and the adoption curves — codes on hardware, links, integrated control — are set by the delivery of the machines the register already lists as planned, discounted by how often such rows have slipped (F3–F5). What the ledger cannot do is time a single machine; what it can do is be wrong in public, one edition later.
8.6 Where the architecture is going
Of the six hypotheses, 4 are supported, 1 partly and 1 not. From count to encoded qubits and links. The three layers most often empty on a machine — code, decoder and interconnect, with no technology or an undisclosed one on 64 %, 80 % and 81 % of the machines — are the layers every fault-tolerant roadmap must fill (H4, H5, H6): the next generation of quantum computers will be judged by the logical error per cycle and by the link between modules, not by the count (H1). A division of roles between families rather than a winner. The largest devices are tweezer arrays, the best gate is an ion trap and the fastest clock a transmon lattice; the medians no longer converge once each figure is read in its own comparability class (H2) while the extremes stay apart; hardware is shared only between kindred families while codes and decoders cross all of them (§8.1) — and the roadmaps assume many modules joined by links rather than one module grown large (H5). The slow variable is control. Integrated control is a necessity where the physics forces it and a plan elsewhere (H3); the map's placement attribute will move last. The binding constraint is the error budget. Roadmaps are short on qubits too (a median ×7) but far more on error (×1,000) (H6), so the machines that matter next are the ones that move the logical error per operation, whatever their qubit count.
8.7 Verification and limits
Table 8.7 — what each verdict rests on
| Hypothesis | Verdict | Sample | Filters applied | Evidence grade of the inputs | What would overturn it |
|---|---|---|---|---|---|
| H1 | supported | 102 gate-capable devices | status ∈ {deployed, demonstrated, retired}; no target/component/analogue/no-gate flag | register field physical_qubits_num (press-level for most machines) |
a gate-capable median of another family above the atoms’, or a larger gate-capable device outside the atoms |
| H2 | not supported | superconducting circuits 21, trapped ions 6, neutral atoms 3, semiconductor spins 2 | devices; hero-pair, target and component numbers excluded | register field err_2q_median (paper-level where a figure is cited, else press) |
a family median more than ×2 from the others, or a non-ion best |
| H3 | supported | 184 | none (all rows); the ≥ 100-qubit clause on devices | control layer cells: 45 % ✅ (82/184) | integrated control on more than 30 % of machines, or a ≥ 100-qubit superconducting device driven cryogenically |
| H4 | partly supported | 148 machines in cohorts 2023–2026 | cohort = year of the status date | code layer cells: 39 % ✅ (71/184) | a falling share across three cohorts, or ten machines with a decoder in the loop |
| H5 | supported | 184 | primary cells only; none, undisclosed, gap and in-module packaging counted as “no link” | interconnect layer cells: 25 % ✅ (46/184) | links between modules on a quarter of the machines |
| H6 | supported | 128 roadmap × algorithm rows | verdict = SHORT | register table roadmap-feasibility (targets as published by the vendors) |
the error deficit larger than the qubit deficit in fewer than half of the SHORT rows |
Limits. The cohort is the year of the register's status date, which mixes first light, general availability and the latest milestone; the classifiers are string rules over free-text fields, printed at the top of the chapter's generator in the Atlas's repository (build/machines_chapter.py) so that a reviewer can object to a rule rather than to a number; the population is the register's, which favours machines with an English-language document. 22 machines have no verified cell at all (press pages only) and enter the counts at press level: 70-qubit ion quantum computer (FIAN / Rosatom roadmap), 72-qubit neutral-atom (Rb) quantum computer prototype (50 qubits in Dec 2024), Alloy Pioneer (Quobly), Fujitsu 1,000-qubit machine, Groove Quantum 18-qubit germanium spin processor, Haituo (Quafu platform), Hanyuan-1, Hanyuan-2, Hitachi x Intel 18A spin programme, IBM Quantum System One, Ehningen, IBM Quantum System Two at Amaravati Quantum Valley Tech Park, IBM Quantum System Two, Donostia-San Sebastian, Infleqtion Illinois neutral-atom quantum computer (IQMP, Chicago), KRISS 50-qubit-class superconducting system, KRISS domestic superconducting QPU, Lucy, Qinghe-1 (Qinghe No. 1, 清河一号), Quantum Spain quantum computer at BSC, Quantum X Labs neutral-atom platform (50+ qubits, claimed), RIKEN RQC-Fujitsu 64-qubit superconducting quantum computer, Rigetti Ankaa-3, Tianyan-504 / "Xiaohong" chip. Every hypothesis is re-tested by each build; a verdict that flips between editions is itself a finding and will be reported in the changelog.
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BRTechnology briefs
Every technology on the map has a brief, and the depth of each one follows the technology's centrality in the graph — how many platform families and architectures depend on it and how recently it reached hardware — so a node a dozen architectures run through gets about 2,000 words and a single-platform node about 800. Centrality is a statement about the graph, not a verdict on the technology; it is shown in each brief's header and in the index below.
Every brief carries the same section skeleton — identity and lineage, physics and limits, engineering state of the art, manufacturing and supply chain, role in the stack, actors and economics, outlook and open questions, sources, and open verification items — so any two briefs can be read against each other. The Actors & economics section is verified against dated primary sources. Evidence tags mark the standing of every claim: D measured or peer-reviewed, C company claim, R roadmap or target, S simulation or estimate, G established or general fact (where the chip is a link it opens the dated primary source), P preprint or trade press.
Numbers are the Atlas’s: a work has the same number here, in §9 and in every other brief; online sources were accessed in September 2026.
| layer | id | technology | centrality | one line |
|---|---|---|---|---|
| 1 Qubit carrier | ion | Trapped atomic ion | 10.9 | Single Yb⁺/Ba⁺/Ca⁺ ions in rf traps, entangled through shared motional modes; the highest-fidelity and slowest qubit in commercial service. |
| 1 Qubit carrier | transmon | Transmon | 10.9 | Capacitively shunted Josephson junction (Koch 2007); the carrier behind Willow, Heron/Nighthawk and Zuchongzhi, with the fastest deterministic gate and QEC cycle of any demonstrated qubit. |
| 1 Qubit carrier | majorana | Majorana parity (InAs–Pb tetron) | 10.7 | Fermion parity stored non-locally in a gate-defined semiconductor–superconductor wire pair; only single-wire parity readout has been measured. |
| 1 Qubit carrier | alkali | Alkali atom (Rb/Cs) in optical tweezers | 10.6 | Hyperfine ground-state qubit in a single rubidium or caesium atom held by a far-detuned optical tweezer, moved on demand. |
| 1 Qubit carrier | ae_atom | Alkaline-earth(-like) atom (Yb/Sr) — erasure-native | 9.9 | Ytterbium/strontium tweezer qubits whose metastable clock manifold makes decay and loss optically detectable, converting physical errors into heralded erasures rather than silent Pauli errors. |
| 1 Qubit carrier | photon | Single photon (discrete variable) | 9.9 | A qubit carried by one optical quantum in path, time-bin or polarisation modes; entangling is probabilistic and the dominant error is loss. |
| 1 Qubit carrier | qd_spin | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) | 9.9 | Electron or hole spin in a lithographically gated dot; exchange gives deterministic ns-scale two-qubit gates on a CMOS die. |
| 1 Qubit carrier | cavity | Bosonic cavity mode | 7.7 | A harmonic microwave mode of a 3D or planar superconducting resonator used as the qubit carrier; its error is structured photon loss, not generic Pauli noise. |
| 1 Qubit carrier | fluxonium | Fluxonium | 6.7 | Josephson-junction-array-shunted superconducting qubit at 0.2–1 GHz with large anharmonicity and long T1, bought at the price of a flux-bias line per qubit. |
| 1 Qubit carrier | fluxq | rf-SQUID flux qubit (annealer) | 6.7 | Superconducting double-well loop used as a programmable Ising spin in D-Wave's annealers; no gate set, no code. |
| 1 Qubit carrier | squeezed | Squeezed light mode (CV) | 6.7 | A continuous-variable optical mode with one quadrature below vacuum noise; the carrier for GKP and cluster-state photonics, where integration loss, not nonlinearity, sets the ceiling. |
| 1 Qubit carrier | defect | Colour-centre / defect spin (NV, SiV, SnV, T centre) | 4.2 | An optically addressable point-defect spin in diamond or silicon whose electron couples coherently to a photon, making it a network node with a small nuclear register rather than a processor qubit. |
| 1 Qubit carrier | donor | Donor spin (P in ²⁸Si) | 4.2 | Phosphorus donors placed by STM lithography in enriched silicon-28, the bound electron giving drive and readout, the ³¹P nucleus the long-lived qubit. |
| 2 Encoding | enc_dualrail | Dual-rail (erasure) encoding | 16.9 | One excitation shared between two modes; loss leaves the code space and is heralded as a located erasure, not an unknown Pauli. |
| 2 Encoding | enc_omg | Metastable ('omg') erasure encoding | 15.4 | Qubit lives in a metastable manifold so its dominant decay leaves the subspace detectably, converting Pauli errors into located erasures. |
| 2 Encoding | enc_gkp | GKP grid encoding | 12.9 | A qubit encoded in periodic grid states of one bosonic mode — microwave cavity or optical — correcting small quadrature shifts and handing the decoder an analogue syndrome. |
| 2 Encoding | enc_cat | Cat-code encoding (biased noise) | 7.4 | A two-photon-dissipation-stabilised coherent-state qubit whose bit-flips fall exponentially with photon number while phase-flips rise linearly with it. |
| 2 Encoding | enc_hf | Hyperfine / clock-state qubit | 7.2 | Two ground-state hyperfine or nuclear-spin sublevels at a field-insensitive clock point, the default qubit for every trapped-ion and neutral-atom vendor. |
| 2 Encoding | enc_spin_ld | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding | 5.5 | One qubit per spin-1/2 — a confined electron, hole or nucleus — with no encoded subspace, giving the smallest footprint and no leakage channel. |
| 2 Encoding | enc_opt | Optical narrow-line qubit (ion S–D, atom clock) | 4.4 | A qubit split between a ground level and a metastable level one optical photon above it — the S₁/₂–D₅/₂ quadrupole line of ⁴⁰Ca⁺ or ⁸⁸Sr⁺, or the ¹S₀–³P₀ clock line of neutral Sr/Yb — with one narrow-line laser driving every gate. |
| 2 Encoding | enc_bare | Bare physical qubit (no encoding) | 4.2 | The {|0⟩,|1⟩} subspace of a weakly anharmonic Josephson oscillator used directly as the qubit, with no bosonic, erasure or bias structure on top. |
| 2 Encoding | enc_eo | Exchange-only / singlet–triplet spin encoding | 4.2 | One logical qubit in the total-spin subspace of three exchange-coupled spins (exchange-only) or two spins plus a field gradient (singlet–triplet), driven entirely by baseband voltage pulses, with leakage as the price of removing microwave control. |
| 2 Encoding | enc_gr | Ground–Rydberg analogue qubit | 4.2 | A two-level qubit formed by an atomic ground state |g⟩ and a Rydberg state |r⟩, driven globally under an Ising-type Hamiltonian: the computational basis of analogue Rydberg simulators, not an error-suppressing code. |
| 2 Encoding | enc_parity | Fermion-parity encoding (tetron) | 4.2 | One logical qubit in the fermion parity of four Majorana zero modes on two wires; Z and X are parities of different mode pairs, both non-local. |
| 2 Encoding | enc_timebin | Time-bin / path photonic encoding | 1 | Photonic dual-rail qubit in arrival-time bins or waveguide path; loss is the dominant error, and it is heralded — an erasure at a known location — rather than a silent error. |
| 3 Gate mechanism | g_ryd | Rydberg-blockade CZ | 13.9 | Global laser pulses drive neighbouring tweezer-trapped atoms to a Rydberg state whose interaction blocks double excitation, giving a deterministic 270 ns CZ. |
| 3 Gate mechanism | g_elec | Electronic microwave gate (ions, laser-free: near-field or static gradient) | 12.9 | Currents in a microfabricated trap chip entangle ions through microwave field gradients, with no laser and no ground-state cooling. |
| 3 Gate mechanism | g_tc | Tunable-coupler CZ / iSWAP | 10.6 | A flux-tuned coupler switches the exchange and ZZ interaction between transmons on and off, giving deterministic 25–70 ns CZ or iSWAP gates. |
| 3 Gate mechanism | g_exch | Exchange gate (spins; incl. shuttled-spin CZ) | 9.1 | Voltage-pulsed Heisenberg exchange between neighbouring or shuttled spins in gate-defined dots or donors — the only entangling mechanism that needs nothing but CMOS gate electrodes. |
| 3 Gate mechanism | g_ms | Mølmer–Sørensen / light-shift laser gate | 9.1 | Bichromatic-laser spin-dependent force that entangles trapped ions through a geometric phase on a shared motional mode, which the gate leaves as it found it. |
| 3 Gate mechanism | g_bos | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) | 8.4 | Driven SQUID/SNAIL couplers and transmon ancillas mediate beamsplitter and entangling gates between superconducting bosonic cavity modes, for cat, GKP and dual-rail encodings. |
| 3 Gate mechanism | g_catcnot | Bias-preserving cat–cat CNOT | 8.2 | A direct entangling gate between two dissipative cat qubits that keeps the exponential bit-flip suppression intact through the interaction — theory only. |
| 3 Gate mechanism | src_resource | Multi-photon resource-state generator (RSG; 6-ring etc.) | 8.2 | The source-plus-fusion subsystem that must mass-produce encoded multi-photon graph states at code rate to feed fusion-based fault tolerance; nothing runs near that rate. |
| 3 Gate mechanism | g_fusion | Linear-optical fusion (heralded) | 7.7 | Probabilistic Bell-basis measurement on two photons — 50% unboosted, 75% with ancillae — whose failure is heralded and erases one of the two measured outcomes; the entangling primitive of fusion-based photonics. |
| 3 Gate mechanism | g_mbq | Measurement-based Majorana gate | 5.7 | Clifford gates generated by sequences of joint fermion-parity measurements instead of physical braiding; specified since 2008, never operated. |
| 3 Gate mechanism | g_rydanalog | Analogue Rydberg Hamiltonian evolution | 4.6 | Global laser fields drive a programmable Rydberg Ising Hamiltonian on a whole tweezer array at once: the waveforms Ω(t), Δ(t), a fixed local-detuning pattern and the atom geometry are the program, and there is no discrete gate. |
| 3 Gate mechanism | g_lointer | Programmable linear-optical interferometer (no entangling primitive) | 4.4 | A programmable passive unitary on N optical modes — a beamsplitter/phase-shifter mesh or time-bin fibre loops — that scatters squeezed light or single photons into detectors for sampling, with no entangling gate and no feed-forward. |
| 3 Gate mechanism | g_anneal | Quantum annealing (analogue evolution) | 4.2 | Continuous-time Hamiltonian evolution (coherent quench, 3.6–27 ns) driving Ising or Rydberg spins toward a ground state; not a discrete gate. |
| 3 Gate mechanism | g_cr | Cross-resonance (fixed-frequency, all-microwave) | 4.2 | All-microwave entangling gate driving one fixed-frequency transmon at its neighbour's frequency through a static bus; no flux line, no tunable coupler. |
| 3 Gate mechanism | g_cv | CV Gaussian gates + GKP-assisted non-Gaussian operations | 4.2 | Beamsplitters, squeezers and homodyne feed-forward on optical modes, with GKP grid states supplying the non-Gaussian resource fault tolerance requires. |
| 3 Gate mechanism | g_mwspin | Microwave / optical spin gates (defect centres, 1Q spins) | 1.7 | Resonant microwave rotation of a defect electron spin, hyperfine-conditional rotation of its neighbouring nuclei, and optical pulses for initialisation and readout. |
| 4 Connectivity / transport | cx_lr | Long-range on-chip couplers (c-couplers, mm-scale) | 18.4 | Waveguide- or resonator-extended tunable couplers that entangle fixed superconducting qubits millimetres apart, buying the degree-6 graphs that qLDPC codes need. |
| 4 Connectivity / transport | cx_shuttle | Spin shuttling (conveyor mode) | 14.4 | Coherent transport of a spin qubit along a gate-defined conveyor, buying distance and layout sparsity with a dephasing budget rather than with wiring. |
| 4 Connectivity / transport | cx_nn | Static nearest-neighbour lattice | 13.4 | A coupling graph fixed at mask level in which each qubit interacts only with lithographic neighbours; the default topology under every fielded superconducting and spin processor. |
| 4 Connectivity / transport | cx_qccd | Ion shuttling (QCCD, junctions, grid traps) | 11.6 | Moving trapped ions between zones through junctions or grid traps so a small gate-able crystal inherits all-to-all connectivity. |
| 4 Connectivity / transport | cx_aod | Atom transport by AOD tweezers (zoned architecture) | 10.9 | Crossed acousto-optic deflectors move tweezers to shuttle atoms between storage, entangling and readout zones at ~99.95% per move. |
| 4 Connectivity / transport | cx_switch | Photonic switching / routing (electro-optic, feed-forward) | 8.4 | Electro-optic and MEMS switches route photons between waveguides on a real-time heralding decision, the loss-dominated transport layer every photonic architecture shares. |
| 4 Connectivity / transport | cx_reload | Continuous atom reloading (reservoir + optical conveyor belt) | 7.9 | A continuously fed atom reservoir (optical-lattice conveyor belts from a distant MOT, a cavity-enhanced lattice or a molasses-stopped beam) from which tweezers extract fresh atoms into the array while the stored qubits keep their coherence. |
| 4 Connectivity / transport | cx_crossbar | Crossbar shared-line control (spins) | 5.7 | Row- and column-shared plunger and barrier lines address a two-dimensional dot array with line count scaling as the square root of dot count, trading addressing granularity for wireability. |
| 4 Connectivity / transport | cx_bus | Ion-chain motional bus (all-to-all in chain) | 4.2 | A shared collective motional mode entangles any pair in one trap, giving genuine all-to-all connectivity at the price of gate time growing with chain length. |
| 5 Control | ct_cryocmos | Cryo-CMOS controller (4 K / mK) | 17.6 | Commercial CMOS ASICs inside the cryostat that synthesise qubit control waveforms and bias next to the qubits, replacing room-temperature racks and their coaxial lines. |
| 5 Control | ct_sfq | SFQ digital control (4 K / mK) | 14.4 | Quantised flux pulses from a niobium digital chip flip-chipped onto the qubit die drive gates at millikelvin, replacing per-qubit microwave coax. |
| 5 Control | ct_ionmw | Chip-integrated microwave control (ions) | 12.9 | Ion gate drive synthesised as electrical signals and delivered by conductors inside the trap chip instead of by laser beams. |
| 5 Control | ct_pic_trap | PIC-generated tweezers / integrated optics for atoms | 11.2 | Generating, routing and collecting the light that traps, addresses and images single atoms from a photonic integrated circuit instead of free-space optics. |
| 5 Control | ct_base | Baseband electrical control (spins, Majorana) | 10.2 | DC-to-few-GHz voltage pulses on lithographic gate electrodes drive exchange, tunnelling and parity in spin and Majorana devices, with no resonant drive. |
| 5 Control | ct_fluxdac | On-chip flux-DAC multiplexing | 9.7 | SFQ on-chip flux digital-to-analogue converters that hold each qubit's or coupler's DC bias at the mK stage, replacing one room-temperature wire per bias with a multiplexed on-chip network. |
| 5 Control | ct_ionlaser | Laser control with integrated photonics (ions) | 9.7 | On-chip waveguides route cooling, gate and readout light to trapped ions, replacing free-space beams with lithographically fixed optical paths. |
| 5 Control | ct_rt | Room-temperature electronics + per-qubit coax/flex | 9.4 | One coherent line per drive, flux and readout port runs from room-temperature racks through attenuated coax or flex cable into the mixing chamber. |
| 5 Control | ct_laser | Laser + AOD/SLM optical control (atoms) | 8.4 | Free-space lasers, holographic modulators and acousto-optic deflectors generate, move, image and drive the optical-tweezer arrays that hold neutral-atom qubits. |
| 5 Control | ct_vio | Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring | 6.4 | Control and readout lines from room-temperature electronics reach each superconducting qubit through the face of the chip — coaxial pins, contact probes, superconducting vias or a stacked signal die — instead of being routed in the chip plane to its edge. |
| 5 Control | ct_ionaod | Free-space laser addressing of ions (AOM/AOD beams) | 6.2 | Gate light from a room-temperature optical bench is switched and steered onto individual ions of one chain by multi-channel acousto-optic modulators or acousto-optic deflectors and focused through bulk optics above the trap. |
| 5 Control | ct_eo | Electro-optic drive + feed-forward electronics (room temperature) | 5.2 | Room-temperature modulators driven from detector outcomes inside one optical clock cycle — the feed-forward layer every photonic architecture needs. |
| 6 Readout | ro_erasure | Mid-circuit erasure check | 20.6 | Ancilla- or fluorescence-based test of whether a qubit is still in its code space, flagging decay/leakage as a located erasure without reading the logical state. |
| 6 Readout | ro_spd | Single-photon detection (SNSPD / TES) | 13.2 | Cryogenic superconducting detectors that destroy a photon to register it; the shared readout organ of every photonic and photon-linked platform. |
| 6 Readout | ro_disp | Dispersive microwave readout (+TWPA, Purcell) | 10.4 | The qubit state is read as a dispersive shift of a coupled resonator, Purcell-filtered on chip and amplified near the quantum limit before the HEMT. |
| 6 Readout | ro_fluor | Fluorescence state detection (ions, defects) | 9.4 | State-dependent resonance fluorescence, counted on a PMT, EMCCD, SNSPD or trap-integrated photodiode, is the default non-destructive mid-circuit readout for trapped ions. |
| 6 Readout | ro_img | Fluorescence imaging of atom arrays | 8.4 | Camera-based fluorescence detection of neutral atoms — non-destructive, mid-circuit, millisecond by default, microsecond in single-group demos. |
| 6 Readout | ro_s2c | Spin-to-charge conversion + rf reflectometry | 8.4 | Spin converted into a charge-motion event by Pauli spin blockade or energy-selective tunnelling, then read by an rf-matched charge sensor in microseconds without destroying the qubit. |
| 6 Readout | ro_qcap | rf quantum-capacitance parity readout | 5.7 | Dispersive gate sensing of a Majorana island's quantum capacitance by rf reflectometry, reading fermion parity without charge transfer; non-destructive and mid-circuit. |
| 6 Readout | ro_reset | Fast unconditional / dissipative qubit reset | 5.6 | Returning a superconducting qubit to |0⟩ in ~100–500 ns by handing its excitation to a lossy mode, usually the readout resonator, instead of waiting for T1 or measuring and flipping. |
| 6 Readout | ro_homodyne | Homodyne quadrature detection (CV) | 4.5 | A signal mode interfered with a strong local oscillator on a balanced photodiode pair, whose difference current samples one chosen field quadrature — the computational measurement of continuous-variable and GKP machines. |
| 6 Readout | ro_fluxro | Flux readout via QFP / SQUID shift registers (annealers) | 3 | At the end of an anneal each flux qubit's persistent-current state is latched by a quantum flux parametron and carried as a classical bit to a detector — a dc SQUID, or on Advantage a frequency-multiplexed microresonator at the chip perimeter; no qubit is coupled to a readout resonator. |
| 7 Code | code_erasure | Erasure-adapted codes | 18.4 | Surface and block codes decoded with located-error flags; thresholds 4–10% and Λ ≈ 27 in simulation, 1.7–1.9× gains in hardware. |
| 7 Code | code_surface | Rotated surface code (+ yoked variants) | 16.6 | Weight-4 CSS stabiliser code on a square lattice; the only code with below-threshold hardware data on three platforms, and the most expensive. |
| 7 Code | code_qldpc | Non-local qLDPC codes (bivariate bicycle, 'gross') | 16.1 | Sparse high-rate stabiliser codes on a degree-6 torus that cut physical-per-logical overhead roughly tenfold against the surface code. |
| 7 Code | code_highrate | High-rate concatenated codes with transversal gates | 14.9 | Many logical qubits per block (iceberg, tesseract, concatenated [[4,2,2]]), Clifford gates transversal, paid for with all-to-all connectivity and post-selection. |
| 7 Code | code_magic | Magic-state factory (cultivation / distillation / code switching) | 14.9 | The subsystem that manufactures non-Clifford resource states so a code with transversal Cliffords can run universal circuits. |
| 7 Code | code_bosonic | Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) | 12.9 | A discrete outer code — repetition or qLDPC — wrapped around a bosonic inner qubit whose noise is already shaped, so the outer code corrects only one residual channel. |
| 7 Code | code_color | Colour code (transversal Cliffords) | 12.4 | Triangular 2D stabiliser code whose whole Clifford group acts transversally, skipping lattice surgery, at roughly 1.9× the surface code's teraquop footprint (physical qubits per logical qubit for 10¹² reliable operations). |
| 7 Code | code_aft | Algorithmic FT / transversal architectures | 11.4 | Replacing O(d) syndrome-extraction rounds per logical gate with a constant number, via transversal block-to-block gates plus correlated decoding. |
| 7 Code | code_detect | Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) | 8 | Codes that flag any single fault and discard the run instead of correcting it: [[4,2,2]], the distance-2 surface code, the [[k+2,k,2]] iceberg code and spacetime checks on Clifford circuits. |
| 7 Code | code_fusion | Fusion-based fault tolerance | 6.7 | A fault-tolerant code assembled from destructive linear-optical fusions on pre-made photonic resource states, tolerating 2.7–17.4% photon loss in theory and never run end-to-end. |
| 7 Code | code_mitig | Error mitigation in the code slot (ZNE, PEC) — not a code | 5 | Classical post-processing of many noisy runs — zero-noise extrapolation, probabilistic error cancellation or amplification, readout twirling, tensor-network noise inversion — that removes bias from expectation values without encoding, detecting or correcting a single error. |
| 8 Decoder | dec_nn | Neural decoders (AlphaQubit 2, CNN, transformers) | 13.9 | Learned syndrome decoders — recurrent transformers, CNNs, LSTMs, state-space models — that beat matching by absorbing non-Pauli device noise from data. |
| 8 Decoder | dec_mwpm | MWPM / Sparse Blossom (+ correlated matching) | 12.7 | Graph-matching decoder turning the syndrome history — detection events across rounds — into the likeliest error chain; the accuracy reference and the shipped real-time decoder for surface codes. |
| 8 Decoder | dec_gpu | GPU decoding via NVQLink | 11.7 | RoCE link putting a GPU inside the QEC feedback loop at 3.84 µs mean round trip, so decoding runs as CUDA software on GH200-class hardware instead of a fixed FPGA bitstream. |
| 8 Decoder | dec_relaybp | Relay-BP for qLDPC (FPGA) | 11.7 | Belief propagation with disordered, partly negative memory strengths, chained in relay legs, decoding bivariate bicycle qLDPC syndromes at 24 ns per iteration on an FPGA. |
| 8 Decoder | dec_cryo | Cryogenic / on-chip decoder (cryo-CMOS, SFQ) | 10.4 | Syndrome decoding or predecoding executed inside the cryostat — SFQ logic at millikelvin, CMOS at 4 K — instead of at room temperature. |
| 8 Decoder | dec_corr | Correlated / loss-aware decoding (transversal, atom loss) | 7.7 | Decoders that consume atom-loss heralds as located erasures and decode across transversal gate layers instead of round-by-round. |
| 8 Decoder | dec_fpga | FPGA real-time decoders (LCD, Deltaflow) | 7.4 | Room-temperature FPGAs running clustering or matching decoders fast enough to clear surface-code syndromes inside the QEC cycle, ahead of GPU and cryogenic alternatives. |
| 8 Decoder | dec_rl | In-loop RL calibration / control steering | 6.7 | Detection events from the running code double as the reward signal for a reinforcement-learning agent that retunes control parameters during QEC, replacing scheduled recalibration. |
| 9 Interconnect | ic_transducer | Microwave–optical transducer (useful efficiency) | 14.4 | A quantum-coherent microwave-to-telecom converter good enough to entangle superconducting processors in separate refrigerators; nothing in 2026 comes close. |
| 9 Interconnect | ic_mcm | Multi-chip modules / l-couplers (same cryostat) | 13.9 | Splitting a superconducting processor across several dies inside one cryostat, joined by bump-bonded chiplet links or metre-scale superconducting l-couplers. |
| 9 Interconnect | ic_cryolink | Cryogenic microwave link between refrigerators | 11.9 | Superconducting waveguide held below 50 mK along its whole length, carrying itinerant 5–7 GHz photons or squeezed states between two independently cooled dilution refrigerators. |
| 9 Interconnect | ic_ionphoton | Ion–photon link | 10.9 | Heralded ion–photon entanglement over fibre links separate ion traps into one machine; best published rate 250 s⁻¹ against a ~10⁴ s⁻¹ need. |
| 9 Interconnect | ic_spinphoton | Spin–photon solid-state link (SiV, NV, T centre) | 10.4 | Heralded photonic entanglement between separated solid-state spin registers — diamond NV and SiV centres, silicon T centres — through deployed telecom fibre. |
| 9 Interconnect | ic_atomcavity | Atom–photon cavity interface | 9.2 | An optical cavity around tweezer-trapped neutral atoms Purcell-enhances atom–photon coupling so an atom's state can be written onto a flying photon. |
| 9 Interconnect | ic_fanout | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) | 6.6 | A millikelvin router die, an on-die multiplexer or 3D stacked wiring that turns a few cold input lines into the tens to thousands of gate voltages a spin-qubit array needs. |
| 9 Interconnect | ic_multidie | Multi-die packaging in one module (flip-chip, bump-bonded control die) | 5.8 | A qubit die bump-bonded face to face with a second superconducting die that carries wiring, resonators, a second material or control logic, inside one package, across a vacuum gap of a few to ~20 µm. |
| 9 Interconnect | ic_fibre | Fibre links between photonic modules | 5.2 | Telecom fibre carrying heralded entanglement between photonic chips and racks — priced per connector, not per metre, and with no published rate. |
| 10 Manufacturing | fab_cmos | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) | 17.9 | Industrial 300 mm CMOS lines fabricating quantum-dot spin qubits, cryo-CMOS controllers and superconducting wiring; the only qubit manufacturing route with wafer-scale yield statistics. |
| 10 Manufacturing | fab_pic | Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) | 13.2 | A CMOS foundry flow putting low-loss nitride waveguides, electro-optic switches, single-photon detectors and fibre attach on one 300 mm wafer. |
| 10 Manufacturing | fab_sc | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) | 11.1 | 300 mm junction lithography and post-fabrication frequency trimming (laser annealing, ABAA) set the frequency spread every superconducting architecture inherits. |
| 10 Manufacturing | fab_trap | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) | 10.9 | Planar rf/DC electrode chips that confine and shuttle ions, built on MEMS lines or, increasingly, on merchant semiconductor foundry wafers. |
| 10 Manufacturing | fab_optics | Optical / mechanical assembly (lasers, vacuum, objectives) | 8.7 | The laser, ultra-high-vacuum and imaging-optics stack that traps, cools, addresses and reads out both trapped-ion and neutral-atom qubits — infrastructure, not a qubit. |
| 10 Manufacturing | fab_3d | 3D machined superconducting cavities | 5.2 | CNC-machined aluminium or niobium resonator bodies with internal Q above 0.5×10⁹; the cm-scale body per mode is the structural cost of cavity-based bosonic codes. |
| 10 Manufacturing | fab_bulk | Bulk-optics and fibre assembly (photonic samplers) | 4.2 | Photonic processors assembled from discrete parts — free-space squeezers and interferometers, fibre delay loops, fibre-coupled modulators and cryogenic single-photon detectors — aligned and locked by hand and servo rather than patterned on a wafer. |
| 10 Manufacturing | fab_mbe | III-V MBE heterostructures (InAs–Pb wires, QD sources) | 4.2 | Molecular beam epitaxy of III-V nanostructures with vacuum-unbroken superconductor shells for Majorana wires, and of quantum dots for single-photon sources. |
| 10 Manufacturing | fab_diamond | Diamond growth / implantation (NV, SiV, SnV) | 1.7 | Plasma CVD growth of single-crystal diamond, ion implantation and annealing to form NV, SiV or SnV centres, and undercut etching to build the nanophotonics around them. |
| 10 Manufacturing | fab_stm | STM hydrogen-resist lithography (donors) | 1.7 | A scanning-tunnelling tip desorbs hydrogen from passivated Si(100) to open single sites, phosphine dopes them, and epitaxial silicon buries the donors — atom-precise, serial, and without a foundry equivalent. |
БРОбзоры по технологиям
У каждой технологии на карте есть обзор, а его глубина следует центральности технологии в графе — сколько семейств платформ и архитектур от неё зависят и насколько недавно она дошла до железа, — так что узел, через который идёт дюжина архитектур, получает около 2 000 слов, а узел одной платформы — около 800. Центральность — утверждение о графе, а не вердикт о технологии; она показана в шапке каждого обзора и в индексе ниже.
Все обзоры построены по одному скелету разделов — сущность и происхождение, физика и пределы, достигнутый инженерный уровень, производство и цепочка поставок, роль в стеке, участники и экономика, перспективы и открытые вопросы, источники, открытые пункты верификации, — поэтому любые два обзора читаются друг против друга. Раздел «Участники и экономика» верифицирован по датированным первичным источникам. Теги свидетельств показывают статус каждого утверждения: D измерено или рецензировано, C заявление компании, R дорожная карта или цель, S симуляция или оценка, G установленный или общий факт (чип-ссылка открывает датированный первоисточник), P препринт или отраслевая пресса.
Номера общие для всего Атласа: у работы один и тот же номер здесь, в §9 и в любом другом обзоре; онлайн-источники просмотрены в сентябре 2026 г.
| слой | id | технология | центральность | одной строкой |
|---|---|---|---|---|
| 1 Носитель кубита | ion | Ион в ловушке | 10.9 | Одиночные ионы Yb⁺/Ba⁺/Ca⁺ в ВЧ-ловушках, запутываемые через общие колебательные моды; самый точный и самый медленный кубит в коммерческой эксплуатации. |
| 1 Носитель кубита | transmon | Трансмон | 10.9 | Джозефсоновский переход, шунтированный ёмкостью (Koch, 2007); носитель, стоящий за Willow, Heron/Nighthawk и Zuchongzhi, с самым быстрым детерминированным вентилем и самым быстрым циклом QEC среди всех продемонстрированных кубитов. |
| 1 Носитель кубита | majorana | Майорановская чётность (тетрон InAs–Pb) | 10.7 | Фермионная чётность, хранимая нелокально в паре полупроводник-сверхпроводниковых проводов, задаваемых затворами; измерено только считывание чётности одиночного провода. |
| 1 Носитель кубита | alkali | Щелочной атом (Rb/Cs) в пинцете | 10.6 | Кубит на сверхтонких состояниях основного уровня одиночного атома рубидия или цезия, удерживаемого далёким от резонанса оптическим пинцетом и перемещаемого по требованию. |
| 1 Носитель кубита | ae_atom | Щёлочноземельный (и подобный ему) атом (Yb/Sr) — естественные стирания | 9.9 | Кубиты в оптических пинцетах на иттербии/стронции, у которых метастабильный часовой мультиплет делает распад и потерю атома оптически детектируемыми, превращая физические ошибки в стирания (erasure) с оповещением (heralded), а не в «немые» ошибки Паули. |
| 1 Носитель кубита | photon | Одиночный фотон (дискретные переменные) | 9.9 | Кубит, переносимый одним оптическим квантом в путевых, временны́х (time-bin) или поляризационных модах; запутывание вероятностно, а доминирующая ошибка — потеря. |
| 1 Носитель кубита | qd_spin | Спин в квантовой точке, формируемой затворами (Si/SiGe, SiMOS, Ge) | 9.9 | Спин электрона или дырки в литографически затворённой точке; обменное взаимодействие даёт детерминированные двухкубитные вентили наносекундного масштаба на КМОП-кристалле. |
| 1 Носитель кубита | cavity | Бозонная мода резонатора | 7.7 | Гармоническая микроволновая мода 3D- или планарного сверхпроводникового резонатора, используемая как носитель кубита; её ошибка — структурированная потеря фотонов, а не универсальный шум Паули. |
| 1 Носитель кубита | fluxonium | Флаксониум | 6.7 | Сверхпроводниковый кубит, зашунтированный массивом джозефсоновских переходов, с частотой 0.2–1 GHz, большой ангармоничностью и длинным T1, купленными ценой отдельной линии потокового смещения на каждый кубит. |
| 1 Носитель кубита | fluxq | Потоковый кубит на ВЧ-СКВИДе (отжигатель) | 6.7 | Сверхпроводящая петля с двухъямным потенциалом, используемая как программируемый изинговский спин в отжигателях D-Wave; ни набора вентилей, ни кода. |
| 1 Носитель кубита | squeezed | Сжатая мода света (непрерывные переменные) | 6.7 | Оптическая мода в непрерывных переменных, у которой одна квадратура лежит ниже уровня вакуумного шума; носитель для GKP и кластерной фотоники, где потолок задают потери интеграции, а не нелинейность. |
| 1 Носитель кубита | defect | Центр окраски / спин дефекта (NV, SiV, SnV, T-центр) | 4.2 | Оптически адресуемый спин точечного дефекта в алмазе или кремнии, электрон которого когерентно связывается с фотоном, что делает его сетевым узлом с небольшим ядерным регистром, а не кубитом процессора. |
| 1 Носитель кубита | donor | Донорный спин (P в ²⁸Si) | 4.2 | Атомы фосфора, размещённые СТМ-литографией в обогащённом кремнии-28: связанный электрон даёт возбуждение и считывание, ядро ³¹P — долгоживущий кубит. |
| 2 Кодирование | enc_dualrail | Двухрельсовое кодирование (со стираниями) | 16.9 | Одно возбуждение, поделённое между двумя модами; потеря выводит систему из кодового пространства и сопровождается оповещением (heralded) как локализованное стирание (erasure), а не как неизвестная ошибка Паули. |
| 2 Кодирование | enc_omg | Метастабильное («omg») кодирование со стираниями | 15.4 | Кубит живёт в метастабильном мультиплете, поэтому его доминирующий распад детектируемо выводит систему из подпространства, превращая паулиевские ошибки в локализованные стирания (erasure). |
| 2 Кодирование | enc_gkp | GKP-кодирование (решётка) | 12.9 | Кубит, закодированный в периодических сеточных состояниях одной бозонной моды — микроволнового резонатора или оптической, — исправляющий малые сдвиги квадратур и передающий декодеру аналоговый синдром. |
| 2 Кодирование | enc_cat | Кошачье кодирование (смещённый шум) | 7.4 | Кубит на когерентных состояниях, стабилизированный двухфотонной диссипацией: перевороты бита (bit-flip) падают экспоненциально с числом фотонов, тогда как перевороты фазы (phase-flip) растут с ним линейно. |
| 2 Кодирование | enc_hf | Сверхтонкий кубит / кубит на часовом переходе | 7.2 | Два сверхтонких или ядерно-спиновых подуровня основного состояния в нечувствительной к полю часовой точке — кубит по умолчанию у всякого вендора ионных ловушек и нейтральных атомов. |
| 2 Кодирование | enc_spin_ld | Кодирование на одиночном спине (Лосса–ДиВинченцо) / ядерном спине | 5.5 | Один кубит на спин-1/2 — локализованный электрон, дырка или ядро — без кодированного подпространства, что даёт минимальную занимаемую площадь и отсутствие канала утечки (leakage). |
| 2 Кодирование | enc_opt | Оптический кубит на узком переходе (S–D иона, часовой переход атома) | 4.4 | Кубит, разделённый между основным уровнем и метастабильным уровнем на один оптический фотон выше — квадрупольная линия S₁/₂–D₅/₂ у ⁴⁰Ca⁺ или ⁸⁸Sr⁺ либо часовая линия ¹S₀–³P₀ у нейтральных Sr/Yb, — причём все вентили возбуждает один узкополосный лазер. |
| 2 Кодирование | enc_bare | «Голый» физический кубит (без кодирования) | 4.2 | Подпространство {|0⟩,|1⟩} слабо ангармонического джозефсоновского осциллятора, используемое непосредственно как кубит, без надстройки в виде бозонной структуры, стирания (erasure) или асимметрии ошибок. |
| 2 Кодирование | enc_eo | Чисто обменное / синглет-триплетное спиновое кодирование | 4.2 | Один логический кубит в подпространстве полного спина трёх обменно-связанных спинов (чисто обменное кодирование) или двух спинов в градиенте поля (синглет-триплетное кодирование), управляемый исключительно импульсами напряжения в основной полосе частот (baseband), где утечка (leakage) — цена отказа от микроволнового управления. |
| 2 Кодирование | enc_gr | Аналоговый кубит основное–ридберговское состояние | 4.2 | Двухуровневый кубит, образованный основным состоянием атома |g⟩ и ридберговским состоянием |r⟩ и возбуждаемый глобально под гамильтонианом изингового типа: вычислительный базис аналоговых ридберговских симуляторов, а не код, подавляющий ошибки. |
| 2 Кодирование | enc_parity | Кодирование в фермионной чётности (тетрон) | 4.2 | Один логический кубит в фермионной чётности четырёх майорановских мод на двух проводах; Z и X — чётности разных пар мод, обе нелокальные. |
| 2 Кодирование | enc_timebin | Time-bin / путевое фотонное кодирование | 1 | Фотонный двухрельсовый кубит во временных интервалах прихода или в волноводном пути; доминирующей ошибкой служат потери, и они сопровождаются оповещением (heralded) — это стирание (erasure) в известном месте, — а не скрытая ошибка. |
| 3 Механизм вентиля | g_ryd | CZ через ридберговскую блокаду | 13.9 | Глобальные лазерные импульсы переводят соседние атомы в оптических пинцетах в ридберговское состояние, взаимодействие которого блокирует двойное возбуждение, давая детерминированный CZ за 270 ns. |
| 3 Механизм вентиля | g_elec | Электронный СВЧ-вентиль (ионы, без лазера: ближнее поле или статический градиент) | 12.9 | Токи в микроизготовленном чипе ловушки запутывают ионы через градиенты СВЧ-поля, без лазера и без охлаждения в основное состояние. |
| 3 Механизм вентиля | g_tc | CZ / iSWAP через перестраиваемый элемент связи | 10.6 | Перестраиваемый потоком элемент связи включает и выключает обменное и ZZ-взаимодействие между трансмонами, давая детерминированные вентили CZ или iSWAP длительностью 25–70 ns. |
| 3 Механизм вентиля | g_exch | Обменный вентиль (спины; вкл. CZ на переносимых спинах) | 9.1 | Гейзенберговский обмен, включаемый импульсом напряжения между соседними или перенесёнными спинами в квантовых точках, формируемых затворами, либо на донорах, — единственный механизм запутывания, которому не нужно ничего, кроме электродов затворов КМОП. |
| 3 Механизм вентиля | g_ms | Вентиль Мёльмера–Соренсена / на световом сдвиге (лазерный) | 9.1 | Спин-зависимая сила бихроматического лазера, запутывающая ионы в ловушках через геометрическую фазу на общей колебательной моде, которую вентиль оставляет в том состоянии, в каком её застал. |
| 3 Механизм вентиля | g_bos | Бозонные вентили через анциллу (CX кошачьих кубитов, CZ двухрельсовых, светоделитель) | 8.4 | Накачиваемые элементы связи СКВИД/SNAIL и трансмонные анциллы опосредуют светоделительные и запутывающие вентили между бозонными модами сверхпроводниковых резонаторов — для кошачьего кода, GKP и двухрельсового кодирования. |
| 3 Механизм вентиля | g_catcnot | Сохраняющий смещение CNOT между кошачьими кубитами | 8.2 | Прямой запутывающий вентиль между двумя диссипативными кошачьими кубитами, сохраняющий экспоненциальное подавление переворотов бита (bit-flip) на всём протяжении взаимодействия, — пока только теория. |
| 3 Механизм вентиля | src_resource | Генератор многофотонных ресурсных состояний (RSG; 6-ring и т.п.) | 8.2 | Подсистема «источник + слияние (fusion)», обязанная массово производить кодированные многофотонные графовые состояния с темпом кода, чтобы питать отказоустойчивость на слияниях; ничто и близко не работает на таком темпе. |
| 3 Механизм вентиля | g_fusion | Линейно-оптическое слияние (с оповещением) | 7.7 | Вероятностное измерение пары фотонов в базисе Белла — 50% без усиления, 75% со вспомогательными фотонами, — отказ которого сопровождается оповещением (heralded) и даёт стирание (erasure) одного из двух измеряемых исходов; запутывающий примитив фотоники на слияниях (fusion). |
| 3 Механизм вентиля | g_mbq | Майорановский вентиль через измерения | 5.7 | Вентили Клиффорда, порождаемые последовательностями совместных измерений фермионной чётности вместо физического плетения; специфицированы с 2008 года, ни разу не приведены в действие. |
| 3 Механизм вентиля | g_rydanalog | Аналоговая эволюция под ридберговским гамильтонианом | 4.6 | Глобальные лазерные поля возбуждают программируемый ридберговский изинговский гамильтониан сразу на всём массиве пинцетов: программой служат формы сигналов Ω(t), Δ(t), фиксированный узор локальной отстройки и геометрия атомов, а дискретного вентиля нет. |
| 3 Механизм вентиля | g_lointer | Программируемый линейно-оптический интерферометр (без запутывающего примитива) | 4.4 | Программируемый пассивный унитарный оператор на N оптических модах — сетка светоделителей и фазовращателей или волоконные петли с временными бинами (time-bin), — который рассеивает сжатый свет или одиночные фотоны на детекторы для сэмплинга, без запутывающего вентиля и без прямой связи (feed-forward). |
| 3 Механизм вентиля | g_anneal | Квантовый отжиг (аналоговая эволюция) | 4.2 | Непрерывная во времени гамильтонова эволюция (когерентный квенч (quench), 3.6–27 ns), уводящая изинговские или ридберговские спины к основному состоянию; не дискретный вентиль. |
| 3 Механизм вентиля | g_cr | Кросс-резонанс (фиксированная частота, только СВЧ) | 4.2 | Полностью микроволновый запутывающий вентиль: трансмон фиксированной частоты возбуждают на частоте его соседа через статическую шину; ни линии потока, ни перестраиваемого элемента связи. |
| 3 Механизм вентиля | g_cv | Гауссовы вентили на непрерывных переменных + негауссовы операции с помощью GKP | 4.2 | Светоделители, сжиматели и гомодинное упреждающее управление над оптическими модами, где решёточные состояния GKP поставляют негауссов ресурс, требуемый отказоустойчивостью. |
| 3 Механизм вентиля | g_mwspin | СВЧ / оптические спиновые вентили (центры окраски, однокубитные спины) | 1.7 | Резонансный микроволновый поворот электронного спина дефекта, поворот соседних ядер, обусловленный сверхтонкой связью, и оптические импульсы для инициализации и считывания. |
| 4 Связность / транспорт | cx_lr | Дальние элементы связи на чипе (c-couplers, mm-масштаб) | 18.4 | Перестраиваемые элементы связи, удлинённые волноводом или резонатором, которые запутывают неподвижные сверхпроводниковые кубиты, разнесённые на миллиметры, и тем самым дают графы степени 6, необходимые кодам qLDPC. |
| 4 Связность / транспорт | cx_shuttle | Перемещение спинов (конвейерный режим) | 14.4 | Когерентный транспорт спинового кубита вдоль конвейера, задаваемого затворами: расстояние и разреженность топологии покупаются бюджетом дефазировки, а не разводкой. |
| 4 Связность / транспорт | cx_nn | Статическая решётка со связью ближайших соседей | 13.4 | Граф связей, зафиксированный на уровне масок, в котором каждый кубит взаимодействует только с литографическими соседями; топология по умолчанию под всяким эксплуатируемым сверхпроводниковым и спиновым процессором. |
| 4 Связность / транспорт | cx_qccd | Перемещение ионов (QCCD, перекрёстки, решётчатые ловушки) | 11.6 | Перемещение ионов в ловушках между зонами через перекрёстки или решётчатые ловушки, благодаря чему небольшой пригодный для вентилей кристалл получает связность «все со всеми». |
| 4 Связность / транспорт | cx_aod | Транспорт атомов пинцетами на АОД (зонная архитектура) | 10.9 | Скрещённые акустооптические дефлекторы перемещают пинцеты, перевозя атомы между зонами хранения, запутывания и считывания с показателем ~99.95% на одно перемещение. |
| 4 Связность / транспорт | cx_switch | Фотонная коммутация / маршрутизация (электрооптика, прямая связь) | 8.4 | Электрооптические и МЭМС-переключатели маршрутизируют фотоны между волноводами по решению, принимаемому в реальном времени по оповещающему (heralding) отсчёту, — транспортный слой с доминирующими потерями, общий для всех фотонных архитектур. |
| 4 Связность / транспорт | cx_reload | Непрерывная дозагрузка атомов (резервуар + оптический конвейер) | 7.9 | Непрерывно пополняемый резервуар атомов (конвейерные ленты оптической решётки от удалённой MOT, решётка с резонаторным усилением или атомный пучок, остановленный оптической патокой), из которого пинцеты извлекают свежие атомы в массив, пока хранимые кубиты сохраняют когерентность. |
| 4 Связность / транспорт | cx_crossbar | Кроссбар с общими линиями (спины) | 5.7 | Разделяемые по строкам и столбцам линии плунжеров и барьеров адресуют двумерный массив точек так, что число линий растёт как корень из числа точек, — разводимость покупается ценой гранулярности адресации. |
| 4 Связность / транспорт | cx_bus | Шина на колебательных модах ионной цепочки (все со всеми в цепочке) | 4.2 | Общая коллективная колебательная мода запутывает любую пару ионов в одной ловушке, давая настоящую полную связность ценой роста времени вентиля с длиной цепочки. |
| 5 Управление | ct_cryocmos | Крио-КМОП-контроллер (4 K / mK) | 17.6 | Серийные КМОП-ASIC внутри криостата, которые синтезируют управляющие формы сигналов и смещения непосредственно рядом с кубитами, заменяя стойки комнатной температуры вместе с их коаксиальными линиями. |
| 5 Управление | ct_sfq | Цифровое управление на БОК-логике (4 K / mK) | 14.4 | Квантованные импульсы магнитного потока с ниобиевого цифрового кристалла, смонтированного flip-chip на кубитную пластину, выполняют вентили при милликельвинах, заменяя микроволновый коаксиал на каждый кубит. |
| 5 Управление | ct_ionmw | СВЧ-управление, интегрированное в чип (ионы) | 12.9 | Возбуждение вентилей на ионах синтезируется как электрические сигналы и подводится проводниками внутри чипа ловушки, а не лазерными лучами. |
| 5 Управление | ct_pic_trap | Пинцеты от ФИС / интегральная оптика для атомов | 11.2 | Формирование, разводка и сбор света, который удерживает, адресует и отображает одиночные атомы, — на фотонной интегральной схеме вместо оптики свободного пространства. |
| 5 Управление | ct_base | Электрическое управление в основной полосе частот (спины, майораны) | 10.2 | Импульсы напряжения от постоянного тока до единиц GHz на литографических электродах затворов управляют обменом, туннелированием и чётностью в спиновых и майорановских устройствах — без резонансной накачки. |
| 5 Управление | ct_fluxdac | Мультиплексирование потоковых ЦАП на чипе | 9.7 | Расположенные на кристалле БОК-ЦАП магнитного потока, которые удерживают постоянное смещение каждого кубита или элемента связи на mK-ступени и заменяют один комнатнотемпературный провод на каждое смещение мультиплексированной сетью на кристалле. |
| 5 Управление | ct_ionlaser | Лазерное управление с интегральной фотоникой (ионы) | 9.7 | Волноводы на кристалле подводят к ионам в ловушках излучение охлаждения, вентилей и считывания, заменяя пучки в свободном пространстве оптическими трассами, зафиксированными литографией. |
| 5 Управление | ct_rt | Электроника при комнатной температуре + коаксиальный / гибкий кабель на кубит | 9.4 | На каждый порт возбуждения, потокового смещения и считывания идёт своя когерентная линия — от комнатнотемпературных стоек через аттенюированный коаксиал или гибкий шлейф в камеру смешения. |
| 5 Управление | ct_laser | Оптическое управление лазером через АОД/SLM (атомы) | 8.4 | Лазеры свободного пространства, голографические модуляторы и акустооптические дефлекторы создают, перемещают, снимают и возбуждают массивы оптических пинцетов, удерживающие кубиты на нейтральных атомах. |
| 5 Управление | ct_vio | Вертикальный (внеплоскостной) подвод сигналов — VIO, коаксмон, 3D разводка | 6.4 | Линии управления и считывания от электроники при комнатной температуре подходят к каждому сверхпроводниковому кубиту через лицевую поверхность чипа — коаксиальные штыри, контактные зонды, сверхпроводниковые переходные отверстия (vias) или уложенный в стопку сигнальный кристалл, — а не разводятся в плоскости чипа к его краю. |
| 5 Управление | ct_ionaod | Свободнопространственная лазерная адресация ионов (пучки АОМ/АОД) | 6.2 | Свет для вентилей от оптического стола при комнатной температуре переключается и направляется на отдельные ионы одной цепочки многоканальными акустооптическими модуляторами или акустооптическими дефлекторами и фокусируется объёмной оптикой над ловушкой. |
| 5 Управление | ct_eo | Электрооптическое управление + электроника прямой связи (комн. т.) | 5.2 | Модуляторы при комнатной температуре, управляемые исходами детектирования в пределах одного оптического такта, — слой упреждающего управления, необходимый любой фотонной архитектуре. |
| 6 Считывание | ro_erasure | Внутрисхемная проверка стирания | 20.6 | Проверка на основе анциллы или флуоресценции, отвечающая на вопрос, находится ли кубит всё ещё в своём кодовом пространстве, и помечающая распад/утечку как локализованное стирание (erasure) без считывания логического состояния. |
| 6 Считывание | ro_spd | Детектирование одиночных фотонов (SNSPD / TES) | 13.2 | Криогенные сверхпроводниковые детекторы, разрушающие фотон ради его регистрации; общий орган считывания для всех фотонных и фотонно-связанных платформ. |
| 6 Считывание | ro_disp | Дисперсионное СВЧ-считывание (+TWPA, фильтр Парселла) | 10.4 | Состояние кубита читается как дисперсионный сдвиг связанного резонатора; сигнал фильтруется на кристалле фильтром Парселла и усиливается вблизи квантового предела ещё до HEMT. |
| 6 Считывание | ro_fluor | Детектирование состояния по флуоресценции (ионы, дефекты) | 9.4 | Зависящая от состояния резонансная флуоресценция, регистрируемая на ФЭУ, EMCCD, SNSPD или встроенном в ловушку фотодиоде, — стандартное неразрушающее внутрисхемное считывание для ионов в ловушках. |
| 6 Считывание | ro_img | Регистрация флуоресценции массивов атомов | 8.4 | Детектирование нейтральных атомов по флуоресценции с помощью камеры — неразрушающее, внутрисхемное, по умолчанию миллисекундное и микросекундное в демонстрациях отдельных групп. |
| 6 Считывание | ro_s2c | Преобразование спина в заряд + радиочастотная рефлектометрия | 8.4 | Спин преобразуется в событие перемещения заряда паулиевской блокадой или энергетически селективным туннелированием, после чего считывается согласованным по радиочастоте зарядовым сенсором за микросекунды и без разрушения кубита. |
| 6 Считывание | ro_qcap | Радиочастотное считывание чётности по квантовой ёмкости | 5.7 | Дисперсионное детектирование через затвор квантовой ёмкости майорановского острова методом радиочастотной рефлектометрии, читающее фермионную чётность без переноса заряда; неразрушающее и внутрисхемное. |
| 6 Считывание | ro_reset | Быстрый безусловный / диссипативный сброс кубита | 5.6 | Возврат сверхпроводникового кубита в |0⟩ за ~100–500 ns передачей его возбуждения диссипативной (lossy) моде, обычно резонатору считывания, вместо ожидания T1 или измерения с последующим переворотом. |
| 6 Считывание | ro_homodyne | Гомодинное детектирование квадратур (непрерывные переменные) | 4.5 | Сигнальная мода, интерферирующая с сильным локальным осциллятором на балансной паре фотодиодов, разностный ток которой отбирает одну выбранную квадратуру поля, — вычислительное измерение машин на непрерывных переменных и GKP. |
| 6 Считывание | ro_fluxro | Считывание потока через QFP / СКВИД и сдвиговые регистры (отжигатели) | 3 | В конце отжига состояние незатухающего тока каждого потокового кубита защёлкивается квантовым параметроном потока и переносится как классический бит к детектору — ПТ-СКВИДу или, на Advantage, микрорезонатору с частотным мультиплексированием на периметре чипа; ни один кубит не связан с резонатором считывания. |
| 7 Код | code_erasure | Коды, адаптированные к стираниям | 18.4 | Поверхностные и блочные коды, декодируемые с флагами локализованных ошибок; пороги 4–10% и Λ ≈ 27 в моделировании, выигрыш 1.7–1.9× на оборудовании. |
| 7 Код | code_surface | Повёрнутый поверхностный код (+ yoked-варианты) | 16.6 | CSS-стабилизаторный код веса 4 на квадратной решётке; единственный код с подпороговыми аппаратными данными на трёх платформах — и самый дорогой. |
| 7 Код | code_qldpc | Нелокальные qLDPC-коды (bivariate bicycle, «gross») | 16.1 | Разреженные стабилизаторные коды высокой скорости на торе степени 6, снижающие накладные расходы «физических на логический» примерно в десять раз по сравнению с поверхностным кодом. |
| 7 Код | code_highrate | Высокоскоростные каскадные коды с трансверсальными вентилями | 14.9 | Много логических кубитов на блок (iceberg, tesseract, каскадный [[4,2,2]]), клиффордовы вентили трансверсальны, заплачено связностью «все со всеми» и постселекцией. |
| 7 Код | code_magic | Фабрика магических состояний (культивация / дистилляция / переключение кодов) | 14.9 | Подсистема, изготавливающая неклиффордовы ресурсные состояния, чтобы код с трансверсальными клиффордовыми вентилями мог исполнять универсальные схемы. |
| 7 Код | code_bosonic | Бозонное каскадирование (repetition-cat, LDPC-cat, GKP+qLDPC) | 12.9 | Дискретный внешний код — повторяющий или qLDPC, — обёрнутый вокруг бозонного внутреннего кубита, шум которого уже сформирован, так что внешнему коду остаётся исправлять лишь один остаточный канал. |
| 7 Код | code_color | Цветовой код (трансверсальные клиффордовы вентили) | 12.4 | Треугольный двумерный стабилизаторный код, у которого вся группа Клиффорда действует трансверсально, минуя решёточную хирургию, ценой примерно 1.9× teraquop-площади поверхностного кода. |
| 7 Код | code_aft | Алгоритмическая отказоустойчивость / трансверсальные архитектуры | 11.4 | Замена O(d) раундов извлечения синдрома на один логический вентиль постоянным их числом — за счёт трансверсальных вентилей между блоками кода и коррелированного декодирования. |
| 7 Код | code_detect | Коды обнаружения ошибок ([[4,2,2]], поверхностный d = 2, iceberg, пространственно-временные) | 8 | Коды, которые помечают любой одиночный сбой и отбрасывают прогон вместо того, чтобы исправлять ошибку: [[4,2,2]], поверхностный код расстояния 2, код iceberg [[k+2,k,2]] и пространственно-временные проверки клиффордовых схем. |
| 7 Код | code_fusion | Отказоустойчивость на основе слияний | 6.7 | Отказоустойчивый код, собираемый из разрушающих линейно-оптических слияний (fusion) над заранее изготовленными фотонными ресурсными состояниями; теоретически терпит 2.7-17.4% потерь фотонов и ни разу не был выполнен сквозным образом. |
| 7 Код | code_mitig | Смягчение ошибок в слоте кода (ZNE, PEC) — не код | 5 | Классическая постобработка множества зашумлённых запусков — экстраполяция к нулевому шуму, вероятностная компенсация или усиление ошибок, твирлинг считывания, тензорно-сетевое обращение шума, — которая устраняет смещение средних значений (expectation values), не кодируя, не обнаруживая и не исправляя ни одной ошибки. |
| 8 Декодер | dec_nn | Нейросетевые декодеры (AlphaQubit 2, CNN, трансформеры) | 13.9 | Обучаемые декодеры синдрома — рекуррентные трансформеры, CNN, LSTM, модели пространства состояний, — которые обходят паросочетание (matching) за счёт усвоения непаулевского шума устройства прямо из данных. |
| 8 Декодер | dec_mwpm | MWPM / Sparse Blossom (+коррелированное паросочетание) | 12.7 | Декодер на паросочетании (matching) в графе, превращающий историю синдрома — события детектирования по раундам — в наиболее правдоподобную цепочку ошибок; эталон точности и реально поставляемый декодер реального времени для поверхностных кодов. |
| 8 Декодер | dec_gpu | GPU-декодирование через NVQLink | 11.7 | Канал RoCE, помещающий GPU внутрь петли обратной связи QEC при среднем времени кругового обхода 3.84 µs, так что декодирование исполняется как программа CUDA на оборудовании класса GH200, а не как фиксированная прошивка ПЛИС. |
| 8 Декодер | dec_relaybp | Relay-BP для qLDPC (ПЛИС) | 11.7 | Распространение доверия (belief propagation) с разупорядоченными, частично отрицательными силами памяти, сцепленное в эстафетные участки и декодирующее синдромы qLDPC двумерно-циклического (bivariate-bicycle) семейства за 24 ns на итерацию на ПЛИС. |
| 8 Декодер | dec_cryo | Криогенный декодер / декодер на чипе (крио-КМОП, БОК) | 10.4 | Декодирование синдрома или его предварительное декодирование выполняется внутри криостата — логика БОК при милликельвинах, КМОП при 4 K — вместо комнатной температуры. |
| 8 Декодер | dec_corr | Коррелированное декодирование / декодирование с учётом потерь (трансверсальные вентили, потеря атомов) | 7.7 | Декодеры, которые принимают оповещения (heralding) о потере атома как локализованные стирания (erasure) и декодируют сразу по трансверсальным слоям вентилей, а не раунд за раундом. |
| 8 Декодер | dec_fpga | ПЛИС-декодеры реального времени (LCD, Deltaflow) | 7.4 | ПЛИС комнатной температуры, на которых работают декодеры кластеризации или паросочетания (matching), достаточно быстрые, чтобы разбирать синдромы поверхностного кода внутри цикла QEC, опережая альтернативы на GPU и криогенные. |
| 8 Декодер | dec_rl | RL-калибровка в контуре / подстройка управления | 6.7 | События детектирования от работающего кода одновременно служат сигналом вознаграждения для агента обучения с подкреплением, который перенастраивает параметры управления прямо по ходу QEC, заменяя плановую перекалибровку. |
| 9 Межсоединение | ic_transducer | СВЧ-оптический преобразователь (полезной эффективности) | 14.4 | Квантово-когерентный преобразователь микроволнового диапазона в телеком-диапазон, достаточно хороший, чтобы запутывать сверхпроводниковые процессоры в разных криостатах; в 2026 году к этому не приблизилось ничто. |
| 9 Межсоединение | ic_mcm | Многокристальные модули / l-couplers (один криостат) | 13.9 | Разделение сверхпроводникового процессора на несколько кристаллов внутри одного криостата, соединённых чиплетными связями на индиевых бампах или сверхпроводниковыми l-couplers метрового масштаба. |
| 9 Межсоединение | ic_cryolink | Криогенная СВЧ-линия связи между криостатами | 11.9 | Сверхпроводниковый волновод, удерживаемый ниже 50 mK по всей своей длине и переносящий бегущие фотоны 5–7 GHz или сжатые состояния между двумя независимо охлаждаемыми рефрижераторами растворения. |
| 9 Межсоединение | ic_ionphoton | Ион-фотонный интерфейс | 10.9 | Запутывание ион — фотон с оповещением (heralded) по волокну связывает отдельные ионные ловушки в одну машину; лучшая опубликованная скорость 250 с⁻¹ при потребности ~10⁴ с⁻¹. |
| 9 Межсоединение | ic_spinphoton | Твердотельный спин-фотонный интерфейс (SiV, NV, T-центр) | 10.4 | Фотонная запутанность с оповещением (heralded) между разнесёнными твердотельными спиновыми регистрами — NV- и SiV-центрами в алмазе, T-центрами в кремнии — через проложенное телекоммуникационное волокно. |
| 9 Межсоединение | ic_atomcavity | Атом-фотонный интерфейс через резонатор | 9.2 | Оптический резонатор вокруг нейтральных атомов в оптических пинцетах усиливает по Парселлу связь атом — фотон, так что состояние атома можно записать на летающий фотон. |
| 9 Межсоединение | ic_fanout | Криогенная разводка сигналов для спиновых массивов (кристалл-маршрутизатор, 3D многослойная разводка) | 6.6 | Милликельвиновый кристалл-маршрутизатор, мультиплексор на кристалле или 3-D многослойная разводка, превращающие несколько холодных входных линий в десятки–тысячи напряжений на затворах, которые нужны массиву спиновых кубитов. |
| 9 Межсоединение | ic_multidie | Многокристальная сборка в одном модуле (flip-chip, bump-bonding с управляющим кристаллом) | 5.8 | Кристалл с кубитами, соединённый бампами лицом к лицу со вторым сверхпроводниковым кристаллом, который несёт разводку, резонаторы, второй материал или управляющую логику, — внутри одного корпуса, через вакуумный зазор от нескольких до ~20 µm. |
| 9 Межсоединение | ic_fibre | Волоконные линии связи между фотонными модулями | 5.2 | Телекоммуникационное волокно, переносящее запутанность с оповещением (heralded) между фотонными кристаллами и стойками, — цена определяется разъёмом, а не метром, а темп нигде не опубликован. |
| 10 Производство | fab_cmos | КМОП-фабрика 300 mm (спины, крио-КМОП, сверхпроводниковая разводка) | 17.9 | Промышленные КМОП-линии 300 mm, изготавливающие спиновые кубиты на квантовых точках, крио-КМОП-контроллеры и сверхпроводниковую разводку; единственный маршрут производства кубитов со статистикой выхода годных в масштабе пластины. |
| 10 Производство | fab_pic | Фабрика ФИС (SiN, BTO, TFLN, SNSPD на 300 mm) | 13.2 | Маршрут КМОП-фабрики, собирающий малопотерьные нитридные волноводы, электрооптические коммутаторы, однофотонные детекторы и присоединение волокна на одной 300 mm пластине. |
| 10 Производство | fab_sc | Литография сверхпроводниковых кубитов (переходы Al/AlOx/Al, разводка из Nb, 300 mm) | 11.1 | Литография переходов на 300 mm и последующая подгонка задают разброс частот, который наследует каждая сверхпроводниковая архитектура. |
| 10 Производство | fab_trap | Изготовление ионных ловушек (планарные чипы; фрезерованные 3D ловушки-лезвия) | 10.9 | Планарные чипы с РЧ/DC-электродами, удерживающие и перемещающие ионы; изготавливаются на МЭМС-линиях или, всё чаще, на пластинах контрактных полупроводниковых фабрик. |
| 10 Производство | fab_optics | Оптическая / механическая сборка (лазеры, вакуум, объективы) | 8.7 | Стек лазеров, сверхвысокого вакуума и оптики формирования изображения, который захватывает, охлаждает, адресует и считывает кубиты как на ионах в ловушках, так и на нейтральных атомах, — инфраструктура, а не кубит. |
| 10 Производство | fab_3d | Объёмные сверхпроводниковые резонаторы (механическая обработка) | 5.2 | Корпуса резонаторов из алюминия или ниобия, изготовленные на станках с ЧПУ, с собственной добротностью Q выше 0.5×10⁹; сантиметровый корпус на каждую моду — структурная цена бозонных кодов на резонаторах. |
| 10 Производство | fab_bulk | Сборка из объёмной оптики и волокна (фотонные сэмплеры) | 4.2 | Фотонные процессоры, собранные из дискретных деталей — источников сжатого света и интерферометров в свободном пространстве, волоконных петель задержки, модуляторов с волоконным вводом и криогенных детекторов одиночных фотонов, — которые юстируются и стабилизируются вручную и сервосистемами, а не формируются литографией на пластине. |
| 10 Производство | fab_mbe | Гетероструктуры A3B5 (МЛЭ; проволоки InAs–Pb, КТ-источники) | 4.2 | Молекулярно-лучевая эпитаксия наноструктур A3B5 со сверхпроводящими оболочками, наносимыми без разрыва вакуума, для майорановских проводов, а также квантовых точек для однофотонных источников. |
| 10 Производство | fab_diamond | Выращивание алмаза / имплантация (NV, SiV, SnV) | 1.7 | Плазменное CVD-выращивание монокристаллического алмаза, ионная имплантация и отжиг для формирования NV-, SiV- или SnV-центров, а также подтравливание для построения нанофотоники вокруг них. |
| 10 Производство | fab_stm | СТМ-литография (доноры) | 1.7 | Остриё сканирующего туннельного микроскопа десорбирует водород с пассивированной поверхности Si(100), открывая одиночные площадки, фосфин легирует их, а эпитаксиальный кремний заращивает доноры — атомарно точно, последовательно и без фабричного эквивалента. |
BRתקצירי הטכנולוגיות
Every technology on the map has a brief, and the depth of each one follows the technology's centrality in the graph — how many platform families and architectures depend on it and how recently it reached hardware — so a node a dozen architectures run through gets about 2,000 words and a single-platform node about 800. Centrality is a statement about the graph, not a verdict on the technology; it is shown in each brief's header and in the index below.
Every brief carries the same section skeleton — identity and lineage, physics and limits, engineering state of the art, manufacturing and supply chain, role in the stack, actors and economics, outlook and open questions, sources, and open verification items — so any two briefs can be read against each other. The Actors & economics section is verified against dated primary sources. Evidence tags mark the standing of every claim: D measured or peer-reviewed, C company claim, R roadmap or target, S simulation or estimate, G established or general fact (where the chip is a link it opens the dated primary source), P preprint or trade press.
Numbers are the Atlas’s: a work has the same number here, in §9 and in every other brief; online sources were accessed in September 2026.
| layer | id | technology | centrality | one line |
|---|---|---|---|---|
| 1 נושא הקיוביט | ion | יון אטומי לכוד | 10.9 | יונים בודדים של Yb⁺/Ba⁺/Ca⁺ במלכודות RF, הנשזרים דרך אופני תנועה משותפים; הקיוביט בעל הנאמנות הגבוהה ביותר והאיטי ביותר בשירות מסחרי. |
| 1 נושא הקיוביט | transmon | טרנסמון | 10.9 | צומת ג'וזפסון המחובר במקביל לקבל (Koch 2007); נושא הקיוביט של Willow, Heron/Nighthawk ו-Zuchongzhi, עם השער הדטרמיניסטי ומחזור תיקון השגיאות המהירים ביותר מכל קיוביט שהודגם. |
| 1 נושא הקיוביט | majorana | זוגיות מיורנה (טטרון InAs–Pb) | 10.7 | זוגיות פרמיונית המאוחסנת באופן לא-מקומי בזוג תילים של מוליך למחצה–מוליך-על המוגדרים באלקטרודות שער; נמדדה רק קריאת זוגיות בתיל יחיד. |
| 1 נושא הקיוביט | alkali | אטום אלקלי (Rb/Cs) במלקחיים אופטיים | 10.6 | קיוביט ברמות העל-דקות של מצב היסוד באטום רובידיום או צזיום בודד, המוחזק במלקחיים אופטיים רחוקים מתהודה ומוזז לפי דרישה. |
| 1 נושא הקיוביט | ae_atom | אטום אלקלי-עפרורי או דומה לו (Yb/Sr) — מחיקה מובנית | 9.9 | קיוביטי איטרביום/סטרונציום במלקחיים אופטיים, שמכלול השעון המטא-יציב שלהם הופך דעיכה ואובדן לניתנים לגילוי אופטי, וממיר שגיאות פיזיות למחיקות מבושרות במקום לשגיאות פאולי שקטות. |
| 1 נושא הקיוביט | photon | פוטון בודד (משתנה בדיד) | 9.9 | קיוביט הנישא בקוונט אופטי יחיד באופני מסלול, משבצת זמן או קיטוב; השזירה הסתברותית, והשגיאה השולטת היא אובדן. |
| 1 נושא הקיוביט | qd_spin | ספין בנקודה קוונטית המוגדרת באלקטרודות שער (Si/SiGe, SiMOS, Ge) | 9.9 | ספין של אלקטרון או של חור בנקודה שאלקטרודות השער שלה מוגדרות בליתוגרפיה; החילוף נותן שערים דו-קיוביטיים דטרמיניסטיים בסדר גודל של ns על פיסת CMOS. |
| 1 נושא הקיוביט | cavity | אופן בוזוני של מהוד | 7.7 | אופן מיקרוגל הרמוני של מהוד מוליך-על תלת-ממדי או מישורי, המשמש כנושא הקיוביט; השגיאה שלו היא אובדן פוטונים מובנה, לא רעש פאולי כללי. |
| 1 נושא הקיוביט | fluxonium | פלוקסוניום | 6.7 | קיוביט מוליך-על שצומת הג'וזפסון שלו מחובר במקביל למערך צמתים, בתדר 0.2–1 GHz, עם אנהרמוניות גדולה ו-T1 ארוך, הנקנים במחיר של קו ממתח שטף לכל קיוביט. |
| 1 נושא הקיוביט | fluxq | קיוביט שטף rf-SQUID (מחשב הרפיה) | 6.7 | לולאה מוליכת-על בעלת בור כפול, המשמשת כספין איזינג ניתן לתכנות במחשבי ההרפיה של D-Wave; אין ערכת שערים, אין קוד. |
| 1 נושא הקיוביט | squeezed | אופן של אור סחוט (CV) | 6.7 | אופן אופטי של משתנה רציף שאחת הקוודרטורות שלו מתחת לרעש הוואקום; הנושא של פוטוניקת GKP ומצבי אשכול, שבה אובדן האינטגרציה, ולא האי-ליניאריות, קובע את התקרה. |
| 1 נושא הקיוביט | defect | ספין במרכז צבע / ספין פגם (NV, SiV, SnV, מרכז T) | 4.2 | ספין של פגם נקודתי ביהלום או בצורן, בר-מיעון אופטי, שהאלקטרון שלו מצטמד באופן קוהרנטי לפוטון — וזה הופך אותו לצומת רשת עם אוגר גרעיני קטן, ולא לקיוביט של מעבד. |
| 1 נושא הקיוביט | donor | ספין של אטום תורם (P ב-²⁸Si) | 4.2 | אטומי זרחן תורמים הממוקמים בליתוגרפיית STM בצורן-28 מועשר; האלקטרון הקשור מספק את ההנעה ואת הקריאה, וגרעין ה-³¹P הוא הקיוביט ארוך החיים. |
| 2 קידוד | enc_dualrail | קידוד מסילה כפולה (מחיקה) | 16.9 | עירור אחד המשותף לשני אופנים; אובדן יוצא ממרחב הקוד ומבושר כמחיקה ממוקמת, לא כשגיאת פאולי לא ידועה. |
| 2 קידוד | enc_omg | קידוד מחיקה מטא-יציב ("omg") | 15.4 | הקיוביט שוכן במכלול מטא-יציב, כך שהדעיכה השולטת שלו יוצאת מתת-המרחב באופן הניתן לגילוי, וממירה שגיאות פאולי למחיקות ממוקמות. |
| 2 קידוד | enc_gkp | קידוד רשת GKP | 12.9 | קיוביט המקודד במצבי רשת מחזוריים של אופן בוזוני אחד — מהוד מיקרוגל או אופן אופטי — המתקן הזזות קטנות בקוודרטורות ומוסר למפענח סינדרום אנלוגי. |
| 2 קידוד | enc_cat | קידוד חתול (רעש מוטה) | 7.4 | קיוביט של מצבים קוהרנטיים המיוצב בדיסיפציה דו-פוטונית, שהיפוכי הביט שלו יורדים מעריכית עם מספר הפוטונים, בעוד שהיפוכי הפאזה עולים איתו ליניארית. |
| 2 קידוד | enc_hf | קיוביט על-דק / קיוביט מצב-שעון | 7.2 | שתי תת-רמות על-דקות, או תת-רמות של ספין גרעיני, של מצב היסוד בנקודת שעון שאינה רגישה לשדה; קיוביט ברירת המחדל של כל ספק של יונים לכודים ושל אטומים ניטרליים. |
| 2 קידוד | enc_spin_ld | קידוד בספין יחיד (לוס–דיווינצ'נזו) / בספין גרעיני | 5.5 | קיוביט אחד לכל ספין-1/2 — אלקטרון, חור או גרעין כלואים — ללא תת-מרחב מקודד, ומכאן טביעת הרגל הקטנה ביותר והיעדר ערוץ דליפה. |
| 2 קידוד | enc_opt | קיוביט אופטי צר-קו (S–D ביון, שעון אטומי) | 4.4 | קיוביט המפוצל בין רמת יסוד לבין רמה מטא-יציבה הנמצאת פוטון אופטי אחד מעליה — הקו הקוודרופולי S₁/₂–D₅/₂ של ⁴⁰Ca⁺ או של ⁸⁸Sr⁺, או קו השעון ¹S₀–³P₀ של Sr/Yb ניטרלי — ולייזר צר-קו אחד מניע כל שער. |
| 2 קידוד | enc_bare | קיוביט פיזי חשוף (ללא קידוד) | 4.2 | תת-המרחב {|0⟩,|1⟩} של מתנד ג'וזפסון בעל אנהרמוניות חלשה, המשמש ישירות כקיוביט, בלי מבנה בוזוני, מבנה מחיקה או מבנה הטיה מעליו. |
| 2 קידוד | enc_eo | קידוד ספין בחילוף בלבד / סינגלט-טריפלט | 4.2 | קיוביט לוגי אחד בתת-המרחב של הספין הכולל של שלושה ספינים המצומדים בחילוף (קידוד בחילוף בלבד) או של שני ספינים ועוד גרדיאנט שדה (קידוד סינגלט–טריפלט), המונע כולו בפולסי מתח בפס בסיס, כשהדליפה היא המחיר של סילוק בקרת המיקרוגל. |
| 2 קידוד | enc_gr | קיוביט אנלוגי יסוד–רידברג | 4.2 | קיוביט דו-רמתי הבנוי ממצב יסוד אטומי |g⟩ וממצב רידברג |r⟩, המונע באופן גלובלי תחת המילטוניאן מטיפוס איזינג: הבסיס החישובי של סימולטורי רידברג אנלוגיים, לא קוד המדכא שגיאות. |
| 2 קידוד | enc_parity | קידוד בזוגיות פרמיונית (טטרון) | 4.2 | קיוביט לוגי אחד בזוגיות הפרמיונית של ארבעה אופני מיורנה על שני תילים; Z ו-X הם הזוגיות של זוגות אופנים שונים, ושניהם אינם מקומיים. |
| 2 קידוד | enc_timebin | קידוד פוטוני במשבצות זמן / במסלולים | 1 | קיוביט פוטוני במסילה כפולה, המקודד במשבצות זמן-הגעה או במסלול מוליך הגל; האובדן הוא השגיאה השולטת, והוא מבושר — מחיקה במיקום ידוע — ולא שגיאה שקטה. |
| 3 מנגנון השער | g_ryd | CZ בחסימת רידברג | 13.9 | פולסי לייזר גלובליים מעוררים אטומים שכנים הלכודים במלקחיים אופטיים למצב רידברג, שהאינטראקציה בו חוסמת עירור כפול, ומספקים CZ דטרמיניסטי של 270 ns. |
| 3 מנגנון השער | g_elec | שער מיקרוגל אלקטרוני (יונים, ללא לייזר: שדה קרוב או גרדיאנט סטטי) | 12.9 | זרמים בשבב מלכודת שיוצר במיקרו-ייצור שוזרים יונים באמצעות גרדיאנטים של שדה מיקרוגל, ללא לייזר וללא קירור למצב היסוד. |
| 3 מנגנון השער | g_tc | CZ / iSWAP במצמד בר-כוונון | 10.6 | מצמד המכוונן בשטף מפעיל ומכבה את אינטראקציית החילוף וה-ZZ בין טרנסמונים, ומספק שערי CZ או iSWAP דטרמיניסטיים של 25–70 ns. |
| 3 מנגנון השער | g_exch | שער חילוף (ספינים; כולל CZ בספינים מוסעים) | 9.1 | חילוף הייזנברג בפולסי מתח בין ספינים שכנים או מוסעים, בנקודות המוגדרות באלקטרודות שער או באטומים תורמים — מנגנון השזירה היחיד שאינו צריך דבר מלבד אלקטרודות שער של CMOS. |
| 3 מנגנון השער | g_ms | שער לייזר מולמר–סורנסן / הסטת אור | 9.1 | כוח תלוי-ספין של לייזר דו-כרומטי, השוזר יונים לכודים דרך פאזה גאומטרית על אופן תנועה משותף, שהשער מותיר כפי שמצא אותו. |
| 3 מנגנון השער | g_bos | שערים בוזוניים בתיווך קיוביט עזר (CX חתול, CZ מסילה כפולה, מפצל אלומה) | 8.4 | מצמדי SQUID/SNAIL מונעים וקיוביטי עזר טרנסמוניים מתווכים שערי מפצל-אלומה ושערי שזירה בין אופנים בוזוניים של מהודים מוליכי-על, עבור קידודי חתול, GKP ומסילה כפולה. |
| 3 מנגנון השער | g_catcnot | CNOT חתול–חתול משמר-הטיה | 8.2 | שער שזירה ישיר בין שני קיוביטי חתול דיסיפטיביים, המשמר ללא פגע את הדיכוי המעריכי של היפוכי הביט לאורך האינטראקציה — תאוריה בלבד. |
| 3 מנגנון השער | src_resource | מחולל מצבי משאב רב-פוטוניים (RSG; טבעת-6 וכו') | 8.2 | תת-המערכת של מקורות והיתוך שחייבת לייצר בייצור המוני, בקצב הקוד, מצבי גרף רב-פוטוניים מקודדים כדי להזין סבילות לתקלות מבוססת-היתוך; שום דבר אינו פועל בקרבת הקצב הזה. |
| 3 מנגנון השער | g_fusion | היתוך באופטיקה ליניארית (מבושר) | 7.7 | מדידה הסתברותית בבסיס בל על שני פוטונים — 50% ללא הגברה, 75% עם פוטוני עזר — שכישלונה מבושר ומוחק אחת משתי התוצאות הנמדדות; פרימיטיב השזירה של הפוטוניקה מבוססת-ההיתוך. |
| 3 מנגנון השער | g_mbq | שער מיורנה מבוסס-מדידה | 5.7 | שערי קליפורד הנוצרים מרצפים של מדידות משותפות של זוגיות פרמיונית במקום קליעה פיזית; מוגדרים מאז 2008, מעולם לא הופעלו. |
| 3 מנגנון השער | g_rydanalog | התפתחות אנלוגית תחת המילטוניאן רידברג | 4.6 | שדות לייזר גלובליים מניעים המילטוניאן איזינג-רידברג הניתן לתכנות על מערך מלקחיים אופטיים שלם בבת אחת: צורות הגל Ω(t), Δ(t), תבנית קבועה של היסט מקומי והגאומטריה של האטומים הם התוכנית, ואין שער בדיד. |
| 3 מנגנון השער | g_lointer | אינטרפרומטר אופטי-ליניארי ניתן לתכנות (ללא פרימיטיב שזירה) | 4.4 | אוניטרי פסיבי ניתן לתכנות על N אופנים אופטיים — רשת של מפצלי אלומה ומזיזי פאזה או לולאות סיב במשבצות זמן — המפזר אור סחוט או פוטונים בודדים אל גלאים לצורך דגימה, ללא שער שזירה וללא הזנה קדימה. |
| 3 מנגנון השער | g_anneal | הרפיה קוונטית (התפתחות אנלוגית) | 4.2 | התפתחות המילטוניאנית בזמן רציף (הרפיה חטופה קוהרנטית, 3.6–27 ns) המובילה ספיני איזינג או רידברג לעבר מצב יסוד; לא שער בדיד. |
| 3 מנגנון השער | g_cr | תהודה צולבת (תדר קבוע, מיקרוגל בלבד) | 4.2 | שער שזירה במיקרוגל בלבד, המניע טרנסמון אחד בתדר קבוע בתדר של שכנו דרך אפיק סטטי; ללא קו שטף, ללא מצמד בר-כוונון. |
| 3 מנגנון השער | g_cv | שערים גאוסיים CV + פעולות לא-גאוסיות בסיוע GKP | 4.2 | מפצלי אלומה, מקורות סחיטה והזנה קדימה הומודינית על אופנים אופטיים, כשמצבי רשת GKP מספקים את המשאב הלא-גאוסי שהסבילות לתקלות דורשת. |
| 3 מנגנון השער | g_mwspin | שערי ספין במיקרוגל / אופטיים (מרכזי פגם, ספינים 1Q) | 1.7 | סיבוב תהודתי במיקרוגל של ספין האלקטרון בפגם, סיבוב המותנה בצימוד העל-דק של הגרעינים השכנים לו, ופולסים אופטיים לאתחול ולקריאה. |
| 4 קישוריות והובלה | cx_lr | מצמדים לטווח ארוך על השבב (מצמדי c, בסדר גודל של mm) | 18.4 | מצמדים ברי-כוונון המוארכים במוליך גל או במהוד, השוזרים קיוביטים מוליכי-על נייחים המרוחקים מילימטרים זה מזה, וקונים את הגרפים מדרגה 6 שקודי qLDPC צריכים. |
| 4 קישוריות והובלה | cx_shuttle | הסעת ספינים (מצב מסוע) | 14.4 | הובלה קוהרנטית של קיוביט ספין לאורך מסוע המוגדר באלקטרודות שער, הקונה מרחק ודלילות פריסה בתקציב דה-פאזה ולא בחיווט. |
| 4 קישוריות והובלה | cx_nn | סריג סטטי של שכנים קרובים | 13.4 | גרף צימוד שנקבע ברמת המסכה, שבו כל קיוביט מקיים אינטראקציה רק עם שכניו הליתוגרפיים; טופולוגיית ברירת המחדל שבבסיס כל מעבד מוליך-על וכל מעבד ספינים שהוצבו בשטח. |
| 4 קישוריות והובלה | cx_qccd | הסעת יונים (QCCD, צמתים, מלכודות רשת) | 11.6 | הזזת יונים לכודים בין אזורים דרך צמתים או מלכודות רשת, כך שגביש קטן שאפשר להפעיל עליו שערים יורש קישוריות של כל-לכל. |
| 4 קישוריות והובלה | cx_aod | הובלת אטומים במלקחי AOD (ארכיטקטורה מחולקת לאזורים) | 10.9 | מסיטים אקוסטו-אופטיים מוצלבים מזיזים מלקחיים אופטיים כדי להסיע אטומים בין אזורי אחסון, שזירה וקריאה, ב-~99.95% להזזה. |
| 4 קישוריות והובלה | cx_switch | מיתוג / ניתוב פוטוני (אלקטרו-אופטי, הזנה קדימה) | 8.4 | מתגים אלקטרו-אופטיים ומתגי MEMS מנתבים פוטונים בין מוליכי גל לפי החלטת בישור בזמן אמת — שכבת ההובלה שבה שולט האובדן, המשותפת לכל ארכיטקטורה פוטונית. |
| 4 קישוריות והובלה | cx_reload | טעינה מחדש רציפה של אטומים (מאגר + מסוע אופטי) | 7.9 | מאגר אטומים המוזן ברציפות (מסועים של סריג אופטי מ-MOT מרוחק, סריג מוגבר-מהוד או אלומה הנעצרת במולסה), שממנו מלקחיים אופטיים שולפים אטומים טריים אל המערך בזמן שהקיוביטים המאוחסנים שומרים על הקוהרנטיות שלהם. |
| 4 קישוריות והובלה | cx_crossbar | בקרת crossbar בקווים משותפים (ספינים) | 5.7 | קווי plunger ו-barrier המשותפים לשורות ולעמודות ממענים מערך נקודות דו-ממדי, ומספר הקווים גדל כשורש הריבועי של מספר הנקודות — יכולת החיווט נקנית במחיר רזולוציית המיעון. |
| 4 קישוריות והובלה | cx_bus | אפיק תנועתי של שרשרת יונים (כל-לכל בשרשרת) | 4.2 | אופן תנועה קולקטיבי משותף שוזר כל זוג במלכודת אחת, ומעניק קישוריות אמיתית של כל-לכל במחיר זמן שער הגדל עם אורך השרשרת. |
| 5 בקרה | ct_cryocmos | בקר CMOS קריוגני (4 K / mK) | 17.6 | רכיבי ASIC מסחריים ב-CMOS בתוך הקריוסטט, המסנתזים את צורות הגל לבקרת הקיוביטים ואת מתחי הממתח לצד הקיוביטים, ומחליפים את המסדים בטמפרטורת החדר ואת הקווים הקואקסיאליים שלהם. |
| 5 בקרה | ct_sfq | בקרה ספרתית SFQ (4 K / mK) | 14.4 | פולסי שטף מקוונטטים משבב ספרתי מניוביום, המורכב בשיטת השבב ההפוך על פיסת הקיוביטים, מניעים שערים בטמפרטורת מיליקלווין ומחליפים את כבל המיקרוגל הקואקסיאלי לכל קיוביט. |
| 5 בקרה | ct_ionmw | בקרת מיקרוגל משולבת בשבב (יונים) | 12.9 | הנעת השערים של היונים מסונתזת כאותות חשמליים ומועברת במוליכים בתוך שבב המלכודת, במקום באלומות לייזר. |
| 5 בקרה | ct_pic_trap | מלקחיים אופטיים הנוצרים ב-PIC / אופטיקה משולבת לאטומים | 11.2 | יצירה, ניתוב ואיסוף של האור הלוכד, הממען והמצלם אטומים בודדים — ממעגל פוטוני משולב במקום מאופטיקה במרחב חופשי. |
| 5 בקרה | ct_base | בקרה חשמלית בפס בסיס (ספינים, מיורנה) | 10.2 | פולסי מתח מ-DC ועד כמה GHz על אלקטרודות שער ליתוגרפיות מניעים חילוף, מנהור וזוגיות בהתקני ספין ובהתקני מיורנה, ללא הנעה תהודתית. |
| 5 בקרה | ct_fluxdac | ריבוב DAC-שטף על השבב | 9.7 | ממירים ספרתיים-אנלוגיים של שטף (DAC-שטף) מבוססי SFQ על השבב, המחזיקים את ממתח ה-DC של כל קיוביט או מצמד בשלב ה-mK, ומחליפים חוט אחד מטמפרטורת החדר לכל ממתח ברשת מרובבת על השבב. |
| 5 בקרה | ct_ionlaser | בקרת לייזר בפוטוניקה משולבת (יונים) | 9.7 | מוליכי גל על השבב מנתבים אור קירור, שער וקריאה אל יונים לכודים, ומחליפים אלומות במרחב חופשי בנתיבים אופטיים הקבועים בליתוגרפיה. |
| 5 בקרה | ct_rt | אלקטרוניקה בטמפרטורת החדר + כבל קואקסיאלי/כבל גמיש לכל קיוביט | 9.4 | קו קוהרנטי אחד לכל מבוא של הנעה, שטף וקריאה עובר ממסדים בטמפרטורת החדר, דרך כבל קואקסיאלי מונחת או כבל סרט גמיש (flex), אל תא הערבוב. |
| 5 בקרה | ct_laser | בקרה אופטית בלייזר + AOD/SLM (אטומים) | 8.4 | לייזרים במרחב חופשי, מאפננים הולוגרפיים ומסיטים אקוסטו-אופטיים יוצרים, מזיזים, מצלמים ומניעים את מערכי המלקחיים האופטיים המחזיקים את קיוביטי האטומים הניטרליים. |
| 5 בקרה | ct_vio | הולכת אותות אנכית (מחוץ למישור) — VIO, קואקסמון, חיווט תלת-ממדי | 6.4 | קווי בקרה וקריאה מאלקטרוניקה בטמפרטורת החדר מגיעים לכל קיוביט מוליך-על דרך פני השבב — פינים קואקסיאליים, גששי מגע, מעברים (vias) מוליכי-על או פיסת אותות מוערמת — במקום להיות מנותבים במישור השבב אל שוליו. |
| 5 בקרה | ct_ionaod | מיעון לייזר של יונים במרחב חופשי (אלומות AOM/AOD) | 6.2 | אור השערים משולחן אופטי בטמפרטורת החדר ממותג ומכוון אל יונים בודדים בשרשרת אחת בידי מאפננים אקוסטו-אופטיים רב-ערוציים או מסיטים אקוסטו-אופטיים, וממוקד דרך אופטיקה נפחית מעל המלכודת. |
| 5 בקרה | ct_eo | הנעה אלקטרו-אופטית + אלקטרוניקת הזנה קדימה (טמפרטורת החדר) | 5.2 | מאפננים בטמפרטורת החדר המונעים לפי תוצאות הגלאים בתוך מחזור שעון אופטי אחד — שכבת ההזנה קדימה שכל ארכיטקטורה פוטונית זקוקה לה. |
| 6 קריאה | ro_erasure | בדיקת מחיקה באמצע המעגל | 20.6 | בדיקה, באמצעות קיוביט עזר או פלואורסצנציה, האם קיוביט עודנו במרחב הקוד שלו; היא מסמנת דעיכה או דליפה כמחיקה ממוקמת בלי לקרוא את המצב הלוגי. |
| 6 קריאה | ro_spd | גילוי פוטון בודד (SNSPD / TES) | 13.2 | גלאים קריוגניים מוליכי-על ההורסים פוטון כדי לרשום אותו; איבר הקריאה המשותף של כל פלטפורמה פוטונית ושל כל פלטפורמה המקושרת בפוטונים. |
| 6 קריאה | ro_disp | קריאה דיספרסיבית במיקרוגל (+TWPA, מסנן פרסל) | 10.4 | מצב הקיוביט נקרא כהסטה דיספרסיבית של מהוד מצומד, מסונן במסנן פרסל על השבב ומוגבר קרוב לגבול הקוונטי לפני ה-HEMT. |
| 6 קריאה | ro_fluor | גילוי מצב בפלואורסצנציה (יונים, פגמים) | 9.4 | פלואורסצנציה תהודה תלוית-מצב, הנספרת ב-PMT, ב-EMCCD, ב-SNSPD או בפוטודיודה המשולבת במלכודת, היא קריאת ברירת המחדל הלא-הורסת באמצע המעגל של יונים לכודים. |
| 6 קריאה | ro_img | דימות פלואורסצנציה של מערכי אטומים | 8.4 | גילוי בפלואורסצנציה של אטומים ניטרליים באמצעות מצלמה — לא-הורס, באמצע המעגל, מילישנייה כברירת מחדל, מיקרושנייה בהדגמות של קבוצה יחידה. |
| 6 קריאה | ro_s2c | המרת ספין-למטען + רפלקטומטריית rf | 8.4 | הספין מומר לאירוע של תנועת מטען בחסימת פאולי או במנהור סלקטיבי לפי אנרגיה, ואז נקרא בחיישן מטען מתואם ל-rf בתוך מיקרושניות בלי להרוס את הקיוביט. |
| 6 קריאה | ro_qcap | קריאת זוגיות בקיבול קוונטי rf | 5.7 | חישת שער דיספרסיבית של הקיבול הקוונטי של אי מיורנה ברפלקטומטריית rf, הקוראת זוגיות פרמיונית בלי העברת מטען; לא הרסנית ובאמצע המעגל. |
| 6 קריאה | ro_reset | איפוס קיוביט מהיר בלתי מותנה / דיסיפטיבי | 5.6 | החזרת קיוביט מוליך-על ל-|0⟩ ב-~100–500 ns במסירת העירור שלו לאופן בעל הפסדים, בדרך כלל מהוד הקריאה, במקום להמתין ל-T1 או למדוד ולהפוך. |
| 6 קריאה | ro_homodyne | גילוי קוודרטורה הומודיני (CV) | 4.5 | אופן אות מתאבך עם מתנד מקומי חזק על זוג פוטודיודות מאוזן, שזרם ההפרש שלו דוגם קוודרטורה נבחרת אחת של השדה — המדידה החישובית של מכונות משתנה רציף ו-GKP. |
| 6 קריאה | ro_fluxro | קריאת שטף באמצעות QFP / אוגרי הזזה SQUID (מחשבי הרפיה) | 3 | בסוף ההרפיה מצב הזרם המתמיד של כל קיוביט שטף ננעל בפרמטרון שטף קוונטי ומועבר כביט קלאסי אל גלאי — dc SQUID, או ב-Advantage מיקרו-מהוד בריבוב תדרים בשולי השבב; אף קיוביט אינו מצומד למהוד קריאה. |
| 7 קוד | code_erasure | קודים מותאמי-מחיקה | 18.4 | קודי משטח וקודי בלוקים המפוענחים עם דגלים של שגיאות ממוקמות; ספים של 4–10% ו-Λ ≈ 27 בסימולציה, רווחים של 1.7–1.9× בחומרה. |
| 7 קוד | code_surface | קוד המשטח המסובב (+ גרסאות רתומות) | 16.6 | קוד מייצב מסוג CSS במשקל 4 על סריג ריבועי; הקוד היחיד עם נתוני חומרה מתחת לסף בשלוש פלטפורמות, והיקר ביותר. |
| 7 קוד | code_qldpc | קודי qLDPC לא-מקומיים (bivariate bicycle, "gross") | 16.1 | קודי מייצב דלילים בעלי קצב גבוה על טורוס מדרגה 6, המקצצים את תקורת הפיזיים-ללוגי בערך פי עשרה לעומת קוד המשטח. |
| 7 קוד | code_highrate | קודים משורשרים בקצב גבוה עם שערים טרנסוורסליים | 14.9 | קיוביטים לוגיים רבים בבלוק אחד (iceberg, tesseract, [[4,2,2]] משורשר), שערי קליפורד טרנסוורסליים, במחיר של קישוריות כל-לכל ובחירה בדיעבד. |
| 7 קוד | code_magic | מפעל מצבי קסם (טיפוח / זיקוק / החלפת קוד) | 14.9 | תת-המערכת המייצרת מצבי משאב לא-קליפורדיים, כדי שקוד עם שערי קליפורד טרנסוורסליים יוכל להריץ מעגלים אוניברסליים. |
| 7 קוד | code_bosonic | שרשור בוזוני (חזרה-חתול, LDPC-חתול, GKP+qLDPC) | 12.9 | קוד חיצוני בדיד — חזרה או qLDPC — העוטף קיוביט פנימי בוזוני שהרעש שלו כבר מעוצב, כך שהקוד החיצוני מתקן ערוץ שיורי אחד בלבד. |
| 7 קוד | code_color | קוד הצבע (שערי קליפורד טרנסוורסליים) | 12.4 | קוד מייצב דו-ממדי משולש שחבורת קליפורד כולה פועלת בו טרנסוורסלית, בדילוג על ניתוח סריג, בכ-1.9× מטביעת הרגל של קוד המשטח למכונת teraquop. |
| 7 קוד | code_aft | סבילות תקלות אלגוריתמית / ארכיטקטורות טרנסוורסליות | 11.4 | החלפת O(d) סבבי חילוץ סינדרום לכל שער לוגי במספר קבוע, באמצעות שערים טרנסוורסליים בין בלוקים ופענוח מתואם. |
| 7 קוד | code_detect | קודים לגילוי שגיאות ([[4,2,2]], קוד משטח d = 2, iceberg, מרחב-זמן) | 8 | קודים המסמנים כל תקלה בודדת ומשליכים את הריצה במקום לתקן אותה: [[4,2,2]], קוד המשטח במרחק 2, קוד ה-iceberg [[k+2,k,2]] ובדיקות מרחב-זמן על מעגלי קליפורד. |
| 7 קוד | code_fusion | סבילות לתקלות מבוססת-היתוך | 6.7 | קוד סובלני לתקלות המורכב מהיתוכים הורסים באופטיקה ליניארית על מצבי משאב פוטוניים מוכנים מראש, הסובל בתאוריה אובדן פוטונים של 2.7-17.4% ומעולם לא הורץ מקצה לקצה. |
| 7 קוד | code_mitig | הפחתת שגיאות במשבצת הקוד (ZNE, PEC) — אינה קוד | 5 | עיבוד קלאסי בדיעבד של ריצות רועשות רבות — אקסטרפולציה לרעש אפס, ביטול או הגברה הסתברותיים של שגיאות, סחרור הקריאה, היפוך הרעש ברשתות טנזורים — המסיר את ההטיה מערכי תוחלת בלי לקודד, לגלות או לתקן אף שגיאה אחת. |
| 8 מפענח | dec_nn | מפענחים מבוססי רשתות עצביות (AlphaQubit 2, CNN, טרנספורמרים) | 13.9 | מפענחי סינדרום נלמדים — טרנספורמרים חוזרים, רשתות CNN, רשתות LSTM, מודלי מרחב-מצבים — הגוברים על הזיווג בכך שהם לומדים מהנתונים את רעש ההתקן שאינו רעש פאולי. |
| 8 מפענח | dec_mwpm | MWPM / Sparse Blossom (+זיווג מתואם) | 12.7 | מפענח זיווג בגרף, ההופך את היסטוריית הסינדרומים — אירועי הגילוי לאורך הסבבים — לשרשרת השגיאות הסבירה ביותר; נקודת הייחוס לדיוק, והמפענח בזמן אמת שכבר מסופק בפועל לקודי המשטח. |
| 8 מפענח | dec_gpu | פענוח ב-GPU דרך NVQLink | 11.7 | קישור RoCE המכניס GPU לתוך לולאת המשוב של תיקון השגיאות, בזמן הלוך-ושוב ממוצע של 3.84 µs, כך שהפענוח רץ כתוכנת CUDA על חומרה ברמת GH200 במקום כקובץ תצורה (bitstream) קבוע של FPGA. |
| 8 מפענח | dec_relaybp | Relay-BP ל-qLDPC (FPGA) | 11.7 | התפשטות אמונה (belief propagation) עם עוצמות זיכרון בעלות אי-סדר, שחלקן שליליות, המופעלת כשרשרת של מקטעי ממסר ומפענחת סינדרומים של קודי qLDPC מסוג bivariate-bicycle ב-24 ns לאיטרציה על FPGA. |
| 8 מפענח | dec_cryo | מפענח קריוגני / על השבב (CMOS קריוגני, SFQ) | 10.4 | פענוח סינדרום או פענוח מקדים המבוצע בתוך הקריוסטט — לוגיקת SFQ בטמפרטורת מיליקלווין, CMOS ב-4 K — במקום בטמפרטורת החדר. |
| 8 מפענח | dec_corr | פענוח מתואם / מודע-אובדן (טרנסוורסלי, אובדן אטומים) | 7.7 | מפענחים הצורכים את אותות הבישור של אובדן אטומים כמחיקות ממוקמות, ומפענחים על פני שכבות של שערים טרנסוורסליים במקום סבב אחר סבב. |
| 8 מפענח | dec_fpga | מפענחי FPGA בזמן אמת (LCD, Deltaflow) | 7.4 | רכיבי FPGA בטמפרטורת החדר, המריצים מפענחי אשכול או זיווג מהר דיים כדי לעבד את סינדרומי קוד המשטח בתוך מחזור תיקון השגיאות, ומקדימים את החלופות של GPU ושל אלקטרוניקה קריוגנית. |
| 8 מפענח | dec_rl | כיול RL בלולאה / היגוי הבקרה | 6.7 | אירועי הגילוי של הקוד הרץ משמשים גם כאות התגמול של סוכן למידת חיזוק, המכוונן מחדש את פרמטרי הבקרה במהלך תיקון השגיאות ומחליף את הכיול מחדש לפי לוח זמנים. |
| 9 חיבור בין-מודולי | ic_transducer | מתמר מיקרוגל–אופטי (בנצילות שימושית) | 14.4 | ממיר ממיקרוגל לתחום הטלקום, השומר על קוהרנטיות קוונטית וטוב דיו כדי לשזור מעבדים מוליכי-על במקררים נפרדים; ב-2026 שום דבר אינו מתקרב לכך. |
| 9 חיבור בין-מודולי | ic_mcm | מודולים מרובי-שבבים / מצמדי l (אותו קריוסטט) | 13.9 | פיצול של מעבד מוליך-על בין כמה פיסות בתוך קריוסטט אחד, המחוברות בקישורי שבבונים בחיבורי בליטות או במצמדי l מוליכי-על באורך בסדר גודל של מטר. |
| 9 חיבור בין-מודולי | ic_cryolink | קישור מיקרוגל קריוגני בין מקררים | 11.9 | מוליך גל מוליך-על המוחזק מתחת ל-50 mK לכל אורכו, ונושא פוטונים נודדים של 5–7 GHz או מצבים סחוטים בין שני מקררי דילול המקוררים באופן בלתי תלוי. |
| 9 חיבור בין-מודולי | ic_ionphoton | קישור יון–פוטון | 10.9 | שזירה מבושרת בין יון לפוטון, דרך סיב אופטי, מחברת מלכודות יונים נפרדות למכונה אחת; הקצב הטוב ביותר שפורסם הוא 250 s⁻¹, מול צורך של ~10⁴ s⁻¹. |
| 9 חיבור בין-מודולי | ic_spinphoton | קישור ספין–פוטון במצב מוצק (SiV, NV, מרכז T) | 10.4 | שזירה פוטונית מבושרת בין אוגרי ספין מרוחקים במצב מוצק — מרכזי NV ו-SiV ביהלום, מרכזי T בצורן — דרך סיב טלקום פרוס. |
| 9 חיבור בין-מודולי | ic_atomcavity | ממשק אטום–פוטון במהוד | 9.2 | מהוד אופטי סביב אטומים ניטרליים הלכודים במלקחיים אופטיים מגביר את צימוד האטום–פוטון באמצעות אפקט פרסל, כך שאפשר לכתוב את מצב האטום על פוטון מעופף. |
| 9 חיבור בין-מודולי | ic_fanout | פיצול אותות קריוגני למערכי ספינים (פיסת נתב, חיווט תלת-ממדי מוערם) | 6.6 | פיסת נתב בטמפרטורת מיליקלווין, מרבב על הפיסה או חיווט תלת-ממדי מוערם, ההופכים קווי כניסה קרים ספורים לעשרות עד אלפי מתחי השער שמערך של קיוביטי ספין צריך. |
| 9 חיבור בין-מודולי | ic_multidie | זיווד מרובה-פיסות במודול אחד (flip-chip, פיסת בקרה בחיבור בליטות) | 5.8 | פיסת קיוביטים המחוברת בבליטות, פנים אל פנים, לפיסה מוליכת-על שנייה הנושאת חיווט, מהודים, חומר שני או לוגיקת בקרה, בתוך מארז אחד, על פני מרווח ואקום של מיקרומטרים ספורים עד ~20 µm. |
| 9 חיבור בין-מודולי | ic_fibre | קישורי סיב בין מודולים פוטוניים | 5.2 | סיב טלקום הנושא שזירה מבושרת בין שבבים ומסדים פוטוניים — מתומחר לפי מחבר, לא לפי מטר, ובלי קצב שפורסם. |
| 10 ייצור | fab_cmos | מפעל CMOS של 300 mm (ספינים, CMOS קריוגני, חיווט מוליך-על) | 17.9 | קווי CMOS תעשייתיים של 300 mm המייצרים קיוביטי ספין בנקודות קוונטיות, בקרי CMOS קריוגני וחיווט מוליך-על; מסלול ייצור הקיוביטים היחיד שיש לו סטטיסטיקה של שיעורי תקינות בקנה מידה של פרוסה. |
| 10 ייצור | fab_pic | מפעל ייצור למעגלים פוטוניים משולבים (SiN, BTO, TFLN, SNSPD על 300 mm) | 13.2 | זרימת תהליך במפעל CMOS המציבה על פרוסה אחת של 300 mm מוליכי גל מניטריד בעלי אובדן נמוך, מתגים אלקטרו-אופטיים, גלאי פוטון בודד וחיבור סיבים. |
| 10 ייצור | fab_sc | ליתוגרפיה של קיוביטים מוליכי-על (צמתי Al/AlOx/Al, חיווט Nb, 300 mm) | 11.1 | ליתוגרפיית צמתים של 300 mm וגיזום לאחר הייצור קובעים את פיזור התדרים שכל ארכיטקטורה של מוליכי-על יורשת. |
| 10 ייצור | fab_trap | ייצור מלכודות יונים (שבבי אלקטרודות משטח; מלכודות להבים תלת-ממדיות בעיבוד שבבי) | 10.9 | שבבי אלקטרודות RF/DC מישוריים הכולאים יונים ומסיעים אותם, הבנויים בקווי MEMS או, יותר ויותר, על פרוסות של מפעלי ייצור מסחריים למוליכים למחצה. |
| 10 ייצור | fab_optics | הרכבה אופטית / מכנית (לייזרים, ואקום, אובייקטיבים) | 8.7 | מחסנית הלייזרים, הוואקום העל-גבוה ואופטיקת הדימות הלוכדת, מקררת, ממענת וקוראת קיוביטים הן של יונים לכודים והן של אטומים ניטרליים — תשתית, לא קיוביט. |
| 10 ייצור | fab_3d | מהודים מוליכי-על תלת-ממדיים בעיבוד שבבי | 5.2 | גופי מהודים מאלומיניום או מניוביום בעיבוד שבבי ב-CNC, עם Q פנימי מעל 0.5×10⁹; הגוף בקנה מידה של cm לכל אופן הוא המחיר המבני של קודים בוזוניים מבוססי-מהוד. |
| 10 ייצור | fab_bulk | הרכבה של אופטיקה נפחית וסיבים (דוגמים פוטוניים) | 4.2 | מעבדים פוטוניים המורכבים מחלקים בדידים — מקורות סחיטה ואינטרפרומטרים במרחב חופשי, לולאות השהיה בסיב, מאפננים מצומדים לסיב וגלאי פוטון בודד קריוגניים — המיושרים והננעלים ידנית ובמערכות סרוו, ולא מיוצרים בתבנית ליתוגרפית על פרוסה. |
| 10 ייצור | fab_mbe | הטרו-מבנים III-V ב-MBE (תילי InAs–Pb, מקורות מנקודות קוונטיות) | 4.2 | אפיטקסיה בקרן מולקולרית של ננו-מבנים III-V עם מעטפות מוליך-על שהושקעו בלי לשבור את הוואקום, לתילי מיורנה, ושל נקודות קוונטיות למקורות פוטון בודד. |
| 10 ייצור | fab_diamond | גידול יהלום / השתלה (NV, SiV, SnV) | 1.7 | גידול יהלום חד-גבישי ב-CVD בפלזמה, השתלת יונים וריפוי ליצירת מרכזי NV, SiV או SnV, ואיכול תחתי לבניית הננו-פוטוניקה סביבם. |
| 10 ייצור | fab_stm | ליתוגרפיית מימן ב-STM (תורמים) | 1.7 | חוד של מיקרוסקופ מנהור סורק מסיר בדסורפציה את המימן מ-Si(100) שעבר פסיבציה וחושף אתרים בודדים, פוספין מסמם אותם, וצורן אפיטקסיאלי קובר את התורמים — בדיוק אטומי, באופן טורי וללא מקבילה במפעל ייצור. |
Trapped atomic ion
Single Yb⁺/Ba⁺/Ca⁺ ions in rf traps, entangled through shared motional modes; the highest-fidelity and slowest qubit in commercial service.
Verdict. Fidelity leader and the only platform running dozens of corrected logical qubits, but throughput is set by transport and cooling, not gates; 2D scaling unproven until Sol (2027).
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A trapped-ion qubit is a single atomic ion — ytterbium, barium, calcium or strontium — confined by rf and static fields above microfabricated electrodes, with logic in hyperfine, Zeeman or optical levels. Ions in a chain repel, so they share quantised motional modes; a spin-dependent force on those modes turns motion into a bus that entangles any pair. Cirac and Zoller proposed it in 1995; Wineland's NIST group demonstrated the first gate the same year, between one ion's internal state and its motion, and two-ion gates followed in 1998–2003. Everything commercial today is that idea plus surface-electrode microfabrication.
Attributes (technology graph): carrier affinity 0.0 — wholly natural, every ion identical by physical law, no fabrication variance to calibrate out; entangling time ≈ 63 µs (10^−4.2 s), deterministic, no heralding; readout by fluorescence on a cycling transition, ≈ 10 µs, non-destructive, mid-circuit capable; mobility by physical transport — ions are shuttled, not wired; control optical, at room temperature; error structure as the code sees it coherent, leakage, Pauli; manufacturing MEMS-class surface-electrode traps.
Physics & limits
Trap frequencies of a few MHz set the clock. Spin–motion coupling scales with the Lamb–Dicke parameter times the drive, so a gate much faster than a motional period either excites the wrong modes or needs optical power that reintroduces scattering; µs-to-hundreds-of-µs gates are a physical compromise, not an engineering lapse. Memory is the opposite: in magnetically insensitive clock states one ion holds coherence beyond an hour D[104], five to six orders longer than a superconducting qubit. Idle error is nearly free; idle time is what costs.
The floor belongs to the drive, not the carrier: laser gates carry an irreducible spontaneous-emission floor, and 8.4(7)×10⁻⁵ two-qubit error at Doppler temperature without ground-state cooling D[102] shows it is removable. What remains is anomalous heating from electrode surfaces, mode crowding as chains lengthen, and background-gas collisions that reorder or eject a chain. That last is the architectural problem: a decoder built for stochastic Pauli noise instead sees ions leak into metastable manifolds or vanish. Leakage is small enough to quote — 1.1×10⁻⁵ per Clifford on Helios D[97] — but quoted separately because it is not Pauli. Cryogenic traps, sympathetic cooling, metastable erasure encodings and better vacuum would move the floor.
Engineering state of the art
Best-demonstrated and typical-at-scale have converged unusually far: Helios runs 98 Ba⁺ qubits at 7.9×10⁻⁴ two-qubit error with all-to-all connectivity, within an order of magnitude of the record. The gap is speed — the gate is ≈ 70 µs, but a full-width layer takes ≈ 55 ms once sorting, transport and re-cooling are counted; transport was ~60% of runtime on H2 D[97], [110].
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-07 | All-electronic control, 10 qubits / 7 zones: 2Q 99.97(1)% | Oxford Ionics | D[257]fact |
| 2025-10 | 2Q error 8.4(7)×10⁻⁵, no ground-state cooling | Oxford Ionics / IonQ | D[102]fact |
| 2025-11 | Helios 98 Ba⁺: 2Q 7.9×10⁻⁴, SPAM 3.3–4.8×10⁻⁴, leakage 1.1×10⁻⁵/Clifford | Quantinuum | D[97] |
| 2026-02 | 48 corrected logical qubits ([[80,48,4]]), logical gate infidelity 1.0–1.2×10⁻⁴ | Quantinuum | D[105]fact |
| 2026-05 | Quantum volume 32,768, rack-mounted LYNX | AQT | C[128] |
| 2026-06 | qLDPC memory break-even within error bars: 3.95 ± 0.68 s (one code) vs 3.84 ± 0.48 s physical (revised Sep 2026) | IonQ | D[109]fact |
The dominant error term at scale is not the gate: it is the cost of moving ions — transport excitation, re-cooling, re-ordering — plus leakage the decoder cannot absorb. High-rate code demonstrations discard 75–97% of shots at depth D[105].
Manufacturing, materials & supply chain
Traps are MEMS-class silicon parts, not qubit-defining lithography: the ion is perfect, so wafer variance shows up as electrode geometry and surface quality, never as qubit-to-qubit spread. Two fabs matter. Infineon runs a dedicated QPU platform in Villach on 6- to 12-inch wafers with anodic wafer bonding; its Generation-3 traps add out-of-plane electrodes claimed to raise confinement ~10×, with eleQtron (three generations), Oxford Ionics, Innsbruck and ETH Zürich as named users C[320]. Honeywell fabricates Quantinuum's traps in-house — Helios carries 1,228 electrodes D[97] — and the Sol grid trap is back from fabrication and in validation C[123]; Infineon separately partnered with Quantinuum on next-generation traps in 2024-11 C[321]. Infineon is a single point of failure for IonQ/Oxford Ionics, eleQtron and Universal Quantum at once P[322] — which is what IonQ's ≈ $1.8 B purchase of SkyWater (closed 2026-07-31) buys its way out of C[19].
The second concentration is optical: TOPTICA (> €140 M revenue, ~600 staff) supplies most major ion experiments, and the UV end — 369 nm for Yb⁺ — is the constrained part P[322]. Vacuum hardware and atomic sources are commodity; photonic interconnects re-import a cryogenic dependency through SNSPDs P[322]fact. Unit economics: AQT delivered a 20-qubit rack to LRZ / Munich Quantum Valley for ≈ €9.8 M (2023-12-05, Bavarian Hightech Agenda) C[323] — ≈ €0.5 M per qubit, turnkey. Export exposure runs through the September-2024 US quantum ECCNs; a bare trap chip's classification is unverified here.
Control, readout & I/O burden
Per-ion optical addressing is what fails to scale linearly: Helios needs at least seven laser wavelengths alongside 1,228 electrode drives D[97]. Readout is cheap — fluorescence onto a PMT or camera in ≈ 10 µs, non-destructive and natively mid-circuit. Latency demands are mild: IonQ assumes 1–5 ms syndrome cycles D[111], inside NVQLink-class round trips C[324]fact.
The wall moves with N. At 10³ it is drive-source count and optical-table area; the WISE study argues a fully connected 1,000-ion machine could run from ~200 sources with in-trap switching electronics, at 40–2,600 gate layers per second S[325]fact — paper design, no chip built. At 10⁴ it is inter-module: remote entanglement stands at 9.7 s⁻¹ over 2 m (Bell 96.9%) D[115] and 250 s⁻¹ in a lab D[116] against ~10⁴ s⁻¹ needed. At 10⁶ it is yield and laser power. Gate generation and microwave control belong to the sibling briefs.
Role in the stack
The carrier feeds three architectures, as the primary carrier of each: Trapped ions — QCCD (transport between zones) (Quantinuum, Universal Quantum), Trapped ions — linear Paul trap with individual laser addressing (IonQ's Aria, Forte and Tempo; AQT; Qudoor; Quantum Art) and Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (IonQ/Oxford Ionics, eleQtron, QUDORA). It requires surface-electrode trap microfabrication and optical/mechanical assembly, and is the substrate for the Mølmer–Sørensen gate, the electronic near-field microwave gate, metastable "omg" erasure encoding, shuttling, fluorescence detection and the ion–photon link. It replaces and conflicts with nothing: ions are a self-contained column, which is why switching away is total — nothing above the carrier survives but the compiler.
Derived clock = sum of the syndrome round: gate layers + transport + readout + reset. On the QCCD architecture transport dominates: ≈ 9.7×10⁻³ s per round, 9.0 ms of it transport, against a ≈ 5.5×10⁻² s full-width layer D[97], [110]. On the electronic-gate architecture the round is ≈ 1.5×10⁻³ s, set by the gate layers D[102]. That six-fold gap is the platform's defining number. Neighbouring empty slot: a cryogenic chip-integrated drive layer for ion traps — the SFQ/cryo-CMOS analogue — has no product-scale occupant.
Evidence — how the numbers were measured
Headline two-qubit numbers come from randomised-benchmarking variants. The 8.4(7)×10⁻⁵ record is a subspace-leakage RB on one ion pair at Doppler temperature, not a device-wide figure, and the retrievable text gives no gate duration D[102]. Helios's 7.9×10⁻⁴ is an averaged device figure, consistent with the earnings language "99.921%" C[123]. Quantum volume and #AQ are vendor-defined composites with no replication protocol C[98], [99]. RB also runs statically, so shuttling and re-cooling are invisible to quoted gate errors. Logical results carry an acceptance fraction (0.62(2) D[105]) and IonQ's break-even is leakage-post-selected D[109]; neither is unconditional. No ion platform has published Λ-type distance scaling.
Conflicts. The electronic gate's duration is 225.8 µs (2025) or ≈ 120 µs (2024) in the technology graph and unstated in the 2025 abstract — unverified. Quantinuum's "near five-nines logical fidelity with a novel QEC code family" C[123] outruns the published 1.0–1.2×10⁻⁴ logical gate infidelity D[105]; the code family is unpublished, so the D value stands. IonQ's Tempo is marketed at "99.9%" and #AQ 64 with no published gate times C[99], [326].
The main report gives IonQ Forte's Mølmer–Sørensen gate times on 30+-ion chains (550–883 µs, median 672 µs; single-qubit 110 µs) without a numbered source. Not published: the export-control classification of a bare, un-populated ion-trap chip under the September-2024 US quantum ECCNs (4A906 family) and allied national controls; any funding amount, date, valuation or qubit count for Qudoor (AbaQ, 32+ claimed patents), the only Chinese ion-trap vendor named in 2026 sources; any delivery, milestone or fidelity result against Universal Quantum's €67 M DLR contract as of 2026-09-03; an equity round with a stated amount and date for AQT or QUDORA Technologies (Braunschweig; Tokyo subsidiary opened 2026-05); and Quantinuum's bookings, backlog, Helios unit sales or customer names, absent from its Q2-2026 release.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US/UK | QCCD laser gates; Helios 98 q, 48 logical qubits; Sol, Apollo | D[105] |
| IonQ | developer | US | Long chains plus Oxford Ionics electronic gates; qLDPC break-even; owns SkyWater | D[109] |
| Honeywell | supplier | US | In-house MEMS fabrication of Quantinuum traps; anchor shareholder | C[122] |
| Infineon Technologies | supplier | AT/DE | Merchant ion-trap foundry, Villach, 6–12″, Gen-3 traps | C[320] |
| AQT | developer | AT | Rack-mounted 19″ ion systems; QV 32,768; LRZ installation | C[323] |
| eleQtron | developer | DE | Microwave ion control; DLR QSea I demonstrator; €54 M backlog | G[327] |
| Quantum Art | developer | IL | Multi-core trapped-ion architecture; $140 M Series A | P[125] |
| Universal Quantum | developer | UK | Modular trap machine under a €67 M DLR contract; nothing delivered | P[328] |
| Tsinghua University | research | CN | 512-ion 2D crystal analogue simulation; hour-scale memory | D[121] |
| Qudoor | developer | CN | AbaQ ion-trap systems and cloud; 32+ claimed patents | P[302] |
Money.
- 2022-11-02 · Universal Quantum · DLR contract · €67 M · announced P[328]fact
- 2023-12-05 · AQT · contract, 20-qubit system for LRZ · ≈ €9.8 M · Bavarian StMWK/StMWi · closed C[323]
- 2025-11-06 · IonQ, Quantinuum · DARPA QBI Stage B · up to $15 M each · selected G[65]fact
- 2025-10-12 · IonQ · equity · $1.0 B + $2.0 B at $93/share · closed fact
- 2025-09-04 · Quantinuum · round · $600 M at $10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed G[122]fact
- 2025-09-17 · IonQ · M&A Oxford Ionics · $1.075 B · closed C[18]fact
- 2026-04-27 · Quantum Art · Series A extension · $100 M → $140 M · closed P[125]fact
- 2026-05-05 · eleQtron · Series A · €57 M · backlog €54 M · closed C[128]fact
- 2026-06-03 · Quantinuum · IPO, Nasdaq QNT · $1.68 B gross at $60/share · closed G[123]fact
- 2026-07-31 · IonQ · M&A SkyWater · ≈ $1.8 B · closed C[19]fact
- 2026-06-30 · Q2 FY26 revenue · Quantinuum $8.0 M, cash $2.1 B, guidance $28–32 M; IonQ $80.1 M, cash $3.0 B, guidance $280–290 M C[123], [326]
Market & supply chain. Equipment money sits with TOPTICA, Infineon and commodity vacuum vendors; concentration risk is real in two places only — UV lasers and Infineon's fab, which underpins three otherwise-independent developers P[322]. Against ≈ €9.8 M for a 20-qubit rack C[323], sector ion revenue is about one large system per quarter plus cloud access. Goals that pay: G1 (Tsinghua's simulator), G2 and G5 (cloud), G3 (Helios logical qubits, IonQ's qLDPC memory), G7 (AQT racks, eleQtron's backlog), G6 in prototype. G4 is funded by capital markets and DARPA, not customers.
IP & standards. Named families: Oxford Ionics' electronic qubit control and the WISE in-trap switching architecture S[325]; Honeywell/Quantinuum QCCD junction and grid-trap patents behind 2.5 kHz ion exchange and 4 m/s transport D[113]; Infineon's anodic-bonding 3D-electrode process C[320]; ID Quantique's detector portfolio, now IonQ's C[19]. No dated ion-specific patent count from a named database was found; PatSnap's landscape published on 2026-06-30 counts 546 quantum patent families for IonQ, eighth among assignees, but breaks out no trapped-ion line Pfact. No ion-specific standard exists.
Roadmaps & track record. Quantinuum: Helios (promised 2024-09-10 · for 2025 · launched 2025-11-05) fact; Sol (promised 2024-09-10 · for 2027 · trap chip fabricated, in validation); Apollo (for 2029 · "on schedule", prototypes only) C[123]. Credibility high — promised dates met — except the unpublished five-nines code family. IonQ: 4,000 qubits (promised 2020 · for 2026 · missed ~40×) P[132]; 256 qubits at 99.99% (promised 2025-06-13 · for 2026 · slipped to H1 2027) R[132]; 10,000 on one chip (for 2027 · no published 2D-trap heating or interconnect data). Credibility mixed: the physics is peer-reviewable, the schedules are not. AQT delivers its QV records on time; Universal Quantum has announced nothing against its 2022 contract P[328].
Strategic reading. If ions win, Honeywell and Infineon capture structural rent — one through vertical integration nobody can copy, the other as the only merchant trap fab — and TOPTICA becomes the choke point. IonQ's SkyWater purchase converts a supplier dependency into an owned asset: a bet that trap fabrication, not qubit physics, is the scarce input. The substitution threat is not superconducting circuits (faster clock, worse fidelity) but neutral atoms: same natural carrier, same optics-heavy engineering, thousands of sites already, fidelity closing. Bargaining power still sits with the platform vendors: Infineon's quantum unit is a rounding error inside a €15 B company P[322] and cannot price like a monopolist.
Outlook & open questions
Confirm if: Sol ships in 2027 with ≥ 192 physical qubits on a 2D grid trap and a published layer time better than ≈ 55 ms; any ion vendor publishes Λ > 1 scaling across d=3→5→7; remote entanglement passes 10³ s⁻¹. Demote if: IonQ has not shown 256 qubits at 99.99% by end-2027 (already slipped once); Sol leaves layer time unimproved; or the five-nines code family stays unpublished a year on.
Best case by 2029: Apollo lands with hundreds of logical qubits at 10⁻⁶–10⁻¹⁰ and ions own early fault tolerance, the clock deficit absorbed by depth-hungry algorithms. Worst case: 2D scaling multiplies transport cost instead of amortising it, layer time stays in tens of milliseconds, and ions become the high-fidelity low-throughput instrument for QEC research while neutral atoms and superconducting circuits take the volume.
Open questions: does grid-trap heating scale with zone count or electrode area? Can leakage be turned into erasure fast enough that decoders stop paying for it? What is the electronic gate's real duration at full width? Is 10⁴ s⁻¹ remote entanglement reachable at all? Who second-sources Infineon?
References
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Русский текст загружается…
הטקסט בעברית נטען…
Transmon
Capacitively shunted Josephson junction (Koch 2007); the carrier behind Willow, Heron/Nighthawk and Zuchongzhi, with the fastest deterministic gate and QEC cycle of any demonstrated qubit.
Verdict. Best-funded and fastest carrier, capped by ~10⁻³ two-qubit and ~10⁻² readout errors at scale and hourly correlated bursts. Confirm if a ≥100-qubit lattice shows Λ ≥ 3 with median 2Q error < 10⁻³ by 2028; otherwise demote to component status.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A transmon is an Al/AlOx/Al Josephson junction shunted by a large capacitor so that EJ/E_C ≈ 50–100 D[282]. Charge dispersion falls exponentially in √(8E_J/E_C), removing 1/f charge noise at the price of a weak anharmonicity α ≈ −EC ≈ −200 to −300 MHz; the qubit is the lowest two levels of a 4–6 GHz oscillator D[282]. Koch et al. proposed it in 2007 D[282]; the 3D transmon (2011) D[283] and the UCSB/Google Xmon (2014) D[284] fixed the two lineages still in use, fixed-frequency (IBM) and flux-tunable (Google, IQM, USTC).
Attributes (technology graph):
- a: affinity 1.0, fabricated (no natural counterpart).
- b: characteristic time 10⁻⁸ s, deterministic entangling; the 1/α leakage bound puts the pulse floor near 10 ns.
- c: readout dispersive microwave, ≈ 320 ns (10^−6.5 s), non-destructive, mid-circuit capable.
- d: mobility static, nearest-neighbour wiring.
- e: control microwave from room-temperature electronics; cold-stage variants (cryo-CMOS or SFQ) at ≤ 5 qubits.
- f: error structure leakage + stochastic Pauli + correlated bursts + coherent/calibration.
- g: manufacturing superconducting lithography.
Physics & limits
Residual thermal population (0.1% at 35 mK in a 3D transmon D[285], ≈ 1% at 40–60 mK for a 5 GHz qubit S[285]) makes reset and readout the SPAM floor. Anharmonicity bounds single-qubit gates at 10–25 ns and tunable-coupler CZ at 25–50 ns D[1], [37]P[286]; cross-resonance takes ≈ 200–500 ns D[287].
The floor is decoherence over gate time: with Willow's mean T1 = 68 µs D[1] a 40 ns CZ carries ≈ 6×10⁻⁴ of incoherent error S[1]; at the record T1 = 1.68 ms of a single Ta-on-Si test transmon D[288] it falls below 5×10⁻⁵ S[288]. Loss is dominated by two-level systems (TLS) in amorphous interface oxides D[288], with quasiparticles, Purcell decay and flux noise below.
Most of the twirled channel is stochastic Pauli, so Willow's Λ = 2.14 D[1] matches theory. Leakage to |2⟩ accumulates under QEC unless removed each cycle (USTC's all-microwave reset cut it 72×, to 6.4×10⁻⁴, on 107 qubits D[3]). Coherent errors (residual ZZ, TLS drift) forced reinforcement-learning recalibration inside Google's 2026-07 QEC run D[2]. Correlated bursts (ionising particles flooding the chip with quasiparticles) hit all qubits at once — roughly one per 10 s on Sycamore in 2021 D[289], about one per hour on Willow after gap engineering D[1], [290] — truncating long memory runs by bursts, not distance. Moving the floor means new materials (Ta, encapsulated Nb), fluxonium-scale anharmonicity, radiation management or erasure conversion (dual-rail).
Long-lived TLS are not specific to fluxonium junction chains: a flux-tunable transmon at Forschungszentrum Jülich showed 44 of them per GHz, spread uniformly over 3–4.5 GHz and each blocking about 2 MHz, so about 9% of the tunable band is affected; the memory they give the environment spans 20 µs to 1 ms, and 58% of them outlive the qubit P[890]. Energy stored in them re-excites the qubit after it is driven, an error that T1 and relaxation spectroscopy do not show.
Engineering state of the art
Best isolated devices: T1 1.68 ms, Q 2.5×10⁷, 1Q 99.994% D[288]; CZ 99.93% and 280 ns readout at 99.94% on a two-qubit IQM chip D[38]; Toshiba's double-transmon coupler CZ 99.90% in 48 ns D[37].
Typical at ≥ 100 qubits: Willow, 105 q — mean T1 68 µs, CZ error 0.33%, readout 99.5%, QEC cycle 1.1 µs D[1]C[32]; IBM fleet error-per-layered-gate 3.7×10⁻³ typical, 1.9×10⁻³ best (2026-07) C[34]; Zuchongzhi 3.0, 105 q — 2Q 99.62%, readout 99.13% D[35]; Rigetti Cepheus-1-108Q, twelve 9-qubit chiplets C[36] — median 2Q 99.1% Cfact.
table
At scale the two-qubit gate is the largest error term (~40% of Google's colour-code budget) D[41], then readout (~10⁻² on fleets C[34]) and leakage; the lattice tail matters more than the median.
Manufacturing, materials & supply chain
Process: Nb or Ta on high-resistivity Si or sapphire; shadow-evaporated Al/AlOx/Al junctions; flip-chip 3D integration. On 300 mm CMOS tooling imec/KU Leuven reported 393 of 400 working transmons (98.25%), median T1 ≈ 75 µs (42–113 µs) D[293]fact: uniformity, not coherence. Fixed-frequency lattices must also hit frequency targets (junction scatter becomes collisions) by laser annealing (IBM), alternating-bias annealing (Rigetti, 97.4% success) D[294] or tunable couplers.
Cost and energy: no vendor publishes $/qubit; proxies are IQM's €33 M LUMI contract P[295] and IBM's 14 nm cryo-controller at 23 mW per qubit at 4 K D[296] — tens of watts at 10³ qubits; SFQ control claims nW per qubit C[54].
Supply chain: dilution refrigerators from Bluefors (FI), Oxford Instruments (UK), FormFactor and Maybell (US); ³He from tritium decay in state inventories (US: NNSA G[297]), no merchant producer; 4 K HEMT (high-electron-mobility transistor) amplifiers effectively one vendor (Low Noise Factory, SE); control electronics competitive (Quantum Machines, Qblox, Zurich Instruments); merchant QPUs from QuantWare (NL) P[298]; foundries Anderon (IBM Albany spin-off, 2026-05; $1 B CHIPS letter of intent, $1 B IBM cash stated separately) P[299]G[300] and GlobalFoundries ($375 M LOI) G[300].
Export controls: the BIS interim final rule of 2024-09-06 covers dilution refrigerators ≥ 600 µW at 0.1 K for 48 h (3A904), cryogenic wafer probers (3B904), parametric amplifiers (3A901.b) and quantum computers (4A906) only where qubit count and C-NOT error fall in the same band — 34–99 qubits at ≤ 10⁻⁴, 100–199 at ≤ 10⁻³, the ceiling rising to 6 × 10⁻³ below 2,000 qubits, any error from 2,000 on G[301]fact; Chinese vendors therefore build 10 mK refrigerators domestically (2026-05-15) P[302].
Control, readout & I/O burden
A tunable lattice needs one XY and one Z line per qubit plus one per coupler (Sycamore: ≈ 3.6 control lines per qubit before readout D[291]); readout multiplexes ≈ 6–10 qubits per feedline D[1]; each line is a DAC channel plus attenuated coax, so cost and heat scale with N.
Latency: the QEC cycle is 1.1 µs; Google's real-time decoder ran at 63 µs mean latency for d=5 D[1]; IBM's Relay-BP targets < 1 µs per cycle in simulation S[48] for the gross code (IBM's [[144,12,12]] bivariate bicycle qLDPC code, 12 logical qubits in 288 physical D[248]).
Walls: 10³ reached (Condor, 1,121 qubits C[292]); Bluefors' KIDE (> 4,000 RF lines, > 1,000 qubits; product page, 2026-06) C[303] is one cryostat's ceiling. 10⁴ needs 4 K cryo-CMOS (HRL: d=5 repetition code from a ≤ 3.5 W controller D[190]fact) or millikelvin SFQ (SEEQC: 1Q up to 99.9% on ≤ 5 qubits D[304]fact) plus multi-cryostat modules (IBM coupled two cells, 2026-08 C[50]). 10⁶ has no closed design: on-chip flux DACs, cold decoding and inter-fridge links (ETH: 30 m at 80.4% Bell fidelity D[305]) are sub-scale.
Role in the stack
Architectures: the transmon lattice with tunable couplers and the dual-rail erasure architecture (transmon as ancilla or one rail). Requires superconducting lithography; provides the carrier for tunable-coupler and cross-resonance gates, the ancilla for bosonic-cavity gates, the bare-qubit subspace, the dispersive shift for microwave readout and the microwave side of the optical transducer. Replaced by fluxonium, which buys anharmonicity and T1 for a flux bias per qubit, sub-GHz control and redesigned readout. Conflicts with SFQ control: switching photons poisoned qubits with quasiparticles in the 2023 multi-chip module (0.96 of 1.2% error per Clifford) D[249]; SEEQC claims it engineered away C[54], so the conflict stands until an independent lattice-scale check. Derived clock of the transmon-lattice architecture ≈ 6.5×10⁻⁷ s (651 ns; derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture), readout 282 ns of it and readout-plus-reset two-thirds, against the measured 1.1 µs Willow cycle D[1] — the fastest demonstrated architecture, which G4 (large-scale fault tolerance) pays for. Bordering empty slots: the microwave–optical transducer (≈ 3 orders of magnitude short of remote gates S[306]) and cryogenic decoding.
Evidence — how the numbers were measured
Headline numbers come from Clifford RB/IRB, simultaneous XEB (Google), IBM's layer fidelity/EPLG and readout assignment matrices; Λ is a fit of logical error vs distance under one decoder. Missed here: isolated vs simultaneous operation (record chips are isolated); coherent errors averaged into a depolarising number; leakage, invisible to RB and often post-selected away; drift between calibration and use; and conventions (Rigetti quotes medians, IBM its best device, IQM a two-qubit chip). IBM's 2026-07 "70 logical qubits" is an error-detecting, post-selected result D[46], not fault tolerance.
Replication: below-threshold scaling reproduced by USTC on 107 qubits with Λ = 1.40 D[3]. Disputes: 2019 supremacy sampling reproduced by tensor networks D[307]; the 2023 IBM "utility" experiment simulated classically within weeks D[308], [309]; Google's 2026-07 paper reports no Λ for the d=7 run D[2]. Value conflict: imec's 300 mm T1 is often quoted as "> 100 µs"; the paper's median is ≈ 75 µs D[293]fact, used here.
The ≈ 200–500 ns cross-resonance gate time is a fleet-typical range inferred from a single-device paper [287]. That 4 K HEMT amplifiers come effectively from one vendor (Low Noise Factory) is a market observation without a database source. Not published: a launch date for Bluefors KIDE (> 4,000 RF lines / > 1,000 qubits), whose product page was revised 2026-06-16.
Actors & economics
Who.
| Organisation | Role | Country | Activity | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | Willow 105 q, Λ = 2.14; d=7 memory | D[1], [2] |
| IBM | developer | US | Heron/Nighthawk fleet; Starling roadmap; Anderon spin-out | C[34], [67]P[299] |
| Rigetti | developer | US | Cepheus-1-108Q chiplets; own fab | C[61] |
| IQM | developer | FI | 26 systems sold, 17 installed | C[58]fact |
| USTC | research | CN | Zuchongzhi 3.x, 105 q; Λ = 1.40 | D[3], [35] |
Money.
- 2025-11-06 · DARPA · QBI Stage B (up to $15 M each) · IBM the only transmon-lattice vendor of eleven; Google and Rigetti stayed at Stage A G[65]factfact
- 2026-01-20 · D-Wave · M&A, Quantum Circuits (dual-rail cavities on transmon ancillae) · $550 M (stock + cash) · closed C[14]factfact
- 2026-05-05 · QuantWare (merchant QPUs; VIO-40K roadmap — VIO is its vertical-wiring architecture Rfact) · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners (new investors, no lead) · > $210 M cumulative · closed P[298]
- 2026-05-18 · Nord Quantique · growth-equity financing · $30 M at a $1.4 B valuation · closed C[89]fact
- 2026-05-21 · US Dept of Commerce · CHIPS letters of intent ($2.013 B, nine companies) · IBM/Anderon $1 B, GlobalFoundries $375 M, Rigetti ≤ $100 M, D-Wave $100 M · non-binding LOI G[300]fact
- 2026-06-02 · IBM · commitment · > $10 B over five years, the $1 B cash into Anderon stated separately · announced C[310]fact
- 2026-06-03 · OQC (coaxmon developer D[311]) · Series C · £260 M (~$350 M) · led by Bullhound · valuation undisclosed · closed C[60]fact
- 2026-07-02 · IQM · listing, Nasdaq and Helsinki · pro-forma cash €337 M · closed Cfact
- 2026-08-04 · IQM · H1-2026 results · revenue €8.9 M (+47%), cash €309 M · reported P[295]
- 2026-08-06 · Rigetti · Q2-2026 results · revenue $5.1 M, GAAP loss $52.6 M, cash $541.3 M · reported C[61]
Market & supply chain. Enabling equipment is more concentrated than the QPU market. Unit economics are unpublished; the €33 M IQM contract P[295] and the $550 M Quantum Circuits price Cfact are the only quotable points. Paying goals: G7 (deployable systems) and G2 (error-mitigated utility) today; G3 (early fault tolerance) via QBI-style programmes from 2027 fact; G4 (large-scale fault tolerance) after 2029 Rfact; G1 (analogue simulation), G5 (optimisation) and G6 (networking) bring no transmon-specific revenue.
IP & standards. PatSnap's landscape published on 2026-06-30: IBM 4,388 quantum patent families, Google 2,385, Microsoft 1,175; superconducting devices (H10N 60) IBM 783, Google 357 P[312]fact. No litigation found; no transmon-specific family verified. Open stacks commoditise the layer above: Qiskit (IBM claims ≈ 70% of developers C[310]), Cirq/Stim, OpenQASM 3, NVQLink Cfact.
Roadmaps & track record.
- IBM Kookaburra (2022-05-10 · 2025, as a 1,386-qubit multi-chip processor C[313]; re-promised 2025-06-10 · 2026, as the first qLDPC module R[67] · not delivered as of 2026-09-03 R[72]fact).
- IBM Nighthawk (2025-06-10 · 2025 · delivered 2025-12) and Starling (2025-06-10 · 2029, 200 logical / 10⁸ gates · open) Rfact.
- Google milestone 3, 10⁻⁶ logical error (undated · no Willow successor published; neutral-atom track opened 2026-03-24) R[2]fact.
- Rigetti 108 q at 99.5% (promised for end-2025 · GA 2026-04-07 at median 99.1%; 99.5% moved to "later 2026") Cfact.
- Fujitsu/RIKEN 1,000 qubits (promised 2025-04-22 · fiscal 2026 · not launched as of 2026-09-03) R[75]fact.
Credibility: IBM high on cadence, weak on its first qLDPC module and on "advantage" claims; Google high on physics, opaque on schedule; Rigetti chronic slips; Fujitsu unproven.
Strategic reading. If transmons win, foundry owners and cryogenic suppliers win regardless of vendor; fabless transmon start-ups lose — consolidation (Atlantic Quantum → Google, 2025-10-03 P[55]fact; Quantum Circuits → D-Wave) is visible. Substitution threats: fluxonium in the same fab, dual-rail/bosonic encodings that demote the transmon to an ancilla, atoms and spins for density. ³He, HEMT and fridge suppliers hold bargaining power; platform vendors escape by vertical integration.
Outlook & open questions
Milestones, 12–24 months: (1) Kookaburra runs a gross-code memory below break-even — confirm; nothing by end-2027 demotes IBM's 2029 date Rfact. (2) Google publishes Λ ≥ 3 or a 10⁻⁶ logical memory at d ≥ 9 — confirm; a second year without a Willow successor demotes D[2]. (3) QBI Stage C (expected around Q4 2026 factP[314]) promotes a transmon vendor. (4) cryo-CMOS or SFQ drives ≥ 50 transmons without a fidelity penalty D[190], [304]. Best case 2029: a Starling-class 200-logical machine Rfact and a d ≥ 11 Google memory; worst: Λ near 2, readout at 10⁻², bursts cap distance, the transmon survives only as an ancilla and capital rotates to atoms and spins. Open questions: does millisecond Ta/Si coherence survive a 100-qubit process with couplers; is the at-scale 2Q floor coherent (calibration) or incoherent; can readout reach 10⁻³ in < 300 ns across a lattice. Watch: Google's next paper, Kookaburra, the Stage C list.
References
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Русский текст загружается…
הטקסט בעברית נטען…
Majorana parity (InAs–Pb tetron)
Fermion parity stored non-locally in a gate-defined semiconductor–superconductor wire pair; only single-wire parity readout has been measured.
Verdict. No topological qubit exists as of 2026-09-03: one measured basis, no X-basis lifetime, no two-qubit operation, no independent replication of the topological claim.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The carrier is the total fermion parity of two hybrid semiconductor–superconductor nanowires (a "tetron"), intended to be held non-locally in Majorana zero modes (MZMs) at the wire ends and so inaccessible to local perturbation. Kitaev proposed the one-dimensional p-wave chain in 2001; the Lutchyn–Oreg proximitised-nanowire recipe (2010) is what every device since has tried to realise; Microsoft's measurement-based architecture, where logic is parity measurement rather than braiding, is what these devices serve. Nothing in the record establishes that the measured parity is topologically protected.
Attributes (technology graph):
- a — affinity: fully fabricated (1.0); the object does not exist until an MBE stack and a gate pattern create it.
- b — characteristic time ≈ 1 µs; entangling operation deterministic (measurement-based, not heralded).
- c — readout: rf quantum-capacitance parity detection, ~100 µs, non-destructive, mid-circuit capable.
- d — mobility: static; the carrier is not transported.
- e — control: low-frequency gate voltages, electronics at room temperature.
- f — dominant error structure: unknown as the code sees it; no error model measured on a working qubit.
- g — manufacturing: molecular beam epitaxy (MBE) of III-V heterostructures.
Physics & limits
The intended floor is exponential: a parity error requires a quasiparticle to cross between MZMs separated by many coherence lengths, so the rate should fall as exp(−L/ξ). That is the argument, not the demonstration. Two scales govern the devices: the induced gap, which sets the thermal quasiparticle population and is why lead replaced aluminium; and the hybridisation splitting, resolved on InAs–Pb to µeV precision from h/2e-periodic quantum-capacitance shifts C[21].
Failure modes divide into quasiparticle poisoning — one unpaired fermion entering the island flips parity, which is what the ~20 s figure bounds — and dephasing between parity states, which is what an X loop measures. The published asymmetry is the whole story: Z loop 12.4 ms against X loop 14.5 µs, roughly 1000× shorter D[20]. Long Z with short X is equally consistent with a well-isolated charge island and says nothing about topology. With no X loop re-measured on InAs–Pb, the physics that would move the floor — larger gap, lower disorder, longer wires — stays untested against the only discriminating observable.
Engineering state of the art
Best demonstrated, 2026-06-02: a characteristic parity switching time of ~20 s, "with some instances reaching minute-scale", by interferometric single-shot parity measurement on one hybrid nanowire of one tetron in a multi-tetron array, InAs–Pb C[21]. Typical at scale does not exist: no array yield, no assignment error, no X-loop lifetime, no two-qubit operation, no entanglement, no Bell test, no qubit T1/T2 C[21]fact. Microsoft's blog calls the 20 s a "qubit lifetime"; the preprint claims a parity lifetime in one wire C[215].
Records timeline
| Date | Figure | Who | Tag+key |
|---|---|---|---|
| 2018-03-28, retracted 2021-03-08 | quantised 2e²/h Majorana conductance; recalibration moved plateaus 8%, points fell outside 2σ | Zhang et al. (Delft, Eindhoven, Microsoft) | D[365] |
| 2023-03-01 | e/4 interference with the predicted even–odd effect at ν=5/2 and ν=7/2 | Nokia Bell Labs, PRX 13, 011028 | D[366] |
| 2025-02 | single-shot parity readout, 1% assignment error, ms dwell times, InAs–Al | Microsoft, Nature | D[13] |
| 2025-07 | tetron Z loop 12.4 ms vs X loop 14.5 µs | Microsoft, preprint | D[20] |
| 2026 | Kitaev-chain parity readout > 1 ms | QuTech, Nature | D[216] |
| 2026-06-02 | ~20 s parity switching, one wire of one InAs–Pb tetron | Microsoft, preprint | C[21] |
| 2026-07-10 | coherent parity oscillations in coupled minimal Kitaev chains, "limited protection" | QuTech, preprint | D[217] |
Dominant term of the error budget: unquantified. The only channel with a measured rate is the Z-basis parity flip; no budget attributing the X/Z ratio to disorder, hybridisation or readout back-action has been published.
Manufacturing, materials & supply chain
The stack is MBE-grown InAs with an in-situ superconductor — now lead — patterned into tetrons by electrostatic gates. It is the least manufacturable process in the carrier layer: MBE throughput is wafers per day; the semiconductor–superconductor interface determines yield and has no published in-line metric; and the device is defined by gate tuning, so "yield" means the fraction of gate settings passing a screen — the contested Topological Gap Protocol [22].
No yield, uniformity, cost- or energy-per-qubit figure has been published for any Majorana device as of 2026-09-03. Microsoft moved fabrication capacity to Lyngby, Denmark, where the November 2025 opening was reported as enabling "the full fabrication of the Majorana chip core in Denmark", against cumulative Danish quantum-infrastructure investment above DKK 1 bn (≈ USD 156 M) P[367]. GlobalFoundries lists topological among the modalities its Quantum Technology Solutions unit serves, with Microsoft Quantum named, but gives no wafer size, node or fab C[353]fact — a captive research fab, not a foundry flow. Single points of failure: MBE tool supply, III-V source material, and the concentration of tetron know-how in one company and two university groups. No ECCN specific to Majorana devices was found.
Control, readout & I/O burden
Control is DC-to-low-frequency gate voltages from room-temperature electronics plus rf readout lines; no per-qubit microwave drive, no laser — the architecture's genuine advantage. Readout is the gate operation: parity is inferred from an h/2e-periodic shift in the quantum capacitance of a dot coupled to the wire ends, non-destructively and mid-circuit, at ~100 µs (graph record). I/O scales with gates and resonators per tetron, both of order ten, so at 10³ tetrons the burden resembles a large spin-qubit array, addressable in principle by cryo-CMOS multiplexing. At 10⁴ and 10⁶ nothing can be said: no multiplexed Majorana-array readout is published, and no error model exists to set a latency requirement.
Role in the stack
The node sits on one architecture, Topological — tetron (Majorana). It requires III-V MBE heterostructures and provides the physical layer for the measurement-based Majorana gate, the fermion-parity (tetron) encoding and rf quantum-capacitance parity readout. It replaces and conflicts with nothing, because nothing depends on it. That isolation is the strategic fact: failure strands the branch with no partial credit — readout and MBE know-how transfer to hybrid-device physics, the encoding, gate set and error model nowhere.
Derived clock for the architecture = sum of the syndrome round: gate layers + transport + readout + reset: no code runs here, so only the ~100 µs parity-measurement term is defined and reset is unpublished, since logic is measurement and transport is absent — a design figure, not a demonstrated round. Neighbouring empty slots: a two-tetron joint-parity (X-type) measurement, and any decoder for a measured Majorana error model.
Evidence — how the numbers were measured
The headline 20 s is a switching-time fit to a telegraph signal in one wire, not a randomised-benchmarking number, and has no companion in the conjugate basis: parity lifetime and qubit coherence are different quantities, and only the former was measured C[21]. The February 2025 Nature paper carries an editor's note stating the results do not by themselves establish the presence of Majorana zero modes in the devices D[13], [214].
Independent work does not replicate the claim. QuTech has shown Kitaev-chain parity readout beyond 1 ms D[216] and, in July 2026, coherent parity oscillations in coupled minimal Kitaev chains while stating that "poor man's" Majoranas carry only limited protection D[217]: replication of the technique, explicit non-replication of the protection.
Legg argues the Topological Gap Protocol can label the same region gapped or gapless depending on analysis choices such as field range and junction transparency, and that the conductance data show no clear gap [22]; it became a Nature Matters Arising in June 2026 with a multi-author Microsoft reply that concedes nothing [22], [23]. History is load-bearing: the 2018 "quantized Majorana conductance" Letter was retracted on 2021-03-08 after undisclosed charge-jump corrections, a mislabelled axis, and a recalibration moving plateau values by 8% that left points outside 2σ D[365]. Only one group reports the headline numbers, so no value conflict arises.
The "beyond 1 ms" parity-readout figure for [216] comes from the main report and is not confirmed against the paper. The DKK 1 bn in [367] is total Danish quantum-infrastructure investment, not Microsoft's own outlay. Nokia's claimed end-2025 Pauli-X control result appears only in trade press [369], [371]; its device size of "15×15 µm" and its "hours to days" state stability come from [369] and [368], not from a peer-reviewed source. Not published: the assignment error, readout fidelity and device yield of the InAs–Pb generation [21]; Microsoft's topological R&D spend, Lyngby capex and headcount; the value of DARPA's US2QC contract with Microsoft [218]; an export-control rule or ECCN specific to Majorana or III–V superconducting hybrid devices; and a dated market-share figure for MBE tool vendors.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Sole source of tetron devices and of every headline number; measurement-based architecture; 2029 fault-tolerance target | C[21], [215]fact |
| Microsoft Quantum Lab Lyngby | supplier (captive fab) | DK | Fabrication of the Majorana chip core; opened 2025-11-13 | P[367] |
| QuTech | research | NL | Minimal Kitaev chains; independent parity readout and a coherent parity qubit with explicitly limited protection | D[216], [217] |
| TU Eindhoven | supplier (materials) | NL | InSb/InAs nanowire growth feeding the Kitaev-chain devices | D[217] |
| Nokia Bell Labs | developer | US | ν=5/2 fractional quantum Hall in GaAs, ~15×15 µm devices; target end-2026 for a topological qubit in superposition | D[366]C[368]P[369] |
| DARPA | funder | US | Microsoft in the final US2QC phase since 2025-02; absent from QBI Stage B | G[218]fact |
| GlobalFoundries | supplier | US | Quantum Technology Solutions covers the topological modality; Microsoft Quantum a named partner | C[353]fact |
| Atom Computing | partner (hedge) | US | Neutral-atom hardware for Microsoft's Magne logical-qubit machine — not topological | fact |
| QuNorth | user | DK | Bought Magne for €80 M, funded by EIFO and the Novo Nordisk Foundation | fact |
| H. F. Legg | critic | — | Matters Arising challenging the Topological Gap Protocol | [22] |
Money.
- 2025-02 · Microsoft · DARPA US2QC final phase (with PsiQuantum only) · amount not disclosed · DARPA · in progress G[218]fact
- 2025-07-17 · QuNorth · order for "Magne", 1,225 physical / 50 logical qubits · €80 M · EIFO + Novo Nordisk Foundation · ordered, delivery around the turn of 2026/27 fact
- 2025-11-06 · Microsoft · not selected for DARPA QBI Stage B (11 companies, up to $15 M each) · n/a · DARPA · confirmed absent fact
- 2025-11-13 · Microsoft · Lyngby lab opening; cumulative Danish quantum-infrastructure investment above DKK 1 bn (≈ USD 156 M) · announced P[367]
- 2026-01-23 · Microsoft · Quantum Pioneers Program 2026, academic grants up to USD 200,000 per proposal, decisions 2026-03-15 · announced P[370]
- 2026-05-12 · Microsoft · returning investor in Photonic Inc.'s $200 M round at a $2 B valuation · closed fact
- 2026-05-21 · GlobalFoundries · CHIPS letter of intent covering a unit that lists topological · $375 M · US Dept of Commerce · LOI C[353]fact
- Microsoft's topological R&D spend, headcount and Lyngby capex: not disclosed anywhere found.
Market & supply chain. Nobody sells equipment specific to this technology; inputs are general MBE tools, III-V substrates and standard dilution refrigerators. Concentration risk is total: one vendor, one captive fab, no merchant supply. Unit economics are unquotable — no device sold, no cloud access, no attributable revenue. Only G3 and G4 (early and large-scale fault tolerance) would pay for it; G1, G2, G5 and G7 are served by machines Microsoft buys from others, which the Magne order documents fact.
IP & standards. No topological-specific patent count from a named database was found; the only dated figure is the 1,175 Microsoft quantum patent families counted in PatSnap's landscape published on 2026-06-30 Pfact, spanning all modalities. No litigation over Majorana device IP was found, and there is no standards body; the only openly published aligned stack is Microsoft's Q#/Azure Quantum Development Kit, whose instruction model presumes the architecture rather than validating it.
Roadmaps & track record. (promised on · promised for · status 2026-09-03): 2018-03 · quantised Majorana conductance · retracted 2021-03-08 D[365]. 2025-02 · topological qubit demonstrated · contested, with a Nature editor's note D[13], [214]. 2025 · "years, not decades" · superseded C[215]. 2026-06 · 2029 fault tolerance · no two-qubit operation exists C[215]. Nokia: end-2025 · Pauli-X control result · no publication found; end-2026 · qubit in superposition · outstanding P[369]. Microsoft delivers excellent measurements on schedule and labels them with claims they do not support — consistent from 2018 to 2026; a 2029 date resting on zero demonstrated two-qubit physics is an intention, not a forecast. QuTech's statements have matched its data. Nokia's roadmap is too thinly published to judge.
Strategic reading. If it works, Microsoft owns a carrier no competitor can match by engineering alone, devaluing the rival capital stack at the physical layer. If it fails — the base case on today's evidence — Microsoft loses little: its delivery vehicle is other people's hardware plus its own error correction, which is why it bought Magne and invested in Photonic. Substitution runs the other way, as qLDPC codes erode the overhead argument that made topological qubits necessary. Supplier bargaining power is nil; platform-vendor power depends on whether a two-qubit result appears.
Outlook & open questions
Falsifiable within 12–24 months. Confirm: an X-loop or joint-parity lifetime on InAs–Pb within two orders of magnitude of the Z loop's 20 s; any two-tetron measurement-based operation with a reported fidelity; independent reproduction of the InAs–Pb parity lifetime; Nokia publishing a ν=5/2 qubit in superposition, promised for end-2026 P[369]. Demote: another year of Z-basis single-wire numbers only, or a second Matters Arising surviving reply.
Best case 2029: a few tetrons with balanced X/Z lifetimes and a two-qubit parity gate — a research device, not the promised fault-tolerant machine. Worst case: the InAs–Pb signal proves to be trivial Andreev states and the branch closes.
Open questions: why no X-loop number exists for the lead generation; what fraction of tetrons pass screening; how parity lifetime scales with wire length, the measurement that tests exponential protection directly; whether US2QC's final phase can be satisfied by a Z-only result; and whether Nokia's route, with its peer-reviewed non-Abelian interference signature D[366], is the better-evidenced bet.
References
- [13] Microsoft Azure Quantum, “Interferometric single-shot parity measurement in InAs–Al hybrid devices,” Nature, vol. 638, no. 8051, pp. 651–655, Feb. 2025, doi: 10.1038/s41586-024-08445-2. D
- [20] M. Aghaee et al., “Distinct Lifetimes for X and Z Loop Measurements in a Majorana Tetron Device,” arXiv:2507.08795, Jul. 2025. D
- [21] M. Aghaee et al., “20 Second Parity Lifetime in an InAs–Pb Tetron Device,” arXiv:2606.03884, Jun. 2026. C
- [22] H. F. Legg, “On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E22–E26, Jun. 2026, doi: 10.1038/s41586-026-10567-8. arXiv:2503.08944. D
- [23] Microsoft Quantum, “Reply to: On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E27–E28, Jun. 2026, doi: 10.1038/s41586-026-10568-7. D
- [214] P. Ball, “Experts Weigh in on Microsoft's Topological Qubit Claim,” Physics, vol. 18, p. 57, 2025. [Online]. Available: https://physics.aps.org/
articles/ Dv18/ 57 - [215] C. Nayak, “Majorana 2 – Microsoft's Scalable Quantum Processor With Reliable, Long-Lasting Qubits,” Microsoft Quantum. [Online]. Available: https://quantum.microsoft.com/
en-us/ Cinsights/ blogs/ majorana-2-scalable-quantum-processor - [216] N. van Loo et al., “Single-shot parity readout of a minimal Kitaev chain,” Nature, vol. 650, no. 8101, pp. 334–339, Feb. 2026, doi: 10.1038/s41586-025-09927-7. D
- [217] F. Zatelli et al., “Majorana parity qubit in coupled minimal Kitaev chains,” arXiv:2607.09511, Jul. 2026. D
- [218] DARPA, “DARPA selects two discrete utility-scale quantum computing approaches for evaluation,” Feb. 6, 2025. [Online]. Available: https://www.darpa.mil/
news/ G2025/ quantum-computing-approaches - [353] GlobalFoundries, “GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing,” May 21, 2026. [Online]. Available: https://gf.com/
gf-press-release/ Also https://investors.gf.com/globalfoundries-launches-quantum-technology-solutions-to-scale-us-quantum-manufacturing/ news-releases/ . Cnews-release-details/ globalfoundries-launches-quantum-technology-solutions-scale-us - [365] H. Zhang et al., “Quantized Majorana conductance,” Nature, vol. 556, no. 7699, pp. 74–79, Mar. 2018, doi: 10.1038/nature26142. Retracted: Nature, vol. 591, p. E30, Mar. 2021, doi: 10.1038/s41586-021-03373-x. D
- [366] R. L. Willett et al., “Interference Measurements of Non-Abelian e/4 & Abelian e/2 Quasiparticle Braiding,” Phys. Rev. X, vol. 13, no. 1, Art. no. 011028, Mar. 2023, doi: 10.1103/PhysRevX.13.011028. D
- [367] M. Abdel-Kareem, “Microsoft Opens Largest Quantum Lab Globally in Denmark to Advance Topological Qubit Fabrication,” Quantum Computing Report, Nov. 13, 2025. [Online]. Available: https://quantumcomputingreport.com/
microsoft-opens-largest-quantum-lab-globally-in-denmark-to-advance-topological-qubit-fabrication/ P - [368] Nokia Bell Labs, “Topological Quantum Computing,” Nokia.com, Feb. 24, 2025. [Online]. Available: https://www.nokia.com/
bell-labs/ Cresearch/ air-lab/ data-and-devices/ topological-quantum-computing/ - [369] J. Burt, “Bell Labs Takes A Topological Approach To Quantum 2.0,” The Next Platform, Jul. 21, 2025. [Online]. Available: https://www.nextplatform.com/
2025/ P07/ 21/ bell-labs-takes-a-topological-approach-to-quantum-2-0/ - [370] M. U. Rehman, “Microsoft Opens 2026 Quantum Pioneers Program for Measurement-Based Topological Computing Research,” The Quantum Insider, Jan. 23, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P01/ 23/ microsoft-2026-quantum-pioneers-program-measurement-based-computing/ - [371] P. R. Allison, “Bell Labs' Michael Eggleston on Nokia's research into topological quantum computing,” IT Pro, Apr. 28, 2026. [Online]. Available: https://www.itpro.com/
technology/ Pbell-labs-michael-eggleston-on-nokias-research-into-topological-quantum-computing
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Alkali atom (Rb/Cs) in optical tweezers
Hyperfine ground-state qubit in a single rubidium or caesium atom held by a far-detuned optical tweezer, moved on demand.
Verdict. Identical, free, transportable qubits with second-scale coherence; the binding constraints are trap-laser watts, millisecond imaging and atom loss — not fabrication.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A single neutral ⁸⁷Rb or ¹³³Cs atom in a far-off-resonant dipole trap of ~1 µm waist, the qubit encoded in two hyperfine ground states split by 6.83 GHz (Rb) or 9.19 GHz (Cs). The trap, order 1 mK deep, confines but does not define the qubit, so every carrier is the same object to the precision of atomic physics. Single-atom trapping dates to 2001 (Institut d'Optique); the platform begins with the 2016 demonstrations of deterministic defect-free arrays assembled by moving tweezers (Harvard; Institut d'Optique).
Attributes. Carrier affinity: fully natural — nothing fabricated, nothing to bin. Characteristic time: ~0.25 µs entangling interaction, deterministic, not heralded. Readout: fluorescence imaging, ~0.5 ms, non-destructive, mid-circuit capable. Mobility: the atom is physically transported by moving tweezers, so connectivity is reconfigured mid-circuit. Control: optical, room-temperature, outside the vacuum. Error structure as the code sees it: atom loss and leakage first, coherent error second — loss is detectable at imaging, hence erasure-convertible. Manufacturing: optical assembly, not lithography.
Physics & limits
The trap sets the scaling law. Holding a laser-cooled atom costs roughly 0.5–1 mW of 850–1064 nm light: Tsinghua's 18,225-site array took 33 W incident and 12.2 W effective trapping power, ~0.67 mW per site D[145]. Trap light grows strictly linearly with qubit count: a 10⁶-atom array is a kilowatt-class optical plant, not a larger version of today's machine.
Coherence is not the constraint. Hyperfine clock states are first-order magnetically insensitive: T2 = 12.6(1) s in a 6,100-atom Cs array D[138]; T2 = 1.09(3) s in Rb while a magneto-optical trap ran 0.5 m away, against a shielded 1.34(4) s D[144]. Against a millisecond cycle both are enormous.
The floor is atom loss. Background-gas collisions and photon-scattering heating give a tweezer-limited lifetime near 60 s in a room-temperature cell D[144]; loss runs ~0.09% per two-qubit gate D[134], and over 80% of leakage in a logical circuit is loss D[4]. That is the defining asymmetry: the dominant error announces itself. Moving the floor takes cryogenic vacuum, reloading during computation (300,000 atoms/s into tweezers, >30,000 initialised qubits/s D[144]) or a species change — alkalis buy the simplest laser system and the best-characterised Rydberg structure but lack the manifolds that make erasure conversion and loss-free imaging native in Sr/Yb.
Engineering state of the art
Records timeline.
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-03 → 2025-07 | 6,100 Cs atoms in ~12,000 sites; T2 12.6(1) s; imaging survival 99.98952(1)% | Caltech | D[138] |
| 2025-09-15 | 3,217 Rb atoms in one shot, >3,000 held >2 h; 300,000 atoms/s loaded; ~60 s lifetime | Harvard/MIT | D[144] |
| 2025-11-10 | 448 atoms under fault-tolerant control; 2.14(13)× below threshold, four rounds | Harvard/MIT/QuEra | Dfact |
| 2026-06-01 | 11,022 Rb atoms in 18,225 metasurface tweezers, 60.5% filling, no gates | Tsinghua/Qosmos | D[145] |
Typical at scale trails the records: QuEra's shipping Gemini is 260 physical qubits at 1 shot/s, SPAM 99.7% Cfact. The gap between 11,022 trapped and 448 under logical control is the field's honest position as of 3 September 2026, and atom loss dominates the budget in every regime. The carrier-quality bound set by the best entangling gate — 0.087(5)% atom loss per CZ Dfact — is a loss figure, not a coherence figure.
Manufacturing, materials & supply chain
There is no wafer. The process is an optical assembly: a UHV glass cell, an alkali dispenser, a high-NA objective — or, at Tsinghua, a 19.8 mm silicon-nitride metasurface 2.5 mm outside the cell replacing the objective entirely D[145] — an SLM for the static array, crossed acousto-optic deflectors for movable tweezers, a scientific camera. Uniformity is a runtime property, not a yield: stochastic loading fills 50–60% of sites and rearrangement repairs the array every shot. Substituting sorting for yield is this carrier's structural advantage over every fabricated one.
The supply chain is optics, concentrated in Europe and Japan P[329]. Lasers: TOPTICA (Munich), Exail (in Pasqal's racks), M Squared, and Menlo Systems and NKT — both Hamamatsu subsidiaries. SLMs: Meadowlark, Hamamatsu LCOS, Holoeye. Acousto-optics: AA Opto-Electronic, Gooch & Housego, Isomet. Cameras: Hamamatsu ORCA-Quest qCMOS, chosen for mid-circuit imaging in the Harvard/QuEra machine. Vacuum: Pfeiffer, Edwards, Kurt J. Lesker, VACOM. Over 90% of system size and cost is lasers and photonics P[329]. There is no Bluefors-equivalent chokepoint, but Hamamatsu appears simultaneously in lasers, SLMs and cameras — the one name hard to route around. No vendor discloses a per-system price. Export exposure runs through tunable lasers and vacuum equipment under Wassenaar Categories 6 and 2 and the 2024 US BIS quantum rule; exact ECCNs are unverified below.
Control, readout & I/O burden
The I/O burden does not scale with N: one SLM hologram makes the static array, one deflector pair addresses whichever subset is operated on. Wiring count — the wall for every solid-state carrier — is replaced by optical power and bandwidth. The cost lands in time: imaging 0.5–1 ms, transport 0.1–1 ms, correction cycle 1–4.5 ms, three orders slower than superconducting circuits, with the compensating benefit that a real-time decoder has an easy latency target (NVQLink 3.84 µs C[324]).
At 10³ the platform is done. At 10⁴ the constraints are aggregate trap power (12 W at the atoms today), deflector bandwidth, rearrangement time and camera field of view. At 10⁶ nothing demonstrated applies: kilowatt trap light, no multi-core interconnect, no sorting scheme finishing inside a cycle. Photonic delivery is the proposed answer, and Pasqal's four chip-trapped Rb atoms, ~27.5 s lifetime (2026-08-10) C[330], are three and a half orders from mattering.
Role in the stack
Two architectures, primary in both: "Rydberg tweezer array — alkali (Rb/Cs)" and "Neutral-atom analogue simulator (Rydberg arrays, lattice gases)". It requires optical/mechanical assembly and provides the carrier for Rydberg-blockade CZ, for fluorescence imaging of atom arrays, and for the atom–photon cavity interface a network layer would need. It replaces the slot of alkaline-earth and alkaline-earth-like atoms (Sr, Yb): switching costs a laser rebuild (narrow-line cooling and clock lasers at 689/698 nm) plus a decade of alkali Rydberg calibration, and buys native erasure conversion and non-destructive nuclear-spin readout. The field splits on that line — QuEra, Pasqal, Infleqtion (Cs), Harvard, Tsinghua on alkalis; Atom Computing (Yb), planqc (Sr), Caltech's gate work (Sr) on alkaline-earth(-like) atoms. Derived clock on the alkali tweezer array = sum of the syndrome round (gates 1 µs, transport 0.80 ms, 1Q 10 µs, readout 0.50 ms) ≈ 1.3 × 10⁻³ s, set by transport then readout, never the gate. Neighbouring empty slots: no cavity interconnect at array scale, no cryogenic-vacuum array above 10³.
Evidence — how the numbers were measured
The headline coherence is a dynamically decoupled, array-averaged T2: it absorbs site-to-site trap-depth inhomogeneity into the pulse sequence rather than reporting it. Imaging survival of 99.98952(1)% is per image at a stated exposure and bounds nothing about loss during transport or Rydberg excitation. The 60.5% filling fraction is pre-rearrangement — "11,022 atoms" and "11,022 usable qubits" are different claims. No protocol here separates loss from depolarising error, so error-per-Clifford figures are not comparable to solid-state ones without the post-selection.
Conflicts. The Caltech abstract says "over 6,100 atoms in around 12,000 sites"; versions differ (v1 2024-03, v4 2025-07) and the 12.6 s figure belongs to v4, the later revision, which takes precedence D[138]. The review arguing a 99.9% blockade ceiling also tabulates a 2025 USTC CZ of 99.84% that no primary source corroborates P[140].
Not published: the computing atom species of Infleqtion and of planqc (if strontium, planqc belongs to the alkaline-earth atoms technology), a vacuum-limited trap lifetime for the Tsinghua metasurface array, and a per-qubit or per-system capital cost for any tweezer machine.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuEra | developer | US | Rb arrays; Gemini 260 q shipping; Libra promised 2028 | C[137], [162] |
| Harvard/MIT | research | US | 448-atom architecture; 3,000-qubit continuous run; CZ record | D[4], [144] |
| Caltech | research | US | 6,100-atom Cs array; T2 12.6 s; record imaging survival | D[138] |
| Pasqal | developer | FR | Rb machines; on-chip trapping; Nasdaq PSQL | C[330], [331] |
| Infleqtion | developer | US | Sqale line; NYSE INFQ; Illinois system 2027 | G[155], [332] |
| Tsinghua | research | CN | 11,022-atom metasurface array, largest trapped ensemble | D[145] |
| Google Quantum AI | research | US | neutral-atom track opened 2026-03 under Adam Kaufman | C[9] |
| Atom Computing | developer | US | Yb competitor; Magne with Microsoft; QBI Stage B | G[11] |
| planqc | developer | DE | Sr competitor; DLR and LRZ builds; 1,000 qubits at LRZ circa 2027 | C[246] |
| TOPTICA | supplier | DE | dominant supplier of Rb/Cs cooling and trapping lasers | P[329] |
| Hamamatsu | supplier | JP | LCOS-SLMs and qCMOS cameras; owns Menlo and NKT | P[329] |
Money.
- 2022-05-04 / 2024-07-08 · planqc · DLR contract EUR 29 M; Series A EUR 50 M · DLR Quantum Computing Initiative; lead undisclosed · closed C[246]
- 2025-07-17 · QuNorth · "Magne" order from Atom Computing/Microsoft · EUR 80 M · EIFO + Novo Nordisk Foundation · ordered fact
- 2025-09-09 · QuEra · financing round · > USD 230 M · Google, SoftBank Vision Fund 2, NVentures · closed Cfact
- 2025-11-06 · QuEra · DARPA QBI Stage B · up to USD 15 M · DARPA · selected fact
- 2026-02-17 · Infleqtion · NYSE listing (INFQ) · > USD 550 M gross · SPAC · closed fact
- 2026-05-21 · Infleqtion · CHIPS letter of intent · USD 100 M · US Dept of Commerce · LOI (non-binding) fact
- 2026-06-15 · QuEra · Libra 2028 roadmap, expanded AWS Braket collaboration · undisclosed · AWS · roadmap Rfact
- 2026-08-12 · Infleqtion · Q2 2026 results · revenue USD 12.6 M (+116% y/y), H1 USD 22.094 M, FY26 guidance ~USD 43 M, Q2 net loss USD 25.5 M, cash USD 582 M · reported G[332]
- 2026-08-27 · Pasqal · SPAC completion, Nasdaq PSQL · ~USD 360 M cash; 2025 revenue EUR 16.5 M · Bleichroeder Acquisition Corp. II · closed fact
Market & supply chain. The enabling equipment is sold by photonics firms that were profitable before quantum existed; concentration is real but diffuse, with over 90% of system cost in lasers and photonics P[329]. Unit economics are undisclosed; the only quotable figure is 0.67 mW of trap light per tweezer D[145]. G1 (analogue simulation) is what alkali arrays are actually paid for today; G5 (optimisation) is what is marketed; G3 (early fault tolerance) is where every 2028 promise sits; G4 is the thesis behind the valuations. G6 is blocked on the cavity-interface slot.
IP & standards. The foundational tweezer-array and coherent-transport families come from Harvard/MIT, licensed into QuEra; the CNRS/Institut d'Optique lineage feeds Pasqal. Vertical integration is the visible move: Pasqal acquired Aeponyx for silicon-nitride photonics under 18 months before its August 2026 result C[330]. Open-source stacks: Bloqade (QuEra), Pulser (Pasqal), both with analogue-Hamiltonian front ends no other modality needs. No litigation found; no dated patent count from a named database.
Roadmaps & track record. QuEra (promised 2024-01 · for 2026 · 100 logical qubits undelivered as of 2026-09-03, replaced by Libra >256 logical in 2028 — a two-year slip). Pasqal (promised 2024-03 · for 2026 · 10,000 physical slipped to 2028; 100 logical now 2029). Infleqtion (reaffirmed 2026-08-12 · for 2026 · 30 logical qubits, unverified; >50 logical at Illinois 2027). planqc (promised 2024-11 · for ~2027 · 1,000 qubits at LRZ; no device metrics published since). Credibility: Harvard/MIT outrun every roadmap because they publish rather than promise; QuEra and Pasqal have each slipped a flagship number by two years and read as 2029 companies; Infleqtion alone reports audited revenue against its claims; planqc has contracts but no published metrics.
Strategic reading. If alkali arrays win, value accrues asymmetrically to component vendors — TOPTICA, Hamamatsu, Meadowlark — paid identically whichever developer prevails and facing no substitution risk from the alkaline-earth(-like) branch beyond a change of wavelength catalogue. The real threat to this node is internal: Sr/Yb carriers convert the dominant error into an erasure for free. Bargaining power sits with buyers — Infleqtion holds USD 582 M, Pasqal ~USD 360 M, against far smaller European vendors — and the response is acquisition rather than negotiation.
Outlook & open questions
Confirm if a defect-free array above 2,000 atoms runs gates by end-2027; if Infleqtion demonstrates 30 logical qubits by 2026-12-31; if a chip-delivered tweezer array exceeds 100 traps by end-2027. Demote if no group shows Λ > 2 over more than 50 rounds with continuous reloading by end-2027 — Atom Computing's toric-code run lost its suppression precisely when reloading was included D[148], and that, not gate fidelity, is the load-bearing question.
Best case by 2029: Libra-class systems above 256 logical qubits on cloud, chip or metasurface optics collapsing the footprint, loss handled as erasure end to end. Worst case: 10³-qubit analogue simulators with a few dozen logical qubits, the millisecond cycle fatal outside simulation, alkalis losing fault tolerance to Sr/Yb.
Open questions. (1) Does continuous reloading survive contact with error correction, or does stray light impose a coherence tax growing with duty cycle? (2) Can rearrangement of >10⁴ sites finish inside a correction cycle, or does sorting become the clock? (3) Are metasurface and chip-based trap delivery compatible with the trap depths and beam quality high-fidelity gates require?
Watch: Infleqtion's Q4 2026 report against the 30-logical claim; a QuEra Libra milestone in 2027; Pasqal's chip channel count; Google's first neutral-atom paper; any vacuum-limited lifetime above 300 s at array scale.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [9] H. Neven, “Building superconducting and neutral atom quantum computers,” Google, Mar. 24, 2026. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ neutral-atom-quantum-computers/ - [11] Novo Nordisk Foundation, “New quantum computer with great potential to boost Nordic research and innovation,” Novo Nordisk Fonden, Jul. 17, 2025. [Online]. Available: https://novonordiskfonden.dk/
en/ Gnews/ new-quantum-computer-with-great-potential-to-boost-nordic-research-and-innovation/ - [134] S. J. Evered et al., “High-fidelity entangling gates and nonlocal circuits with neutral atoms,” arXiv:2604.25987, Apr. 2026. D
- [137] QuEra Computing Inc., “Gemini-Class Gate-Model Quantum Computer.” [Online]. Available: https://www.quera.com/
gemini C - [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [140] J. Wang, Z. Wang, L. Li, F. Wang, S. Liang, and K. Yan, “Neutral Atom Quantum Computing: Principles, Routes, Progress, and Challenges,” arXiv:2608.05010, Aug. 2026. P
- [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [145] Y. Wang et al., “Trapping 11,000 Atoms in a Tweezer Array Generated by a Single Metasurface,” arXiv:2606.02715, Jun. 2026. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [155] L. Roady, “Infleqtion Becomes First Neutral-Atom Quantum Company to Go Public,” Infleqtion, Feb. 17, 2026. [Online]. Available: https://infleqtion.com/
infleqtion-becomes-first-neutral-atom-quantum-company-to-go-public/ G - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [246] planqc, “News.” [Online]. Available: https://planqc.eu/
news C - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [329] M. Ivezic, “The Tweezer Array's Hidden Supply Chain: Who Really Wins If Neutral-Atom Quantum Computing Wins,” PostQuantum.com, Nov. 17, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Pneutral-atom-quantum-ecosystem/ - [330] Pasqal, “Pasqal brings qubit control on-chip, advancing the path to fault-tolerant quantum computing at scale,” Aug. 10, 2026. [Online]. Available: https://www.pasqal.com/
news/ Cpasqal-brings-qubit-control-on-chip-advancing-the-path-to-fault-tolerant-quantum-computing-at-scale/ - [331] Pasqal, “Newsroom.” [Online]. Available: https://www.pasqal.com/
newsroom/ C - [332] Infleqtion, “Infleqtion Reports Record Q2 Revenue, Raises 2026 Outlook as Quantum Commercialization Accelerates,” Aug. 12, 2026. [Online]. Available: https://ir.infleqtion.com/
news-events/ Gpress-releases/ detail/ 201/ infleqtion-reports-record-q2-revenue-raises-2026-outlook-as-quantum-commercialization-accelerates
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Alkaline-earth(-like) atom (Yb/Sr) — erasure-native
Ytterbium/strontium tweezer qubits whose metastable clock manifold makes decay and loss optically detectable, converting physical errors into heralded erasures rather than silent Pauli errors.
Verdict. Erasure conversion is real and internally consistent (1.9(4)× unconditional decay suppression), but the metastable encoding costs ~6× in CZ error and is unreplicated outside Princeton and Caltech.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
¹⁷¹Yb and ⁸⁷Sr have two valence electrons: a seconds-scale ³P₀/³P₂ metastable triplet above the ¹S₀ ground singlet, on a narrow clock line (578 nm Yb, 698 nm Sr). A ground-manifold imaging beam is dark to a metastable-manifold qubit, so decay and loss scatter photons while the code space stays quiet — the "omg" (optical–metastable–ground) scheme, from a 2021 ion-trap blueprint D[333]. Errors then arrive located, as erasures, not silent Pauli flips. Demonstrated in Yb (Princeton) and Sr (Caltech), May 2023 D[141], [143].
Attributes: natural carrier; deterministic Rydberg-blockade entanglement ~250 ns; fluorescence readout ~0.5 ms, non-destructive, mid-circuit-capable.
Optical control from room temperature; error structure erasure and loss, not native Pauli; manufacture by optical assembly, not lithography.
Physics & limits
Erasure conversion relabels error rather than reducing it; the payoff is in the decoder — at 1% erasure the erasure-aware surface code tolerates Pauli error to 0.51%, 5.2× the standard protocol D[334]. The gate floor sits elsewhere: Rydberg-blockade CZ runs in a few hundred nanoseconds against Rydberg spontaneous plus blackbody decay (0.05–0.1%), laser phase noise (0.1–0.2%) and thermal motion (~0.1%), which a 2026 review argues caps the standard scheme near 99.9% absent a new gate mechanism P[140]. Atom loss is over 80% of leakage events D[4] — precisely what omg sees. Moving the floor needs a cryogenic enclosure against blackbody-driven Rydberg decay, lower trap-light scattering out of the metastable manifold (it sets the check interval), and imaging that spares neighbouring sites.
Engineering state of the art
table
| Year | Figure | Who | Tag/key |
|---|---|---|---|
| 2023-05 | 56% of 1Q errors → erasures, ¹⁷¹Yb (98% ceiling) | Princeton | D[141] |
| 2024-07 | Sr CZ 99.71% | Caltech | D[136] |
| 2024-11 | Yb CZ 99.72% post-selected / 99.40% raw | Atom Computing | D[135] |
| 2026-06 | Metastable CZ error 0.016(1), 38(6)% flagged; [[4,2,2]] decay 1.9(4)× slower | Princeton | D[142]fact |
| 2026-08 | 17.6 µs imaging, 99.89(5)% discrimination, 98.80(44)% survival, ¹⁷⁴Yb | Kyoto/Yaqumo | P[261]fact |
The dominant term is the gate, not the erasure machinery: Princeton's metastable CZ error 0.016(1) is ~6× Atom Computing's raw ground-state Yb CZ of 0.0060 D[135], [142], and only ~38% of it returns as flags. The 17.6 µs record is spinless ¹⁷⁴Yb, not ¹⁷¹Yb readout, so 0.5 ms stays the honest cycle.
Manufacturing, materials & supply chain
No lithographic chip: the fab is a UHV chamber, a high-NA objective, SLM/AOD steering and clock, Rydberg, imaging and shelving lasers; yield is per-site loading probability plus SLM-aberration trap non-uniformity. Optics is the cost driver — Fraunhofer ILT's 2026 system makes 2,000 controllable Rydberg tweezers from four beams totalling 20 W Dfact, about 10 mW per site, so 10⁴ sites is a 100 W-class laser problem S. The thin points are not foundries: two crossed-AOD vendors appear anywhere in the literature (AA Opto-Electronic, Gooch & Housego) Dfact and Hamamatsu's SLM and camera line has no identified alternative Pfact. Export exposure is at system level: ECCN 4A906 controls quantum computers above a qubit-count and error-rate threshold (in force 2024-09-06, Licence Exception IEC for partners); no ECCN names tweezer optics, AODs or UHV chambers G[301]fact.
Control, readout & I/O burden
Addressing is AOD/SLM tweezers plus global clock and Rydberg beams; readout is imaging at 0.5–1 ms. A mid-circuit erasure check must be manifold-selective and must not heat the neighbours it illuminates — the constraint holding demonstrated conversion at 38–56% rather than the 98% ceiling D[141], [142]. Global beams plus AOD addressing suffice at 10³ sites; at 10⁴ beam steering bottlenecks parallel local operations — a deflector resolves as many spots as its rf bandwidth times the acoustic transit across the beam, a transit that also bounds how fast it re-points, and liquid-crystal modulators reframe at tens of hertz — and trap power crosses 100 W; at 10⁶ no path exists short of metasurface or photonic delivery.
Role in the stack
This carrier defines the "Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native" architecture (Atom Computing/Microsoft, Princeton, Caltech, planqc, Yaqumo) and is the alternate carrier of the "Neutral-atom analogue simulator (Rydberg arrays, lattice gases)" (ICFO's QUIONE, an ⁸⁴Sr lattice gas): optical assembly only, no foundry and no cryostat, hence no CHIPS-style capital wall. It feeds Rydberg-blockade CZ, the omg encoding, imaging readout, fast (≤20 µs) array readout and the atom–photon cavity interface. It replaces alkali species; a Rb incumbent's switching cost is a new laser and imaging system. Derived clock on the tweezer array of alkaline-earth and alkaline-earth-like atoms (Sr, Yb) = sum of the syndrome round (gates 1 µs, transport 800 µs, 1Q 0.34 µs, readout 501 µs) = 1.3 ms, transport-limited, against the measured ~1–4 ms round. The salient empty slot is an erasure-aware real-time decoder fed by live array syndromes.
Evidence — how the numbers were measured
Fractions come from state-selective fluorescence after gates; CZ fidelity from randomised benchmarking or tomography, reported raw and post-selected on the flag. A code spends a correction cycle on every heralded erasure, so raw numbers govern cost. The 1.9(4)× vs 3.6× conflict resolves inside arXiv:2506.13724v2: both figures are in that paper and describe different quantities — decay is 3.6(1)× slower during hold for the post-selected logical qubit, 1.9(4)× slower under unconditional decoding with erasure information D[142]. Only 1.9(4)× is architecturally meaningful; the Nature Physics text is paywalled [142]. The 56% (1Q, 2023) and 38(6)% (CZ, 2026) figures are different metrics and must not be averaged. No independent replication was found.
Not published: Magne's installation status after the 2025-07-17 order announcement. The ≈10 mW per site trap power at 10⁴ sites is an extrapolation from the Fraunhofer figures, not a measurement S. No ECCN names tweezer optics, AODs or UHV chambers; only the finished system is export-controlled.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Atom Computing | developer | US | Ships ¹⁷¹Yb arrays; 1,225-site Magne | C[154] |
| Princeton University | research | US | Originated Yb erasure conversion; [[4,2,2]] logical qubit | D[141], [142] |
| Caltech | research | US | Sr erasure excision; 99.71% CZ | D[136], [143] |
| Microsoft | developer | US | Co-sells Magne; QEC and decoder stack | C[11] |
| Hamamatsu Photonics | supplier | JP | SLM and camera; sole identified source | P[335] |
| US Dept of Commerce | regulator | US | CHIPS LOI; ECCN 4A906 | G[300], [301] |
Money.
2025-07-17 · QuNorth · "Magne" order, 1,225 physical / 50 logical, from Atom Computing/Microsoft · €80 M · EIFO + Novo Nordisk Foundation · ordered C[11]fact
2025-11-06 · Atom Computing · DARPA QBI Stage B · up to $15 M · DARPA · awarded G[65]fact
2026-05-21 · Atom Computing · CHIPS letter of intent · $100 M · US DoC, $2.013 B package · LOI G[300]fact
2026-06-16 · Atom Computing · Series C · $100 M · Third Point · cumulative > $300 M · closed C[154]fact
Market & supply chain. Specialty optics, not silicon: narrow-linewidth lasers, crossed AODs (two vendors named anywhere), SLMs and cameras (one), UHV chambers. No $/qubit is public; QuNorth's €80 M for 1,225 physical / 50 logical implies ≈ €65 k per site and ≈ €1.6 M per logical qubit C[11]. G3 pays for this node, G4 conditionally, G1 shared with Rb arrays.
IP & standards. No dated patent family specific to alkaline-earth(-like) erasure encoding was found; the nearest grant is Amazon's US 11,748,652 B1 (2023-09-05), heralding amplitude-damping decay on dual-rail superconducting embodiments, not atoms G[336]fact. No standards activity identified.
Roadmaps & track record. Magne, 50 logical (promised 2025-07-17 · for turn of 2026/27 · no completion announcement as of 4 Sep 2026) R[11]; QuEra, 100 logical (2024-01 · for 2026 · became Libra, >256 logical, 2028) R[162]; Pasqal, 10,000 physical (2024-03 · for 2026 · slipped to 2028, SPAC-funded ~$360 M) R[156]. Princeton is peer-reviewed and self-consistent; Atom Computing ships hardware but saw suppression vanish once reloading was included D[148].
Strategic reading. If erasure bias holds at code distance, Yb/Sr gains a structural overhead edge toward G3/G4 over Rb incumbents, who must pivot lasers and imaging or invent native-Rb heralding; Google's undeclared species is the tell C[9]. Optics suppliers win either way, so the AOD and camera duopolies hold the durable bargaining power. The substitution threat is superconducting dual-rail erasure on a ~500 ns clock, D-Wave's $550 M purchase of Quantum Circuits being the bet Cfact.
Outlook & open questions
Milestones (12–24 months): Magne shows 50 logical qubits under erasure-biased decoding in situ, not post-selected (confirm); an outside group replicates >50% 1Q conversion (confirm); a real-time decoder consumes array erasure flags inside the cycle budget (confirm) — or conversion vanishes under reloading as Λ did (demote). Best case 2029: erasure-native arrays underpin a >100-logical-qubit machine with validated overhead reduction; worst case, conversion stays a single-gate effect and the millisecond cycle decides the platform. Open questions: does conversion survive ms-scale reloading; can the metastable encoding recover its 6× gate deficit; does trap power or AOD bandwidth bind first above 10⁴. Watch: Magne acceptance, Google's species choice, the first non-Princeton replication.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [9] H. Neven, “Building superconducting and neutral atom quantum computers,” Google, Mar. 24, 2026. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ neutral-atom-quantum-computers/ - [11] Novo Nordisk Foundation, “New quantum computer with great potential to boost Nordic research and innovation,” Novo Nordisk Fonden, Jul. 17, 2025. [Online]. Available: https://novonordiskfonden.dk/
en/ Cnews/ new-quantum-computer-with-great-potential-to-boost-nordic-research-and-innovation/ - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [135] J. A. Muniz et al., “High-fidelity universal gates in the ¹⁷¹Yb ground state nuclear spin qubit,” arXiv:2411.11708, Nov. 2024. D
- [136] R. B.-S. Tsai, X. Sun, A. L. Shaw, R. Finkelstein, and M. Endres, “Benchmarking and linear response modeling of high-fidelity Rydberg gates,” arXiv:2407.20184, Jul. 2024. D
- [140] J. Wang, Z. Wang, L. Li, F. Wang, S. Liang, and K. Yan, “Neutral Atom Quantum Computing: Principles, Routes, Progress, and Challenges,” arXiv:2608.05010, Aug. 2026. P
- [141] S. Ma et al., “High-fidelity gates with mid-circuit erasure conversion in a metastable neutral atom qubit,” Nature, vol. 622, p. 279, 2023, doi: 10.1038/s41586-023-06438-1. arXiv:2305.05493. D
- [142] B. Zhang et al., “Logical qubits with erasure conversion using metastable neutral atoms,” Nat. Phys., vol. 22, no. 6, pp. 910–916, Jun. 2026, doi: 10.1038/s41567-026-03309-0. arXiv:2506.13724. D
- [143] P. Scholl, A. L. Shaw, R. B.-S. Tsai, R. Finkelstein, J. Choi, and M. Endres, “Erasure conversion in a high-fidelity Rydberg quantum simulator,” Nature, vol. 622, p. 273, 2023, doi: 10.1038/s41586-023-06516-4. arXiv:2305.03406. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ R08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [261] R. Yokoyama et al., “Minimally Destructive Fast Imaging of Single Atoms in an Optical Tweezer Array with Coherent Excitation,” arXiv:2605.24175, Jun. 2026. Also https://arxiv.org/
abs/ . P2605.24175 - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [333] D. T. C. Allcock et al., “omg blueprint for trapped ion quantum computing with metastable states,” Appl. Phys. Lett., vol. 119, no. 21, Art. no. 214002, Nov. 2021, doi: 10.1063/5.0069544. arXiv:2109.01272. D
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patent/ GUS11748652B1/ en
Русский текст загружается…
הטקסט בעברית נטען…
Single photon (discrete variable)
A qubit carried by one optical quantum in path, time-bin or polarisation modes; entangling is probabilistic and the dominant error is loss.
Verdict. Best component metrics of any platform, worst system result: no photonic logical qubit exists as of 2026-09-03 and loss sits 20–24× above threshold.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A discrete-variable photonic qubit encodes one bit in which of two optical modes a single quantum occupies — two waveguides (path/dual-rail), two time slots, or two polarisations. Nothing in it decoheres: at 1550 nm the quantum carries 0.8 eV, four orders above room-temperature thermal energy, so there is no T1 and no T2. The photon either arrives intact or does not, so the dominant error model is erasure with known location and the problem is transport, not isolation. Dual-rail as an error-suppressing encoding dates to Chuang and Yamamoto (1995); the platform starts with Knill, Laflamme and Milburn (2001), who proved linear optics, single-photon detection and feed-forward universal — at the price of making every two-qubit interaction probabilistic D[337]fact.
Attributes, from the graph record:
- a — affinity: 0.25, near the fabricated end; the photon is natural, the mode defining the qubit is lithography.
- b — time, entangling: 10⁻⁷ s per layer, heralded — fusion succeeds with probability ≤ 1/2 unless boosted.
- c — readout: single-photon detection, ~10⁻⁸ s, destructive, no mid-circuit measurement.
- d — mobility: flying; transport is free, standing still is what costs.
- e — control: electro-optic, driven from room temperature though the chip sits near 2 K.
- f — error structure: loss, seen by the code as erasure.
- g — manufacturing: photonic integrated circuit.
Physics & limits
Two indistinguishable photons meeting on a beamsplitter bunch, and detecting the right output pattern projects the remaining modes into an entangled state. Because the projection succeeds only sometimes, a fusion network must over-attempt and repair failures with redundancy in the resource state.
The floor is a loss budget and every element spends against it. In Omega: fibre-to-chip 52 ± 12 mdB, splitter 0.5 ± 0.2 mdB, barium-titanate switch 100 mdB insertion, single-mode SiN 1.8 ± 0.2 dB/m (0.5 dB/m multimode) D[169]fact. Theory tolerates 2.7% per-photon loss with 6-ring resource states, up to 17% with 168-qubit states nobody can build S[179]. A photon crossing thirty switches has spent 3 dB — half of itself. Xanadu, on the continuous-variable side but with the same optics, quantifies the gap: 24.1× above threshold in 2026, targeting 1.0× in 2030 C[178]fact.
The standard fix for probabilistic sources costs the budget it protects: spontaneous four-wave mixing (SFWM) must run at ~1% heralding probability to suppress multi-photon events, so near-determinism needs multiplexing depth around ten — ten times the switches at 100 mdB each. Deterministic quantum-dot sources break that circle, which is why 71.2% system efficiency, first above the 2/3 loss-tolerance threshold, is the most consequential source number on record D[170]. Secondary failure modes: distinguishability (mismatch degrades HOM visibility and appears as Pauli rather than erasure error), multi-photon contamination, dark counts, and feed-forward latency — the photon waits in delay while a classical decision is made, and delay is loss.
Engineering state of the art
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2023-11 | QD source system efficiency 71.2% — first above the 2/3 threshold | USTC (Ding et al.) | D[170] |
| 2025-02 | Omega: purity 99.5%, HOM 99.5%, fusion Bell 99.22 ± 0.12%, chip-to-chip Bell 99.72 ± 0.04% over 42 m, on-chip SNSPD median efficiency 93.4%, ~2 K, 300 mm | PsiQuantum / GlobalFoundries | D[169] |
| 2025 | Commercial QD source S1: 55.3% system efficiency, 26.2 MHz detected rate | Sparrow Quantum | D[338] |
| 2025-10 | 12-qubit Belenos/Lucy delivered to CEA TGCC | Quandela | C[176] |
| 2026 | QD source S3: raw HOM visibility 97.1 ± 0.1%, purity 99.9 ± 0.1% | Sparrow Quantum | D[338] |
| 2026-05 | Gaussian boson sampling on squeezed light, 3,050 photon clicks | USTC (Jiuzhang 4.0) | D[175] |
| 2026-07 | 8-qubit universal MBQC subsystem (Carina) delivered to DLR QCI | QuiX Quantum | C[177] |
Best-demonstrated and typical-at-scale are further apart here than on any other platform: component fidelities are excellent, the largest fielded universal DV machine is twelve qubits C[176], and no photonic logical qubit exists as of 2026-09-03. The dominant error term is not a fidelity but per-photon survival through the switch network.
Manufacturing, materials & supply chain
Foundry detail belongs to the photonic-IC brief; specific to the carrier is that two incompatible source technologies compete. SFWM in SiN or Si rings is monolithic with the circuit, CMOS-compatible, III-V-free and runs at 2 K beside the detectors, but is probabilistic and buys determinism with multiplexing switches (PsiQuantum, Xanadu, QuiX). Quantum dots (InAs/GaAs in photonic-crystal waveguides) are near-deterministic — 71.2% in the lab D[170], 55.3% shipped, 20–35% typical D[338] — but need ~4 K, emit near 900–950 nm rather than telecom, grow at random positions and energies (a yield problem), and must be heterogeneously integrated (Quandela, Sparrow).
Single points of failure: one 300 mm line of record Cfact; one merchant deterministic-source vendor D[338]; a switch base on two small thin-film-lithium-niobate suppliers Pfact. No vendor publishes a per-qubit cost or system price. Export exposure runs through the September 2024 US quantum controls and the EU dual-use list; the exact classification of single-photon sources is unverified.
Control, readout & I/O burden
Drivers are room-temperature electro-optics and the chip sits at ~2 K, where a cryoplant has roughly a thousand times the cooling capacity available at 10 mK — the platform's real scaling advantage. The wall is channel count and latency, not power. Every operation ends in destructive detection, so channels scale with mode count: 10³ modes is ordinary cryogenic wiring, 10⁴ needs multiplexed readout, 10⁶ needs something like the row-column architecture behind the 400,000-pixel SNSPD camera D[339] plus decision logic inside the cryostat. At 0.5 dB/m multimode SiN, holding a photon 100 ns costs ~20 m of waveguide and 10 dB, so feed-forward must be nanosecond-class. QuiX names fast feed-forward, with sources, as the two problems its 2026 system must solve C[340].
Role in the stack
The node sits on the fusion-based photonic architecture (PsiQuantum, Quandela, QuiX) and is the alternate carrier of the boson sampler architecture. It requires the photonic-IC foundry for sources and waveguides, and provides photons to linear-optical fusion, the resource-state generator (RSG), time-bin and path encodings, and single-photon detection. It replaces continuous-variable squeezed light; switching costs the whole stack — different sources, homodyne rather than click detection, GKP rather than fusion codes. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: none is defined, the architecture being measurement-driven; the native 1.0×10⁻⁷ s clock stands instead, and multiplexing and fusion retries set the effective logical rate. Empty neighbouring slots are conspicuous: no deterministic photon–photon gate, no photonic memory good enough for multiplexing at scale (ORCA's rubidium hollow-core fibre is the only commercial attempt), no non-destructive mid-circuit measurement.
Evidence — how the numbers were measured
HOM visibility, g²(0) by Hanbury Brown–Twiss, and fusion Bell fidelity by tomography on coincidence-post-selected data are the standard instruments. What they do not capture is loss: nearly every photonic fidelity is conditioned on the photons having been detected, so the error that dominates the machine is divided out of the number describing it. "Fusion Bell fidelity 99.22%" and "24× above the loss threshold" describe the same optics; treating the first as the platform's error rate mis-ranks it by two orders of magnitude.
Conflicts. (i) The main report's 0.5 dB/m is the multimode figure; single-mode SiN in Omega is 1.8 ± 0.2 dB/m D[169]fact — both used here, labelled. (ii) QD efficiency 71.2% (lab) vs 55.3% (shipped) vs 20–35% (typical) is a lab-to-product gap; use the product figure D[170], [338]. (iii) Jiuzhang 4.0's advantage is contested by loss-exploiting classical spoofing D[175]. (iv) Sparrow's "highest HOM visibility to date" is an unreplicated vendor claim D[338]. Omega has never been independently reproduced.
PsiQuantum's $31.8 M Stage C award is dated 2025-09 in some sources and placed inside a July 2026 package in others; the $125 M expansion date (2026-07-22) is firm. ORCA Computing's funding is known only as a secondary range (~£8–15 M Series A plus 2023–24 capital). Not published: the exact date and instrument mix (equity, loan or grant) of the A$940 M Australian commitment to PsiQuantum, beyond the total and the two governments [183]; Sparrow Quantum's Series A lead investor and cumulative funding; a primary release, cumulative total or valuation for ORCA Computing; the ECCN of single-photon sources and detectors under the September 2024 US quantum rule; and Quandela's cumulative funding, or any 2025–26 round after its €50 M of 2023-11-07.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US / AU | Fusion-based DV on 300 mm GlobalFoundries; Omega chipset; Brisbane, Chicago | D[169]fact |
| Quandela | developer | FR | QD sources plus own processors; 12-qubit Lucy at CEA | C[176]fact |
| QuiX Quantum | developer | NL | Universal MBQC photonic processors; Carina at DLR | C[177]C[340] |
| ORCA Computing | developer | UK | Time-bin boson sampling with Rb memory; nine PT-1 units fielded | P[341] |
| Xanadu | developer | CA | CV/squeezed route — the in-platform substitution threat | C[178]fact |
| Sparrow Quantum | supplier | DK | Merchant deterministic QD single-photon source chips | D[338]P[342] |
| USTC (Pan group) | research | CN | Jiuzhang boson sampling (squeezed light); best QD source efficiency on record | D[170]D[175] |
| Photonic Inc. | developer (adjacent) | CA | T centres in silicon: spin–photon interface, telecom-band links | P[186]fact |
| GlobalFoundries | supplier | US | 300 mm photonic quantum manufacturing, integrated SNSPD | Cfact |
| DARPA | funder | US | QBI Stage A/B/C and US2QC validation money | fact |
| CEA/GENCI, DLR QCI | users | FR / DE | Buy and host photonic systems for HPC centres | C[176]C[177] |
Money.
- 2023-11-07 · Quandela · round, €50 M · Serena, Crédit Mutuel Innovation, EIC Fund, Bpifrance, OMNES, Quantonation; France 2030 · closed C[343]
- 2024-04 · PsiQuantum · Australian federal + Queensland commitment, A$940 M · definitive P[183]
- 2025-04-10 · Sparrow Quantum · Series A, €21.5 M ($24 M) · lead undisclosed · closed P[342]
- 2025-07-10 · QuiX Quantum · Series A, €15 M · Invest-NL and EIC Fund co-lead; PhotonVentures, Oost NL, FORWARD.one · closed C[340]
- 2025-09-10 · PsiQuantum · Series E, $1 B at $7 B · BlackRock, Temasek, Baillie Gifford · closed fact
- 2025-09 · PsiQuantum · DARPA QBI Stage C via US2QC, $31.8 M · announced P[181]
- 2026-05-12 · Photonic Inc. · round, $200 M at $2 B, $350 M cumulative · Microsoft among returning investors · closed P[186]
- 2026-05-21 · PsiQuantum · CHIPS letter of intent, $100 M · US Dept of Commerce · LOI, non-binding fact
- 2026-06-16 · Quandela · DARPA QBI/QBIT Stage A selection · amount undisclosed · announced fact
- 2026-06-19 · Sparrow Quantum · EuroHPC Grand Challenge (EU-SCALE), €300,000 · EuroHPC JU · in preparation P[342]
- 2026-07-22 · PsiQuantum · DARPA QBI Stage C expanded agreement, $125 M · announced fact
Market & supply chain. The enabling layer is thin: one merchant 300 mm quantum-photonics offering Cfact, one merchant deterministic-source vendor D[338], a switch base on two small TFLN suppliers Pfact, with open-access European capacity under PIXEurope (~EUR 400 M, 2024-11-24) fact. Unit economics are unquotable: Quandela's machines for OVHcloud and CEA, QuiX's for DLR and the nine ORCA PT-1 units all sold at undisclosed value. G6 pays today, photons being the only carrier that moves; G1 and G5 pay marginally via sampling and optimisation demos; G4 is the whole PsiQuantum and Quandela thesis but is funded by governments, not customers; G3 pays photonics nothing, there being no logical qubit to sell.
IP & standards. The one dated grant surfaced is ORCA Computing US 12,437,225, "Linear-optical encoded GHZ measurements and fault-tolerant quantum computation and communication", filed 2023-10-16, granted 2025-10-07 fact. No dated patent count from a named database was obtained. Open-source stacks are vendor-led (Quandela's Perceval, Xanadu's PennyLane); no photonic interoperability standard exists.
Roadmaps & track record. PsiQuantum (promised 2024-04 · for end-2027 · commercially useful Brisbane machine; status: site moved to Moreton Bay Central, groundbreaking slipped to 2026-06, cryoplant delivery due 2H 2027 Cfact, no 2026 hardware publication) — the money and DARPA validation are real, the date is not. Quandela (promised · for 2025 · first logical qubit; missed) and (promised · for 2028 · 50 logical qubits; pending) — ships machines on schedule, misses fault-tolerance milestones. QuiX (promised 2025-07 · for 2026 · first-generation universal computer; status: Carina delivered 2026-07, commissioning pending) — credible on delivery, unproven on universality. ORCA (promised · for 2026 · PT-3; undelivered) — ships units, but non-universal ones. Xanadu (promised 2026-08-31 · for 2028–31 · fault tolerance 2028–29, 1,000+ logical by 2031) — the only photonic roadmap publishing its distance from threshold.
Strategic reading. If DV photonics works, value migrates to the fab, the detector base and whoever owns the low-loss switch; the loser is the cryogenic-electronics complex around millikelvin qubits, because 2 K is cheap. Substitution threats sit inside photonics as much as outside: CV/GKP (Xanadu) and spin–photon hybrids (Photonic Inc.) both claim to sidestep probabilistic sources, while atoms and ions already have logical qubits — so photonics must win on manufacturing volume, not physics. Bargaining power sits with the foundry and the few firms able to make a deterministic source; no platform vendor gains leverage until one shows an encoded qubit.
Outlook & open questions
Confirm if PsiQuantum publishes a fusion-network result with measured end-to-end loss, or DARPA advances it past Stage C; if QuiX commissions Carina and runs a universal feed-forward MBQC circuit by mid-2027; if any group demonstrates an encoded photonic qubit with measured error suppression. Demote if there is no PsiQuantum hardware publication by end-2027 while Brisbane slips again; if Quandela reaches end-2027 without one logical qubit while holding a 50-logical-by-2028 target; if PT-3 stays undelivered through 2027.
Best case 2029: deterministic sources above 70% system efficiency on a foundry PIC, switch loss below 50 mdB, a first photonic logical qubit, a utility-scale machine in commissioning. Worst case 2029: loss within 3× of today, no logical qubit, the computing claim migrating to spin–photon hybrids while photonics consolidates into networking.
Open questions. (1) Can QD sources be integrated at foundry scale without breaking the 2 K budget or abandoning telecom wavelengths? (2) Is there a feed-forward technology whose optical delay costs less loss than the multiplexing it enables? (3) How much loss is heralded rather than silent? (4) Why has PsiQuantum published nothing since Omega? (5) Do RSGs scale sub-linearly in switch count?
References
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- [175] H.-L. Liu et al., “Gaussian boson sampling with 1,024 squeezed states in 8,176 modes,” Nature, vol. 653, no. 8115, pp. 687–692, May 2026, doi: 10.1038/s41586-026-10523-6. arXiv:2508.09092. D
- [176] Quandela, “Quandela delivers Lucy, the most advanced photonic quantum computer worldwide, to EuroHPC and GENCI at CEA's TGCC,” Oct. 23, 2025. [Online]. Available: https://www.quandela.com/
about-us/ Cnewsroom/ quandela-delivers-lucy-the-most-advanced-photonic-quantum-computer-worldwide-to-eurohpc-and-genci-at-ceas-tgcc/ - [177] QuiX Quantum, “QuiX Quantum Delivers Carina Core Hardware Platform to DLR QCI, Advancing Europe's Universal Photonic Quantum Computing Roadmap,” Jul. 14, 2026. [Online]. Available: https://www.quixquantum.com/
news/ Cquix-quantum-delivers-carina-core-hardware-platformto-dlr-qci - [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. S
- [181] M. Abdel-Kareem, “PsiQuantum Secures $125 Million Expanded Agreement with DARPA under QBI Program,” Quantum Computing Report, Jul. 22, 2026. [Online]. Available: https://quantumcomputingreport.com/
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news/ Pinnovation/ psiquantums-stalled-quantum-plant-to-break-ground-after-location-switch/ - [186] M. Abdel-Kareem, “Photonic Inc. Reaches $2B Valuation with $200M Final Close,” Quantum Computing Report, May 12, 2026. [Online]. Available: https://quantumcomputingreport.com/
photonic-inc-reaches-2b-valuation-with-200m-final-close/ P - [337] E. Knill, R. Laflamme, and G. Milburn, “Efficient Linear Optics Quantum Computation,” Nature, vol. 409, pp. 46–52, Jun. 2000, doi: 10.1038/35051009. arXiv:quant-ph/0006088. D
- [338] J. C. Loredo et al., “Deterministic quantum dot single-photon sources: operational principles and state-of-the-art specifications,” Appl. Phys. Rev., vol. 13, no. 1, Mar. 2026, doi: 10.1063/5.0316046. arXiv:2511.23232. D
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about-us/ Cnewsroom/ quandela-secures-e50-million-to-support-international-expansion/
Русский текст загружается…
הטקסט בעברית נטען…
Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge)
Electron or hole spin in a lithographically gated dot; exchange gives deterministic ns-scale two-qubit gates on a CMOS die.
Verdict. Only carrier fabricated on a 300 mm line at scale, but two-qubit fidelity has sat at 99.0–99.6% on foundry devices for a year and no array above 12 qubits has published all-pairs numbers.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An electron or hole is trapped in an electrostatic well ~50 nm across, formed by metal gates over a Si/SiGe quantum well, an electron accumulation layer at the SiMOS Si/SiO₂ interface, or a Ge/SiGe hole gas. The spin is the computational degree of freedom; the barrier between neighbouring dots sets an exchange coupling J, and pulsing J for ħπ/J gives a deterministic entangling gate. Loss and DiVincenzo proposed the architecture in 1998; the first single-spin and singlet–triplet qubits in silicon appeared 2010–2012, the lineage date used here.
Attributes, as the graph record records them:
- a — affinity: 1.0, wholly fabricated; every dot is a lithography outcome.
- b — characteristic time: ~50 ns per operation, entangling deterministic via exchange, not heralded.
- c — readout: spin-to-charge conversion on an rf charge sensor, ~6 µs, non-destructive, mid-circuit capable.
- d — mobility: static, unless a separate shuttling mechanism is invoked.
- e — control: baseband gate voltages plus microwave or EDSR drive, electronics normally at room temperature.
- f — error structure as the code sees it: coherent, Pauli, and leakage into valley or charge states.
- g — manufacturing: CMOS.
Physics & limits
Three energy scales govern everything. Zeeman splitting (~10–100 µeV at 0.3–1 T) defines the qubit; exchange J, tunable over 10–100 MHz, defines the gate; valley splitting in silicon (0.1–0.3 meV, non-uniform because it tracks interface roughness) defines the leakage floor. Ge hole dots have no valley degeneracy and need no micromagnet, but their spin–orbit coupling turns electrical noise directly into dephasing.
Two baths set the coherence floor. Nuclear spins are suppressible: ²⁸Si enrichment gives Hahn-echo T2 of 1.31(4) ms on foundry material and Ramsey T2 of 41(2) µs D[197]. Charge noise is not — 1/f fluctuators in the oxide couple through exchange, so fidelity degrades exactly when J is on: the entangling interaction is also the dominant noise channel. Errors reach the code as coherent over-/under-rotation, Pauli dephasing, and leakage that repetition and surface codes miss without leakage reduction units (LRUs). HRL's dissection is the most useful single statement of where the error lives: about 80% of its CNOT error is extrinsic — control and calibration, not physics* D[190]. Moving the floor needs quieter dielectrics, more uniform valley splitting and better calibration, in that order of difficulty and the inverse order of cost.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: two-qubit fidelity 99.04–99.56% on a 300 mm foundry SiMOS device D[189]; 18 qubits in one array, twice, on different materials D[190]D[195]. Typical at scale is worse, and the gap is the story — imec's eight-qubit 300 mm device validated a two-qubit gate on one of four double-dot pairs D[197]. No device above 12 qubits has published all-pairs two-qubit fidelities on this platform.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2022-01 | 2Q 99.5% (gate-set tomography), Si/SiGe — first crossing of the surface-code threshold | QuTech/TU Delft | D[346] |
| 2024-03 | 2Q 98.9% at 1 K operating temperature | Diraq/UNSW | D[194] |
| 2025-09 | 2Q 99.04–99.56%, SPAM 99.9%, on 300 mm foundry SiMOS | Diraq + imec | D[189] |
| 2026-04 | 18-qubit Ge 2×N array; 1Q mean 99.8%, median 99.9% | Groove Quantum + QuTech | D[195] |
| 2026-05 | CZ between two moving spins, 98.86 ± 0.29%, 58 ns | QuTech/TU Delft | D[193] |
| 2026-07 | 8-qubit 300 mm device; Hahn-echo T2 1.31 ms; 2Q on 1 of 4 pairs | imec + Diraq | D[197] |
| 2026-07 | 18 exchange-only qubits from 54 dots; 1Q 2×10⁻⁴, CNOT 3×10⁻³; d=5 repetition code, 200 rounds, Λ₅/₃ = 4.7 | HRL Laboratories | D[190] |
The dominant error term today is not decoherence but calibration drift: 54 dots need hundreds of interdependent voltages, and the tune-up surface limits array size, not T2.
The first germanium array beyond a quasi-one-dimensional layout, a 6×6 hole-dot grid with one shared ('merged') barrier gate and individual plunger gates (QuTech, October 2026), formed 34 of its 36 dots, reached 30 coherently and ran 10 qubits placed sparsely, driven and read out five at a time; the sparse placement cut crosstalk 42× and gave simultaneous single-qubit Clifford fidelities above 99% P[898].
Manufacturing, materials & supply chain
The distinguishing claim is fabrication on unmodified CMOS lines — Intel reports >24,000 devices per 300 mm EUV wafer D[199] and 96% tune-up yield over 232 twelve-dot devices of one wafer D[766], and Quantum Motion characterised 1,024 dots in five minutes on GlobalFoundries 22FDX C[200]. Process detail belongs to the 300 mm CMOS foundry brief; wafer-scale statistics exist here and for no other carrier.
Materials are the exposure. Enriched ²⁸Si is a genuine single point of failure: ASP Isotopes began commercial production of enriched silicon-28 at its second Pretoria facility on 2025-03-27, with two undisclosed US customers C[347]. On 2026-07-16 the US DOE Office of Isotope R&D and Production announced that ORNL and PNNL now make silane at 99.9999% ²⁸Si and germane with Ge-73 below 1 ppm, "at least 100×" more depleted than any commercial material — a deliberate re-shoring G[348]. Ge/SiGe heterostructures come from a handful of academic reactors (Scappucci's group at Delft), a narrower bottleneck than the fab. Export-control exposure is indirect: the dies are ordinary CMOS, but enriched isotopes and dilution refrigerators fall under the 2024 multilateral quantum controls (US ECCN 3A901/3A904).
Control, readout & I/O burden
Baseband voltages plus a microwave or EDSR drive per qubit, and one rf reflectometry sensor per one-to-several dots. No lasers — the I/O problem is line count and heat. HRL's 4 K controller (≤3.5 W typical, 366 DACs, 296 lines) sequenced a full 18-qubit QEC experiment with no room-temperature real-time electronics D[190]; UNSW/Diraq have shown mK cryo-CMOS beside the qubits D[203]. Those controllers are the cryo-CMOS control brief's subject.
The wall is readout, not gates. At ~6 µs spin-to-charge conversion plus settling the cycle runs to hundreds of microseconds — three orders slower than the 50 ns gate, so the syndrome round sets the logical clock. At 10³ qubits line count is survivable only with crossbar shared-line addressing; at 10⁴ sensor count and dissipation dominate; at 10⁶ neither dedicated lines nor per-qubit sensors survive.
Role in the stack
The node sits on one architecture, Silicon / germanium quantum-dot spins. It requires a 300 mm CMOS foundry; it provides the dots consumed by exchange gates, exchange-only and singlet–triplet encoding, conveyor-mode spin shuttling, crossbar shared-line control and spin-to-charge readout. It replaces donor spins (SQC's precision-placed phosphorus), which buy 99.10–99.99% gates on 11 qubits D[192] at the cost of no foundry path — the switching price in one line.
Derived clock for the architecture = sum of the syndrome round: gate layers + transport + readout + reset = 8.5 µs, readout 6.3 µs of it and reset 1 µs. Everything the node enables is downstream of it, so a failure here has no fallback elsewhere. The neighbouring empty slot is fast sensor-free readout — Pauli spin blockade (PSB) below 1 µs at >99.9%; nothing in the graph fills it.
Evidence — how the numbers were measured
Headline two-qubit numbers come from interleaved randomised benchmarking or gate-set tomography on the best pair on the die — a legitimate protocol reporting an illegitimate summary, capturing neither crosstalk nor calibration drift. HRL's d=5 repetition code over 200 rounds is the only spin result measuring error in situ under continuous operation, and its Λ₅/₃ = 4.7 D[190] is bit-flip-only, not below-threshold logical memory, which no spin platform has shown.
Conflicts. Diraq's messaging conflicts on scale: a 2026-07-09 release said "thousands of qubits by 2029", the 2026-08-27 roadmap says 150,000 physical and 1,000 logical by 2029 R[211]fact; take the roadmap as the company's position and the discrepancy as evidence about the company. No replication of the 300 mm two-qubit result outside the imec line exists.
On a single-hole Ge/SiGe qubit (T2 = 136 ns, Rabi frequency 19 MHz) the same idle gate scores 99.21(3)% by interleaved randomised benchmarking but 97.48(9)% by gate-set tomography, whose sequences contain long runs of consecutive idles that exceed T2, while the X/2 and Y/2 gates agree within 0.3 points (99.81% and 99.88% by gate-set tomography) P[888]. An idle or memory figure for this carrier is meaningful only with its protocol named.
SemiQon's €17.5 M comes from paywalled trade press with the round type unstated P[354]P[352], and Groove Quantum's €16 M (2026-04-30) has no primary source Pfact. The PatSnap dataset (~60 records) omits HRL, imec, Diraq and Quantum Motion, so it is a sample, not a census P[356]. Not published: SemiQon's cumulative funding and the PostScriptum amount; Groove Quantum's investors; the value of the IBM–HRL deal, and any dated spin milestone on IBM's roadmap C[204]; and ASP Isotopes' enrichment level, capacity and customers, with the DOE quantities and funding C[347]G[348].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Diraq | developer | AU | SiMOS qubits on imec 300 mm; 2Q 99.04–99.56%; 1 K operation | D[189]D[194] |
| HRL Laboratories | developer | US | Exchange-only SiGe, 18 qubits, self-sequenced d=5 QEC | D[190] |
| IBM | investor | US | Acquired HRL; adds spins to a superconducting roadmap | C[204] |
| Intel | developer | US | 300 mm EUV spin devices; 12-qubit Tunnel Falls at Argonne | D[199]P[207] |
| Quantum Motion | developer | UK | 22FDX dots; full-stack CMOS system delivered to NQCC | C[200] |
| QuTech (TU Delft) | research | NL | Shuttled-spin gates, parity checks, Ge heterostructures | D[193]D[349] |
| Groove Quantum | developer | NL | 18-qubit Ge array, spun out of the Delft Ge programme | D[195] |
| Quobly | developer | FR | ²⁸Si FD-SOI lots at ST Crolles since 2025-12 | C[350] |
| Equal1 | developer | IE | Six-qubit rack unit, sold as Bell-1 and since May 2026 as RacQ; installed at ESA Frascati in July 2026 | C[351] fact fact |
| SemiQon | supplier | FI | VTT spin-out; cryo-CMOS chips fabricated in Espoo | P[352] |
| GlobalFoundries | supplier | US | Quantum Technology Solutions unit; 22FDX wafers | C[353] |
Money.
- 2025-02-24 · SemiQon · round · €17.5 M (€15 M equity + €2.5 M grant) · European Innovation Council · closed P[354]
- 2025-11-06 · Diraq, Quantum Motion, SQC · DARPA QBI Stage B · up to $15 M each · DARPA · three of eleven · announced fact[65]
- 2026-01-15 · Equal1 · round · $60 M · ISIF · >$85 M cumulative · closed Cfact[351]
- 2026-04-30 · Groove Quantum · round · €16 M · undisclosed · €26 M cumulative · closed Pfact
- 2026-05-07 · Quantum Motion · Series C · $160 M · DCVC, Kembara · closed C[355]
- 2026-05-21 · Diraq · US CHIPS letter of intent · up to $38 M · Dept of Commerce · LOI G[300]
- 2026-05-21 · GlobalFoundries · US CHIPS LOI, multi-modality quantum foundry · $375 M · Dept of Commerce · LOI G[300]C[353]
- 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · €134 M cumulative · closed C[350]
- 2026-06 · Silicon Quantum Computing · NRFC (donor route) · A$60 M · Australia NRFC · closed fact
- 2026-07-03 · SemiQon · strategic investment · undisclosed · PostScriptum · closed P[352]
- 2026-08-26 · IBM / HRL · M&A completed (announced 2026-07-23) · terms undisclosed · sellers Boeing and General Motors, still application partners · definitive C[204]
Market & supply chain. Nobody sells spin qubits; the sold goods are foundry runs, enriched isotopes and cryo-electronics. Foundry access is bought from imec, GlobalFoundries and STMicroelectronics, with GF productising it as a business unit in 2026 and naming Diraq, Equal1 and Quantum Motion as customers C[353]. Isotope supply is the concentrated risk — one commercial producer of scale plus a restarted US national-lab capability C[347]G[348]. Diraq's "<$1/qubit at two million qubits" R[211] is a projection, not a price. What pays today is G3 (HRL's QEC work, QBI Stage B) and G7 (Quantum Motion at NQCC, Equal1 at ESA); nothing here is bought for G1, G2 or G5.
IP & standards. The one dated database view available — a PatSnap analysis of 2026-06-02, updated 2026-08-21 — is thin: ~60 records 2005–2026, with NewSouth Innovations (UNSW, Diraq's licensing root) largest at five filings, ahead of SIAT/SIMIT, MIT, Intel and SQC P[356]. Too small to be a census. No litigation is on record, no spin-specific standards body exists, and HRL's controller IP is now unpublished inside IBM.
Roadmaps & track record. Diraq (promised 2026-08-27 · for 2029 · 150 k physical / 1 k logical, >2 M by 2031) — six weeks earlier it said "thousands by 2029" R[211]: keep the fidelities, discount the counts. Quobly (2026-06 · for 2032 · millions of qubits) — funded and fabbing at ST, no published multi-qubit device: an intention. SQC (for 2033 · commercial scale) — real 11-qubit donor result D[192], unfalsifiable until 2030. Quantum Motion — the only actor to have delivered a system to a customer on schedule C[200]. Intel — 12 qubits at Argonne, no successor chip and no dated roadmap as of 3 Sep 2026 P[207]: alive but unguided. IBM/HRL — no spin milestone yet on Starling (2029) or Blue Jay (mid-2030s) C[204].
Strategic reading. If the platform succeeds the winners are foundries and isotope suppliers, not qubit designers: a SiMOS qubit is a process recipe, and once qualified the marginal die is cheap and differentiation moves to calibration software. That is why IBM bought HRL — not for 18 qubits but for a cryo-CMOS control stack and packaging reusable across modalities: a supplier acquisition dressed as a platform bet. The losers are pure-play spin startups, whose bargaining power against a foundry that has just productised quantum manufacturing is falling. Manufacturability is the platform's only defensible argument, and if 2Q fidelity is still 99.0–99.6% through 2027 with arrays under 20 qubits, it stops being enough.
Outlook & open questions
Confirm if by end-2027 a group publishes all-pairs two-qubit fidelities above 99% on a ≥16-qubit array, or a spin device shows below-threshold logical memory in a distance-3-to-5 surface code, or IBM places a dated spin milestone on its public roadmap. Demote if foundry two-qubit fidelity is still 99.0–99.6% in mid-2027, if Intel makes no further spin announcement, or if Diraq revises its 2029 figure downward a second time.
Best case by 2029: a few hundred physical qubits on a qualified 300 mm process with shared-line control and a working logical memory — two orders of magnitude short of Diraq's 150 k. Worst case: the platform stays a foundry demonstration, the startups consolidate into IBM, GlobalFoundries and STMicroelectronics, and spin qubits become a control-electronics business with qubits attached.
Open questions. (1) Is 99.5%-class two-qubit fidelity reproducible across all pairs of a die, or only the pair that tunes up? (2) Can valley splitting be made uniform enough that leakage stops being a per-device lottery? (3) Does readout get below 1 µs without a charge sensor per qubit? (4) Did IBM buy a qubit or a control stack?
References
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הטקסט בעברית נטען…
Bosonic cavity mode
A harmonic microwave mode of a 3D or planar superconducting resonator used as the qubit carrier; its error is structured photon loss, not generic Pauli noise.
Verdict. Laboratory memories reach 25.6 ms photon lifetime, but working bosonic devices run two to three orders shorter; the carrier's limit is the ancilla coupled to it, not the cavity.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The quantised harmonic mode of a machined 3D or planar superconducting resonator, driven and read out dispersively through a coupled transmon ancilla. Yale's 3D circuit-QED work made it a carrier in 2013: Q > 0.5×10⁹, 10 ms single-photon lifetime in aluminium D[318]. Readout is ancilla-mediated at ~1 µs, non-destructive, mid-circuit capable; the carrier is fabricated, bus-connected, room-temperature microwave driven.
Physics & limits
A harmonic mode's dominant decay channel is amplitude damping alone — the whole argument for bosonic codes, since an encoding can target one known channel instead of an unstructured Pauli basis. Loss scales linearly with occupation, so κ caps the bias any cat encoding can reach. The floor is surface two-level systems, seam conductance and radiative leakage: 25.6 ms lifetime, 34 ms coherence (Weizmann, 2023), from a geometry that "couples minimally to the control qubit" D[319]. That phrase is the limit — a mode whose ancilla is driven hard inherits its dephasing, and Nord Quantique's working GKP mode runs T1 = 360 µs D[82]. Moving it means ancilla decoupling and surface treatment.
Engineering state of the art
table
Typical at scale is far below best: 18 cat modes (Helium), five storage modes (Ocelot) C[87]D[80]. The dominant operating term is ancilla-induced dephasing plus gate-visible loss, the 0.5%-per-gate erasure being that loss detected D[84].
The 25.6 ms and 34 ms Weizmann figures come from a single group, with no independent replication. Helium's "up to 200× lower hardware requirements" is a company claim with no logical-level data behind it C[87]. Not published: the material (aluminium or niobium) of the Weizmann cavity, and a quality factor for the λ/4 coaxial bodies of the 2026-08 dual-rail CZ [84].
Manufacturing, materials & supply chain
Two routes make the mode. Machined bodies of aluminium or niobium, polished and sealed, hold Nord Quantique's GKP mode and D-Wave's λ/4 dual-rail pairs D[82]D[84]; such a mode occupies cm scale against a transmon's ~100 µm — that ratio, not Q, is the liability. The cat chips are planar: Alice & Bob's are tantalum-on-sapphire circuits, Boson 3's memory a quarter-wave coplanar resonator fact, and Ocelot's modes are coplanar-waveguide resonators on two bump-bonded dies D[80]. Per mode the burden is one drive line plus an ancilla with its own drive and readout chain — at Alice & Bob, a buffer mode and its pumps instead of the ancilla Cfact. No cryogenic-CMOS or on-chip multiplexing of cavity control exists, so lines grow linearly: at 10³ modes the wall is coax count and cryostat volume in one dilution unit; 10⁴–10⁶ needs different packaging. Machining is in-house at every vendor that machines bodies; no third-party foundry and no cavity-specific export rule were found. Concentration sits around it: Bluefors refrigerators, Cryomech pulse tubes included fact.
Role in the stack
Requires one of two manufacturing routes, machined 3D cavities or planar superconducting lithography; provides the mode for cat and GKP encodings, dual-rail erasure, ancilla-mediated gates and dispersive readout. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 2.8 µs on the dual-rail erasure architecture, four 500 ns CZ layers over a ~0.4 µs check D[84], and 1.44 µs on the cat-and-GKP cavity architecture, gate-set, against its measured 2.8 µs cycle D[80]. Verification: the 25.6/34 ms figures are single-group and unreplicated D[319]; the dual-rail CZ's Pauli error is post-selected, and its Λ ≈ 27 is simulated, not measured Sfact.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Alice & Bob | developer | FR | 18-cat-mode Helium system, ~40 kW, sold to GENCI | C[87] |
| D-Wave | developer | US | λ/4 coaxial cavity dual-rail qubits, via Quantum Circuits | D[84] |
| AWS | developer | US | Ocelot: five storage modes, four ancillas, five buffers | D[80] |
| Nord Quantique | developer | CA | Multimode cavity GKP, T1 360 µs | D[82] |
| Weizmann Institute | research | IL | Cavity memory record holder | D[319] |
Money.
2026-01-20 · D-Wave · M&A of Quantum Circuits · $550 M · — · closed fact
2026-08-06 · D-Wave · Q2 report · $9.3 M acquisition cost, $2.3 M inherited bookings · reported fact
2026-05-18 · Nord Quantique · growth equity · $30 M at $1.4 B · — · closed C[89]
Market & supply chain. Nobody sells cavities; the money is downstream in fridges and amplifiers. Unit economics are unpublished — Helium's ~40 kW for 18 modes is a whole-system figure C[87]. G3 pays here, G4 does not at cm scale.
IP & standards. No dated patent family specific to the cavity mode was found; Amazon's US 11,748,652 B1 covers the layer above fact.
Roadmaps & track record. Alice & Bob delivered Helium 2026-06 as promised, without logical data C[87]. D-Wave promises DR17 (2026), DR49 (2027), DR181 (2028), 10 logical (2030), 100 logical (2032) at Λ = 10 Rfact. Both ship on time and defer the numbers that matter.
Strategic reading. If cavity modes stay the best-structured error channel in superconducting hardware, their vendors trade error quality for fewer physical qubits; if planar dual-rail or on-chip GKP match those erasure fractions, cm-scale bodies lose on density and the branch narrows to a memory niche.
Outlook & open questions
Confirm by 2028 if an operating multi-mode device holds photon lifetime above 1 ms; demote if operating lifetimes stay near 10² µs while planar erasure qubits close the gap. Best case 2029: multiplexed control, sub-cm bodies; worst case, single-digit-mode demonstrators indefinitely. Open: how much operating dephasing is ancilla-borne; will anyone publish Q for the λ/4 bodies? Watch Alice & Bob logical data and DR49.
References
- [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [82] S. Turcotte et al., “Quantum error correction of a grid-state qubit with state preparation and measurement errors below 10⁻³,” arXiv:2607.06718, Jul. 2026. D
- [84] N. Mehta et al., “An entangling gate for dual-rail erasure qubits,” Nature, vol. 656, no. 8126, pp. 47–53, Aug. 2026, doi: 10.1038/s41586-026-10822-y. arXiv:2503.10935. D
- [87] N. Coppola, “Alice & Bob Unveils First Quantum System, Helium,” Alice & Bob, Jun. 10, 2026. [Online]. Available: https://alice-bob.com/
newsroom/ Calice-bob-unveils-first-quantum-system/ - [89] Nord Quantique, “Nord Quantique Reaches $1.4 Billion USD Valuation with Latest Investment,” Business Wire, May 18, 2026. [Online]. Available: https://www.businesswire.com/
news/ Chome/ 20260518358351/ en/ Nord-Quantique-Reaches-$1.4-Billion-USD-Valuation-with-Latest-Investment - [318] M. Reagor et al., “Reaching 10 ms single photon lifetimes for superconducting aluminum cavities,” arXiv:1302.4408, Feb. 2013. D
- [319] O. Milul et al., “Superconducting Cavity Qubit with Tens of Milliseconds Single-Photon Coherence Time,” PRX Quantum, vol. 4, no. 3, Art. no. 030336, Sep. 2023, doi: 10.1103/PRXQuantum.4.030336. D
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הטקסט בעברית נטען…
Fluxonium
Josephson-junction-array-shunted superconducting qubit at 0.2–1 GHz with large anharmonicity and long T1, bought at the price of a flux-bias line per qubit.
Verdict. Best two-qubit number on any superconducting carrier (99.94% CNOT, 60 ns, stable 24 days) yet nobody's product carrier as of 2026-09-04; it wins only if cold flux control arrives before transmon couplers close the gap.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A superconducting circuit shunted by a large junction-array inductance, putting the 0→1 transition at 0.2–1 GHz with gigahertz anharmonicity; Manucharyan, Koch, Glazman and Devoret, 2009. Charge dispersion vanishes.
Attributes: fabricated carrier; deterministic entangling ~50 ns (10^-7.3 s); dispersive readout ~0.3 µs, non-destructive, mid-circuit-capable.
Static mobility; low-frequency flux control at room temperature; Pauli plus coherent error; superconducting lithography.
Physics & limits
Dielectric loss scales with ω, so T1 of 160–260 µs at ~300 MHz is routine where a transmon fights the same bath at 5 GHz D[39]. But kT/h ≈ 420 MHz at 20 mK: equilibrium leaves tens of percent in |1⟩, making active reset (~98% D[315]) mandatory. The floor is 1/f flux dephasing — T2* 20–110 µs against those T1 D[39], [316] — second-order at the sweet spot and untunable. In the record CNOT the dominant term is instead coherent: off-resonant control-qubit flips, residual error below 2×10⁻⁴ D[39]. A quieter bias generated closer to the chip is what moves the floor.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2023-09-25 | CZ 99.922 ± 0.009% (RL-optimised mean) | MIT / MIT Lincoln Lab | D[40] |
| 2024-07-22 | CNOT 99.94% in 60 ns, >99.9% for 24 days uncalibrated | Maryland–EPFL–UMass–Wisconsin | D[39] |
| 2025-01-14 | Single-qubit gate 99.998% | MIT EQuS | D[317] |
| 2026-01-23 | On-chip flux-DAC control, T1 ≈ 200 µs preserved | D-Wave | D[316] |
All one- or two-qubit devices; no fluxonium lattice or QEC cycle exists as of 2026-09-04.
D-Wave quotes 200 bias wires (2026-01-06) and ~300 bias lines (2026-01-23) for the same annealer scheme fact. Not published: the gate duration of MIT's 99.922% CZ, which the PRX abstract does not state, and a dated fluxonium-specific patent family.
Manufacturing, materials & supply chain
Same Nb/Al junction lithography as transmon, inheriting its foundries and its TLS problem; record devices come from MIT Lincoln Laboratory and no merchant supplier exists. The I/O cost is drive, readout and a flux line per qubit: a fridge carries a few hundred DC bias lines, so the burden bites at 10³, and at 10⁴–10⁶ the bias must be generated cold. D-Wave flip-chips a multiplexed Φ-DAC die across a ~7 µm gap at 10 mK with no resolvable added decoherence (T1 ≈ 200 µs D[316]), key parts from NASA JPL C[281]; Shenzhen runs XY and Z down one warm line per qubit D[315]. Export exposure is generic superconducting (US EAR ECCN 3A901).
Role in the stack
A drop-in Layer-1 alternative on the transmon lattice with tunable couplers, replacing transmon where coherence beats control simplicity; nothing downstream requires it. Its 60 ns gate does not set the derived clock — dispersive readout at ~0.3 µs does, as for transmon — so fluxonium buys error, not speed. Verification: the headline numbers are RB averages on isolated pairs, blind to lattice crosstalk, flux drift and fluxon leakage, and 99.94% is unreplicated; the main report's 99.92% record D[40] is superseded by it, and 99.922% is itself an RL-optimised mean (unassisted peaks 99.85–99.9%).
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| developer | US | Absorbed Atlantic Quantum's fluxonium team; silent since | P[55] | |
| D-Wave | developer | US | On-chip Φ-DAC control of a fluxonium | D[316] |
| University of Maryland | research | US | Manucharyan-group 99.94% CNOT | D[39] |
| S Lab, Shenzhen | research | CN | Single-channel unified flux control | D[315] |
Money.
2025-10-03 · Google · acquisition of Atlantic Quantum · terms undisclosed · closed P[55]fact
2025-11-06 · Atlantic Quantum · absent from QBI Stage B (11 teams, ≤ $15 M each) · DARPA · official fact
2026-08-06 · D-Wave · H1-2026 revenue $5.9 M, cash $546.2 M · reported C[15]fact
Market & supply chain. No commercial supply chain: transmon's kit plus cryogenic DAC/SFQ control, built only in-house (D-Wave) or at government laboratories (JPL, MIT Lincoln Laboratory) — a single point of failure on the one scalable control path. Pays for G3/G4 and G7.
IP & standards. No dated fluxonium-specific patent family found as of 2026-09-04; PatSnap's 2026-06-30 superconducting-device counts are not broken out by carrier Pfact.
Roadmaps & track record. Atlantic Quantum (2025-04 · fluxonium machine under QBI · absorbed, no roadmap survives). D-Wave (2026-06-01 · DR17/DR49/DR181 · dual-rail cavity qubits, not fluxonium Pfact) — its fluxonium work is control IP with no product attached.
Strategic reading. The advantage over a good transmon is thin — Toshiba's double-transmon coupler gives CZ 99.90% in 48 ns D[37] — so fluxonium wins only if cold flux control lands first. Then cryogenic-control vendors and die-bonding capacity capture the value and power sits with the control-chip supplier, not the qubit fab.
Outlook & open questions
Confirm by end-2027: a ≥ 4-qubit fluxonium under on-chip flux control with published two-qubit RB, or a replication of 99.94%; demote if neither appears. Best case 2029: 2Q error near 10⁻⁴ cuts the surface-code budget for a given Λ; worst case, switching noise from the control die eats the coherence advantage. Does the flux-noise floor survive multiplexing? Can 0.2–1 GHz readout reach 99.5% in a lattice? What became of the Atlantic Quantum team?
References
- [15] D-Wave Quantum Inc., “D-Wave Reports Second Quarter 2026 Results,” Aug. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-reports-second-quarter-2026-results/ - [37] R. Li, K. Kubo, Y. Ho, Z. Yan, Y. Nakamura, and H. Goto, “Realization of High-Fidelity CZ Gate Based on a Double-Transmon Coupler,” Phys. Rev. X, vol. 14, no. 4, Art. no. 041050, Nov. 2024, doi: 10.1103/PhysRevX.14.041050. arXiv:2402.18926. D
- [39] W.-J. Lin, H. Cho, Y. Chen, M. G. Vavilov, C. Wang, and V. E. Manucharyan, “24 days-stable CNOT-gate on fluxonium qubits with over 99.9% fidelity,” arXiv:2407.15783, Jul. 2024. D
- [40] L. Ding et al., “High-Fidelity, Frequency-Flexible Two-Qubit Fluxonium Gates with a Transmon Coupler,” Phys. Rev. X, vol. 13, no. 3, Art. no. 031035, Sep. 2023, doi: 10.1103/PhysRevX.13.031035. D
- [55] M. Swayne, “Atlantic Quantum Joins Google Quantum AI,” The Quantum Insider, Oct. 3, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P10/ 03/ atlantic-quantum-joins-google-quantum-ai/ - [281] D-Wave, “D-Wave Demonstrates First Scalable, On-Chip Cryogenic Control of Gate-Model Qubits,” Jan. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-demonstrates-first-scalable-on-chip-cryogenic-control-of-gate-model-qubits/ - [315] X. Pan et al., “Unified Flux Control Architecture for Fluxonium Qubits,” arXiv:2605.25948, May 2026. D
- [316] D-Wave Quantum Inc., “Digital control of a high-coherence fluxonium qubit,” D-Wave Quantum Inc., Jan. 2026. [Online]. Available: https://www.dwavequantum.com/
media/ D41upubz2/ 14-1090a-a_fluxonium-dac-control.pdf - [317] S. Miller, “Fast control methods enable record-setting fidelity in superconducting qubit,” MIT News, Jan. 14, 2025. [Online]. Available: https://news.mit.edu/
2025/ Dfast-control-methods-enable-record-setting-fidelity-superconducting-qubit-0114
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הטקסט בעברית נטען…
rf-SQUID flux qubit (annealer)
Superconducting double-well loop used as a programmable Ising spin in D-Wave's annealers; no gate set, no code.
Verdict. No D-Wave beyond-classical claim has survived rebuttal as of 4 Sep 2026; falsified if one holds through 2028, confirmed as sampler-not-solver if erosion repeats.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A superconducting loop with a compound Josephson junction: flux bias sets barrier and tilt; the two circulating-current states are an Ising spin. D-Wave's line, D-Wave One (2011) through Advantage2 (GA 2025-05-20: 4,400+ qubits, Zephyr degree-20, 12.5 kW) P[220], rests on it. No gate set, only a programmable transverse-field Ising Hamiltonian, sampled.
Fabricated carrier; ~3 ns characteristic time, no deterministic entangling operation; dispersive readout ~1 µs, non-destructive, not mid-circuit.
Degree-20 coupling; low-frequency flux control at mK; Pauli plus coherent error; superconducting lithography.
Physics & limits
Tunnelling amplitude and persistent current set the well. Landau–Zener demands a sweep slow against the square of the minimum gap, which for hard instances closes exponentially in size: the first floor is combinatorial, not material. The thermal floor binds sooner: at 15–20 mK kT is a few hundred MHz, so below that gap the chip equilibrates with its bath and emits a quasi-Boltzmann sample, not a ground state. 1/f flux noise dephases in the energy eigenbasis, making diabatic loss indistinguishable from a hard gap. Colder stages, larger persistent current or nanosecond quenches move the floor.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2021-09 | Zephyr topology, degree 20 | D-Wave | fact |
| 2025-03 | Beyond-classical claim — quench dynamics, not optimisation | D-Wave | D[221] |
| 2025-05-20 | Advantage2 GA: 4,400+ qubits, 12.5 kW | D-Wave | P[220] |
| 2025–26 | Eroded by belief-propagation tensor networks; t-VMC | Tindall et al.; Mauron & Carleo | D[222]; D[223] |
Dominant error: thermal excitation near the minimum gap.
D-Wave gives 200 bias wires in its 2026-01-06 release and ~300 in whitepaper 14-1090A-A (2026-01-23), the latter tied to a described array. The scope of the SkyWater relationship rests on nine EDGAR full-text hits in D-Wave's 10-Ks, not a quoted sentence. ECCN 4A906 states its threshold in two-qubit gate error; no ruling says whether an annealer falls inside it. Not published: the identity of D-Wave's Fortune-100 QCaaS customer and of the defence end-customer behind the Anduril/Davidson study.
Manufacturing, materials & supply chain
Nb/Al multilayer superconducting lithography, the transmon fabs' family. The FY2024 10-K cites third-party foundries with a demonstrated second source; EDGAR returns nine SkyWater mentions in D-Wave 10-Ks 2023–26 fact, and SkyWater is IonQ-owned since 2026-07-31 fact — that source sits inside a competitor. The real asset is I/O: multiplexed on-chip flux DACs hold room-temperature line count at O(100) for tens of thousands of qubits and couplers, versus O(qubits) for gate machines — though D-Wave quotes 200 bias wires (2026-01-06) and ~300 (whitepaper, 2026-01-23), unreconciled Cfact. The wall at 10⁴–10⁶ spins is minor-embedding overhead and the 12.5 kW cryoplant, not wiring. ECCN 4A906 keys on two-qubit gate error, undefined here; 3A904 refrigerators bite instead G[301].
Role in the stack
Serves the annealing architecture only and feeds no gate-model architecture: D-Wave's gate roadmap runs on acquired Quantum Circuits dual-rail hardware, a different carrier Cfact. The transfer runs the other way: the flux-DAC chip now drives fluxonium, key parts made at NASA JPL C[281]. No derived clock applies, nor randomised benchmarking or quantum volume, so every headline is time-to-solution against a classical solver. The March 2025 claim was eroded within weeks [222], [223]; D-Wave's counter (arXiv:2508.15759) inverts the burden, using the QPU as ground truth to argue tensor-network scaling extrapolations are unreliable P[224]. Unresolved as of 4 Sep 2026.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| D-Wave Quantum | developer | US/Canada | Sole annealer vendor; Advantage2, Leap | C[15] |
| US Dept of Commerce | investor | US | $100 M CHIPS letter of intent | fact |
| Anduril Industries | user | US | Stride solver on Advantage2 | Pfact |
| Florida Atlantic University | user | US | $20 M campus Advantage2 | P[372] |
| NASA JPL | supplier | US | Made flux-DAC chip parts | C[281] |
Money. 2026-01-20 · D-Wave · M&A, Quantum Circuits · $550 M USD · closed Cfact. 2026-01-27 · FAU sale · $20 M USD · announced P[372]. 2026-01-27 · QCaaS, Fortune 100 · $10 M USD · announced C[373]. 2026-05-21 · CHIPS LOI · $100 M USD · Commerce · non-binding fact. 2026-08-06 · H1-2026 · revenue $5.9 M (−67% YoY), bookings $35.5 M (+1,120%), RPO $40.7 M · reported C[15].
Market & supply chain. One vendor, one carrier, one cryoplant class; foundry capacity shared with gate-model lines. Only G1 and parts of G5 pay for it; G3/G4 cannot, absent a code layer.
IP & standards. PatSnap's landscape published on 2026-06-30 counts 975 D-Wave quantum patent families Pfact; no annealing-specific litigation or standard found.
Roadmaps & track record. (2025-05 · for 2029/2031 · 20,000 then 100,000 qubits · open) R[15]. Scale milestones land on schedule; claims do not survive classical solvers; revenue collapsed while bookings and RPO rose, so monetisation is deferred, not lost.
Strategic reading. D-Wave wins if buyers keep paying for good-enough sampling on cheap I/O, loses if error-mitigated gate machines take the optimisation budget — which is why it bought a gate carrier. Pricing power over customers, none over foundries.
Outlook & open questions
Confirm if a claim on a scientifically posed instance class survives a classical round through 2027; demote if erosion repeats. Best case 2029: 20,000 qubits and a defended claim; worst case, the line freezes at Advantage2 while the gate pivot absorbs the cash. Open: does any instance resist belief propagation and t-VMC?
References
- [15] D-Wave Quantum Inc., “D-Wave Reports Second Quarter 2026 Results,” Aug. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-reports-second-quarter-2026-results/ - [220] M. Swayne, “D-Wave Announces General Availability of Advantage2 Quantum Computer,” The Quantum Insider, May 20, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P05/ 20/ d-wave-announces-general-availability-of-advantage2-quantum-computer/ - [221] A. D. King et al., “Beyond-classical computation in quantum simulation,” Science, vol. 388, pp. 199–204, 2025, doi: 10.1126/science.ado6285. arXiv:2403.00910. D
- [222] J. Tindall, A. Mello, M. Fishman, M. Stoudenmire, and D. Sels, “Dynamics of disordered quantum systems with two- and three-dimensional tensor networks,” Science, vol. 392, pp. 868–872, 2026, doi: 10.1126/science.adx2728. arXiv:2503.05693. D
- [223] L. Mauron and G. Carleo, “Challenging the Quantum Advantage Frontier with Large-Scale Classical Simulations of Annealing Dynamics,” arXiv:2503.08247, Mar. 2025. D
- [224] A. Nocera, J. Raymond, W. Bernoudy, M. H. Amin, and A. D. King, “Evaluating classical simulations with a quantum processor,” arXiv:2508.15759, Aug. 2025. P
- [281] D-Wave, “D-Wave Demonstrates First Scalable, On-Chip Cryogenic Control of Gate-Model Qubits,” Jan. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-demonstrates-first-scalable-on-chip-cryogenic-control-of-gate-model-qubits/ - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [372] M. Abdel-Kareem, “D-Wave Announces HQ Relocation, $20M System Sale, $10M Fortune 100 Deal, and Dual-Platform Advancements,” Quantum Computing Report, Jan. 27, 2026. [Online]. Available: https://quantumcomputingreport.com/
d-wave-announces-hq-relocation-20m-system-sale-and-defense-performance-breakthroughs/ P - [373] D-Wave Quantum, “D-Wave Announces $10 Million, Two-Year Enterprise QCaaS Agreement with Fortune 100 Company,” Jan. 27, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-announces-10-million-two-year-enterprise-qcaas-agreement-with-fortune-100-company/
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הטקסט בעברית נטען…
Squeezed light mode (CV)
A continuous-variable optical mode with one quadrature below vacuum noise; the carrier for GKP and cluster-state photonics, where integration loss, not nonlinearity, sets the ceiling.
Verdict. Real: 1.4 dB directly measured on TFLN, 15 dB in bulk optics. Unproven: GKP effective squeezing beyond 0.62 dB on chip against ~9.75 dB needed. Demote if no on-chip GKP figure above 2 dB by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An optical mode whose vacuum fluctuations are redistributed between conjugate quadratures by a parametric process — down-conversion in a χ⁽²⁾ medium or four-wave mixing in a χ⁽³⁾ one (SiN): one quadrature drops below vacuum noise, the other rises. Predicted in the 1970s, first observed in 1985; the lineage that matters is waveguide squeezers feeding CV cluster states and GKP encoding. Attributes: flying carrier, heralded generation at ~1 µs; readout by single-photon detection at ~10 ns, destructive, not mid-circuit; electro-optic room-temperature control, Gaussian-plus-loss errors, photonic-IC fabrication.
Physics & limits
Squeezing is a loss thermometer: the medium can produce arbitrarily strong quadrature reduction, but every dB of loss between generation and detection pulls the measured value toward vacuum, so the number describes the optical path, not the squeezer. Hence 15 dB in bulk optics D[344] against 1.4 dB measured on chip, over 10 dB once a 4 dB homodyne loss budget is subtracted D[345]. Do not conflate raw quadrature squeezing with the effective squeezing of a GKP grid state, which folds in non-Gaussian preparation fidelity as well as loss: fault tolerance prices the latter at ~9.75 dB against 0.62 dB on chip D[174]. Only lower loss, better coupling and higher detection efficiency move it.
The molecular vibronic-spectrum application of Gaussian boson sampling with squeezed light is a linear statistic of the output; the characteristic function of displaced squeezed vacuum is computable exactly in polynomial time, so the spectrum is classically estimable to the experiment's additive accuracy P[889].
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2016 | 15 dB squeezing, bulk optics | Vahlbruch et al., Hannover | D[344] |
| 2025-06 | On-chip GKP effective squeezing 0.62 dB vs ~9.75 dB required | Xanadu | D[174] |
| 2025-08 | 1.4 dB measured on poled TFLN, >10 dB inferred at 62 mW pump | Shi et al. | D[345] |
| 2026-08 | Loss 24.1× above threshold, 1.0× targeted 2030 | Xanadu | R[178]fact |
The on-chip-to-bulk gap is ~13 dB, the GKP gap ~9 dB.
Shi et al.'s 1.4 dB, measured on PPLN TFLN [345], is an independent on-chip squeezing figure; the 0.62 dB GKP effective squeezing rests on Xanadu alone. The >10 dB TFLN figure is loss-corrected, not measured, and stated at one pump power, so it is not comparable with the 15 dB bulk-optics measurement. The ~9.75 dB fault-tolerance requirement, rounded to ~10 dB in the main report, has no single primary source. Xanadu's CAD 195 M and USD 686 M both come from its 2026-08-31 release, not an audited filing.
Manufacturing, materials & supply chain
Squeezers ride the CV photonic-IC line — SiN and thin-film lithium niobate with periodic poling. Merchant TFLN supply is thin: HyperLight (USD 37 M Series B, 2024-09) and Lightium (USD 7 M seed) Pfact, plus the PIXEurope pilot line fact. Xanadu builds rather than buys; no cost per squeezer is public. Poling uniformity and waveguide loss are the yield-limiting defects, both acting on the headline dB. I/O is one pump and one homodyne chain per mode plus phase locking; Aurora ran 35 chips at 12 modes on a 1 MHz cycle D[173]. At 10³ modes the wall is pump distribution and phase stability; at 10⁴–10⁶, detector and DAC channel count. No ECCN names squeezers; 4A906 catches the machine fact.
Role in the stack
Architectures: the continuous-variable photonic GKP architecture and the boson sampler, primary carrier in both. The register lists 7 machines using it, among them Aurora, Borealis and the Jiuzhang line up to 4.0. Requires a photonic-IC foundry; provides the modes for CV Gaussian gates with GKP-assisted non-Gaussian operations and for GKP grid encoding on Xanadu's architecture. It replaces discrete photons as carrier — DV trades erasure-dominated errors for Gaussian-plus-loss ones, and switching costs the whole detector chain. Squeezing level sets the error floor of every CV operation, bounding the derived clock indirectly rather than contributing a gate time. Verification: 0.62 dB is single-source and unreplicated; the independent TFLN result measures raw squeezing, and its ">10 dB" is inferred by subtracting detection loss D[345].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Xanadu | developer | CA | Only actor fielding on-chip CV/GKP systems | D[174] |
| HyperLight, Lightium | supplier | US, CH | TFLN chips and foundry service | Pfact |
| DARPA | investor | US | QBI Stage B, up to USD 15 M | fact |
| Government of Canada | investor | CA | CAD 195 M, Toronto factory | fact |
Money.
2025-11-06 · Xanadu · DARPA QBI Stage B · up to USD 15 M · announced fact
2026-03-26 · Xanadu · SPAC with Crane Harbor · ~USD 302 M gross, ~40% below plan · closed Cfact
2026-08-28 · Xanadu · Canadian factory funding · CAD 195 M · confirmed fact
Market & supply chain. No merchant squeezer exists; upstream the tradable goods are TFLN wafers and poling from two small vendors — concentration risk for anyone not vertically integrated. Only G3/G4 pay for squeezing quality.
IP & standards. No dated patent family specific to on-chip squeezers as of 4 Sep 2026, and no standard defines how effective squeezing is reported.
Roadmaps & track record. (2026-08-31 · loss 24.1× → 1.0× by 2030 · not due); (2026-08-31 · 200 logical qubits by 2029 · not due). Good disclosure record, but every squeezing promise is forward-dated.
Strategic reading. Squeezing quality, not mode count, gates the CV bet: if the on-chip GKP figure does not move, the 2030 target fails and CV loses to DV fusion, having no alternative carrier. If it moves, TFLN and poling suppliers become strategic.
Outlook & open questions
Confirm by 2028: on-chip GKP effective squeezing above 2 dB with its loss budget; demote if still below 1 dB. Best case 2029: a second group publishes a competing GKP figure. Worst case: integration loss pins it near 1 dB and CV/GKP stays a research architecture. Open: does loss fall as the roadmap claims; can poled TFLN reach GKP-grade fidelity.
References
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [174] M. V. Larsen et al., “Integrated photonic source of Gottesman–Kitaev–Preskill qubits,” Nature, vol. 642, no. 8068, pp. 587–591, Jun. 2025, doi: 10.1038/s41586-025-09044-5. D
- [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ R2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [344] H. Vahlbruch, M. Mehmet, K. Danzmann, and R. Schnabel, “Detection of 15 dB Squeezed States of Light and their Application for the Absolute Calibration of Photoelectric Quantum Efficiency,” Phys. Rev. Lett., vol. 117, no. 11, Art. no. 110801, Sep. 2016, doi: 10.1103/PhysRevLett.117.110801. D
- [345] X. Shi et al., “Squeezed Light Generation in Periodically Poled Thin-Film Lithium Niobate Waveguides,” arXiv:2508.08599, Aug. 2025. D
- [889] B. Seron, H. Thomas, E. Araujo, A. Arkhipov, C. Oh, and L. Novo, “Efficient classical algorithm for estimating linear statistics of Boson Sampling,” arXiv:2609.35447, Sep. 2026. P
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Colour-centre / defect spin (NV, SiV, SnV, T centre)
An optically addressable point-defect spin in diamond or silicon whose electron couples coherently to a photon, making it a network node with a small nuclear register rather than a processor qubit.
Verdict. The best spin–photon interface in solid state, but link rates of millihertz to hertz keep every actor in networking and sensing; no defect platform has a logical qubit or a dated processor roadmap.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A point defect — nitrogen-vacancy, the group-IV silicon- and tin-vacancies in diamond, or silicon's T centre — read by fluorescence and entangled with an emitted photon, nearby nuclei as a small memory. Coherent single-spin control dates to 2004. The split that matters is symmetry: NV lacks inversion symmetry and so diffuses spectrally; SiV and SnV are inversion-symmetric.
Attributes: natural defect, engineered placement, static host with a flying photon, ~1 µs gates; fluorescence readout ~100 µs, non-destructive and mid-circuit; optical plus microwave control; Pauli and loss error.
Physics & limits
Everything rests on the chance an excited defect puts a usable photon into fibre. NV emits a few per cent into its zero-phonon line and diffuses spectrally under charge switching, so a cavity is mandatory — Delft's fibre microcavity took resonant collection from ~0.05% to ~0.5% at echo coherence above 100 µs D[359]. Group-IV centres fix the linewidth by symmetry but pay in temperature: SiV below 100 mK, SnV nearer 1–4 K. Heralded rate goes as efficiency squared — 10× optical gain is 100× in rate; link rate, not gate error, is the figure of merit. Loss is heralded, entering the code as erasure — the one structural edge over dot and donor spins.
Engineering state of the art
table
Local gates are not the problem: Fujitsu and QuTech report NV errors below 0.1% by gate-set tomography P[208]. Collection dominates; no defect platform has a logical qubit.
The Fujitsu/QuTech "below 0.1%" NV gate error comes only from a joint press release relayed by trade press [208]. Element Six's lead as the diamond source of most NV-centre companies rests on a secondary survey [364]. Photonic Inc.'s T-centre tCNOT is post-selected [363]. Not published: a peer-reviewed paper with gate-set-tomography error bars for the Fujitsu/QuTech figure; Element Six's capacity, revenue or quantum-segment figures; a journal paper on Photonic Inc.'s T-centre work, as of 2026-09-04, and a gate fidelity for its tCNOT; and the dates of Quantum Brilliance's three deployments at Oak Ridge, Fraunhofer IAF and Pawsey [364].
Manufacturing, materials & supply chain
Hosts: CVD diamond with implanted defects, or defect-engineered silicon for T centres. Element Six is the main merchant supplier, selling DNV-B1 (2020-06-15) by catalogue — but that grade targets NV ensembles C[361]; single-defect nodes need electronic-grade plates. Two smaller sources exist: Diatope, an Ulm University spin-out (2021) selling engineered NV diamond, and Quantum Brilliance's quantum-diamond foundry in Melbourne (2025) P[364]. Device yield is the missing number: QuTech's SnV study P[362] characterised 327 nanocavities at room temperature, found coupled centres in 7 of the 9 it cooled and measured two above cooperativity one, with no chip-wide fraction Dfact. Optical I/O does not multiplex — each node needs its own resonant laser, microwave line, detector and fast feed-forward D[360], so burden scales per node and 10³ nodes is nobody's target. Export control does name diamond: ECCN 3C005.a has covered diamond semiconductor substrates and their ingots above 10⁴ Ω·cm since 2022-08-15, and 3C006 such substrates carrying an epitaxial layer fact; whether a quantum-grade plate counts as a semiconductor substrate is the open question.
Role in the stack
Architecture: colour-centre spins — network nodes (NV/SiV/T), as its primary carrier. The register lists 5 machines using it, among them SaxonQ's QC2026 Dual Core, Quantum Brilliance's Quoll / QB-QDK 2.0 and Fujitsu's Diamond-spin quantum computer prototype. Requires diamond growth or implantation; provides spin gating, fluorescence readout and the spin–photon link consumed upstream. The derived clock is transport-dominated by six to nine orders: ~1 µs gates against heralded links at 7.5 mHz (T centre, 40 m) to ~1 Hz (SiV, 20 m) P[363]D[209]. Two teleported-CNOT (tCNOT) claims coexist, one on T centres and one on NV, and both are right. Photonic Inc.'s T-centre tCNOT between cryostats was post-selected, no feed-forward and no gate fidelity, at Bell 0.60(8) P[363]; QuTech's NV gate is unconditional at 63(4)% D[360]. Only the second is a gate.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuTech | developer | Netherlands | NV cavities, SnV nanocavities, teleported CNOT | D[359], [360], fact |
| Photonic Inc. | developer | Canada | Silicon T-centre modules | P[363] |
| Harvard | research | USA | SiV nodes over urban fibre | D[209] |
| Element Six | supplier | UK | Merchant CVD diamond | C[361] |
| Quantum Brilliance | developer | Australia | Room-temperature diamond units | P[364] |
Money. 2025-11-06 · Photonic Inc. · QBI Stage B · up to USD 15 M · DARPA · awarded fact. 2026-05-12 · Photonic Inc. · equity · USD 200 M at USD 2 B · Microsoft returning · USD 350 M cumulative · closed P[186]. 2026-07 · QuantumDiamonds · EUR 91 M, EUR 76 M of it EU Chips Act · closed P[364].
Market & supply chain. Two concentration points: substrate, where Element Six dominates and its two alternatives date only from 2021 and 2025, and a thin detector base for readout. Sensing revenue funds the field; nothing here is bought against G3 or G4.
IP & standards. No dated patent family from a named database as of 4 Sep 2026; Element Six's DNV grades are a de facto benchmark.
Roadmaps & track record. Photonic Inc. (2023-11 · fault-tolerant distributed computing "within five years" · unmet; its published rate is seven orders below its own ~200 kHz target) P[364]. Quantum Brilliance ships rather than promises; QuTech is on schedule.
Strategic reading. Defect spins win only if distributed modules bind before monolithic fault tolerance does — then every platform buys this interface instead of building it. Element Six holds supplier power because it never competes on qubit design.
Outlook & open questions
Confirm/demote (12–24 months): an unconditional inter-node gate above 90%, or a link above 1 kHz, confirms the thesis; two more years at hertz rates demotes it to sensing. Best case 2029: a multi-node repeater segment with error detection. Worst case: laboratory links only. Open: (1) does anyone publish a chip-wide SnV device yield; (2) do Diatope or Quantum Brilliance's foundry grow into a second source at Element Six's scale; (3) can T-centre rates close on SiV.
References
- [186] M. Abdel-Kareem, “Photonic Inc. Reaches $2B Valuation with $200M Final Close,” Quantum Computing Report, May 12, 2026. [Online]. Available: https://quantumcomputingreport.com/
photonic-inc-reaches-2b-valuation-with-200m-final-close/ P - [208] M. Swayne, “Fujitsu And QuTech Realize High-Precision Quantum Gates,” The Quantum Insider, Mar. 28, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P03/ 28/ fujitsu-and-qutech-realize-high-precision-quantum-gates/ - [209] C. M. Knaut et al., “Entanglement of nanophotonic quantum memory nodes in a telecom network,” Nature, vol. 629, no. 8012, pp. 573–578, May 2024, doi: 10.1038/s41586-024-07252-z. D
- [359] J. Fischer et al., “Spin-photon correlations from a Purcell-enhanced diamond nitrogen-vacancy center coupled to an open microcavity,” Nat. Commun., vol. 16, no. 1, Art. no. 11680, Nov. 2025, doi: 10.1038/s41467-025-66722-8. D
- [360] M. Iuliano et al., “Unconditionally teleported quantum gates between remote solid-state qubit registers,” Nat. Commun., vol. 17, no. 1, Art. no. 4694, May 2026, doi: 10.1038/s41467-026-72818-6. D
- [361] Element Six, “Element Six launches DNV-B1™ – its first commercially-available, general-purpose quantum grade diamond,” Jun. 15, 2020. [Online]. Available: https://www.e6.com/
en/ Cabout/ news/ dnv-b1-launch - [362] QuTech, “Coherent coupling of diamond colour centre to a nanocavity,” Jun. 25, 2026. [Online]. Available: https://qutech.nl/
2026/ P06/ 25/ a-step-toward-faster-quantum-networks/ - [363] F. Afzal et al., “Distributed Quantum Computing in Silicon,” arXiv:2406.01704, Jun. 2024. P
- [364] M. U. Rehman, “Top Diamond NV-Centre Quantum Computing Companies in 2026,” The Quantum Insider, Jul. 10, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P07/ 10/ 8-quantum-computing-companies-working-with-nv-centre-in-diamond-technology/
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Donor spin (P in ²⁸Si)
Phosphorus donors placed by STM lithography in enriched silicon-28, the bound electron giving drive and readout, the ³¹P nucleus the long-lived qubit.
Verdict. Highest published per-gate fidelities in silicon, but a serial atom-by-atom write process and a single practitioner cap the register at eleven qubits with no dated parallelisation scheme.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A single ³¹P donor placed atom-by-atom in enriched ²⁸Si: the bound electron gives drive and spin-to-charge readout, the spin-1/2 ³¹P nucleus the memory. Nuclear qubits inside a register are gated through their hyperfine coupling to a shared electron; registers are linked by electron exchange D[192]. Kane proposed the architecture in 1998; UNSW's Simmons group built the first deterministically placed single-donor device in 2012 D[357]; SQC, its 2017 spin-out, is the sole operator at device scale as of 4 Sep 2026.
Attributes: natural dopant at engineered placement, static, deterministic entangling near 1 µs; spin-to-charge readout ~10 µs, non-destructive and mid-circuit capable; Pauli error; STM fabrication, no foundry equivalent.
Physics & limits
The qubit is a nucleus, not a confined electron: with no orbital degree of freedom there is no first-order charge-noise coupling — the term that plateaus gate-defined dots at 99.0–99.6%. But every operation routes through the one electron that does couple to charge noise, which is coupler, readout probe and dominant error source at once; the budget is set by electron dephasing during the hyperfine-conditional pulse, not by nuclear coherence. Residual ²⁹Si and the regrown STM interface set that electron's T2. A sharper tip will not move the floor: exchange varies exponentially with separation, so a donor mis-sited by a few nm gives a dead register.
Engineering state of the art
table
Dominant term: register size and the electron-mediated gate. The main report's single "99.90% donor nuclear CZ" is not isolable from this work D[192].
The 99.90% donor nuclear-spin CZ fidelity cannot be isolated from [192], whose preprint gives 99.5–99.99% and published version 99.10–99.99%; the fidelity is a range. Not published: a placement yield or cost per donor, from any actor; Firgun Ventures' investment amount, and the split of the A$60 M NRFC total between its two tranches; and any SQC statement on the consequences of IonQ's acquisition of SkyWater.
Manufacturing, materials & supply chain
Serial by construction: one tip, one site, so throughput is qubit-hours, not wafer-hours; no parallel exposure is published. Enriched ²⁸Si is dual-sourced as of 4 Sep 2026 — ASP Isotopes' Pretoria line since 2025-03, US DOE silane at 99.9999% ²⁸Si from 2026-07-16 P[348] — so feedstock is not the constraint. Suppliers: SkyWater for US resonators C[276], Bluefors for cryogenics C[358]. The single point of failure moved in 2026: IonQ closed its ~USD 1.8 B purchase of SkyWater on 2026-07-31 G[19], putting SQC's only named US manufacturing route inside a competitor. Export exposure sits in the feedstock, not the machine: the US rule of 2024-09-06 created Export Control Classification Numbers (ECCNs) for isotopically enriched silicon and germanium — silicon qualifies below 0.08% of the nuclear-spin isotope ²⁹Si — as epitaxial layers (3C907), hydrides such as silane (3C908) and bulk material or oxide (3C909), so qubit-grade ²⁸Si is itself a controlled item; its quantum-computer ECCN, 4A906, starts at 34 qubits and, below 2,000, applies only under a two-qubit (C-NOT) error ceiling set for each size band — out of reach of an eleven-qubit register G[301]. Wiring is not the wall; the write step is.
Role in the stack
Architecture: donor spins in silicon, as its primary carrier. Requires STM hydrogen-resist lithography; provides the carrier for exchange links and spin-to-charge readout; substitutes for gate-defined dots at the cost of the whole process flow. Its clock contribution is not distinctive — µs gates and ~6 µs readout match dot spins, so sum of the syndrome round: gate layers + transport + readout + reset is 7.7 µs against their 8.5 µs, and the real bottleneck is a manufacturing quantity the clock cannot express. Verification: one group, one device, no replication, three inconsistent fidelity framings D[192].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| SQC | developer | Australia | Sole STM donor fabricator, 11-qubit processor | D[192] |
| SkyWater Technology | supplier | USA | Resonators, packaging | C[276] |
| IonQ | supplier | USA | Owns SkyWater since 2026-07-31 | G[19] |
Money. 2025-11-06 · SQC · QBI Stage B award · up to USD 15 M · DARPA · awarded fact. 2026-03-24 and 2026-06-11 · SQC · equity · A$60 M combined · Australia's NRFC · closed fact. 2026-07-31 · IonQ · acquisition of supplier SkyWater · ~USD 1.8 B · closed G[19].
Market & supply chain. No merchant sells an STM placement tool: SQC's asset is know-how, so no second source can be bought. ²⁸Si is the one input with two suppliers P[348]; cost per donor is unpublished. Pays into G2 and G3 on fidelity, not count.
IP & standards. Foundational patents trace to the UNSW/Simmons line; no dated family count from a named database as of 4 Sep 2026.
Roadmaps & track record. SQC (2026-06 · commercial scale by 2033 Rfact · unmet; 11 qubits is the maximum published). It delivers what it publishes, but 2033 presumes a parallelisation scheme absent from the literature — unfalsifiable rather than aggressive.
Strategic reading. If donor spins win, they win as a precision register bolted onto a foundry dot array, and SQC captures little of it: it owns the write process, not the wafer. Acute risk: a competitor owns its US packaging supplier.
Outlook & open questions
Confirm/demote (12–24 months): a device beyond 11 qubits or a dated parallel-write scheme confirms; silence through 2028 demotes this to a physics testbed. Best case 2029: a few dozen donor qubits above 99.5%. Worst case: eleven remains the record. Open: (1) can hydrogen-resist patterning be parallelised; (2) does SkyWater's new owner keep the relationship; (3) does QBI Stage C fund SQC; (4) what is the placement-yield distribution.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Gionq-completes-acquisition-of-skywater-technology - [192] H. Edlbauer et al., “An 11-qubit atom processor in silicon,” Nature, vol. 648, no. 8094, pp. 569–575, Dec. 2025, doi: 10.1038/s41586-025-09827-w. arXiv:2506.03567. D
- [276] Silicon Quantum Computing, “SkyWater x SQC: Advancing Hybrid Quantum-Classical Computing,” Nov. 20, 2025. [Online]. Available: https://sqc.com/
news/ Cskywater-and-sqc-advancing-hybrid-quantum-classical-computing - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [348] U.S. Department of Energy, “DOE Advances Domestic Supply of Silicon, Germanium Isotopes for Quantum Computing,” HPCwire, Jul. 16, 2026. [Online]. Available: https://www.hpcwire.com/
off-the-wire/ Pdoe-advances-domestic-supply-of-silicon-germanium-isotopes-for-quantum-computing/ - [357] M. Fuechsle et al., “A single-atom transistor,” Nat. Nanotechnol., vol. 7, no. 4, pp. 242–246, Apr. 2012, doi: 10.1038/nnano.2012.21. D
- [358] Silicon Quantum Computing, “Silicon Quantum Computing — News,” sqc.com. [Online]. Available: https://sqc.com/
news/ C
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Dual-rail (erasure) encoding
One excitation shared between two modes; loss leaves the code space and is heralded as a located erasure, not an unknown Pauli.
Verdict. The cleanest error channel in superconducting hardware (≈0.5% erasure, 0.03% residual Pauli per CZ), bought with 2× the modes; unproven above eight qubits. Demote if no dual-rail device shows a coded Λ > 2 by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A dual-rail qubit is one quantum of excitation shared between two modes: |0_L⟩ = |10⟩, |1_L⟩ = |01⟩. The dominant hardware error — cavity photon loss, transmon T1 decay, waveguide absorption — is the annihilation operator on either rail, and it sends both logical states to |00⟩, outside the code space. A total-excitation measurement therefore commutes with the logical operators: decay is caught and located without disturbing the encoded state, turning the largest error term from unknown Pauli into heralded erasure. What remains is differential dephasing between two rails never quite identical.
Dual-rail is the native photonic qubit: Chuang and Yamamoto (1995) called it "a simple form of error correction" S[398]; Knill, Laflamme and Milburn built linear optics on it in 2000 S[337]. The superconducting transfer was deliberate — AWS proposed transmon pairs (2022-08) S[334], Yale cavities (2022-12) S[399], both demonstrated July 2023 D[400], [401].
Attributes from the technology graph (a affinity; b time; c readout; d mobility; e control @ placement; f errors; g manufacturing):
- a = 0.25, fabricated — engineered modes, not natural levels.
- b = n/a; no gate time of its own.
- c = none; the check is a separate primitive.
- d = none.
- e = none @ none.
- f = erasure: located, heralded loss.
- g = none; a wiring choice, not an object.
Rank 6 of 111; shared by the photonic and superconducting families.
Physics & limits
The energy scale is one quantum — a 6 GHz microwave or 1.5 µm optical photon — and the time scale is the single-excitation lifetime of the worse rail. Either rail can decay, so the erasure rate is roughly twice the single-mode loss rate: the qubit fails more often than a bare one, and wins only if the code eats located errors more cheaply. It does — erasure locations lift the surface-code threshold to 50% in the ideal limit against ≈19% for depolarising noise, and at 1% erasure the tolerable Pauli rate rises 5.2× S[334], [402].
The measured hierarchy is the point: a Yale double-post cavity gave erasure at 3.981(3) ms⁻¹ against in-code-space dephasing below 0.17 ms⁻¹ D[403]; AWS's transmon pair, erasure 2.19(2)×10⁻³ per single-qubit gate with residual ~40× lower and millisecond code-space coherence from far shorter-lived transmons D[400].
Four floors are intrinsic: rail asymmetry, whose differential frequency shift dephases the code space and does not improve with lifetime; false negatives, re-entering as invisible leakage (3.7% D[404], 6–8% in the qutrit variant D[405]); heating out of the single-excitation manifold; and the check's own exposure. Only longer lifetimes, matched shifts and faster checks move them.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: a cavity dual-rail CZ in ~500 ns at ≈0.5% erasure per gate and 0.029(6)% post-selected Pauli error D[84]. Typical at scale: nothing beyond sixteen sites — OQC GENESIS, 16 dual-rail sites with no published entangling gate (2025-09), Quantum Circuits' 8-qubit Aqumen Seeker (2024-11) C[86], SUSTech's four dual-rail transmons (2025-04) D[406].
Records timeline
| Year | Figure | Who | Evidence |
|---|---|---|---|
| 2023-07 | Erasure 2.19(2)×10⁻³ per 1Q gate, residual ~40× lower | AWS | D[400] |
| 2025-04 / 2026-03 | Four dual-rail transmons: logical CNOT 98.1% process fidelity at a 13% erasure rate, three-qubit GHZ 93.9% (Nature Physics, 2026-03; arXiv v1 of 2025-04: Bell 98.8%, CNOT 96.2%, GHZ 93.5%) | SUSTech | D[406] |
| 2026-04 | 384 ns check; erasure 2.54(1)×10⁻², residual 6.0(2)×10⁻⁴, bias 42(1) | AWS | D[85] |
| 2026-08 | CZ ~500 ns; erasure ≈0.5%/gate, Pauli 0.029(6)%, bit-flip 2.8(4)×10⁻⁶ | Quantum Circuits | D[84] |
| 2025 | Photonic dual-rail: fusion Bell 99.22(12)%, SPAM 99.98(1)% | PsiQuantum | D[169] |
Dominant term today: control-qubit dephasing during the gate in cavities, 3× the target's D[84]; check exposure and false negatives in transmons D[85]; loss in photonics.
Manufacturing, materials & supply chain
Machined cavities (high-purity aluminium, sapphire-mounted ancillas) give the longest photon lifetimes and no foundry path — Quantum Circuits' line. Planar transmon pairs (AWS, SUSTech) inherit ordinary superconducting fabrication but take twice the die area per site and add a requirement bare transmons lack: the rails must be matched in frequency and coupling, so the frequency-collision problem that limits transmon yield now applies pairwise. No vendor publishes a dual-rail yield, cost or energy per qubit. Photonic dual-rail is the best case — path encoding is free in a waveguide — PsiQuantum's 300 mm silicon-nitride platform running 1.8(2) dB/m waveguide loss and 93.4% median detector efficiency at ~2 K D[169].
Superconducting variants ride the export-controlled stack: refrigerators, amplifiers, microwave I/O (BIS ECCNs 3A904, 4A906, 3B904) G[301] fact. Photonics depends on a 300 mm CMOS-photonics foundry, barium-titanate switches and nanowire detectors — single-source risk at both.
Control, readout & I/O burden
The encoding doubles control fan-out: two drive lines per qubit, or two cavities plus an ancilla transmon and its readout. AWS folds that back with one readout resonator coupled symmetrically to the pair, so the check is a single 384 ns pulse costing 8(3)×10⁻⁵ dephasing D[85] fact; the cavity variant needs a number-splitting ancilla measurement, 1.82 µs standalone D[404], now folded into the gate D[84]. The system burden is the flag path: one bit per qubit per round must reach the decoder inside a syndrome cycle, against NVQLink's 3.84 µs round trip fact. At 10³ qubits that is 2×10³ modes and 10³ flag channels; at 10⁴ the ~10 Gb/s flag bandwidth forces cold-stage aggregation; at 10⁶ only planar or photonic survives.
Role in the stack
Dual-rail sits on two architectures: "Dual-rail erasure qubits", as the primary encoding (Quantum Circuits/D-Wave, AWS, OQC, SUSTech), and "Fusion-based photonic (FBQC)", as an alternate (PsiQuantum, Quandela, QuiX). It requires a mid-circuit erasure check and is what that check reads; without one it is merely a lossier qubit. It replaces bare encoding at 2× the modes and conflicts with the plain surface code, which discards heralds. It buys error structure with area, not error rate with coherence.
Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 2.8×10⁻⁶ s on the dual-rail architecture — four 5.0×10⁻⁷ s CZ layers D[84] over a 4.0×10⁻⁷ s check D[85] — gate-set on the cavity and the transmon route alike. Switching away is cheap in hardware, expensive in software: decoder, calibration and benchmarks assume heralds. Neighbouring empty slots: a dual-rail logical memory over repeated rounds, and the erasure-biased code consuming heralds and bias.
Evidence — how the numbers were measured
Every headline number here is post-selected: erasure rates come from heralded tomography or interleaved benchmarking with flagged shots discarded, so a "99.9% gate" is a conditional fidelity whose companion figure, the survival fraction, decides whether the device is useful. The protocols miss correlated two-rail loss, heating into |11⟩, rail-asymmetry drift, and the erasure fraction under two-qubit gates in a repeated cycle rather than idling. False negatives, the least-reported quantity, set the leakage floor the decoder never sees.
Replication is real: transmon AWS 2023 → SUSTech 2025 → AWS 2026; cavity Yale 2023 → 2025 → Quantum Circuits 2026. Conflicts: the 2026 Nature gate is post-selected Pauli < 0.1% (0.12% at depth) with erasure fraction ≈80% in the main report, 0.029(6)% per gate cited from the same paper, "below 0.1%" in the arXiv abstract D[84] — per-gate versus depth-extrapolated, quoted rather than merged. Second, PsiQuantum waveguide loss is 0.5 dB/m in the main report against 1.8(2) dB/m in Nature D[169].
The ≈80% gate-level erasure fraction of the cavity CZ comes from the main report; the arXiv abstract states only ≈0.5% erasure per gate, and no primary source gives the fraction. OQC's erasure-qubit perspective S[402] is a review by an industrial group, not a hardware commitment, and OQC's Series C release names no dual-rail target C[60]. Not published: whether Quandela's and QuiX's path-encoded linear-optical qubits are dual-rail, so no numbers are attributed to them; a dated primary figure for Quantum Circuits' physical-to-logical overhead, reported elsewhere as 10–20 physical per logical and absent from its dual-rail explainer C[411]; yield, cost or energy per dual-rail qubit, from any actor, superconducting or photonic; a dated patent-family count for dual-rail encodings; and the funding of the dual-rail programmes at AWS, SUSTech and Yale, apart from their parent institutions. Not published in the abstract of [84]: the cavity materials, quality factors and packaging of the 2026 Quantum Circuits device.
Actors & economics
Who.
| Organisation | Role | Country | What they do with this encoding | Evidence |
|---|---|---|---|---|
| Quantum Circuits Inc. (D-Wave unit) | developer | US | Cavity dual-rail; Seeker; DR17–DR181 roadmap | D[84] C[86] fact |
| AWS Center for Quantum Computing | developer | US | Transmon dual-rail; symmetric-readout check | D[400] fact |
| Yale University | research | US | Origin of the cavity encoding; C2QA | D[399], [401], [403] fact |
| PsiQuantum | developer | US | Path-encoded dual-rail photonics, 300 mm | D[169] fact |
| SUSTech | research | China | Four dual-rail transmons; logical Bell, CNOT | D[406] fact |
| Oxford Quantum Circuits | developer | UK | GENESIS, 16 dual-rail sites, deployed 2025-09; industrial erasure-qubit review | S[402] fact |
| UMass Amherst | research | US | Transmon-qutrit erasure qubit | D[405] |
| ORCA Computing | developer | UK | Linear-optical dual-rail GHZ patents | G[407] |
Money.
- 2024-08-15 · Quantum Circuits · Series B · > $60 M · ARCH, F-Prime, Sequoia · ≈$84 M cumulative P · closed fact
- 2025-09-10 · PsiQuantum · Series E · $1 B at $7 B · BlackRock · closed fact
- 2025-11-04 · US DOE · NQISRC renewal, C2QA · $125 M of $625 M · awarded fact
- 2025-11-06 · DARPA QBI Stage B · up to $15 M each, eleven teams, no dual-rail vendor G[65] fact
- 2026-01-07 · D-Wave · acquires Quantum Circuits · $550 M ($300 M stock + $250 M cash) · closed 2026-01-20 fact
- 2026-05-21 · D-Wave; PsiQuantum · US DoC CHIPS letters of intent · $100 M each · LOI fact
- 2026-06-03 · Oxford Quantum Circuits · Series C · £260 M · Bullhound · closed C[60] fact
- 2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · $125 M · switch and cryogenics V&V fact
- 2026-08-06 · D-Wave · Q2-2026 · revenue $3.1 M, cash $546.2 M, $1.57 M NSF grant · reported C[15] fact
Market & supply chain. Nobody sells the encoding; it is priced as hardware multiplicity — two modes plus an ancilla per site — plus the readout chain that reads the herald. On superconductors that is 2–3× die area or a machined cavity assembly with no foundry, so the suppliers that matter are the refrigerator and amplifier vendors under BIS control G[301]. On photonics it is free, and the bill of materials is the foundry, the switch and the detector. G2 pays today for post-selected fidelity, which is what Seeker sells C[86]; G3 and G4 pay once codes run 10⁵–10⁶ rounds; G6 pays on the photonic side; G1, G5 and G7 do not.
IP & standards. Amazon Technologies US 11,748,652 B1, heralded amplitude-damping decay for QEC (granted 2023-09-05), covers the transmon embodiment G[336] fact; Yale US 12,288,135, asymmetric-error-channel processing (granted 2025-04-29), sits with the cavity families that passed to D-Wave in January 2026 G[408]; ORCA Computing holds US 12,437,225, linear-optical encoded GHZ measurements (2025-10-07) G[407]. No dated patent-family count was obtainable from a named database; no standard exists, and Stim's HERALDED_ERASE is the de-facto decoder interface P[397].
Roadmaps & track record.
- D-Wave/Quantum Circuits: promised 2026-06-01, restated 2026-08-06 · DR17 (17 qubits, 2× logical error reduction) 2026, DR49 at 20× 2027, DR181 at 2,000× 2028, 10 logical 2030, 100 logical 2032, Λ = 10 · undelivered as of 2026-09-03 R[409] fact.
- PsiQuantum: promised utility scale "before 2033" · Moreton Bay groundbreaking slipped to 2026-06-17 · at risk fact.
- AWS: no dual-rail product promised · three papers delivered 2022–2026 D[85], [400]. Oxford Quantum Circuits: TITAN announced with the Series C · no dated dual-rail target C[60].
Credibility: Quantum Circuits/D-Wave publishes the field's best channel numbers and has shipped only the 8-qubit Seeker; AWS publishes and promises nothing; PsiQuantum's components are the best-characterised anywhere, its systems slip.
Strategic reading. If dual-rail wins, the winners own long-lived modes and cheap area — cavity vendors and photonic foundries — and the losers are transmon roadmaps spending their whole budget on T1, since the encoding makes T1 a detected cost, not a fatal one. Substitution runs hard from inside the family: the transmon-qutrit erasure qubit needs one transmon and one ancilla, not two rails, at logical T1 > 500 µs against a physical ~55 µs D[405]; dual-rail cat codes add bias to the same structure S[410]. Bargaining power sits with platform vendors.
Outlook & open questions
Confirm if, within 12–24 months: DR17 ships with a measured 2× logical error reduction; any group runs a code on ≥ 10 dual-rail qubits with Λ > 2 and publishes the survival fraction; someone reports the erasure fraction under two-qubit gates in a repeated cycle. Demote if none lands by end-2027, or if the qutrit erasure qubit matches dual-rail's bias at half the hardware. Best case by 2029: a 181-qubit machine at the promised suppression. Worst case: doubled modes and check dead time eat the threshold gain, and the encoding survives only where it is free, in photonics.
Open questions. (1) Does the erasure fraction hold under two-qubit gates at depth? (2) What is a production check's false-negative rate, and does it scale? (3) Can planar dual-rail reach cavity-grade lifetimes? (4) Is there a regime where doubling modes beats doubling code distance? Watch D-Wave's quarterly disclosures and the first repeated-round dual-rail memory paper.
References
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dual-resonator-qubits-breakthrough/ C
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הטקסט בעברית נטען…
Metastable ('omg') erasure encoding
Qubit lives in a metastable manifold so its dominant decay leaves the subspace detectably, converting Pauli errors into located erasures.
Verdict. Physics confirmed on atoms and ions, but measured conversion is 38–50%, not the 98% theory assumed, and no vendor ships it. Demote unless a >70%-conversion gate appears by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An omg encoding places the computational basis inside a long-lived metastable manifold, chosen so the dominant decay takes the atom or ion out of the qubit subspace into a state a cycling transition lights up. The error is then not a Pauli flip on an unknown qubit but a heralded, located loss — an erasure.
The name is the ion-side blueprint: optical–metastable–ground, three manifolds in one species so one ion serves as qubit, ancilla and coolant (Allcock, Campbell, Chiaverini, Chuang, Hudson, Wineland and colleagues, 2021) D[333]. Wu, Kolkowitz, Puri and Thompson made it quantitative for neutral atoms: 98% of ¹⁷¹Yb errors convertible, threshold rising from 0.937% under Pauli noise to 4.15% under erasure noise S[8]. Kang, Campbell and Brown carried it to ions S[392]. First hardware: Princeton, 2023 D[141].
Attributes (technology graph): a carrier affinity 0.0, natural carriers. b no characteristic time, no entangling mechanism of its own. c no readout of its own; it delegates to the mid-circuit erasure check it enables. d no mobility. e no control modality or placement. f error structure as the code sees it: erasure. g no manufacturing. Shared by both host families: neutral atoms and trapped ions.
Physics & limits
The mechanism is a hierarchy of lifetimes. In ¹⁷¹Yb the qubit is the nuclear spin of the 6s6p ³P₀ clock state; in ⁴⁰Ca⁺ two Zeeman sublevels of D₅/₂. Both live long against circuit duration and decay to the ground manifold, which scatters photons on a strong transition while the metastable one does not. A short fluorescence check therefore reports which site left the code space without touching those that stayed — Princeton measured the induced error on survivors below 10⁻⁵ D[141].
The floor is set by errors that stay inside the manifold — Raman scattering back into the qubit subspace, magnetic dephasing across small Zeeman splittings, off-resonant coupling between the computational sublevels — all un-heralded Pauli noise. Oregon measured the split: ~94% of spontaneous Raman scattering and nearly all decay events detected, but only half the total error budget converted D[393]; Princeton's [[4,2,2]] run converted 38(6)% D[142]. Erasure buys more per unit rate — at 1% erasure the surface code tolerates 0.51% Pauli error, 5.2× the standard protocol S[334]fact — but the gain scales with conversion fraction, so the residual is a floor only better gate physics removes.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: a two-qubit gate at 99.16% after erasure subtraction on ⁴⁰Ca⁺ D[393], and a [[4,2,2]] block whose decay slows 1.9(4)× with erasure information D[142]. Typical at scale: nothing — every shipped machine uses ground-manifold qubits.
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2022-01 | 98% of ¹⁷¹Yb errors convertible; threshold 0.937% → 4.15% | Princeton | S[8] |
| 2023-10 | Metastable ¹⁷¹Yb: 1Q 0.9990(1), CZ 0.980(1), check error <10⁻⁵ | Princeton | D[141] |
| 2023-10 | ⁸⁸Sr Bell ≥0.9971 after erasure excision | Caltech | D[143] |
| 2024-11 | ⁴⁰Ca⁺ Bell 97.73% raw → 99.16% erasure-subtracted, ≈400 µs | Oregon | D[393] |
| 2026-06 | [[4,2,2]]: CZ 0.984(1), 38(6)% erasures, decay 1.9(4)× slower | Princeton | D[142] |
| 2026-08 | Mid-circuit ground-state cooling and ancilla readout | Oregon | D[394] |
The dominant term is the unconverted residual: half the ≈1.4% raw ⁴⁰Ca⁺ gate error survives the check D[393], as does 62(6)% of a 1.6(1)% CZ error on ¹⁷¹Yb D[142] — far worse than 99.854% raw on Harvard's Rb array D[4] or 7.9×10⁻⁴ on Helios D[97].
Manufacturing, materials & supply chain
No fabrication step: the manufacturing attribute is "none" and the encoding rides whatever trap the host uses. What it changes is optics — a shelving/clock laser (578 nm for ¹⁷¹Yb, 674 nm for Ca⁺, 1762 nm for Ba⁺), repumps out of the manifold, and in Oregon's case a Raman pair at 976 nm detuned −43 THz, bought with power D[393]. Suppliers are the field's usual set: Toptica, M Squared, Menlo Systems and NKT Photonics for sources; Stable Laser Systems for ultra-low-expansion cavities; Hamamatsu and Andor for check cameras. Single points of failure: the ULE cavity and the clock laser, both sub-ten-vendor markets. Export-control exposure runs through the lasers, not the encoding — Wassenaar Category 6 controls and the US BIS quantum rule of 2024-09-06 apply whichever manifold carries the qubit.
Control, readout & I/O burden
Per-qubit line count is unchanged — the encoding's main commercial attraction. What grows is wavelength count and calibration: extra state preparation, a shelving fidelity, and a check whose false-positive rate feeds the decoder. The check's cost against the clock is the decisive number, and it is favourable on both hosts. Atom arrays already pay 0.5–1 ms imaging inside a 1–4.5 ms round D[4]S[31], so a check that is the imaging is nearly free; ion machines run ~55 ms per layer D[97], making a few-hundred-µs fluorescence check ~1% of it. Yale and AWS showed erasure qubits win only when check time is short against the cycle S[395]fact — here it is. The wall at 10³–10⁶ qubits is decoder bandwidth, not I/O: erasure flags roughly double the syndrome payload.
Role in the stack
Three architectures carry it: Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native as the primary encoding (Atom Computing with Microsoft, Princeton, Caltech), and two trapped-ion architectures as an alternate — linear Paul trap with individual laser addressing (IonQ, AQT, Quantum Art) and electronic qubit control (laser-free, microwave-driven gates) (IonQ with Oxford Ionics, eleQtron). It requires an alkaline-earth(-like) atom or a trapped ion with an accessible metastable manifold; it provides the detectable-decay structure a mid-circuit erasure check consumes; it replaces ground-manifold hyperfine encoding. Switching costs a re-calibrated preparation and readout chain plus one or two lasers. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 1.5×10⁻³ s on the electronic-gate ion architecture (gate-set), where the encoding adds ≈1%, and 1.3×10⁻³ s on the alkaline-earth tweezer array (transport-set), where it adds nothing. A rare Layer-2 node with no clock penalty, so conversion fraction, not speed, is what to watch. Empty neighbouring slots: no erasure-native encoding for fabricated carriers, and no sub-100-µs erasure check for ions D[394].
Evidence — how the numbers were measured
Headline numbers come from Bell-state and randomised-benchmarking estimators with post-selection: shots where the check fired are discarded, so the "erasure-subtracted" fidelity is conditional — legitimate for a channel, illegitimate as a system figure of merit. Princeton's [[4,2,2]] result is the honest form: 1.9(4)× is logical, with erasure information actually used D[142]. Not captured: the check's false-positive and false-negative rates, which can halve effective distance S[395], and correlated leakage.
Conflicts. (i) The graph record records the [[4,2,2]] improvement as 3.6×; arXiv:2506.13724 v1 and v2 both state 1.9(4)×, which we use, treating 3.6× as superseded fact. (ii) Oregon's Bell fidelities read 98.56%/99.14% in the arXiv HTML and 98.61%/99.16% in Physical Review A, detuning −43 vs −44 THz; journal values used D[393]. (iii) The 98% conversion figure S[8] is an upper bound on an idealised error inventory, not a missed target.
Not published: the duration and fidelity of Oregon's quantum-logic non-destructive metastable readout [394].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Princeton | research | US | Originated ¹⁷¹Yb metastable erasure conversion; [[4,2,2]] demo | D[8], [141], [142] |
| University of Oregon | research | US | Only metastable-ion gate with erasure conversion; omg mid-circuit cooling | D[393], [394] |
| Caltech | research | US | Sr Rydberg erasure excision | D[143] |
| UCLA | research | US | omg blueprint co-author; metastable ion theory | D[333], [392] |
| MIT Lincoln Laboratory | research | US | Blueprint co-author; single-ion spin-cat correction | D[333], [396] |
| Duke | research | US | Surface-code comparison, ground vs metastable ions | S[392] |
| Atom Computing | developer | US | ¹⁷¹Yb arrays, adoptable without changing species; QBI Stage B | fact |
| QuEra | developer | US | Rb arrays using atom loss, not metastable erasure | Cfact |
| Infleqtion | developer | US | Sr/Rb arrays, 12 logical qubits with loss correction | fact |
| IonQ | developer | US | Laser-free gates remove the error omg heralds | D[102]fact |
| Quantinuum | developer | US | Ba⁺ Helios; natural omg host, no metastable programme | D[97] |
| Microsoft | user | US | Sells Magne with Atom Computing; erasure-aware decoding | fact |
Money. No financing event is earmarked for metastable encoding; this money buys the host platforms.
- 2025-09-17 · IonQ · M&A, Oxford Ionics · $1.075 B · announced 2025-06-09 · closed fact
- 2025-11-04 · US DOE · five National QIS Research Centers renewed · $625 M / five years · closed fact
- 2025-11-06 · DARPA · QBI Stage B, 11 teams incl. Atom Computing, QuEra, IonQ · ≤$15 M each · selected fact
- 2026-02-17 · Infleqtion · IPO, NYSE (INFQ) · >$550 M gross · closed fact
- 2026-04-27 · Quantum Art · Series A extension · $140 M · closed P[125]
- 2026-05-21 · US Dept of Commerce · CHIPS LOIs, Atom Computing $100 M, Infleqtion $100 M · $2.013 B total · non-binding fact
- 2026-06-16 · Atom Computing · Series C plus DoC LOI · >$300 M cumulative · Third Point · closed + LOI C[154]fact
- 2026-06 · Quantinuum · IPO, Nasdaq (QNT) · $1.68 B · after $600 M at $10 B pre-money · closed G[123]
- 2026-07 · IonQ · M&A, SkyWater Technology · $1.8 B · closed G[19]
- 2026-08-28 · Pasqal · SPAC completion · ~$360 M cash · €16.5 M 2025 revenue · closed P[156]
Market & supply chain. No one sells an omg product; the enabling lasers, cavities and cameras are already a dependency of every host platform, so adoption adds one or two laser channels against systems like Magne (€80 M, 50 logical) fact. Only G3 and G4 (early and large-scale fault tolerance) pay for it; G1 benefits marginally via erasure excision in simulators D[143]. G2 and G5–G7 do not.
IP & standards. No patent family specific to metastable erasure encoding was found in a named database as of 3 Sep 2026; nearest granted art is Amazon Technologies US 11,748,652 B1 on heralded amplitude-damping decay (2023-09-05) fact. No litigation, no standards body; Stim models the encoding in software C[397].
Roadmaps & track record. (2021 · omg blueprint · partly delivered — Oregon entanglement 2024 D[393], mid-circuit cooling 2026 D[394]; no product.) (2022-01 · 98% conversion · missed by 2.6×, 38(6)% measured D[142].) (2028 · QuEra Libra >256 logical · on roadmap, no metastable commitment fact.) (2026/27 · Magne 50 logical · installing, ground-manifold Yb fact.) The vendors made no omg promises to break.
Strategic reading. Winners would be alkaline-earth(-like) atom vendors and ion vendors still using laser gates; losers, decoder stacks tuned for Pauli noise. Substitution bites from both sides: atom loss is >80% of array leakage and Harvard detected it on ground-manifold Rb for 2.14(13)× below threshold D[4], while laser-free ion gates at 8.4×10⁻⁵ delete the error omg catches D[102].
Outlook & open questions
Confirm if a gate reports >70% of total error converted with residual below 3×10⁻³, or a vendor announces a metastable product line. Demote if no conversion fraction above 50% is published by end-2027, or a laser-free ion gate below 10⁻⁴ ships at scale. Best case by 2029: an alkaline-earth array runs a distance-5 code with erasure-aware decoding and reports Λ above the loss-only baseline. Worst case: atom loss remains the only erasure anyone needs and this stays a two-laboratory programme.
Open questions. (1) Why is measured conversion 38–50% when the model says 98% — gate, check, or error inventory? (2) Does erasure information still help once false negatives are folded in at distance ≥5? (3) Is the residual Pauli error set by sublevel choice or by the gate laser? (4) Can a metastable ancilla be read non-destructively inside a 1 ms atom cycle? Watch the next Princeton follow-up, whether Atom Computing exposes the metastable manifold, and whether Quantinuum's unpublished "novel code family" is erasure-structured.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [8] Y. Wu, S. Kolkowitz, S. Puri, and J. D. Thompson, “Erasure conversion for fault-tolerant quantum computing in alkaline earth Rydberg atom arrays,” Nat. Commun., vol. 13, Art. no. 4657, 2022, doi: 10.1038/s41467-022-32094-6. arXiv:2201.03540. S
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Gionq-completes-acquisition-of-skywater-technology - [31] H. Zhou et al., “Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays,” Proc. 52nd Annu. Int. Symp. Comput. Archit. (ISCA), 2025, doi: 10.1145/3695053.3731039. arXiv:2505.15907. S
- [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [123] Quantinuum, “Quantinuum Announces Pricing of Upsized Initial Public Offering,” Jun. 3, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Gquantinuum-announces-pricing-of-upsized-initial-public-offering - [125] M. Abdel-Kareem, “Quantum Art Extends Series A to $140M to Scale Trapped-Ion Architecture,” Quantum Computing Report, Apr. 27, 2026. [Online]. Available: https://quantumcomputingreport.com/
quantum-art-extends-series-a-to-140m-to-scale-trapped-ion-architecture/ P - [141] S. Ma et al., “High-fidelity gates with mid-circuit erasure conversion in a metastable neutral atom qubit,” Nature, vol. 622, p. 279, 2023, doi: 10.1038/s41586-023-06438-1. arXiv:2305.05493. D
- [142] B. Zhang et al., “Logical qubits with erasure conversion using metastable neutral atoms,” Nat. Phys., vol. 22, no. 6, pp. 910–916, Jun. 2026, doi: 10.1038/s41567-026-03309-0. arXiv:2506.13724. D
- [143] P. Scholl, A. L. Shaw, R. B.-S. Tsai, R. Finkelstein, J. Choi, and M. Endres, “Erasure conversion in a high-fidelity Rydberg quantum simulator,” Nature, vol. 622, p. 273, 2023, doi: 10.1038/s41586-023-06516-4. arXiv:2305.03406. D
- [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
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2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [333] D. T. C. Allcock et al., “omg blueprint for trapped ion quantum computing with metastable states,” Appl. Phys. Lett., vol. 119, no. 21, Art. no. 214002, Nov. 2021, doi: 10.1063/5.0069544. arXiv:2109.01272. D
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quantumlib/ CStim/ blob/ main/ doc/ gates.md
Русский текст загружается…
הטקסט בעברית נטען…
GKP grid encoding
A qubit encoded in periodic grid states of one bosonic mode — microwave cavity or optical — correcting small quadrature shifts and handing the decoder an analogue syndrome.
Verdict. The only encoding whose syndrome is continuous, and the only one whose every headline number is still post-selected. Unconditional logical error remains unpublished on both branches.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Gottesman, Kitaev and Preskill (Phys. Rev. A 64, 012310, 2001) encode a qubit in a comb of position/momentum grid states of one oscillator: the stabilisers are commuting displacements, and shifts below half the lattice spacing are correctable S[413]. Ideal grid states need infinite energy, so every device approximates them at finite squeezing. The graph record's 2020 date is Campagne-Ibarcq et al. (Yale, Nature 584, 2020-08-19): square and hexagonal GKP states in a superconducting microwave cavity, logical errors suppressed by feedback on non-destructive measurement rather than post-selection D[414].
Attributes: partly fabricated (0.75) — a continuous-variable mode inside a fabricated cavity or photonic circuit; no control channel, readout or transport of its own; Gaussian error structure. "Grid states in a bosonic (microwave cavity) or optical mode; corrects small shifts; needs ~10 dB squeezing" (graph record).
Physics & limits
The syndrome is analogue: measuring each quadrature modulo the lattice period returns a real number, so the decoder receives the size of the shift, not a bit. That soft information is GKP's architectural argument, and why concatenating GKP under an outer code beats concatenating a bare qubit. The floor is squeezing: finite squeezing broadens each comb tooth, and once the shift distribution has weight beyond half the lattice spacing the correction applies the wrong displacement and the error becomes logical. The graph record's ~10 dB is the working requirement, architecture-dependent rather than a constant, and loss is what spends it. What moves the floor: higher-Q cavities, lower-loss photonics, state breeding to raise effective above physical squeezing, and an outer code that relaxes the per-mode requirement.
Engineering state of the art
Best demonstrated is a memory, not a computation. The largest coherence gain from any bosonic code remains Yale's 2.27(7), on a GKP qubit with reinforcement-learning-tuned real-time correction D[415]; the qudit extension gives 1.82(3) for a qutrit and 1.87(3) for a ququart, cavity T1 = 631 µs D[83]. Nord Quantique's single-mode grid qubit reaches 0.0081(2) logical error per round and SPAM 7(7)×10⁻⁴ on cardinal states, but only on shots surviving an all-agree post-selection, 0.24 in preparation × 0.39 in measurement D[82]. Nothing here resembles Λ scaling, and the dominant budget term is acceptance, not the conditional error rate quoted.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2023-03 | Real-time GKP correction beyond break-even, gain 2.27(7) | Yale | D[415] |
| 2025-05 | GKP qudits beyond break-even: qutrit 1.82(3), ququart 1.87(3) | UCSB/Google Quantum AI | D[83] |
| 2025-06 | GKP state on an integrated SiN chip at room temperature, 0.62 dB effective squeezing | Xanadu | D[174] |
| 2026-07 | Single-mode grid qubit: 0.0081(2)/round, survival 0.24×0.39 | Nord Quantique | D[82] |
Manufacturing, materials & supply chain
The two branches share no supply chain. Microwave GKP is machined, not lithographed: aluminium or niobium 3D cavities — Nord Quantique's is a double-post design — plus an ancilla transmon and readout chain per mode, and a refrigerator whose volume, not wafer area, sets the qubit count D[82]. Optical GKP is a 300 mm silicon-nitride process at room temperature, with squeezed-light generation, photon-number-resolving detection and packaging as cost drivers; Xanadu reports 0.085 dB edge-coupling loss per facet, with Corning and DISCO Cfact. No GKP-specific export control exists; the microwave branch inherits ECCN 3A904 G[301].
Control, readout & I/O burden
Microwave GKP is control-heavy per mode. Stabilisation needs conditional-displacement drives and feedback inside the cavity lifetime, and each mode carries an ancilla transmon whose errors propagate into it — the ancilla, not the cavity, is the practical limit at 360 µs–1 ms storage D[82], [83]. The I/O unit is a mode plus a full transmon control-and-readout chain, so at 10³ modes the wiring burden exceeds a bare transmon lattice; efficiency pays only once one mode replaces many physical qubits. Optical GKP substitutes homodyne detection per mode and GHz feed-forward across thousands of detector channels, unproven at system level D[173].
Role in the stack
GKP requires a bosonic cavity mode in the microwave branch and a roughly 10 dB squeezed mode in the optical one; it supplies the inner qubit for bosonic concatenation and is the direct alternative to cat encoding in that slot. It sits, as an alternate, on the cat-and-GKP bosonic cavity architecture (Nord Quantique; Alice & Bob and AWS on the cat variant) and, as the primary encoding, on the continuous-variable photonic GKP architecture (Xanadu), whose design concatenates GKP under a qLDPC outer code Cfact. Switching from cat to GKP swaps a biased channel for an unbiased one with an analogue syndrome: the outer code must be redesigned. The graph record fixes no characteristic time, so its contribution to the derived clock (= sum of the syndrome round: gate layers + transport + readout + reset, 1.44 µs on the cat-and-GKP architecture) is a stabilisation round no actor publishes.
Evidence — how the numbers were measured
Three quantities are reported as if commensurable. Gain is a ratio of decay rates against the best passive encoding D[83], [415]; logical error per round is conditional on survival D[82]; effective squeezing is a state-quality measure D[174]. None converts into another. Xanadu's 0.62 dB effective squeezing is not comparable with raw quadrature squeezing such as the 1.4 dB on periodically poled thin-film lithium niobate D[345], and its "24.1× above threshold" is a system-loss metric Rfact. No independent replication of the Nord Quantique or UCSB/Google results exists as of 4 Sep 2026.
The ~10 dB squeezing requirement is architecture-dependent; no single threshold paper sets it. Nord Quantique's "100+ logical by 2029" comes from company web material with no dated release. Not published: an unconditional (non-post-selected) logical error rate for any GKP demonstration, on either branch; how Xanadu's "24.1× above threshold" system-loss figure relates to its 0.62 dB effective squeezing; and a GKP-specific patent family or export-control category.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Nord Quantique | Developer | CA | Single-mode microwave grid qubits | D[82] |
| Xanadu | Developer | CA | On-chip optical GKP sources; GKP-under-qLDPC architecture | D[174] |
| Google Quantum AI | Research | US | Qudit GKP beyond break-even, with UCSB | D[83] |
| Corning | Supplier | US | Fibre-array packaging for Xanadu's chips | Cfact |
Money.
- 2025-11-06 · Nord Quantique and Xanadu · DARPA QBI Stage B selections · $5 M initial, up to $15 M each · DARPA · closed fact
- 2026-03-26 · Xanadu · SPAC listing with Crane Harbor · ~$302 M gross, ~40% below plan · closed; ~US$686 M liquidity at 2026-06-30 Cfact
- 2026-05-18 · Nord Quantique · growth equity · $30 M at a $1.4 B valuation · closed Cfact
- 2026-08-28 · Xanadu · Toronto factory funding · CAD 195 M · Government of Canada · announced fact
Market & supply chain. No one sells GKP; both branches buy their host platform's equipment — cavity machining, TWPA readout and refrigerators on one side, a narrow set of squeezed-light and photon-number-resolving detector suppliers plus specialist packaging on the other. G3 and G4 are the only goals that pay for GKP.
IP & standards. No dated GKP-specific patent-family count was found; aggregate sector figures (IBM 4,388, Google 2,385 families in PatSnap's landscape published on 2026-06-30) do not break out continuous-variable encodings P[312]. The 2001 construction is prior art, pushing defensible IP into state preparation, breeding and ancilla-control circuits. No standards activity found.
Roadmaps & track record. Xanadu (promised 2026-08-31): loss 24.1× above threshold in 2026 → 1.0× in 2030, 200 logical qubits by 2029, 1,000+ by 2031, on a GKP-plus-qLDPC architecture Rfact. Nord Quantique (company material): 100+ logical by 2029 at "1:1 physical to logical" R[93]. Xanadu quantified its roadmap but raised ~40% below plan against a best published state of 0.62 dB; Nord Quantique's claim rests on a device whose combined survival is under 10%.
Strategic reading. GKP is the hardware-efficiency bet against surface-code brute force: if the squeezing and acceptance gaps close, one mode replaces the tens-to-hundreds of physical qubits an outer code needs. If they hold, both developers fall back on cat or discrete-variable encodings and lose the qubit-count argument behind their valuations, while surface-code incumbents lose nothing. Cat encoding is the substitution threat in the same slot.
Outlook & open questions
Confirm or demote within 12–24 months: does any GKP demonstration publish an unconditional logical error rate; does Nord Quantique lift combined survival above 10%; does an optical GKP state pass 1 dB effective squeezing. Best case by 2029: a multi-mode GKP logical qubit below break-even without post-selection, under a qLDPC outer code. Worst case: it stays a post-selected memory while cat and erasure encodings carry the bosonic architecture.
References
- [82] S. Turcotte et al., “Quantum error correction of a grid-state qubit with state preparation and measurement errors below 10⁻³,” arXiv:2607.06718, Jul. 2026. D
- [83] B. L. Brock et al., “Quantum error correction of qudits beyond break-even,” Nature, vol. 641, no. 8063, pp. 612–618, May 2025, doi: 10.1038/s41586-025-08899-y. D
- [93] Nord Quantique, “Company website.” [Online]. Available: https://www.nordquantique.com/ R
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [174] M. V. Larsen et al., “Integrated photonic source of Gottesman–Kitaev–Preskill qubits,” Nature, vol. 642, no. 8068, pp. 587–591, Jun. 2025, doi: 10.1038/s41586-025-09044-5. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [312] PatSnap, “Quantum Computing Patent Landscape 2026,” Jun. 30, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ quantum-computing-patent-landscape/ - [345] X. Shi et al., “Squeezed Light Generation in Periodically Poled Thin-Film Lithium Niobate Waveguides,” arXiv:2508.08599, Aug. 2025. D
- [413] D. Gottesman, A. Kitaev, and J. Preskill, “Encoding a qubit in an oscillator,” Phys. Rev. A, vol. 64, no. 1, Art. no. 012310, Jun. 2001, doi: 10.1103/PhysRevA.64.012310. arXiv:quant-ph/0008040. S
- [414] P. Campagne-Ibarcq et al., “Quantum error correction of a qubit encoded in grid states of an oscillator,” Nature, vol. 584, no. 7821, pp. 368–372, Aug. 2020, doi: 10.1038/s41586-020-2603-3. D
- [415] V. V. Sivak et al., “Real-time quantum error correction beyond break-even,” Nature, vol. 616, no. 7955, pp. 50–55, Apr. 2023, doi: 10.1038/s41586-023-05782-6. D
Русский текст загружается…
הטקסט בעברית נטען…
Cat-code encoding (biased noise)
A two-photon-dissipation-stabilised coherent-state qubit whose bit-flips fall exponentially with photon number while phase-flips rise linearly with it.
Verdict. The bias is real but small where measured — bias > 25 under a CX at n̄ = 2; the resource estimates imply a cavity lifetime near 50 ms, twice the best ever built.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A qubit spanned by two coherent states of a cavity mode, held there by engineered two-photon exchange with a lossy buffer. Bit-flips must cross phase space between the lobes, exponentially suppressed in n̄; one photon loss flips the phase, linear in n̄. Demonstrated from about 2020 (Lescanne, Leghtas and colleagues), commercialised by Alice & Bob and AWS. It has no gate time or readout of its own; its only product is the asymmetry.
Physics & limits
Γ_Z ≈ n̄/T1: the encoding turns cavity lifetime directly into logical quality, and photon number buys bit-flip suppression at a linear price. Ocelot closes the loop: at n̄ = 2 the storage lifetime is 57–68 µs D[80]. Run that arithmetic at the operating point the estimates assume, n̄ ≈ 19 and 10⁻³ phase-flip per cycle, and the required cavity T1 is n̄·t/p ≈ 53 ms S[80], [95]. The best published cavity memory is 25.6 ms, built by decoupling the mode from its ancilla — the opposite of what a stabilised cat does D[319]. That is the floor: the qubit-count argument is a claim about cavity lifetime under strong drive. What moves it: lower single-photon loss at high pump power, or squeezed cats D[78].
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2025-02 | Per CX at n̄ = 2: phase-flip 9.6(4)×10⁻², bit-flip 3.5(4)×10⁻³ → bias > 25, idle > 30; repetition code 1.75(2)% (d=3, n̄=1) → 1.65(3)% (d=5, n̄=1.5) per 2.8 µs cycle | AWS/Caltech | D[80] |
| 2025-09 | 12-cat chip: mean bit-flip 44 min, peak 252 min, preliminary | Alice & Bob | C[77] |
| 2025-02 | Squeezed-cat variant: 22 s bit-flip | Alice & Bob | D[78] |
Phase-flip dominates: ~10⁻¹ per cycle where a code has run, against the ~10⁻³ assumed; bit-flip suppression stopped being the problem two years ago.
The 9.6×10⁻² is the phase-flip error of the CX gate at n̄ = 2, not a per-QEC-cycle figure; the noise bias is > 25 under the CX and > 30 idle, and the "27–33" in circulation are phase-flip times in µs, not bias values D[80]. The 44-minute mean bit-flip time of the 12-cat chip (September 2025) is preliminary and vendor-published, with no peer-reviewed follow-up, and the vendor's roadmap page gives a 252-minute peak for the same period. The 53 ms cavity-lifetime requirement is derived from Γ_Z ≈ n̄/T1 under the estimates' own assumptions; neither source states it. Nord Quantique's QBI Stage B award [65] funds its GKP route, which does not use this encoding.
Manufacturing, materials & supply chain
It has no fabrication step of its own, adding a continuous parametric pump and buffer mode to the host cavity. That pump is the I/O cost: a drive line, a pump line and a readout chain per cat — through a shared ancilla transmon on Ocelot, through the buffer at Alice & Bob Cfact. Ocelot spends five buffers and four ancilla transmons on five cats D[80]. At 10³ cats the wall is pump-line count and pump heating in one dilution unit; 10⁴–10⁶ needs multiplexed cryogenic drive, undemonstrated here. Supply chain and export exposure are the host cavity's.
Role in the stack
Architecture: bosonic cavity qubits — cat and GKP, where it is the primary encoding. Requires a bosonic cavity mode; provides the biased inner qubit for repetition-cat and LDPC-cat concatenation and for a cat–cat CNOT. It replaces the bare two-level encoding, competes with GKP and conflicts with the unbiased surface code. Derived round 1.44 µs, gate-set, against the measured 2.8 µs syndrome cycle D[80]. Verification: the distance-3 and distance-5 points were taken at n̄ = 1 and n̄ = 1.5, so "flat with distance" mixes distance with operating point D[80]. The 44-minute mean bit-flip is preliminary; the same vendor's roadmap quotes a 252-minute peak from that run C[77]C[412].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Alice & Bob | developer | FR | Bit-flip records, 18-cat Helium, a cat-only roadmap | C[77] |
| AWS | developer | US | Ocelot, the only published cat code with a budget | D[80] |
| DARPA | investor | US | Stage B selected Nord Quantique, not Alice & Bob | fact |
Money.
2025-01-28 · Alice & Bob · Series B · €100 M · — · closed fact
2026-05-22 · Alice & Bob · Series B extension · undisclosed · NVentures lead · closed C[88]
Market & supply chain. Nothing is sold at this layer; the encoding is a design choice on the cavity supply chain, bought as a promise about G3 and G4. Alice & Bob's business rests on it.
IP & standards. No dated patent family specific to cat-code encoding was found; filings attach to gates, pumps and readout.
Roadmaps & track record. The published ladder runs Helium (18 cats, 1 logical, 10⁻², delivered 2026-06) → Lithium (48/4, 10⁻³) → Beryllium (250/5, 10⁻⁴) → Graphene (2,000/100, 10⁻⁶, 2030) R[412]. Chips arrive on time, but no logical error rate has been published for any, so every defining number is a promise. AWS has published no cat roadmap past Ocelot.
Strategic reading. If phase-flip per cycle falls two orders, cat encoding wins the physical-qubit count; if not, the branch is a memory technology and the budget goes to qLDPC or dual-rail erasure.
Outlook & open questions
Confirm by 2027 if phase-flip per cycle falls below 10⁻² with bias above 100 at fixed n̄; demote the efficiency claims if it stays near 10⁻¹. Best case 2029: a cat at n̄ ≥ 5 with millisecond lifetime under active stabilisation. Worst case: bias saturates and the 758-cat and 126,133-cat estimates stay unreachable S[95], [96]. Open: does squeezing survive multi-qubit operation; can pump power rise without loading T1? Watch Lithium and any Ocelot successor.
References
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [77] N. Coppola, “Alice & Bob Shares Preliminary Results Vastly Surpassing Previous Bit-Flip Time Record,” Alice & Bob, Sep. 25, 2025. [Online]. Available: https://alice-bob.com/
newsroom/ Calice-bob-surpasses-bit-flip-stability-record - [78] N. Coppola, “Alice & Bob Improves Error Suppression in Quantum Computers by 'Squeezing' Cat Qubits,” Alice & Bob, Mar. 11, 2025. [Online]. Available: https://alice-bob.com/
newsroom/ Dsqueezed-cat-qubit/ - [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
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roadmap/ C
Русский текст загружается…
הטקסט בעברית נטען…
Hyperfine / clock-state qubit
Two ground-state hyperfine or nuclear-spin sublevels at a field-insensitive clock point, the default qubit for every trapped-ion and neutral-atom vendor.
Verdict. The least differentiating layer in the ion/atom stack — universal, so no moat and no lock-out; the contest is one layer up, in how the qubit is driven.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two hyperfine (or nuclear-spin) ground-state sublevels at a bias field where the first-order Zeeman shift vanishes, leaving only the quadratic term: coherence in seconds to hours, with single-ion memories reaching hour scale [104]. The lineage is the field's own: NIST's first ion-trap logic gate stored a qubit in the internal states of one laser-cooled ion (Monroe, Meekhof, King, Itano, Wineland, PRL 75, 4714, 1995) [374], the default for ions and later atoms ever since.
f = Pauli + leakage — leakage into neighbouring sublevels, invisible to a Pauli decoder; reach: four architectures, QCCD and electronic-gate ions, alkali atoms, and alkaline-earth and alkaline-earth-like atoms (Sr, Yb) [graph].
Physics & limits
The clock point kills first-order field sensitivity; what remains is the quadratic Zeeman term plus field gradients across the register, so memory degrades with register size, not only time. The memory is not the limit — the drive is. Raman gates carry a spontaneous-scattering error falling only as ~1/Δ, and the scattered photon usually lands outside the qubit manifold: leakage, not Pauli error. Deleting the laser deletes that term — 2Q 99.97(1)%, 1Q 99.99916(7)% on a ten-qubit seven-zone trap Dfact, 8.4×10⁻⁵ without ground-state cooling D[102]. The control modality moves the floor, not the encoding.
Engineering state of the art
table
| Date | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-12-05 | ⁴³Ca⁺ clock qubit, chip microwave resonator, room temperature, unshielded: 1.5(4)×10⁻⁷ per Clifford, T2 ≈ 70 s | Oxford | D[103]fact |
| 2025-11 | Helios fleet (98 Ba⁺): 1Q 2.5×10⁻⁵, 2Q 7.9×10⁻⁴, leakage 1.1×10⁻⁵ per Clifford | Quantinuum | D[97] |
On atoms, Cs hyperfine T2 = 12.6 s in a 6,100-atom array D[138]. Fleet-scale term: two-qubit-gate leakage, ~10⁻⁵ per Clifford on ions against ~10⁻⁴ per atom per gate on arrays.
The PatSnap counts mix patents and papers. Not published: the isotope and transition of the hour-scale Yb⁺ memory, which its abstract calls "a single Yb ion-qubit memory"; a multi-qubit fleet-average equivalent of Oxford's 1.5(4)×10⁻⁷; and a dated supplier of isotopically enriched ¹³⁷Ba or ¹⁷¹Yb, so the enrichment chokepoint is unconfirmed.
Manufacturing, materials & supply chain
No dedicated process; the encoding rides whatever surrounds the species (Ba⁺, Yb⁺, Ca⁺, Cs, Rb, Sr). Two control families, two supply chains: Raman gates need the optical stack — Helios runs seven-plus wavelengths across 1,228 electrodes — while chip microwave traces delete it and move the burden to trap fabrication, internalised by IonQ's SkyWater purchase C[19]; eleQtron sells the same idea as MAGIC C[129]. Enriched ¹³⁷Ba and ¹⁷¹Yb are the plausible chokepoint, but no dated supplier fact was found; no specific ECCN.
Role in the stack
Architectures: the primary encoding of all three trapped-ion architectures (QCCD; linear Paul trap with individual laser addressing; electronic qubit control) and of the alkali Rydberg tweezer array, and the alternate on the alkaline-earth tweezer array. Requires nothing — the base encoding, the most reused node in the tree. Its "replaces" edge to omg is an extension: omg keeps these ground states and adds a metastable manifold so one species supplies qubit, ancilla and coolant fact. It adds nothing to the derived clock, set on the QCCD architecture by transport — a 9.66 ms round against the measured ~55 ms full-width layer (≈18 layers/s) and a 70 µs gate. Verification: Oxford's 1.5(4)×10⁻⁷ is one qubit in a dedicated apparatus, Quantinuum's 2.5×10⁻⁵ a 98-ion fleet average — three orders apart; only the fleet number is an architectural input.
Actors & economics
Who.
| Organisation | Role | Country | What exactly | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US | Helios, 98 Ba⁺ qubits | D[97] |
| IonQ | developer | US | Electronic gates, own trap fab | D[102]C[19] |
| University of Oxford | research | UK | ⁴³Ca⁺ single-qubit record | D[103] |
| Atom Computing | developer | US | Yb nuclear-spin clock qubits | C[154] |
Money.
2026-06-03 · Quantinuum · IPO, Nasdaq QNT, after a Sep-2025 round at $10 B pre-money · $1.68 B gross · closed Cfactfact
2026-07-31 · IonQ · SkyWater acquisition closed · ~$1.8 B Cfact
Market & supply chain. Nothing is sold as "hyperfine encoding": the money is in the drive, laser chains against microwave traps. Concentration is low in optics, rising in traps now IonQ owns a fab. Pays G3/G4/G7, the substrate under nearly every logical qubit yet demonstrated.
IP & standards. PatSnap Eureka (2026) ranks IonQ first among named assignees, 9+ records (5 JP, 2 EP, 2 IL pending) on gate pulses and motional modes; the count mixes patents with papers P[375].
Roadmaps & track record. Quantinuum: Sol 2027, Apollo 2029 (promised 2024-09-10); Helios on schedule 2025-11-05, 10×/year quantum volume held. IonQ: 256 qubits at 99.99% slipped to H1 2027, and 4,000 qubits by 2026 (promised 2020) missed ~40×. Quantinuum delivers dates, IonQ physics.
Strategic reading. Universality is the point: everyone uses it, so it is neither moat nor lock-out. The contest is the drive. If all-electronic control scales past ten qubits the laser chain becomes a liability for Quantinuum and every atom vendor; if not, IonQ bought a foundry for a lab result.
Outlook & open questions
Confirm if all-electronic control reaches a fleet average below 10⁻⁵ with published leakage, or a second group replicates 8.4×10⁻⁵; demote if it stays a ten-qubit result. Best case 2029: microwave-driven hyperfine qubits the default. Worst case: gradient-limited leakage caps ions near 10⁻⁵ and omg takes the base.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [103] M. C. Smith, A. D. Leu, K. Miyanishi, M. F. Gely, and D. M. Lucas, “Single-qubit gates with errors at the 10⁻⁷ level,” Phys. Rev. Lett., vol. 134, no. 23, Art. no. 230601, Jun. 2025, doi: 10.1103/42w2-6ccy. arXiv:2412.04421. D
- [104] P. Wang et al., “Single ion-qubit exceeding one hour coherence time,” Nat. Commun., vol. 12, Art. no. 233, Jan. 2021, doi: 10.1038/s41467-020-20330-w. arXiv:2008.00251. D
- [129] A. Cordes, “Quantum computing scale-up eleQtron secures €57 million in one of the largest Series A funding rounds worldwide,” eleQtron, May 5, 2026. [Online]. Available: https://eleqtron.com/
en/ Cquantum-computing-scale-up-eleqtron-secures-57-million-in-one-of-the-largest-series-a-funding-rounds-worldwide/ - [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [374] C. R. Monroe, D. M. Meekhof, B. E. King, W. M. Itano, and D. J. Wineland, “Demonstration of a Fundamental Quantum Logic Gate,” Phys. Rev. Lett., vol. 75, no. 25, pp. 4714–4717, Dec. 1995, doi: 10.1103/PhysRevLett.75.4714. D
- [375] PatSnap, “Trapped Ion Quantum Computing: Technology Landscape 2026,” Apr. 23, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ trapped-ion-quantum-computing-2026-patsnap-eureka/
G Smith, Leu, Miyanishi, Gely, Lucas (Oxford), "Single-qubit gates with errors at the 10^-7 level", arXiv:2412.04421 (2024-12-05, rev 2025-05-28): 43Ca+ hyperfine clock qubit in a mi… · 2024-12-05 · https://arxiv.org/abs/2412.04421
G Loschnauer, Mosca Toba, Hughes, King, Weber, Srinivas, Matt, Nourshargh, Allcock, Ballance, Matthiesen, Malinowski, Harty, "Scalable, high-fidelity all-electronic control of trappe… · 2024-07-10 · https://arxiv.org/abs/2407.07694
G Allcock, Campbell, Chiaverini, Chuang, Hudson, Moore, Ransford, Roman, Sage, Wineland, "omg blueprint for trapped ion quantum computing with metastable states", Applied Physics Let… · 2021 · https://cua.mit.edu/dev_site/publications/omg-blueprint-for-trapped-ion-quantum-computing-with-metastable-states
G Quantinuum raised $600 M at a $10 B pre-money valuation (NVentures, Quanta, QED, JPMorgan), 2025-09-04 · 2025-09-04 · https://www.honeywell.com/us/en/news/press-releases/2025/09/honeywell-announces-600-million-capital-raise-for-quantinuum-at-10b-pre-money-equity-valuation-to-advance-quantum-computing-at-scale
G Quantinuum IPO priced 2026-06-03: 28,000,000 shares at $60 = $1.68 B gross, Nasdaq QNT; Q2-2026 revenue $8.0 M, cash $2.1 B, FY guidance $28–32 M · 2026-06-03 · https://www.quantinuum.com/press-releases/quantinuum-announces-pricing-of-upsized-initial-public-offering
G IonQ acquired SkyWater Technology: $15.00 cash + 0.4883 IonQ shares per share (~$1.8 B at announcement 2026-01-26), closed 2026-07-31 · 2026-07-31 · https://www.ionq.com/news/ionq-completes-acquisition-of-skywater-technology
Русский текст загружается…
הטקסט בעברית נטען…
Single-spin (Loss–DiVincenzo) / nuclear-spin encoding
One qubit per spin-1/2 — a confined electron, hole or nucleus — with no encoded subspace, giving the smallest footprint and no leakage channel.
Verdict. The default encoding on every silicon, germanium, donor and defect platform; it buys minimum area and a clean Pauli error model at the cost of a resonant drive per qubit.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
One physical spin-1/2 is one qubit: an electron or hole in a gate-defined dot, or a nucleus bound to a donor or defect. Loss and DiVincenzo set it out in 1998 — dot-confined electron spins, rotations by a local resonant field, two-qubit gates by pulsed exchange D[819]. The nuclear variant drives a ³¹P or defect nucleus by radio frequency through hyperfine coupling to an electron, trading speed for coherence: nuclei as data, electrons as ancillas. Attributes: affinity — a near-natural carrier with no composite structure; error — coherent dephasing plus Pauli error, no leakage subspace, no control modality or fabrication of its own.
Physics & limits
The computational space is the whole two-level system: nothing leaks out, so every error is Pauli or coherent as the codes assume — and nothing is filtered out either. T2* is set by residual ²⁹Si hyperfine coupling and by charge noise turned into a frequency shift through the g-factor or a micromagnet; ²⁸Si purification removes the first term. Coherence is not the limit today: QuTech's microwave-free array bounds its hopping gate at ≥99.50(6)% D[820] and foundry two-qubit gates sit at 99.04–99.56% D[189] — a calibration-limited plateau, not a T2 limit. Deeper purification, baseband control and cold calibration move the floor.
Engineering state of the art
table
| year | figure | who | tag+key |
|---|---|---|---|
| 2025-07-01 | ≥99.50(6)% hopping gate (lower bound), no microwave, 2×2 array | QuTech/TU Delft | D[820] |
| 2025-09-24 | 99.04–99.56% two-qubit on 300 mm foundry SiMOS | Diraq | D[189] |
| 2025-12-17 | 11-qubit donor register, 9 nuclear plus 2 electron, 99.10–99.99% | Silicon Quantum Computing | D[192] |
Dominant term: calibration drift across the array; no device above 12 qubits publishes all-pairs fidelities.
The 99.90% donor nuclear-spin CZ fidelity cannot be isolated in the SQC abstract, whose published range is 99.10–99.99%. Intel's "scale to hundreds of dots" carries no date or milestone.
Manufacturing, materials & supply chain
The encoding adds no structure — one dot or donor per qubit, about a third of the dots an exchange-only qubit needs — and inherits the carrier's process: Intel's 300 mm EUV line at >24,000 devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766], plus 22FDX, FD-SOI and imec 300 mm. The burden it imposes is control: one resonant drive per qubit frequency, so at 10³ qubits the wall is frequency crowding and microwave power at millikelvin, at 10⁴–10⁶ the count of addressable tones.
Role in the stack
The base encoding for the silicon and germanium quantum-dot architecture, the donor architecture and defect-spin network nodes. It is replaced in some designs by exchange-only encoding — the central fork: microwave hardware for minimum footprint and no leakage, against extra dots for baseband-only control and a leakage channel. It adds nothing to derived clock = sum of the syndrome round: gate layers + transport + readout + reset, which on silicon stays readout-dominated at 8.5×10⁻⁶ s. Verification: the 99.50(6)% is a lower bound and the accompanying ~49 µs Hahn-echo a maximum, both routinely requoted as point estimates D[820]; the main report's "99.90% donor nuclear CZ" conflicts with the published SQC range D[192]; and HRL's 2×10⁻⁴ single-qubit error belongs to exchange-only encoding, not this one D[190].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Intel | developer | USA | 300 mm EUV single-spin devices | D[199] |
| Diraq | developer | Australia | Electron spins on 300 mm imec SiMOS | D[189] |
| QuTech/TU Delft | research | Netherlands | Microwave-free baseband control | D[820] |
| Silicon Quantum Computing | developer | Australia | Nuclear-spin encoding on donors | D[192] |
| Quobly | developer | France | Single spins on STMicroelectronics FD-SOI | Cfact |
Money. 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · €134 M cumulative · closed Cfact. 2026-06 · SQC · NRFC · A$60 M · Australia's National Reconstruction Fund · closed fact.
Market & supply chain. No supplier is specific to this encoding — it is a layout and pulse-sequence choice on shared CMOS lines — and its one distinctive demand, a resonant drive per qubit, is what the control-electronics duopoly sells. Pays into G2, G3 and G6.
IP & standards. The 1998 proposal is prior art long out of patent term D[819]; no dated patent family for single-spin encoding found in a named database as of 4 Sep 2026.
Roadmaps & track record. Intel (2026-01-06 · 12 qubits at Argonne, "scale to hundreds of dots" · no successor chip, no dated roadmap) fact. Diraq (2026-08-27 · 150 k physical, 1 k logical by 2029 · its 2026-07-09 release said "thousands by 2029") Rfact. Both are orders of magnitude beyond any demonstrated device.
Strategic reading. Every spin team can fall back on it, so it differentiates nobody: value accrues to the fab and the control stack. If baseband control matures the microwave vendors lose their strongest claim; if encoded qubits win, area matters less than wafer economics.
Outlook & open questions
Confirm or demote in 12–24 months: all-pairs fidelities above 12 qubits; baseband control beyond a 2×2 array. Best case 2029: baseband plus 1 K operation removes most microwave I/O at >99.5% two-qubit fidelity. Worst case: the plateau holds. Open: (1) whether hopping-gate control scales past four qubits; (2) whether the calibration-limited diagnosis generalises; (3) which platform shows a below-threshold logical qubit.
References
- [189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fidelity,” Nature, vol. 646, no. 8083, pp. 81–87, Sep. 2025, doi: 10.1038/s41586-025-09531-9. D
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [192] H. Edlbauer et al., “An 11-qubit atom processor in silicon,” Nature, vol. 648, no. 8094, pp. 569–575, Dec. 2025, doi: 10.1038/s41586-025-09827-w. arXiv:2506.03567. D
- [199] H. C. George et al., “12-spin-qubit arrays fabricated on a 300 mm semiconductor manufacturing line,” Nano Lett., vol. 25, no. 2, pp. 793–799, Dec. 2024, doi: 10.1021/acs.nanolett.4c05205. arXiv:2410.16583. D
- [766] S. F. Neyens et al., “Probing single electrons across 300-mm spin qubit wafers,” Nature, vol. 629, no. 8010, pp. 80–85, May 2024, doi: 10.1038/s41586-024-07275-6. D
- [819] D. Loss and D. P. DiVincenzo, “Quantum computation with quantum dots,” Phys. Rev. A, vol. 57, no. 1, pp. 120–126, Jan. 1998, doi: 10.1103/PhysRevA.57.120. D
- [820] F. K. Unseld et al., “Baseband control of single-electron silicon spin qubits in two dimensions,” Nat. Commun., vol. 16, no. 1, Art. no. 5605, Jul. 2025, doi: 10.1038/s41467-025-60351-x. D
Русский текст загружается…
הטקסט בעברית נטען…
Optical narrow-line qubit (ion S–D, atom clock)
A qubit split between a ground level and a metastable level one optical photon above it — the S₁/₂–D₅/₂ quadrupole line of ⁴⁰Ca⁺ or ⁸⁸Sr⁺, or the ¹S₀–³P₀ clock line of neutral Sr/Yb — with one narrow-line laser driving every gate.
Verdict. Proven on both carriers — ⁴⁰Ca⁺ in AQT's shipped machines, ⁸⁸Sr clock qubits at 99.62(3) % entangling fidelity in the laboratory — but coherence is set by the laser and the magnetic field, not the atom: 90(30) ms against a 1.168(7) s D₅/₂ lifetime in AQT's demonstrator. As of 2026-09-26 planqc, the register's only company on the atomic clock qubit, publishes no gate error or coherence time of its own.
T2 = Ramsey phase-coherence time; MS = Mølmer–Sørensen gate; CZ = controlled-Z gate; SPAM = state preparation and measurement; QV = quantum volume; TRL = technology readiness level; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The ion realisation stores |1⟩ in |4S₁/₂, m = −1/2⟩ and |0⟩ in |3D₅/₂, m = −1/2⟩ of ⁴⁰Ca⁺, coupled by the 729 nm electric-quadrupole line D[253]. Innsbruck ran the Cirac–Zoller CNOT on two such ions in 2003 D[376]; the encoding carried its fault-tolerant universal gate set of 2022 D[255] and AQT's products. ⁸⁸Sr⁺ at 674 nm is the sister ion, its D₅/₂ lifetime measured on a single ion at NPL D[377]. The atom realisation uses ¹S₀ and ³P₀ of neutral strontium, the lattice-clock line, run in tweezers since 2019 D[378], with alkaline-earth Rydberg entanglement from 2020 D[379]. Attributes: natural carrier; no time, mobility or control of its own; errors Pauli plus leakage.
Physics & limits
Three ceilings. Lifetime: τ(D₅/₂, ⁴⁰Ca⁺) = 1.168(7) s D[253], so T2 ≤ 2τ ≈ 2.3 s; decay from m = −1/2 may land in S₁/₂, m = +1/2, outside the qubit pair — leakage G. The Sr ³P₀ level outlives the >3 s atomic coherence measured in a tweezer clock D[378]. Field: ⁴⁰Ca⁺ has no hyperfine structure, hence no field-insensitive line; with g(D₅/₂) = 6/5 and g(S₁/₂) ≈ 2.002 the qubit line moves 0.40 μB B ≈ 5.6 kHz per µT, so 0.1 µT of noise shifts it 560 Hz, a radian in 0.3 ms S. Mitigations: shielding, mains feed-forward, dynamical decoupling, decoherence-free pairs. The J = 0 → J = 0 clock line has no first-order electronic Zeeman shift G. Laser: every gate references the laser phase, so T2 is the laser's coherence over the circuit. AQT measured Ramsey T2 = 90(30) ms on the optical qubit against 18(1) ms on the ground-state Zeeman qubit, naming magnetic noise from mains and neighbouring magnets beyond 25 ms D[253] — 26× below the lifetime bound S.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2003-03 | Cirac–Zoller CNOT on two ⁴⁰Ca⁺ S–D qubits | Innsbruck | D[376] |
| 2019 | Sr tweezer clock, >3 s coherence, duty cycle up to 96 % | JILA | D[378] |
| 2021-06 | τ(D₅/₂) 1.168(7) s; T2 90(30) ms; 24-ion GHZ fidelity 0.544(7) | AQT/Innsbruck | D[253] |
| 2022-08 | Sr clock-qubit Bell state 92.8(2.0) % SPAM-corrected; Bell coherence 4.2(6) s | JILA | D[380] |
| 2024-10 | ⁸⁸Sr clock-qubit entangling gate 99.62(3) %; ancilla readout | Caltech | D[381] |
| 2026-05 | LYNX QV 32,768; first units Q4 2026 | AQT | C[128] |
The shipped figure: IBEX Q1, 12 qubits, 1Q 99.97(1) %, 2Q 98.7(3) % over all pairs, QV 128 C[382]; MARMOT, 20 qubits, 2Q (98.47 ± 0.3) % on an 11-qubit register C[383]. Atoms lead on fidelity, ions on deployment.
Manufacturing, materials & supply chain
No fabricated part; the item is the narrow-line laser — 729 nm (Ca⁺), 674 nm (Sr⁺), 698 nm (Sr) — locked to a high-finesse reference cavity G. AQT's demonstrator uses seven wavelengths (375, 397, 423, 515, 729, 854, 866 nm); the 854 nm quench laser exists only because the qubit level is metastable D[253]. IBEX Q1 fills two 19-inch racks, 2 m², <2 kW, at (22.0 ± 1.5) °C C[382].
Control, readout & I/O burden
One phase-stable laser per species, split into individually addressed 729 nm beams on the ion chain D[255]; fibre and modulator phase noise lands directly on the qubit S. Readout is electron shelving — D₅/₂ stays dark on the 397 nm cycling line — by camera or photodiode, ~99.9 % in 300 µs D[253]; atoms add ancilla-based readout with non-destructive conditional reset D[381].
Role in the stack
Slot 2 of Trapped ions — linear Paul trap with individual laser addressing, and of Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native, beside enc_hf and enc_omg. It requires either ion (S–D quadrupole transition) or ae_atom (¹S₀–³P₀ of Sr/Yb). It is replaced by enc_hf, whose field-insensitive ground-state pair trades the one-laser drive for Raman or microwave control. It provides single-laser universality and shelving readout, and the metastable manifold that the omg erasure scheme reuses S[333]; it defines the channel metric τ(D₅/₂) = 1.17 s. Register: IBEX Q1 (Marmot / PINE / LYNX) ✅ and University of Innsbruck / IQOQI research trap ✅; PIAST-Q 🔎 (20 AQT qubits, species unnamed — consistent with MARMOT); MAQCS and DiNAQC 🔎. Gap G-enc-clock is answered: the ledger's 10–100 ms is planqc's range in a press profile P[247], 30–300× below published clock-qubit arrays D[380], so it measures a laser, not the encoding.
Evidence — how the numbers were measured
AQT's 98.7(3) % is an all-pairs product average C[382]; a secondary 97.7 % in the register stays unreconciled. The demonstrator's 0.997(6) is a two-ion Bell-state fidelity, not randomised benchmarking D[253]. Caltech's 99.62(3) % is averaged over symmetric input states D[381]. LYNX publishes QV without qubit count or fidelity C[128]. No vendor reports T2 beside τ, as of 2026-09-26.
Not published: planqc's computing species and transition — its technology and LRZ pages name neither strontium nor the clock transition — and the species and product of PIAST-Q.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| AQT | developer | Austria | IBEX Q1, MARMOT, LYNX on ⁴⁰Ca⁺ | C[383] |
| University of Innsbruck | research | Austria | Origin; fault-tolerant gates on ⁴⁰Ca⁺ | D[255] |
| planqc | developer | Germany | Sr clock-transition qubits; MAQCS at LRZ | P[247] |
| JILA / Kaufman group | research | US | Sr clock-qubit Bell states | D[380] |
| Caltech / Endres group | research | US | ⁸⁸Sr clock-qubit gates, ancilla readout | D[381] |
Money.
- 2024-07 · planqc · Series A · €50 M · closed P[247]
- 2026-09-09 · planqc / LRZ · MAQCS, first hardware delivered · almost €20 M (BMFTR) · under construction C[161]
Market & supply chain. One ultrastable laser and cavity per species is the concentration point. Pays into G2, G3 and G7.
IP & standards. No patent search was run; no standard defines reporting of laser-limited T2, as of 2026-09-26.
Roadmaps & track record. (AQT · LYNX first units · Q4 2026) C[128]; (planqc · MAQCS co-processor · end-2027, TRL 5 today, 6–7 targeted) R[161].
Strategic reading. On ions the encoding is AQT's legacy, its depth capped by τ; on atoms it is the best-gated clock qubit, and a clock-grade laser on a processor is the prize.
Outlook & open questions
Confirm the atomic branch if planqc publishes clock-qubit T2 and CZ fidelity on MAQCS hardware by 2027-12-31; demote it to metrology if not. Confirm the ion branch if LYNX ships in Q4 2026 with per-pair 2Q figures. Open questions. (1) What laser linewidth would bring ⁴⁰Ca⁺ T2 to its 2.3 s bound? (2) Is planqc's 10–100 ms the lattice, the laser or the field? (3) How much D₅/₂ decay leaks versus flips? (4) Will AQT move to a hyperfine or omg species? (5) Can one clock laser serve 10³ sites?
References
- [128] Alpine Quantum Technologies GmbH, “AQT Sets New European Industry Standard: Introducing the ‘LYNX’ Series with Record-Breaking Quantum Volume,” AQT, May 5, 2026. [Online]. Available: https://www.aqt.eu/
lynx-quantum-volume-record/ C - [161] planqc, “MAQCS takes shape as first quantum computing hardware arrives at LRZ,” Sep. 9, 2026. [Online]. Available: https://planqc.eu/
news/ Cmaqcs-takes-shape-as-first-quantum-computing-hardware-arrives-at-lrz - [247] M. Ivezic, “Planqc,” PostQuantum, May 22, 2025. [Online]. Available: https://postquantum.com/
quantum-computing-companies/ Pplanqc/ - [253] I. Pogorelov et al., “Compact Ion-Trap Quantum Computing Demonstrator,” PRX Quantum, vol. 2, no. 2, Art. no. 020343, Jun. 2021, doi: 10.1103/PRXQuantum.2.020343. arXiv:2101.11390. D
- [255] L. Postler et al., “Demonstration of fault-tolerant universal quantum gate operations,” Nature, vol. 605, pp. 675–680, 2022, doi: 10.1038/s41586-022-04721-1. arXiv:2111.12654. D
- [333] D. T. C. Allcock et al., “omg blueprint for trapped ion quantum computing with metastable states,” Appl. Phys. Lett., vol. 119, no. 21, Art. no. 214002, Nov. 2021, doi: 10.1063/5.0069544. arXiv:2109.01272. S
- [376] F. Schmidt-Kaler et al., “Realization of the Cirac–Zoller controlled-NOT quantum gate,” Nature, vol. 422, pp. 408–411, Mar. 2003, doi: 10.1038/nature01494. D
- [377] V. Letchumanan, M. A. Wilson, P. Gill, and A. G. Sinclair, “Lifetime measurement of the metastable 4d ²D₅/₂ state in ⁸⁸Sr⁺ using a single trapped ion,” Phys. Rev. A, vol. 72, Art. no. 012509, Jul. 2005, doi: 10.1103/PhysRevA.72.012509. D
- [378] M. A. Norcia et al., “Seconds-scale coherence on an optical clock transition in a tweezer array,” Science, vol. 366, p. 93, 2019. arXiv:1904.10934. D
- [379] I. S. Madjarov et al., “High-fidelity entanglement and detection of alkaline-earth Rydberg atoms,” Nat. Phys., vol. 16, pp. 857–861, May 2020, doi: 10.1038/s41567-020-0903-z. arXiv:2001.04455. D
- [380] N. Schine, A. W. Young, W. J. Eckner, M. J. Martin, and A. M. Kaufman, “Long-lived Bell states in an array of optical clock qubits,” Nat. Phys., vol. 18, pp. 1067–1073, Aug. 2022, doi: 10.1038/s41567-022-01678-w. arXiv:2111.14653. D
- [381] R. Finkelstein et al., “Universal quantum operations and ancilla-based read-out for tweezer clocks,” Nature, vol. 634, pp. 321–327, Oct. 2024, doi: 10.1038/s41586-024-08005-8. D
- [382] Alpine Quantum Technologies, “19-inch rack-mounted quantum computer,” AQT. [Online]. Available: https://www.aqt.eu/
products/ Cibex-q1/ - [383] Alpine Quantum Technologies (AQT), “Quantum computer products built for performance,” AQT. [Online]. Available: https://www.aqt.eu/
products/ C
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הטקסט בעברית נטען…
Bare physical qubit (no encoding)
The {|0⟩,|1⟩} subspace of a weakly anharmonic Josephson oscillator used directly as the qubit, with no bosonic, erasure or bias structure on top.
Verdict. The default of every mainstream superconducting vendor as of 2026-09-04; its structural cost is leakage plus an unbiased error model, which caps measured Λ at 1.4–2.1 where erasure encodings simulate an order of magnitude higher.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Using the lowest two levels of a Josephson circuit directly as a qubit is as old as the Cooper-pair box (Nakamura, 1999); the transmon (Koch et al., 2007) made it the default by buying charge insensitivity with lower anharmonicity — which is what creates the leakage problem.
Attributes: it adds no characteristic time, readout, mobility, control or fabrication of its own — each is the carrier's.
Error structure as the code sees it: unbiased Pauli plus leakage out of the subspace.
Physics & limits
The scale that matters is α ≈ −EC ≈ 2π × 200–300 MHz: it sets the minimum gate time and the leakage per gate, which DRAG (derivative removal by adiabatic gate) pulse shaping suppresses but cannot remove. Raising α costs charge dispersion, which grows as exp(−√(8E_J/E_C)); that trade is the floor here. Leakage persists where a Pauli fault does not: the second excited state survives tens of QEC cycles at Willow's 1.1 µs D[1], feeding the decoder correlated wrong syndromes. Hence dedicated removal: USTC's all-microwave scheme suppresses leakage 72×, to a residual 6.4(5)×10⁻⁴ after 40 cycles D[3]. What moves the floor is leakage-aware decoding and faster multi-level reset.
Engineering state of the art
table
Best in class is one characterised IQM pair, CZ 99.93% over 40 h D[38]; typical at scale is IBM's fleet EPLG 3.7×10⁻³, best 1.9×10⁻³ D[34], and Rigetti's 108-qubit median 99.1% C[36].
The 72× leakage suppression and the 6.4(5)×10⁻⁴ residual come from one USTC device, unreplicated as of 2026-09-04; the paper does not name the processor, and the "Zuchongzhi 3.2" label comes from outside it. Not published: a leakage figure for IBM's fleet, whose EPLG aggregates all error mechanisms.
Manufacturing, materials & supply chain
Nothing of its own: it inherits the carrier's 300 mm Nb/Al lithography, yield spread and one drive plus one readout line per qubit. That is the whole commercial argument — dual-rail erasure adds a rail and a check per qubit (384 ns, 2.54×10⁻² erasure D[85]), cat codes a pump and buffer mode. The I/O wall is the carrier's: coax per qubit, ~10³ qubits per fridge. What this encoding adds at 10⁴–10⁶ is leakage removal inside every 1.1 µs cycle and the decoder bandwidth to use it. Export exposure is the carrier's (US EAR ECCN 3A901).
Role in the stack
The default Layer-2 encoding on the transmon lattice with tunable couplers (IBM, Google, Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu). Dual-rail erasure or cat encoding replaces it when a vendor trades control complexity for a friendlier error structure: Alice & Bob, AWS and D-Wave/Quantum Circuits have, IBM and Google have not. The price is quantifiable: measured dual-rail gate errors simulate to Λ ≈ 27 against 14 for 0.1% depolarising noise S[84], where this encoding measures 2.14 and 1.40(6) D[1], [3]. It adds nothing to the derived clock, which stays the carrier's 0.65 µs round inside its measured 1.1 µs cycle. Verification: the 72× is one unreplicated USTC device, and leakage is self-reported with no cross-vendor protocol.
Actors & economics
Who.
Money.
2026-06-02 · IBM · investment commitment · > $10 B over five years · announced G[57]fact
2026-07-02 · IQM · Nasdaq and Helsinki listing · pro-forma cash €337 M · closed C[58]fact
Market & supply chain. No supply chain of its own; concentration sits one layer down, in Nb/Al lithography and dilution refrigerators. Being free, it is what every G1–G4 budget on this architecture buys.
IP & standards. No dated patent family found for bare-subspace leakage mitigation as of 2026-09-04; PatSnap's 2026-06-30 counts are not encoding-specific Pfact.
Roadmaps & track record. IBM (2025-06-10 · Starling, 200 logical / 10⁸ gates in 2029 · Nighthawk on plan, Kookaburra slipped a year fact). Google (2025 · long-lived logical qubit at 10⁻⁶ · no successor to Willow). Neither publishes a leakage target.
Strategic reading. Its edge is that it is free, so the fork is capital allocation: money spent switching to erasure is not spent scaling the bare fleet. If Λ stays near 2, erasure encodings win on physical qubits per logical; otherwise incumbents keep the field.
Outlook & open questions
Confirm by end-2027: ≥ 50× leakage suppression in a below-threshold code outside USTC, or leakage published as a line item in a vendor's logical error budget; otherwise demote it to a single-device claim. Best case 2029: leakage falls under the correlated-event floor (≈10⁻¹⁰, hourly bursts on Willow D[1]); worst case, Λ stays near 2 and physical-per-logical above 10³. Does leakage or 2Q error dominate at 10⁴ qubits? Can removal keep up at 10⁶? Does erasure conversion ever cross over commercially?
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [3] T. He et al., “Experimental Quantum Error Correction below the Surface Code Threshold via All-Microwave Leakage Suppression,” Phys. Rev. Lett., vol. 135, no. 26, Art. no. 260601, Dec. 2025, doi: 10.1103/rqkg-dw31. D
- [34] IBM Quantum, “What's new at IBM Quantum - Q2 2026.” [Online]. Available: https://www.ibm.com/
quantum/ Dblog/ whats-new-q2-2026 - [36] Rigetti Computing, Inc., “Rigetti Announces General Availability of 108-Qubit System,” Apr. 7, 2026. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ rigetti-announces-general-availability-108-qubit-system - [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
- [57] IBM Quantum, “Why IBM is investing $10 billion into quantum computing,” Jun. 2, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Gblog/ 10-billion-investment-faq - [58] IQM Quantum Computers, “IQM Quantum Computers Becomes First European Quantum Computing Company Listed on a Major U.S. Exchange,” Jul. 2, 2026. [Online]. Available: https://iqm.tech/
press-releases/ Ciqm-quantum-computers-becomes-first-european-quantum-computing-company-listed-on-a-major-u-s-exchange/ - [84] N. Mehta et al., “An entangling gate for dual-rail erasure qubits,” Nature, vol. 656, no. 8126, pp. 47–53, Aug. 2026, doi: 10.1038/s41586-026-10822-y. arXiv:2503.10935. S
- [85] J. S.-C. Hung et al., “Fast, High-Fidelity Erasure Detection of Dual-Rail Qubits with Symmetrically Coupled Readout,” arXiv:2604.16292, Apr. 2026. D
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הטקסט בעברית נטען…
Exchange-only / singlet–triplet spin encoding
One logical qubit in the total-spin subspace of three exchange-coupled spins (exchange-only) or two spins plus a field gradient (singlet–triplet), driven entirely by baseband voltage pulses, with leakage as the price of removing microwave control.
Verdict. The only spin encoding that has run error correction with no room-temperature real-time electronics; it costs three dots per qubit and a leakage channel, and its headline code result is bit-flip only.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two or three spins in adjacent dots encode one qubit in a subspace of fixed total spin, every gate a pulse of Heisenberg exchange — baseband voltage, never a microwave tone. The basis is DiVincenzo, Bacon, Kempe, Burkard and Whaley, Nature 408, 339 (2000): exchange alone implements any circuit, so local single-qubit drive disappears S[416]. Scaled three-dot demonstrations date from about 2013. Attributes: affinity — fully composite, the opposite pole from the bare spin; error — leakage plus coherent exchange error, no control modality or fabrication of its own.
Physics & limits
Three spins span eight states and the qubit uses two, so population leaks into the spin-3/2 manifold, invisible to a Pauli-frame decoder unless converted into detectable error. That is the encoding-specific floor: 0.015% per Clifford for always-on two-exchange operation against a 0.029% single-exchange average D[417]. In return it is a decoherence-free subspace against uniform field noise, but exchange depends exponentially on barrier voltage, so charge noise enters the gate. Neither term dominates: HRL attributes roughly 80% of its CNOT error to extrinsic control and calibration D[190]. Sweet-spot operation, always-on pulsing (1.9 versus 2.7 pulses per Clifford D[417]) and cold calibration move it.
Engineering state of the art
table
Dominant term: extrinsic control and calibration, then leakage; best reproducible CNOT 9×10⁻⁴ D[190].
Benchmarked as one system rather than as encoded qubits, 48 spins of HRL's 54-dot device span the whole total-spin-zero space, of dimension C₂₄ ≈ 2⁴⁰ (a Catalan number), which includes the states a three-spin encoding treats as leakage; mirror randomised benchmarking gives an error of 3.2×10⁻⁴ per exchange pulse (2.2×10⁻⁴ device-wide by cross-entropy benchmarking), with the 4 K cryo-CMOS controller in the loop P[900]. That is an error per exchange pulse, not a two-qubit gate error: at 37 exchanges per encoded CNOT the additive estimate is about 1%. The space has no local qubits, and no method yet compiles programs or runs error correction in it P[900].
The 0.2 W per qubit is derived from HRL's published controller power and qubit count; the paper states no scaling figure. HRL's ~80% extrinsic-error attribution is self-reported, and neither the UCLA nor the HRL result has an independent replication. Not published: all-pairs two-qubit fidelities for any exchange-only device.
Manufacturing, materials & supply chain
Three dots per qubit — two for singlet–triplet — triples gate-stack density per logical unit on the hosting 300 mm process, with no encoding-specific step. The win is control: purely baseband, no microwave lines or micromagnets, the sequencer inside a 4 K controller in commercial 130 nm RF CMOS — 366 DACs, 296 lines, ≤3.5 W, no room-temperature real-time electronics D[190] — the first sign a control rack can become a cold ASIC. That sets the wall: ≤3.5 W for 18 qubits is ≈0.2 W per qubit, so 10³ qubits need hundreds of watts at 4 K, one to two orders beyond a standard pulse-tube stage S[190]. Power per qubit, not line count, is the scaling problem.
Role in the stack
Requires a gate-defined quantum-dot carrier at three dots per qubit, in the silicon and germanium quantum-dot spin architecture; replaces single-spin encoding, the central fork. Exchange pulses are nanoseconds, but a Clifford costs about two, so the encoding multiplies gate count, not gate time; readout still sets derived clock = sum of the syndrome round: gate layers + transport + readout + reset at 8.5×10⁻⁶ s, 6.3 µs of it readout. Verification: Λ₅/₃ = 4.7 and the 5.0×10⁻³ logical error come from a distance-5 repetition code, bit-flip only, not below-threshold operation of a full code; the [[4,2,2]] fidelity of 0.95 is post-selected D[190]. The UCLA 99.86% is single-qubit blind benchmarking, not device-wide D[417]; neither result is replicated.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| HRL Laboratories | developer | USA | 18 exchange-only qubits, 4 K controller | D[190] |
| IBM | developer | USA | Acquired HRL; no spin milestone on its roadmap | Cfact |
| UCLA | research | USA | Always-on two-exchange qubit | D[417] |
| Quantum Machines | supplier | Israel | Named control-stack supplier to HRL | Cfact |
Money. 2026-06-02 · IBM · quantum programme commitment · >$10 B over five years · announced Cfact. 2026-08-26 · IBM · HRL acquisition completed · undisclosed · closed Cfact.
Market & supply chain. No encoding-specific supply chain exists; the distinctive asset is HRL's cryogenic controller, now IBM property. Removing microwave generation shrinks the rack vendors' share of the bill — the only spin encoding threatening the control duopoly. Pays into G3.
IP & standards. The 2000 exchange-universality result is prior art out of patent term S[416]; IBM's HRL purchase is the clearest IP consolidation, terms undisclosed Cfact. No dated patent family for the encoding is in a named database as of 4 Sep 2026.
Roadmaps & track record. IBM and HRL (2026-08-26 · acquisition completed · no dated qubit-count milestone, no spin entry on Starling 2029 or Blue Jay) Cfact. The July 2026 paper is a physics demonstration, not a scaling promise.
Strategic reading. If leakage holds near 10⁻⁴ per Clifford at scale, three dots per qubit buys away the microwave subsystem and the rack — a system win for IBM and any fab printing dense arrays. If single-spin encoding closes the calibration gap, the overhead is pure area cost and the rack vendors keep their position.
Outlook & open questions
Confirm or demote in 12–24 months: a second laboratory reproducing the 18-qubit result; a full code below threshold; a dated IBM milestone. Best case 2029: IBM folds the cold sequencer into a foundry-scale device with unconditional performance. Worst case: a single-laboratory result. Open: (1) whether controller power per qubit falls two orders; (2) whether leakage stays flat as arrays grow; (3) whether always-on pulsing becomes the standard.
References
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [416] D. P. DiVincenzo, D. Bacon, J. Kempe, G. Burkard, and K. B. Whaley, “Universal quantum computation with the exchange interaction,” Nature, vol. 408, no. 6810, pp. 339–342, 2000, doi: 10.1038/35042541. arXiv:quant-ph/0005116. S
- [417] J. D. Broz, J. C. Hoke, E. Acuna, and J. R. Petta, “Demonstration of an always-on exchange-only spin qubit,” Nat. Commun., vol. 17, no. 1, Art. no. 4794, Apr. 2026, doi: 10.1038/s41467-026-70943-w. D
- [900] HRL Quantum Team and Microsoft collaborators, “Benchmarking exchange-only control of a 48-spin singlet manifold,” arXiv:2610.07393, Oct. 2026. P
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הטקסט בעברית נטען…
Ground–Rydberg analogue qubit
A two-level qubit formed by an atomic ground state |g⟩ and a Rydberg state |r⟩, driven globally under an Ising-type Hamiltonian: the computational basis of analogue Rydberg simulators, not an error-suppressing code.
Verdict. Its ceiling is the black-body-limited Rydberg lifetime (~150 µs for Rb 70S at 300 K), but its working window is set by Doppler and laser-phase dephasing (T2* ≈ 5–6 µs), which caps Aquila programs at 4 µs. As of 2026-09-26 it has no memory and no code, and both vendors' gate-model lines use the hyperfine basis instead.
Ω = Rabi frequency; Δ = detuning; C6 = van der Waals coefficient; Rb = blockade radius; T2* = Ramsey dephasing time; T2echo = spin-echo coherence time; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The qubit is a level pair inside one atom: |g⟩ in the 5S₁/₂ ground manifold and |r⟩ = |70S₁/₂⟩ in QuEra's ⁸⁷Rb machine Aquila, reached by a two-photon 420 nm + 1013 nm drive via 6P₃/₂ C[262]. "Encoding" names the computational basis of an analogue machine, not a code: the program is a Hamiltonian, the output a g/r pattern. The line starts with the 51-atom Harvard–MIT Ising-type simulator of 2017 D[384], co-authored by QuEra's CEO Alexander Keesling C[262]; Pasqal's architecture paper calls it the analogue level, "programming Hamiltonian sequences" C[385]. Attributes: natural carrier, nothing fabricated; no step time, control modality or placement of its own; loss and coherent errors.
Physics & limits
Aquila runs H(t) = (Ω/2)Σᵢ(e^{iφ}|gᵢ⟩⟨rᵢ| + h.c.) − ΔΣᵢnᵢ + Σ_{i<j} C6/|xᵢ−xⱼ|⁶ nᵢnⱼ, nᵢ = |rᵢ⟩⟨rᵢ|, with C6 = 5.42×10⁶ rad µm⁶ µs⁻¹ for 70S, |Ω| ≤ 15.8 rad/µs, |Δ| ≤ 125 rad/µs C[262]; Pulser uses the same convention for Pasqal's "ground-rydberg" basis C[386]. Blockade forbids two excitations within Rb = (C6/Ω)^{1/6} ≈ 8.4 µm at full drive S[262].
Three limits act on |r⟩. Decay: Rb 70S lives 410 µs at 0 K but 152 µs at 300 K (60S: 104 µs) S[387], black-body radiation carrying ~63% of the rate — the ceiling, and a loss channel. Doppler: for counter-propagating beams (k_eff ≈ 8.8 µm⁻¹) at 10 µK, a detuning spread σ ≈ 0.27 rad/µs gives a Ramsey 1/e time ≈ 5 µs S[262], matching the measured T2* = 4.5(1) µs D[388]. Phase noise and scattering: echo leaves T2 = 32(6) µs; T1 = 51(6) µs combines the 146 µs Rydberg lifetime with ~80 µs of 6P3/2 scattering D[388]. The 12.6(1) s hyperfine T2 of a Cs tweezer array D[138] does not apply: |r⟩ cannot be shelved, so there is no memory.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2017-07-13 | 51-atom programmable Ising-type model on g–r qubits | Harvard/MIT | D[384] |
| 2018-05 | g–r Rabi damping traced to several few-percent effects | Browaeys–Lahaye group | D[389] |
| 2018-09 | T2* 4.5(1) µs, T2echo 32(6) µs, Bell fidelity 0.97(3) | Harvard/MIT | D[388] |
| 2023-06-20 | Aquila: 256 sites, T2* 5.8 µs, T2echo 11.4 µs, 4 µs cap | QuEra | C[262] |
| 2023-10-11 | Sr g–r Bell fidelity ≥0.9971 after erasure excision | Caltech | D[143] |
| 2024-10-21 | (2+1)D string breaking, kagome array, local-detuning quench | QuEra, Zoller, Lukin | D[226] |
The window has barely moved: T2* rose from 4.5 to 5.8 µs, and Aquila stops programs at 4 µs, the "approximate timescale of coherent evolution" C[262].
Manufacturing, materials & supply chain
Nothing is fabricated at this layer; fabrication sits in fab_optics. The demand is spectral: a Rydberg laser pair beside 780 nm tweezers C[262] whose phase noise, not power, sets coherence; the 2018 gain came from reference-cavity filtering (FWHM ≈ 2π × 500 kHz) and injection locking D[388]. A cold enclosure would move 70S from 152 µs toward 410 µs S[387]; the register profiles the commercial machines as room-temperature.
Control, readout & I/O burden
Aquila drives one global Ω(t), Δ(t), φ(t) set C[262], so drive I/O is flat in atom number; local detuning, the first site-resolved knob, drove the string-breaking quench D[226] and is promised for Pasqal's Vela R[390]. Readout is destructive imaging with an asymmetric budget — Rydberg read as ground 0.08, ground as Rydberg 0.01, filling error 0.007 C[262] — so r-populations are undercounted S[262]. At under 10 shots per second C[262], 10⁴ shots take over a quarter-hour.
Role in the stack
On the architecture "Neutral-atom analogue simulator (Rydberg arrays, lattice gases)" (atom_analog) the technology fills slot 2; slots 7–9 (code to interconnect) are empty. It requires an atom with a Rydberg level (alkali), provides the ground–Rydberg states g_rydanalog requires, and is replaced by enc_hf. Register machines: Aquila (primary, ✅), Fresnel / Fresnel 2 (primary, 🔎), Orion Alpha/Beta/Gamma (alternate, analogue mode on atom_rb, 🔎 inferred). Gate-model lines use enc_hf: QuEra's Gemini is a 260-qubit digital machine C[137]; the Harvard–MIT gate work encodes in |F=1,mF=0⟩, |F=2,mF=0⟩ and visits 53S1/2 only during gates D[391]; Pasqal drives a separate "digital" basis |g⟩,|h⟩ by Raman channel C[386]. The gap ledger stands: enc_hf does not describe analogue machines. Its atom_rb/atom_ae placement became atom_analog; the alkaline-earth variant D[143] has no register machine.
Evidence — how the numbers were measured
Gate benchmarks do not apply; the figures are T2*, echo T2, Rabi damping, blockaded-pair coherence and readout asymmetry. Aquila publishes all of them (Rabi 7.5 µs, blockaded Rabi 8.9 µs) C[262], none independently re-measured; beyond classical simulation, programs are checked against phase diagrams D[226]. Grades: Aquila ✅; Fresnel 🔎, the paper's abstract confirming only the analogue/digital split C[385]; Orion 🔎, its cited blog naming neither analogue mode nor encoding C[390] — Pulser's basis definition is better evidence.
Gemini's product page names ⁸⁷Rb and a digital mode, not the hyperfine pair; its placement under hyperfine encoding rests on the Harvard–MIT gate papers. The string-breaking abstract does not name Aquila; only QuEra's authorship points to it. Not published: the Rydberg level, T2* and echo time of Pasqal's Fresnel and Orion, on Pasqal's pages; and, in the Aquila text, the beam geometry assumed in the Doppler estimate and the F, mF sublevel of |g⟩ in analogue mode.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| QuEra Computing | developer | US | Aquila, 256-site g–r machine with public coherence budget | C[262] |
| Pasqal | developer | France | Fresnel; "ground-rydberg" basis in Pulser | C[385]C[386] |
| Harvard/MIT (Lukin group) | research | US | Origin of the g–r simulator and its coherence analysis | D[384]D[388] |
| Caltech (Endres group) | research | US | Strontium g–r qubit with erasure detection | D[143] |
Money. No dated financial item is specific to the ground–Rydberg encoding as of 2026-09-26.
Market & supply chain. Two commercial actors, both also selling gate-model machines; Pasqal lists five hosting clouds and five sites, mode unstated C[390]. Concentration sits in Rydberg lasers and cavities. Pays into G1.
IP & standards. No standard for analogue-qubit figures was found as of 2026-09-26; the shared Hamiltonian convention is the de facto interface C[262]C[386].
Roadmaps & track record. Pasqal (2026-01-29): Vela in 2026, over 256 qubits with local detuning; measurable quantum advantage before mid-2026 R[390] — not scored here. QuEra's next product is gate-model C[137].
Strategic reading. Scale without per-qubit control, code or storage, bounded by a few-microsecond window. If analogue results survive classical challenge, it keeps a G1 niche as a mode of digital machines; if not, both vendors already sell the hyperfine alternative.
Outlook & open questions
Confirm if by 2027-12-31 a commercial analogue machine publishes T2 above 20 µs; demote if Vela ships without coherence figures or no peer-reviewed analogue-advantage result appears by 2027-06-30. Open questions. (1) Why is Aquila's echo time a third of the 2018 value? (2) How does T2 scale with register size? (3) Will erasure-detecting alkaline-earth g–r qubits reach a product? (4) Which Rydberg level and coherence do Fresnel and Orion run? (5) Does the readout asymmetry bias published phase diagrams?
References
- [137] QuEra Computing Inc., “Gemini-Class Gate-Model Quantum Computer.” [Online]. Available: https://www.quera.com/
gemini C - [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [143] P. Scholl, A. L. Shaw, R. B.-S. Tsai, R. Finkelstein, J. Choi, and M. Endres, “Erasure conversion in a high-fidelity Rydberg quantum simulator,” Nature, vol. 622, p. 273, 2023, doi: 10.1038/s41586-023-06516-4. arXiv:2305.03406. D
- [226] D. González-Cuadra et al., “Observation of string breaking on a (2 + 1)D Rydberg quantum simulator,” Nature, vol. 642, no. 8067, pp. 321–326, Jun. 2025, doi: 10.1038/s41586-025-09051-6. D
- [262] J. Wurtz et al., “Aquila: QuEra's 256-qubit neutral-atom quantum computer,” arXiv:2306.11727, Jun. 2023. C
- [384] H. Bernien et al., “Probing many-body dynamics on a 51-atom quantum simulator,” Nature, vol. 551, pp. 579–584, Nov. 2017, doi: 10.1038/nature24622. arXiv:1707.04344. D
- [385] L. Henriet et al., “Quantum computing with neutral atoms,” Quantum, vol. 4, Art. no. 327, Sep. 2020, doi: 10.22331/q-2020-09-21-327. arXiv:2006.12326. C
- [386] Pasqal (Pulser open-source project), “Conventions — Pulser 1.9.1 documentation,” Pulser documentation. [Online]. Available: https://pulser.readthedocs.io/
en/ Cstable/ conventions.html - [387] I. I. Beterov, I. I. Ryabtsev, D. B. Tretyakov, and V. M. Entin, “Quasiclassical calculations of blackbody-radiation-induced depopulation rates and effective lifetimes of Rydberg nS, nP, and nD alkali-metal atoms with n ≤ 80,” Phys. Rev. A, vol. 79, no. 5, Art. no. 052504, 2009, doi: 10.1103/PhysRevA.79.052504. arXiv:0810.0339. S
- [388] H. Levine et al., “High-fidelity control and entanglement of Rydberg-atom qubits,” Phys. Rev. Lett., vol. 121, no. 12, Art. no. 123603, Sep. 2018, doi: 10.1103/PhysRevLett.121.123603. arXiv:1806.04682. D
- [389] S. de Léséleuc, D. Barredo, V. Lienhard, A. Browaeys, and T. Lahaye, “Analysis of imperfections in the coherent optical excitation of single atoms to Rydberg states,” Phys. Rev. A, vol. 97, no. 5, Art. no. 053803, May 2018, doi: 10.1103/PhysRevA.97.053803. arXiv:1802.10424. D
- [390] L. Garbini, “Inside Pasqal's 2026 Vision on Quantum for Industry and Research,” Pasqal, Jan. 29, 2026. [Online]. Available: https://www.pasqal.com/
blog/ Rinside-pasqals-2026-vision-on-quantum-for-industry-and-research/ - [391] S. J. Evered et al., “High-fidelity parallel entangling gates on a neutral-atom quantum computer,” Nature, vol. 622, no. 7982, pp. 268–272, Oct. 2023, doi: 10.1038/s41586-023-06481-y. arXiv:2304.05420. D
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הטקסט בעברית נטען…
Fermion-parity encoding (tetron)
One logical qubit in the fermion parity of four Majorana zero modes on two wires; Z and X are parities of different mode pairs, both non-local.
Verdict. Not a working encoding as of 4 Sep 2026 — its X channel lives ~1000× shorter than its Z channel; falsified as fault-tolerance-relevant unless that ratio falls below 10× by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Four Majorana zero modes (MZMs) on two wires joined by a superconducting backbone hold one qubit: Z is the parity of one wire's mode pair, X of a pair spanning both, so neither logical operator is local. Karzig et al. defined the tetron and hexon layouts in 2017, with Cliffords by measurement rather than braiding S[421]. Only Z-type parity has been read with a stated fidelity; the X measurement the encoding requires has not D[21].
a fabricated (1.0) · b not a gate · c no readout · d no transport
e no control · f asymmetric, poisoning-dominated · g inherits the wire fab
Physics & limits
Protection is a length and a gap: parity splitting falls exponentially with length over coherence length, poisoning as the gap rises against temperature and quasiparticle density S[421]. Neither is published. Published instead: 12.4 ms on the Z loop against 14.5 µs on the X loop in one device D[20]. Both are fermion parities, so the ~1000× factor is geometric: the X loop encloses both wires and captures quasiparticles over a larger cross-section D[20]. A code needs comparable rates on both bases, and this is not usable bias: the short basis is the one a measurement-based gate projects most. Moving the floor means a larger gap (lead replaced aluminium D[21]), quasiparticle trapping and a smaller X loop.
Engineering state of the art
table
No logical state prepared, no X measurement, no coherence time or logical error rate for a tetron D[21].
The arXiv text of [20] also gives X ~4 µs and Z ~9.3 ms for other tunings, against the 14.5 µs / 12.4 ms quoted above. No non-Microsoft tetron exists. Not published: a Majorana splitting, a wire length over coherence length or a quasiparticle density for any tetron, so the protection claim cannot be checked numerically; and whether the X/Z asymmetry is geometric or intrinsic.
Manufacturing, materials & supply chain
No process of its own; the encoding fixes a geometry. Two wires, a backbone and the dots closing each loop cost more area and steps than a bare wire, and the X loop's coupling elements are exactly what a Z-only measurement avoids. Bring-up is per device: the 2026 rf technique resolves wire-end-state splitting to µeV so array devices can be tuned at all D[21]. Below it is in-house InAs–Pb epitaxy, unreplicated outside Microsoft; no export-control category specific to it.
Role in the stack
Architecture: topological — tetron (Majorana), where it is the primary encoding. It requires two wires per qubit and supplies the logical degree of freedom a measurement-based gate would act on; nothing else consumes it, and it sets no clock. Verification is one-sided: telegraph statistics on parity loops, no logical error per cycle, no Λ, no independent tetron. The dispute runs deeper: Legg's Matters Arising (2026-06-24) argues the regions read out in 2025 were disordered and gapless, making the encoded object trivial rather than protected; Microsoft's same-day reply concedes nothing D[22]. QuTech's parity qubit in coupled Kitaev chains is an alternative encoding with limited protection, not a tetron replication D[217].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Defined the tetron and holds the only Z/X data | D[20] |
| DARPA | investor | US | US2QC final Validation & Co-Design stage since 2025-02-06 | fact |
| QuTech | research | NL | Competing parity encoding in coupled Kitaev chains | D[217] |
| Nokia Bell Labs | research | US | Fractional-quantum-Hall anyon route, a different encoding | Dfact |
Money. 2025-02-06 · Microsoft · US2QC final Validation & Co-Design stage · undisclosed · DARPA · announced fact. 2026-01-23 · Microsoft · Quantum Pioneers Program, QEC an award topic · ≤ USD 200,000 per proposal · announced Pfact.
Market & supply chain. Nothing is sold; it consumes wires and readout and pays back only in G4, after an X measurement exists.
IP & standards. The tetron layout is Microsoft's published lineage S[421]; no dated patent count specific to it as of 4 Sep 2026.
Roadmaps & track record. (tetron as the fault-tolerance unit, promised 2017, restated for 2029 in 2026; status 4 Sep 2026: no X measurement, no logical qubit) C[215]. Nine years from design to a one-wire measurement, with no interim milestone for the X/Z ratio.
Strategic reading. Every topological claim above sits on this ratio. If it closes, Microsoft's fabrication lead becomes a code; if not, the tetron gives way to a longer Kitaev chain and the wire stack loses its justification. Risk is single-vendor and single-design.
Outlook & open questions
Falsifiable in 12–24 months: any X-basis parity measurement with a stated assignment error; an X/Z ratio below 100×; a joint measurement across two tetrons. Confirm on the first two; demote to theory if none appears by end-2027. Best case, loop redesign and a larger gap bring X into milliseconds; worst case, X-loop poisoning is intrinsic and the design is abandoned. Open: is the asymmetry geometric or intrinsic; does anyone build a tetron outside Microsoft.
References
- [20] M. Aghaee et al., “Distinct Lifetimes for X and Z Loop Measurements in a Majorana Tetron Device,” arXiv:2507.08795, Jul. 2025. D
- [21] M. Aghaee et al., “20 Second Parity Lifetime in an InAs–Pb Tetron Device,” arXiv:2606.03884, Jun. 2026. D
- [22] H. F. Legg, “On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E22–E26, Jun. 2026, doi: 10.1038/s41586-026-10567-8. arXiv:2503.08944. D
- [215] C. Nayak, “Majorana 2 – Microsoft's Scalable Quantum Processor With Reliable, Long-Lasting Qubits,” Microsoft Quantum. [Online]. Available: https://quantum.microsoft.com/
en-us/ Cinsights/ blogs/ majorana-2-scalable-quantum-processor - [217] F. Zatelli et al., “Majorana parity qubit in coupled minimal Kitaev chains,” arXiv:2607.09511, Jul. 2026. D
- [421] T. Karzig et al., “Scalable designs for quasiparticle-poisoning-protected topological quantum computation with Majorana zero modes,” Phys. Rev. B, vol. 95, no. 23, Art. no. 235305, Jun. 2017, doi: 10.1103/PhysRevB.95.235305. arXiv:1610.05289. S
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הטקסט בעברית נטען…
Time-bin / path photonic encoding
Photonic dual-rail qubit in arrival-time bins or waveguide path; loss is the dominant error, and it is heralded — an erasure at a known location — rather than a silent error.
Verdict. The two halves have diverged: path encoding won on chip (PsiQuantum Omega), time-bin survives in fibre, because an on-chip delay costs 0.27 dB per ns. No fusion logical qubit by 2028 leaves it a communication encoding.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
One photon, two orthogonal modes: two arrival-time bins, or two waveguides. Nothing continuous decoheres, so the dominant error is loss — and a lost photon fails to herald, detectable where it happens. Time-bin entanglement came from Brendel, Gisin, Tittel and Zbinden at Geneva in 1999, built for telecom fibre D[418]; path encoding is the on-chip descendant, and Omega says so plainly — "a path-encoded qubit using a heralded photon and two-mode interferometers" D[169]. Attributes: no mobility, no control modality, no fabrication of its own; pure-loss error.
Physics & limits
The floor is a loss budget, not an infidelity: every interferometer, coupler and switch removes amplitude, and the two halves of this node price it differently. A 1 ns time bin needs ~0.15 m of on-chip delay at group index 2, which at PsiQuantum's measured 1.8 ± 0.2 dB/m SiN loss D[169] costs ~0.27 dB — over half a ~0.5 dB per-photon budget, against ~0.04 mdB in fibre. That is why chips are path-encoded and fibres time-bin encoded — one node only in the abstract. The erasure advantage needs a trusted herald: Omega's median on-chip detector efficiency is 93.4% D[169], so about one heralded event in fifteen is an unflagged loss entering the code as ordinary error.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2025-02 | Fusion Bell fidelity 99.22 ± 0.12%, chip-to-chip 99.72 ± 0.04% | PsiQuantum | D[169] |
| 2025-02 | Single-mode SiN loss 1.8 ± 0.2 dB/m; on-chip SNSPD 93.4% | PsiQuantum | D[169] |
| 2026-06-26 | Unencoded 6-ring loss threshold 0.38–0.82% | Löbl et al. | S[264] |
No logical qubit exists in this encoding, and the threshold it must meet is disputed: 2.7% per photon for a boosted 6-ring and 17.4% for a {7,4}-encoded state S[179] against 0.38–0.82% unencoded S[264] — an order of magnitude apart, unreconciled fact.
The main report's "waveguide loss 0.5 dB/m" is not the Omega single-mode silicon-nitride figure, 1.8 ± 0.2 dB/m fact. Loss thresholds for 6-ring fusion differ by an order of magnitude between sources, unreconciled fact. No platform has demonstrated syndrome extraction with heralded loss. The 0.27 dB per nanosecond of on-chip delay is derived from published loss figures, not measured. Not published: whether Toshiba's 2025–26 deployments use time-bin encoding; its public pages do not say so [420].
Manufacturing, materials & supply chain
No fabrication step of its own: the encoding rides its host — PsiQuantum's 300 mm silicon nitride, Quandela's III-V quantum dots, QuiX's SiN meshes. Control is inherited: no per-qubit drive line, but every interferometer needs a phase shifter and every output a detector — thousands of cryogenic channels and their fan-out at 10³–10⁴ qubits. Chokepoints are the detector vendors (Single Quantum, ID Quantique, Photon Spot) and the III-V and SiN foundries Pfact; ECCN 4A906 applies fact.
Role in the stack
The encoding under the fusion-based discrete-variable architecture (PsiQuantum, Quandela, QuiX); it needs only a single-photon source, and its one rival there is the dual-rail encoding, primary on PsiQuantum's Omega and QuiX's Carina. Swapping path for time-bin trades interferometer phase stability for delay-line loss, unaffordable on chip. It also caps fusion: passive linear-optical Bell measurement on a dual-rail qubit succeeds at 50%, at least 75% with unentangled ancillae S[419]. Verification: no group has run a syndrome cycle using heralded loss as an erasure flag, so the advantage is a design argument, not a measurement.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | Path-encoded qubits on Omega | D[169] |
| Quandela | developer | FR | Photonic QPUs on quantum-dot sources | Cfact |
| QuiX Quantum | developer | NL | Carina core delivered to DLR, dual-rail encoded | C[340] |
| Sparrow Quantum | supplier | DK | Only merchant single-photon source vendor | P[342] |
Money.
2025-04-10 · Sparrow Quantum · Series A · EUR 21.5 M · lead undisclosed · closed P[342]
2025-09-10 · PsiQuantum · Series E · USD 1 B at USD 7 B · BlackRock, Temasek · closed Cfact
2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · USD 125 M · DARPA · announced Pfact
Market & supply chain. Sparrow is the only merchant source vendor, shipping 20–35% system efficiency against a 71.2% laboratory record P[342], so every fusion architecture pays a multiplexing tax set by one supplier's yield. Pays for G1/G2, is PsiQuantum's G3–G4 substrate, and pays separately for G6 through QKD.
IP & standards. ORCA holds US 12,437,225 on linear-optical encoded GHZ measurements (granted 2025-10-07), the only photonic dual-rail family a dated search surfaced G[407]; no computing-side standard exists.
Roadmaps & track record. PsiQuantum has published no hardware result since Omega, so 2026 progress is legible only through DARPA V&V Pfact. QuiX promised a universal machine for 2026 and delivered the core, not the machine C[340]. Quandela missed its 2025 first-logical-qubit milestone, still targeting 50 by 2028 R.
Strategic reading. Whoever cuts system-level loss wins the fusion race — likely whoever controls detector efficiency and source multiplexing, not whoever designs the encoding, which is free where its host is not. QKD monetises the same physics, so a fusion failure strands PsiQuantum and Quandela but not QKD.
Outlook & open questions
Confirm by 2027: a hardware syndrome cycle consuming heralded loss as an erasure flag; absent that it stays theory. Best case 2029: a small fusion-based logical qubit; worst case, commercially real only in QKD. Open: does anyone reconcile the 0.38% and 2.7% thresholds; can detector efficiency reach herald-trust levels at scale.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. S
- [264] M. C. Löbl, L. A. M. Pettersson, J. Dragašević, S. X. Chen, and O. A. D. Sandberg, “The subthreshold issue of fusion-based quantum computing,” arXiv:2606.28490, Jun. 2026. S
- [340] QuiX Quantum, “QuiX Quantum Secures €15 Million to Deliver First-Generation Universal Photonic Quantum Computer,” Jul. 10, 2025. [Online]. Available: https://www.quixquantum.com/
news/ Cquix-quantum-series-a - [342] M. Abdel-Kareem, “Sparrow Quantum Secures €21.5M ($24M USD) in Series A Funding to Advance Photonic Quantum Chip Production,” Quantum Computing Report, Apr. 10, 2025. [Online]. Available: https://quantumcomputingreport.com/
sparrow-quantum-secures-e21-5m-24m-usd-in-series-a-funding-to-advance-photonic-quantum-chip-production/ P - [407] ORCA Computing Limited, “Linear-optical encoded GHZ measurements and fault-tolerant quantum computation and communication,” Justia Patents, Oct. 7, 2025. [Online]. Available: https://patents.justia.com/
patent/ G12437225 - [418] J. Brendel, N. Gisin, W. Tittel, and H. Zbinden, “Pulsed Energy-Time Entangled Twin-Photon Source for Quantum Communication,” Phys. Rev. Lett., vol. 82, no. 12, pp. 2594–2597, Mar. 1999, doi: 10.1103/PhysRevLett.82.2594. arXiv:quant-ph/9809034. D
- [419] F. Ewert and P. van Loock, “3/4-Efficient Bell Measurement with Passive Linear Optics and Unentangled Ancillae,” Phys. Rev. Lett., vol. 113, no. 14, Art. no. 140403, Sep. 2014, doi: 10.1103/PhysRevLett.113.140403. arXiv:1403.4841. S
- [420] Toshiba Europe, “News Hub - The Latest Quantum Security News from Toshiba,” Toshiba Quantum Technology. [Online]. Available: https://www.toshiba.eu/
quantum/ Cnews/
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הטקסט בעברית נטען…
Rydberg-blockade CZ
Global laser pulses drive neighbouring tweezer-trapped atoms to a Rydberg state whose interaction blocks double excitation, giving a deterministic 270 ns CZ.
Verdict. Best natural-carrier entangler by speed; 99.854% raw as of April 2026, but the standard scheme sits within ~0.05% of its own ceiling and its residual error is atom loss.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two atoms ~2 µm apart in tweezers are driven on the qubit-to-Rydberg transition by one beam covering both. Because a doubly-excited pair repels through a van der Waals shift V=C6/R6 far larger than the drive, double excitation is pushed out of resonance and the pair acquires a phase set by how many atoms started in the coupled state — a controlled-phase gate. Jaksch, Cirac, Zoller, Rolston, Côté and Lukin proposed it in 2000 D[427]; blockade between two atoms was seen in 2009 (~58% fidelity) P[140], with the first gates and a CNOT in 2010. Levine et al. replaced the three-pulse addressed sequence with a two-pulse global time-optimal CZ in 2019 (97.4%) D[428] — the form every leading group still runs, and why the gate needs no per-qubit control line.
Attributes (technology graph). a — carrier affinity: fully natural; the gate adds no fabricated structure to the qubit. b — characteristic time: 10-6.6 s ≈ 250 ns, deterministic rather than heralded. c — readout: not set here; inherited from the atom and imaging nodes. d — mobility: connectivity by physically transporting atoms between gate zones, not fixed couplers. e — control @ placement: optical, generated entirely at room temperature. f — error structure as the code sees it: atom loss, leakage out of the qubit space, coherent over/under-rotation. g — manufacturing: optics, not lithography.
Physics & limits
Three scales set everything. The drive Ω (Harvard: peak 2π×17 MHz, two-photon 420 + 1015 nm at 7.8 GHz intermediate detuning, Rb 53S1/2) fixes the gate at 270 ns D[134]D[4]; the blockade shift must satisfy V≫ℏΩ, residual double excitation costing roughly (Ω/V)2. The Rydberg lifetime (tens of µs at n≈53, blackbody-limited) costs the Rydberg dwell time divided by it. Raising Ω cuts decay and raises leakage, so the optimum is shallow: a 2026 review adds spontaneous Rydberg emission (0.05–0.1%), laser phase noise (0.1–0.2%) and thermal motion (~0.1%) and concludes the standard blockade CZ has a "physical limit of 99.9%" absent new mechanisms such as Förster-resonance gates P[140].
The measured budget agrees in shape but not in villain. In the April 2026 Harvard result the largest single term is atom loss, 0.087(5)% per gate, about 60% of the total error, with leakage to other hyperfine levels 0.008(1)% per atom per gate; the authors assign the remainder to ground-Rydberg coherence (T2^), intermediate-state scattering and unwanted coupling to a nearby Rydberg level, and project 99.9–99.95% from better T2^, suppression of that coupling and more laser power D[134]. That makes the gate structurally interesting: its dominant failure is detectable — the atom is gone from the image — so it converts to an erasure, not an unlocated Pauli. Loss-post-selection lifts the same data from 99.854(4)% to 99.941(3)% D[134], and in the 448-atom architecture >80% of leakage events are atom loss, used as "supercheck" information in decoding D[4]fact.
What moves the floor: single-photon UV excitation, with no intermediate state to scatter from — the Yb and Sr route D[135]D[136]; spectrally clean lasers against servo-bump phase noise at Ω; ground-state cooling against Doppler and position spread; and new gate physics (Förster resonance, modulated off-resonant driving, circular Rydberg states) P[140]. None is demonstrated above 99.9% raw as of 3 Sep 2026.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2009 | ~58% two-atom entanglement via blockade | Wisconsin (Saffman/Walker) | P[140] |
| 2019 | 97.4% CZ, two-pulse global scheme | Harvard/MIT (Levine) | D[428] |
| 2023 | 99.5% CZ, parallel across an array | Harvard/MIT/QuEra (Evered) | D[391] |
| 2024-07 | 99.71(5)% CZ, Sr, leakage-corrected | Caltech (Endres) | D[136] |
| 2024-11 | 99.72(3)% post-selected / 99.40(3)% raw, ¹⁷¹Yb nuclear spin | Atom Computing | D[135] |
| 2026-04 | 99.854(4)% raw / 99.941(3)% loss-post-selected, stable 10 h | Harvard | D[134] |
| 2026 | 99.2% global two-qubit on a 260-physical-qubit product | QuEra Gemini | C[137] |
Best-versus-typical is the story: the record comes from ~8 sparsely spaced gate sites at 20–30 Hz D[134], the shipped figure is 99.2% global on 260 qubits C[137], the largest array under fault-tolerant control is 448 atoms D[4], and arrays of 6,100 and 11,000 atoms exist without gates at these fidelities D[138]D[145].
Manufacturing, materials & supply chain
There is no wafer; the manufacturing surface is the laser and beam-steering chain. Alkali two-photon excitation needs a fibre-amplified 1013–1015 nm source of tens of watts plus a frequency-doubled 420 nm beam; Yb/Sr need a single ~300–320 nm UV source; all need phase noise suppressed near the Rabi frequency, plus acousto-optic deflectors and spatial light modulators for placement. Yield and uniformity become intensity and phase homogeneity across the array; Harvard's 10-hour run drifted mainly through Rydberg laser power and pointing D[134]. The vendor pool for narrow-linewidth high-power lasers, UV sources, AODs and SLMs is small — TOPTICA, M Squared, Coherent, AA Opto-Electronic, Gooch & Housego, Hamamatsu, Meadowlark are the usual names — but no dated procurement disclosure ties a machine to a supplier (see Open verification items). Export control runs through the US BIS quantum controls of September 2024 (ECCN 3A901 and related) and Category 6 laser entries; which applies to a 10 W 1013 nm amplifier is unsettled in any public ruling found.
Control, readout & I/O burden
The gate is global: one beam pair entangles every blockaded pair at once, so per-qubit control lines scale as O(1), not O(N). The cost is optical power — holding 2π×17 MHz over N atoms scales power linearly in N — and beam steering: an acousto-optic deflector resolves as many spots as its rf bandwidth times the acoustic transit across the beam, a transit that also bounds how fast it re-points, while liquid-crystal modulators reframe at tens of hertz. At 103 nothing breaks; at 104 power and steering bind; at 106 multi-core optical interconnects are required and undemonstrated. The gate's own control latency is sub-µs, but it sits inside a round dominated by ~0.8 ms of transport between gate layers and ~0.5 ms imaging, giving measured QEC rounds of ~1–4.5 ms D[4]S[31]; the compensating theory is transversal gates with correlated decoding, keeping syndrome rounds constant per logical gate S[152].
Role in the stack
The gate serves both Rydberg tweezer-array architectures — alkali (Rb/Cs: Harvard/MIT, QuEra, Pasqal, Infleqtion, Google) and alkaline-earth(-like) (Yb/Sr: Atom Computing/Microsoft, Princeton, Caltech). It requires an atom in a tweezer plus the laser and deflector chain, and provides the entangling channel every atom-based code consumes; it has no in-platform replacement at comparable fidelity, so the switching price is the platform itself. A natural, unfabricated carrier gets a sub-microsecond deterministic entangler where trapped ions pay 10–100 µs — hence the platform's clock problem lives in imaging and transport, not the gate. Derived clock = sum of the syndrome round (gates 1×10⁻⁶ s, transport 8×10⁻⁴ s, 1Q 1×10⁻⁵ s, readout 5×10⁻⁴ s) ≈ 1.3 ms on both tweezer-array architectures, of which the gate is 0.08%. Neighbouring empty slots: sub-100 µs non-destructive array readout, and a blockade gate whose dominant error is not atom loss.
Evidence — how the numbers were measured
The 2026 record uses echo randomised benchmarking and symmetric stabiliser benchmarking on ~8 sparse gate sites D[134]; Atom Computing used Clifford and symmetric-subspace RB with >200 CZ gates per circuit D[135]; Caltech built a fidelity-response theory and quotes 0.9971(5) downward-corrected for leakage D[136]. What these miss: loss-post-selection removes 60% of the error, so 99.941% is not a circuit-level number and must not be set against a raw superconducting figure; sparse-site benchmarking misses dense-array crosstalk and next-nearest-neighbour blockade error; and none measures the gate inside a transport-and-image cycle, where re-trapping and heating act. Conflict: the August 2026 review tabulates a 2025 USTC CZ of 99.84% P[140] that no primary source corroborates, so this brief uses Harvard's 99.854(4)% D[134]. Note also three conventions behind three headline numbers — Atom Computing's 99.72/99.40 is post-selected/raw D[135], Caltech's is leakage-corrected D[136], Harvard's is raw plus post-selected D[134].
The 270 ns gate duration is the value in [4]; the April 2026 record paper gives a peak Rabi frequency of 2π×17 MHz but no extractable gate duration, so the two are treated as one scheme. Not published: the laser, AOD or SLM supplier of any specific neutral-atom machine in a dated procurement disclosure — the vendor names under Manufacturing are the field's usual pool; an export-control ruling on high-power 1013 nm Rydberg-laser subsystems (US BIS quantum ECCNs against Category 6 laser entries); and QuEra Gemini's availability date, deployment site and price.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Harvard/MIT (Lukin, Greiner, Vuletić) | research | US | Hold the CZ record and the 448-atom architecture | D[134]D[4] |
| QuEra | developer | US | Commercialises that line; Gemini ships 99.2% two-qubit | C[137]Cfact |
| Atom Computing | developer | US | ¹⁷¹Yb nuclear spin, single-photon excitation; builds Magne | D[135]Cfact |
| Microsoft | integrator | US | Logical layer on Atom hardware; co-sells Magne | Cfact |
| Pasqal | developer | FR | Rb arrays, analogue and digital; SPAC-listed Aug 2026 | Pfact |
| Infleqtion | developer | US | Cs arrays, logical qubits with loss correction | Cfact |
| Caltech (Endres) | research | US | Sr gates, erasure excision, benchmarking theory | D[136] |
| Princeton (Thompson) | research | US | Metastable Yb erasure conversion on this gate | D[142] |
| Google Quantum AI | developer | US | Neutral-atom track opened under Adam Kaufman | Cfact |
| DARPA | funder | US | QBI Stage B includes Atom Computing and QuEra | fact |
| US Dept of Commerce | funder | US | $100 M CHIPS LOIs to Atom Computing and Infleqtion | fact |
| QuNorth (EIFO + Novo Nordisk Fdn) | buyer | DK | Ordered Magne, 1,225 physical / 50 logical | Cfact |
Money.
- 2025-07-17 · QuNorth · order (Magne, from Atom Computing/Microsoft) · €80 M · EIFO + Novo Nordisk Foundation · ordered Cfact
- 2025-09-09 · QuEra · financing round · $230 M+ · Google, SoftBank Vision Fund 2, NVentures · closed Cfact
- 2025-11-06 · Atom Computing, QuEra · DARPA QBI Stage B · up to $15 M each · DARPA · selected fact
- 2026-02-17 · Infleqtion · IPO (NYSE: INFQ) · >$550 M gross · SPAC · closed Cfact
- 2026-03-24 · Google · neutral-atom hardware programme · amount undisclosed · internal · announced Cfact
- 2026-05-21 · Atom Computing, Infleqtion · CHIPS letters of intent · $100 M each, of $2.013 B to nine companies · US Dept of Commerce · LOI, non-binding fact
- 2026-06-16 · Atom Computing · Series C plus LOI · $100 M equity, >$300 M cumulative · Third Point · closed + LOI Cfact
- 2026-08-28 · Pasqal · SPAC completion (Nasdaq: PSQL) · ~$360 M cash; 2025 revenue €16.5 M · closed Pfact
Market & supply chain. What is sold is systems, not gates: Magne prices 1,225 physical / 50 logical qubits at €80 M, roughly €65 k per physical qubit Cfact; Gemini packages 260 physical qubits at 1 shot/second C[137]. The enabling-equipment pool — high-power 1013 nm amplifiers, UV sources, AODs, SLMs — is narrow enough that one vendor's lead time can gate a machine build, though it is shared with atomic clocks and cold-atom sensing. G1 (analogue simulation) and G5 (optimisation) pay for atom arrays today; the gate fidelity discussed here is bought almost entirely for G3 (early fault tolerance) and, through Magne and Libra, G4. G6 (networking) has no demonstrated atom-to-atom photonic link at this scale.
IP & standards. No dated patent-family count from a named database was found for Rydberg-gate IP, so none is asserted. Open stacks: QuEra's Bloqade, Pasqal's Pulser, Infleqtion's Superstaq, with AWS Braket the named delivery channel for QuEra's 2028 system Cfact; no gate-level standard or consortium specific to Rydberg CZ exists as of 3 Sep 2026.
Roadmaps & track record. QuEra (promised 2024-01 · 100 logical qubits in 2026 · not delivered; superseded 2026-06 by Libra, >256 logical in 2028 — a two-year slip) Cfact. Atom Computing/Microsoft (promised 2025-07 · Magne, 50 logical, turn of 2026/27 · being installed as of 3 Sep 2026) Cfact. Pasqal (promised 2024-03 · 10,000 physical in 2026 · slipped to 2028; 100 logical 2029) Cfact. Infleqtion (promised 2025 · 30 logical in 2026 · unverified as of 3 Sep 2026) C[150]. Judgment: Harvard/MIT's device claims have survived replication and are the most credible; Atom Computing has a customer, a price and a delivery date, the strongest commercial commitment here; QuEra and Pasqal have each slipped a headline number by two years, so their 2028–29 dates read as intentions.
Strategic reading. If raw fidelity crosses 99.9% while loss stays erasure-convertible, neutral atoms reach fault tolerance without a wiring problem: platform vendors and laser suppliers win, and the superconducting camp's argument that only cryogenic integration scales loses. If it stalls at 99.85%, the millisecond cycle leaves atoms as the analogue-simulation and optimisation platform while ions and superconductors take fault tolerance. There is no substitution threat within the platform — every neutral-atom company runs this gate — making the ceiling a sector risk, not a company risk, and giving these laser suppliers more bargaining power than their revenue suggests.
Outlook & open questions
Confirm/demote milestones for 12–24 months: (1) a raw CZ ≥99.9% in a dense array by 2027-09 confirms the review's ceiling was engineering, not physics; failure demotes the gate to saturated; (2) Magne accepted at QuNorth with 50 logical qubits by mid-2027; (3) a >50-round below-threshold memory run with continuous reloading showing Λ>2 — the Atom/Microsoft 90-round toric-code run lost its suppression once reloading was included D[148]; (4) a CZ fidelity measured inside a transport-and-image QEC cycle. Best case by 2029: 99.95% raw, loss converted to erasures, Libra-class 256-logical machines on a cloud channel. Worst case: 99.85% raw persists, the millisecond cycle stays, atoms hold G1/G5 and cede G3/G4.
Open questions. Does the loss channel scale with array density and transport, or is 0.087% per gate a floor set by trap depth? Can single-photon UV excitation recover the phase-noise and scattering terms without new UV-induced loss? Is Förster-resonance or modulated-driving physics real above 99.9%? Does erasure conversion survive at circuit level, where a decoder must locate losses inside a 1 ms budget? Watch for a raw record without post-selection, and whether Google's atom track publishes a gate before 2027.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [31] H. Zhou et al., “Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays,” Proc. 52nd Annu. Int. Symp. Comput. Archit. (ISCA), 2025, doi: 10.1145/3695053.3731039. arXiv:2505.15907. S
- [134] S. J. Evered et al., “High-fidelity entangling gates and nonlocal circuits with neutral atoms,” arXiv:2604.25987, Apr. 2026. D
- [135] J. A. Muniz et al., “High-fidelity universal gates in the ¹⁷¹Yb ground state nuclear spin qubit,” arXiv:2411.11708, Nov. 2024. D
- [136] R. B.-S. Tsai, X. Sun, A. L. Shaw, R. Finkelstein, and M. Endres, “Benchmarking and linear response modeling of high-fidelity Rydberg gates,” arXiv:2407.20184, Jul. 2024. D
- [137] QuEra Computing Inc., “Gemini-Class Gate-Model Quantum Computer.” [Online]. Available: https://www.quera.com/
gemini C - [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [140] J. Wang, Z. Wang, L. Li, F. Wang, S. Liang, and K. Yan, “Neutral Atom Quantum Computing: Principles, Routes, Progress, and Challenges,” arXiv:2608.05010, Aug. 2026. P
- [142] B. Zhang et al., “Logical qubits with erasure conversion using metastable neutral atoms,” Nat. Phys., vol. 22, no. 6, pp. 910–916, Jun. 2026, doi: 10.1038/s41567-026-03309-0. arXiv:2506.13724. D
- [145] Y. Wang et al., “Trapping 11,000 Atoms in a Tweezer Array Generated by a Single Metasurface,” arXiv:2606.02715, Jun. 2026. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [150] L. Roady, “Infleqtion Unveils New Architecture to Accelerate Its Quantum Computing Roadmap To Achieve 1000 Logical Qubits by 2030,” Infleqtion, Sep. 17, 2025. [Online]. Available: https://infleqtion.com/
infleqtion-unveils-new-architecture-to-accelerate-its-quantum-computing-roadmap-to-achieve-1000-logical-qubits-by-2030/ C - [152] H. Zhou et al., “Low-Overhead Transversal Fault Tolerance for Universal Quantum Computation,” Nature, vol. 646, no. 8084, pp. 303–308, 2025, doi: 10.1038/s41586-025-09543-5. arXiv:2406.17653. S
- [391] S. J. Evered et al., “High-fidelity parallel entangling gates on a neutral-atom quantum computer,” Nature, vol. 622, no. 7982, pp. 268–272, Oct. 2023, doi: 10.1038/s41586-023-06481-y. arXiv:2304.05420. D
- [427] D. Jaksch et al., “Fast Quantum Gates for Neutral Atoms,” Phys. Rev. Lett., vol. 85, no. 10, pp. 2208–2211, Sep. 2000, doi: 10.1103/PhysRevLett.85.2208. arXiv:quant-ph/0004038. D
- [428] H. Levine et al., “Parallel Implementation of High-Fidelity Multiqubit Gates with Neutral Atoms,” Phys. Rev. Lett., vol. 123, no. 17, Art. no. 170503, Oct. 2019, doi: 10.1103/PhysRevLett.123.170503. arXiv:1908.06101. D
Русский текст загружается…
הטקסט בעברית נטען…
Electronic microwave gate (ions, laser-free: near-field or static gradient)
Currents in a microfabricated trap chip entangle ions through microwave field gradients, with no laser and no ground-state cooling.
Verdict. Holds the highest two-qubit fidelity measured on any modality (8.4×10⁻⁵ error) but only on chips of ≤10 qubits; demote if no ≥50-qubit device publishes gate time, heating and crosstalk by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An entangling gate on hyperfine ion qubits driven entirely by currents in the trap chip. Oscillating currents in electrodes tens of micrometres from the ion produce a microwave field whose gradient, not its amplitude, couples spin to the shared motional mode; a state-dependent force closes a loop in phase space and imprints a geometric phase, as a Mølmer–Sørensen gate does, with a ~10 GHz field replacing two laser beams. Demonstrated at NIST Boulder in 2011 (76(3)%, 20 ns single-qubit pulses) D[444], brought to useful fidelity at Oxford in 2016 with dynamically decoupled ⁴³Ca⁺ clock qubits D[445], industrialised by Oxford Ionics — the Ballance/Harty spin-out of that group, part of IonQ since 2025 — as Electronic Qubit Control C[446]. A parallel lineage at Sussex (Hensinger), its spin-out Universal Quantum, and eleQtron's MAGIC drives global microwave fields across a static gradient P[328], [447]; the near-field variant here holds the records.
Attributes (technology graph):
- Carrier affinity: fully natural — the qubit is an atomic ion; only the trap is fabricated.
- Characteristic time: 2×10⁻⁴ s per entangling operation, deterministic, not heralded.
- Readout: not defined by this node; it inherits the host ion's fluorescence detection.
- Mobility: shared motional bus within a zone, ions transported between zones.
- Control modality and placement: microwave, sources at room temperature.
- Error structure as the code sees it: Pauli plus a coherent component.
- Manufacturing: microfabricated surface trap with buried current traces.
Physics & limits
Gate rate is set by the microwave gradient at the ion and the Lamb–Dicke parameter; both are geometric. Halving the ion–electrode distance roughly doubles the gradient but raises anomalous heating steeply (surface noise near d⁻⁴), so speed is bought against motional decoherence — hence durations of 120–226 µs, not sub-microsecond. There is no photon-scattering floor, the dominant fundamental error of laser gates, which is why the achievable ceiling is higher D[102].
What replaces it is a.c. Zeeman shift from the field's non-gradient component, magnetic-field noise, and residual spin–motion entanglement at finite temperature. The first two are attacked with clock qubits and dynamical decoupling D[445]; the third bound everything until the 2025 "smooth gate", which ramps the gate detuning to adiabatically eliminate spin–motion entanglement and tolerate a hot mode — it ran at mean phonon number n̄ = 9.4(3), above the Doppler limit, with error ≲5×10⁻⁴ even hotter D[102]. The residual error is largely coherent — miscalibrated phase and gradient amplitude — which a code sees as correlated rather than depolarising noise, so logical extrapolations assuming Pauli noise run optimistic. Moving the floor further needs lower trap-surface noise and better microwave amplitude and phase stability, not new physics.
Engineering state of the art
Best demonstrated: two-qubit error 8.4(7)×10⁻⁵ (2025-10) on a laboratory chip D[102]. Typical at scale: no gate figure above ten qubits is published — the 2024 device giving 99.97(1)% two-qubit and 99.99916(7)% single-qubit fidelity is a seven-zone chip controlling up to ten qubits D[257], and eleQtron's 30-ion JION, deployed 2026-09-03, launched without a gate fidelity. That gap is the most important fact about this node.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2011 | First near-field microwave two-qubit gate, 76(3)% | NIST Boulder (Ospelkaus, Leibfried, Wineland) | D[444] |
| 2016 | 99.7(1)% two-qubit, ⁴³Ca⁺ clock qubits, dynamically decoupled | Oxford (Harty, Lucas) | D[445] |
| 2024-07 | 99.97(1)% two-qubit, 99.99916(7)% single-qubit, seven-zone chip, ≤10 qubits | Oxford Ionics | D[257] |
| 2024-12 | Single-qubit error 1.5(4)×10⁻⁷ per Clifford, chip-integrated microwave resonator | Oxford (Lucas group) | D[103] |
| 2025-10 | Two-qubit error 8.4(7)×10⁻⁵ at n̄ = 9.4(3), no ground-state cooling | Oxford Ionics / IonQ | D[102] |
Dominant terms today: temperature-dependent residual spin–motion entanglement and coherent control error. The headline is an estimate from subspace-leakage randomised benchmarking, not tomography D[102]. Gate duration is 225.8 µs in 2025 and ≈120 µs (two 60 µs pulses) in 2024 D[102], [257].
Manufacturing, materials & supply chain
The trap is a surface-electrode chip with buried current-carrying traces and local tuning electrodes in a standard semiconductor process; IonQ's framing is that control lives on "classical semiconductor chips" built in "existing semiconductor fabs" C[446]. That claim is now vertically integrated: IonQ closed the SkyWater Technology acquisition (~$1.8 B, announced 2026-01-26, closed 2026-07-31) Cfact[19], giving it a US 200 mm trusted foundry instead of a merchant relationship. Packaging is the named weak point: Oxford Ionics uses Bay Photonics for the electrical, photonic and electrostatically shielded packaging of high-density trap devices C[448]. No yield, uniformity, defect-density or per-qubit cost figure is published by any actor as of 3 Sep 2026. Export exposure runs through the US BIS interim final rule of 2024-09-06, which created ECCN 4A906 for quantum computers (34-qubit floor with error-rate tiers) plus 3A904/3B904 for enabling equipment fact[301]: a ≥34-qubit electronic-gate system meeting the error tiers falls inside it, and the UK-design/US-parent structure makes licensing a design constraint.
Control, readout & I/O burden
A laser-gate machine of comparable ambition needs many wavelengths and per-zone optical addressing — Helios uses at least seven laser wavelengths and 1,228 electrodes D[97]. The electronic gate deletes the gate lasers, leaving light only for cooling, state preparation and readout, and substitutes room-temperature microwave sources plus d.c. electrode drivers. Per-qubit I/O becomes a mixed-signal ASIC problem — coherent microwave channels and many d.c. lines — a familiar scaling exercise rather than an optical one.
The wall moves rather than disappears. At 10³ qubits it is the count of independent microwave channels and their phase coherence, since amplitude and phase errors are the leading coherent term. At 10⁴ it is routing current-carrying traces, with on-chip dissipation and zone-to-zone crosstalk; no actor has published a crosstalk or heating figure for a 2D array. At 10⁶ nothing in the public record connects this gate to a demonstrated 2D trap. Control-loop latency demands are modest — millisecond-class syndrome cycles suffice.
Role in the stack
The node sits on the architecture "Trapped ions — electronic qubit control (laser-free, microwave-driven gates)" (IonQ/Oxford Ionics, eleQtron, QUDORA) as its primary gate, and is the alternate gate on "Trapped ions — QCCD (transport between zones)" (Universal Quantum). It requires a trapped atomic ion as carrier and chip-integrated microwave control as signal source; it provides nothing downstream that the laser gate does not, and directly replaces the laser Mølmer–Sørensen gate. The switching price is one-directional: buried traces and electrode geometry are co-designed with the gate, so an electronic-gate machine cannot fall back to lasers, while a laser machine can in principle add microwave electrodes. Here a natural, unfabricated carrier is steered by purely electronic control — a semiconductor supply chain driving an atomic qubit. Contribution to the derived clock: 2.3×10⁻⁴ s per entangling gate. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture ≈1.5×10⁻³ s, gate layers 1.4 ms of it; on a multi-zone machine transport dominates instead (Helios ~55 ms per full-width layer D[97]), so the gate's speed advantage is invisible at product scale. The neighbouring empty slot is the cryogenic version: nothing published combines electronic gates with a cryogenic trap, which is where the heating-versus-gradient trade would be won.
Evidence — how the numbers were measured
The headline 8.4(7)×10⁻⁵ comes from subspace-leakage randomised benchmarking at Doppler temperature, not from tomography or interleaved RB against an independent reference D[102]. Two-qubit RB twirls coherent errors into an effective depolarising rate, understating the coherent residual, and says nothing about crosstalk to spectator ions — the term that will decide performance at scale. No independent group has replicated the electronic gate above 99.9%: the 2016 Oxford D[445] and 2011 NIST D[444] results are the only non-Oxford-Ionics near-field microwave gates on record, and neither eleQtron nor Universal Quantum has published a comparable fidelity as of 3 Sep 2026. The company line "99.99% two-qubit gate fidelity" C[446] rounds the preprint's 1 − 8.4(7)×10⁻⁵ — consistent, but with no error bar and no width.
The 225.8 µs gate duration of the 2025 record is not stated in the abstract of arXiv:2510.17286. Not published: a patent family or patent count for Oxford Ionics / IonQ Electronic Qubit Control; any delivery or milestone under Universal Quantum's €67 M DLR contract (four-year term from 2022-11) as of 2026-09-03; eleQtron's ion species, qubit count, fidelity and gate time, MAGIC being described only qualitatively; the value of the Innovate UK / DSIT Quantum Missions Pilot award to Oxford Ionics; and any crosstalk, heating-rate or on-chip dissipation figure for an electronic-gate trap chip.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IonQ | developer | US | Owns Oxford Ionics and its Electronic Qubit Control line; holds the gate record | D[102] C[446] |
| Oxford Ionics | developer | UK | Designs the trap chips and ran both record experiments | D[102], [257] |
| eleQtron | developer | DE | MAGIC static-gradient microwave ion control; €57 M Series A, >€54 M backlog | Pfact[129], [447] |
| Universal Quantum | developer | UK | Sussex spin-out; modular microwave machines under a German state contract | P[328] |
| University of Oxford | research | UK | Lucas group: single-qubit 1.5(4)×10⁻⁷ with a chip-integrated microwave resonator | D[103] |
| NIST Boulder | research | US | Originated the near-field microwave gate in 2011 | D[444] |
| NQCC | user | UK | Hosts the Oxford Ionics "Quartet" system; 2D trap upgrade | C[448] |
| Innovate UK | funder | UK | Quantum Missions Pilot award for the 2D trap upgrade, value undisclosed | C[448] |
| SkyWater Technology | supplier | US | 200 mm US foundry, acquired by IonQ to fabricate trap chips in-house | Cfact[19] |
| Bay Photonics | supplier | UK | Packaging of high-density trap devices | C[448] |
| DARPA | evaluator | US | QBI: Oxford Ionics in Stage A, IonQ carried into Stage B | fact[243] fact[65] |
Money.
- 2022-11-02 · Universal Quantum · contract · €67 M · German Aerospace Center (DLR); two machines in four years, multi-chip system up to 100 qubits · — · announced P[328]
- 2025-03-11 · Oxford Ionics · programme award (Quantum Missions Pilot, "Q-Surge") · undisclosed · DSIT and Innovate UK · — · announced C[448]
- 2025-04-03 · Oxford Ionics · DARPA QBI Stage A selection · — · DARPA · — · selected fact[243]
- 2025-09-17 · IonQ · M&A, Oxford Ionics (announced 2025-06-09) · $1.075 B · — · — · closed Cfact[18]
- 2025-10-12 · IonQ · equity · $2.0 B at $93/share, after $1.0 B on 2025-07-08 · — · cash $3.0 B · closed Cfact[326]
- 2025-11-06 · IonQ · DARPA QBI Stage B selection, up to $15 M each · — · DARPA · — · selected fact[65]
- 2026-04-27 · Quantum Art · Series A extension · $140 M, from $100 M on 2025-12-10 · — · — · closed Pfact[125]
- 2026-05-05 · eleQtron · Series A · €57 M · Schwarz Digits lead, with EIC Fund, Earlybird, Ankaa Ventures, Precitec, NRW.BANK · backlog >€54 M · closed Pfact[129], [447]
- 2026-07-31 · IonQ · M&A, SkyWater (announced 2026-01-26) · ~$1.8 B · — · — · closed Cfact[19]
- 2026-Q2 · IonQ · revenue · $80.1 M, +287% YoY; FY guidance $280–290 M · — · cash $3.0 B · reported Cfact[326]
Market & supply chain. There is no merchant market for electronic ion gates. The enabling assets are trap-chip fabrication (in-house at IonQ via SkyWater), microwave sources and amplifiers (commodity RF, low concentration risk) and specialist packaging — Bay Photonics is a genuine single point of failure for the UK line. Concentration risk is corporate rather than industrial: one company holds the record, the patents and the fab. Unit economics are unquotable; nobody publishes cost or power per qubit. The goals that pay for it are G3 (early fault tolerance) and G7 (deployable systems): the case for deleting gate lasers is manufacturability and field-deployability, not speed. G6 is untouched — the node provides no photonic interface.
IP & standards. Oxford Ionics describes Electronic Qubit Control as patented C[446], and the $1.075 B acquisition price is best read as a purchase of that portfolio plus the team; no patent family number, database-sourced count or litigation could be verified as of 3 Sep 2026 (Google Patents assignee search is robots-blocked). No standards body or consortium is specific to this gate.
Roadmaps & track record. (promised on · promised for · status as of 2026-09-03): IonQ, 2025-06-13 · 256 qubits at 99.99% in 2026 · slipped to commissioning in H1 2027 Rfact[132]. IonQ, 2025-06-13 · 10,000 physical qubits on one chip in 2027 and 2 M physical / 40–80 k logical by 2030 · no 2D-trap heating, gate-time or interconnect data published Rfact[132]. Universal Quantum, 2022-11-02 · two machines including up to 100 qubits within four years · no delivery announced as the term elapses P[328]. Credibility: Oxford Ionics' physics claims have held and improved on schedule; IonQ's scale promises have not — the 2020 roadmap's 4,000 qubits by 2026 missed by roughly 40× — so read fidelity commitments as credible and qubit-count dates as aspirational.
Strategic reading. If the electronic gate scales, IonQ converts a physics lead into a manufacturing lead and the optical supply chain for ions loses its strongest customer class; Quantinuum's advantage narrows to systems engineering and error correction rather than gate quality. If it stalls at a few tens of ions, the record becomes a laboratory curiosity and laser gates with integrated photonics win on demonstrated width. Bargaining power sits with the platform vendor: nothing in the chain is scarce except packaging know-how, and IonQ has internalised the fab.
Outlook & open questions
Confirm-or-demote milestones for 12–24 months: a device above ~30 electronic-gate qubits with published two-qubit fidelity, gate time and crosstalk (absent by end-2027, demote); IonQ's 256-qubit system commissioned in H1 2027 near 99.99%; any independent replication above 99.9%; a 2D trap running electronic gates with published heating rates. Best case by 2029: chip-trap machines of a few thousand ions, laser hardware reduced to cooling and readout, gate error near 10⁻⁴, error correction limited by transport rather than gates. Worst case: fidelity degrades by an order of magnitude once hundreds of microwave channels share a die, and the platform reverts to laser gates for addressing.
Open questions: does the microwave gradient survive dense 2D routing without unacceptable crosstalk and dissipation? How much of the residual 8.4×10⁻⁵ is coherent, and what does that do to Λ? Does SkyWater's process yield trap chips at volume, or was the acquisition supply security rather than capability?
References
- [18] IonQ, “IonQ Completes Acquisition of Oxford Ionics, Rapidly Accelerating Its Quantum Computing Roadmap,” Sep. 17, 2025. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-oxford-ionics-rapidly-accelerating-its-quantum - [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
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הטקסט בעברית נטען…
Tunable-coupler CZ / iSWAP
A flux-tuned coupler switches the exchange and ZZ interaction between transmons on and off, giving deterministic 25–70 ns CZ or iSWAP gates.
Verdict. Falsifiable — isolated pairs are already at the coherence limit, so if fleet-width error does not fall below 0.2% by 2027 the binding constraint is T1 and calibration, not the coupler.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A flux-tunable coupler is a third element — usually a tunable transmon — bridging two data qubits. Its frequency sets an indirect coupling path that interferes with the direct capacitive one, so a bias sweep tunes net exchange through zero: at the off point static ZZ cancels; a pulse away from it drives a deterministic CZ or iSWAP via the |11⟩–|20⟩ crossing. Google/UCSB introduced it as the gmon in 2014, coupling settable to zero at nanosecond resolution without spoiling coherence D[422].
Attributes: carrier affinity a = 1.0, fully fabricated, no natural analogue. Gate time ≈40 ns (10^−7.4 s), deterministic.
Physics & limits
The coupler buys speed and isolation at the cost of a third noisy degree of freedom. Tens of MHz on-coupling sets 25–70 ns gates. Three mechanisms set the floor. Coherence: at 40 ns against Willow's mean T1 of 68 µs, relaxation and dephasing during the pulse already cost a few 10⁻⁴, most of the gap between the 99.88% device mean and unity D[1] — pulse shaping cannot recover it, only longer T1 or shorter gates. Leakage: the pulse passes near |20⟩ and the coupler's second level, so population leaves the computational space — an unheralded, sticky error to the code. And 1/f flux noise on the bias moves the off point between calibrations, leaving a drifting residual ZZ that appears as coherent, correlated error. What moves the floor: higher T1, larger anharmonicity (fluxonium couplers), shaped flux pulses, and couplers biased at a flux-insensitive point.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-11 | Double-transmon coupler CZ 99.90% in 48 ns | Toshiba | D[37] |
| 2024-12 | Willow, 105 q: mean 2Q 99.88%, mean T1 68 µs, 1.1 µs cycle | D[1] | |
| 2025-08 | CZ 99.93% over 40 h, 1Q 99.98%, readout >99.94% on one device | IQM | D[38] |
| 2026-07 | Fleet EPLG, full width: best 0.19%, typical 0.37% | IBM | C[34] |
Three regimes, not one number: a characterised pair reaches 99.93% D[38]; a 105-qubit device averages 99.88% D[1]; IBM's full-width fleet benchmark reads 0.37% typical, 0.19% best C[34]. Zuchongzhi 3.0 sits at 99.62% over 105 qubits D[35]. The two-qubit gate is still ~40% of Google's colour-code error budget, leakage next D[41].
Manufacturing, materials & supply chain
There is no separate coupler process: the coupler is another junction and SQUID loop in the same superconducting lithography, so its defects are the platform's own — junction-frequency spread and two-level-system defects pulling the off point. The manufacturing cost is I/O, not lithography: Nighthawk carries 218 couplers across 120 qubits, each demanding a bias line C[49]. QuantWare is the only merchant seller of tunable-coupler chips, funded by a $178 M Series B and building a Delft fab P[298]. Export control names whole computers (4A906) and cryogenic electronics (3A901), not gate mechanisms G[301]. No coupler yield or cost is published.
Control, readout & I/O burden
On a square lattice couplers outnumber qubits about two to one, each needing a fast flux line with its own DAC and filtering. At 10³ qubits that is thousands of flux lines; at 10⁴ it binds before fidelity does, and the only demonstrated escape is an on-chip bias source, as in D-Wave's flip-chip flux DAC on a fluxonium at 10 mK C[316]. The recurring cost is calibration, not latency: off points drift with 1/f flux noise, so calibration scales with coupler count — hence Google steering it by reinforcement learning during error correction, at 7.72×10⁻⁴ logical error per cycle at d=7 D[2].
Role in the stack
It belongs to the transmon lattice with tunable couplers (Google, IBM, Rigetti, IQM, OQC, USTC, Fujitsu) and requires the transmon carrier. It replaces fixed-frequency cross-resonance; the switching price is redesigning every qubit-coupler-qubit cell, roughly double the bias lines and a new calibration stack — the trade IBM accepted at Heron (2023-12) after a decade on cross-resonance and kept in Nighthawk C[49]. Its clock contribution is small: derived clock = sum of the syndrome round: gate layers + transport + readout + reset is 0.65 µs, its gate-layer term ~0.16 µs at 0.048 µs per layer D[1], so this node moves the error budget more than the clock. No neighbouring empty slot in the technology graph.
Evidence — how the numbers were measured
The 99.90% and 99.93% headlines are interleaved randomised benchmarking on one characterised pair, and RB is blind to leakage unless a leakage protocol runs alongside — leakage being this gate's second error term. EPLG is a different observable, full-width layered gates including crosstalk, so the 0.37% versus 0.07% gap is definitional as much as fleet variability. Neither record has been replicated by an independent laboratory. One attribution conflict: the cited "25 ns at 99.8%" Oxford result is a fixed-coupling coaxmon pair with no coupler at all C[423].
Not published: the gate duration of IQM's 99.93% CZ, of which only the fidelity and the 40-hour averaging window are stated; a coupler-specific yield or defect rate from any vendor; and the share of IBM's fleet EPLG due to residual coupler-off ZZ rather than coherence or crosstalk.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Google | developer | US | Originated the gmon; Willow uses tunable couplers | D[422] |
| IBM | developer | US | Nighthawk: 218 couplers on 120 qubits; coupler patent | C[49] |
| IQM | developer | Finland | Record CZ 99.93% with a floating tunable coupler | D[38] |
| QuantWare | supplier | Netherlands | Sells tunable-coupler transmon chips; Delft fab | P[298] |
| Rigetti | developer | US | Tunable-coupler chiplets, median 2Q 99.1% | Cfact |
Money.
- 2026-06-02 · IBM · programme (5-year quantum commitment) · >$10 B · — · announced fact
- 2026-05-05 · QuantWare · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners · closed P[298]fact
- 2026-07-02 · IQM · listing (Nasdaq/Helsinki) · cash €337 M, H1-2026 revenue €8.9 M · closed fact
- 2025-11-06 · DARPA · QBI Stage B, IBM the only transmon vendor of eleven · ≤$15 M each · announced fact
Market & supply chain. What this gate consumes is flux control — multi-channel AWGs (arbitrary waveform generators) and DACs from Zurich Instruments, Quantum Machines and Keysight, none coupler-specific — so concentration risk sits in chips, not instruments. QuantWare is the only merchant route; everyone else fabricates in-house, making coupler design proprietary and control electronics commodity. G2 and G3 pay for this node: both need 10⁻³ two-qubit error at fleet width.
IP & standards. IBM holds US 11,727,297 B2, "Tunable quantum coupler facilitating a quantum gate between qubits" (granted 2023-08-15), claiming an opposite-sign second coupling path that cancels unwanted coherent rotation G[424]; Google's 2014 gmon work is published prior art D[422]. No litigation identified, no standards body for coupler design or reporting.
Roadmaps & track record. IBM: Nighthawk 5,000 two-qubit gates per circuit (promised 2025-06-10 · for 2025 · delivered 2025-12) → 7,500 in 2026 → 10,000 in 2027 Rfact, on schedule, though the coupler switch is one generation old. IQM: 2Q above 99.94% (promised for 2025–26) is within error of the 99.93% delivered D[38]. Rigetti: 108 qubits at 99.5% slipped to "later 2026", the gap sitting in the coupler-mediated gate Cfact.
Strategic reading. IBM's move off cross-resonance settles the architecture argument for tunable coupling, strengthening control-electronics vendors — every coupler is another channel sold — and merchant chip suppliers. The substitution threat is not cross-resonance but passive ZZ cancellation by design: a fixed-coupling coaxmon pair reached 25 ns at 99.8% with no coupler and no flux line C[423]; if that scales, the line tax becomes a liability. Bargaining power stays with whoever owns the fab.
Outlook & open questions
Confirm or demote within 12–24 months: does Nighthawk reach 7,500 two-qubit gates by end-2026; does any fleet report typical EPLG below 0.2%; does a second laboratory reproduce 99.93%. Best case by 2029: fleet-width error near 10⁻³ at 10³ qubits, on-chip biasing removing the line tax. Worst case: coupler count caps chips near 10³ qubits and the 40 ns coherence limit holds error at a few 10⁻⁴, too high for Λ to grow. Open questions: does IBM's patent constrain merchant coupler chips; can fluxonium couplers cut leakage; will fixed coupling remove the line tax at scale.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [34] IBM Quantum, “What's new at IBM Quantum - Q2 2026.” [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ whats-new-q2-2026 - [35] D. Gao et al., “Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor,” Phys. Rev. Lett., vol. 134, Art. no. 090601, Mar. 2025, doi: 10.1103/PhysRevLett.134.090601. arXiv:2412.11924. D
- [37] R. Li, K. Kubo, Y. Ho, Z. Yan, Y. Nakamura, and H. Goto, “Realization of High-Fidelity CZ Gate Based on a Double-Transmon Coupler,” Phys. Rev. X, vol. 14, no. 4, Art. no. 041050, Nov. 2024, doi: 10.1103/PhysRevX.14.041050. arXiv:2402.18926. D
- [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
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2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance C - [298] M. Ivezic, “QuantWare Raises $178M Series B — What It Means for Quantum Open Architecture,” PostQuantum.com, May 6, 2026. [Online]. Available: https://postquantum.com/
industry-news/ Pquantware-178m-series-b-qoa/ - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
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media/ C41upubz2/ 14-1090a-a_fluxonium-dac-control.pdf - [422] Y. Chen et al., “Qubit architecture with high coherence and fast tunable coupling,” Phys. Rev. Lett., vol. 113, no. 22, Art. no. 220502, Nov. 2014, doi: 10.1103/PhysRevLett.113.220502. arXiv:1402.7367. D
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patent/ GUS11727297/ en
General facts cited above: fact, fact, fact, fact, fact, fact, fact.
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הטקסט בעברית נטען…
Exchange gate (spins; incl. shuttled-spin CZ)
Voltage-pulsed Heisenberg exchange between neighbouring or shuttled spins in gate-defined dots or donors — the only entangling mechanism that needs nothing but CMOS gate electrodes.
Verdict. Best exchange CNOT is 9×10⁻⁴ (HRL, 18 qubits) and foundry pairs sit at 99.0–99.6%, but ~80% of two-qubit error is calibration rather than physics, and no device past eight qubits publishes all-pairs fidelity.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A voltage pulse lowers the tunnel barrier between two neighbouring quantum-dot or donor spins, turning on Heisenberg exchange J for a set time to realise a SWAP-family entangler; nothing is radiated, so no antenna, laser or resonator is needed. Loss and DiVincenzo proposed spin qubits on it in 1998; DiVincenzo, Bacon, Kempe, Burkard and Whaley showed in 2000 that exchange alone is universal at ~3× more qubits and ~10× more two-qubit operations — the encoding HRL builds on S[416]. The shuttled variant moves one electron through a conveyor potential into exchange range with a distant partner.
Attributes: fully fabricated carrier; deterministic entangling at ≈10⁻⁷ s (~100 ns), static nearest-neighbour coupling by default.
Baseband voltage control, room temperature but moving cryogenic; error coherent, Pauli, leakage; manufacturing is CMOS.
Physics & limits
J rises exponentially as the barrier is lowered and tunes electrically from near zero to tens of MHz; gate time goes as 1/J, which is why measured gates land at 58–500 ns for 10–90 MHz exchange. The exponential is the liability: the lever that makes J fast makes δJ/J large under gate-voltage and charge-trap noise, so there is a working point rather than a maximum — push J up and charge noise dephases the gate, pull it down and the longer pulse does. Hence HRL's finding that roughly 80% of two-qubit error is extrinsic control and calibration, not decoherence D[190]. Beneath that sit the residual ²⁹Si bath, 1/f charge noise at the oxide interface and small valley splitting, which makes leakage a first-class error. Moving the floor needs ²⁸Si enrichment, better interfaces, and a controller that keeps 1/f noise off the barrier gates.
Engineering state of the art
Best exchange gate: HRL's exchange-only CNOT at 9×10⁻⁴ best reproducible, 3×10⁻³ mean across 18 qubits formed from 54 dots, single-qubit mean 2×10⁻⁴, sequenced by a 4 K controller in commercial 130 nm RF CMOS D[190]. At foundry scale Diraq and imec report 99.04–99.56% two-qubit and 99.9% SPAM on 300 mm SiMOS D[189]. The shuttled variant adds a weight-four parity check at 97.7% per 1.2 µm round trip, motion and idling supplying about a quarter of its error D[349]. SQC's 11-qubit donor device is different in kind: nuclear spins hyperfine-coupled to a shared electron, registers linked by exchange D[192]. Nothing beyond eight qubits publishes all-pairs fidelity.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-09 | Two-qubit 99.04–99.56%, 300 mm foundry | Diraq with imec | D[189] |
| 2025-12 | 11 donor qubits, registers linked by exchange | Silicon Quantum Computing | D[192] |
| 2026-05 | Shuttled-spin CZ 98.86% in 58 ns | QuTech | D[193] |
| 2026-07 | Exchange-only CNOT 9×10⁻⁴ best, 18 qubits | HRL Laboratories | D[190] |
Manufacturing, materials & supply chain
It needs only gate electrodes and voltage pulses, so it rides existing lines: Intel 300 mm EUV (>24,000 devices per wafer D[199]; 96% tune-up yield on 232 devices of one wafer D[766]), imec 300 mm, GlobalFoundries 22FDX, STMicroelectronics FD-SOI. Two concentrations matter — GlobalFoundries has folded the modality into one business unit behind a USD 375 M CHIPS letter of intent C[353], and Quantum Machines' control stack sits under Diraq, HRL, imec, Equal1, Sandia and the UK NQCC C[449]. Export exposure is direct: the 2024-09-06 BIS rule created ECCN 3A901.a for CMOS circuits designed to run at or below 4.5 K — a design-intent test, so a cryo-CMOS controller design file of the HRL type is itself controlled G[301].
Control, readout & I/O burden
A double dot needs roughly 4–6 baseband channels, so wiring grows faster than qubit count under room-temperature control; HRL's answer is 296 lines and 366 DACs inside the fridge at ≤3.5 W, with no real-time room-temperature loop D[190]. Readout, not the gate, sets the cycle: 1–100 µs against a 58–500 ns gate. At 10³ qubits room-temperature fan-out is impractical without cryogenic integration; at 10⁴–10⁶ the crossbar schemes that cut wire count collide with the need to calibrate every exchange pair separately — this mechanism's unresolved architectural conflict.
Role in the stack
It entangles two families: silicon and germanium quantum-dot spins (Intel, Diraq, Quantum Motion, HRL under IBM, Quobly, Equal1) and donor spins (SQC). It requires a gate-defined dot or donor plus baseband control, and provides the entangling layer both families build codes on — at HRL a distance-5 repetition code with Λ(5/3) = 4.7 over 200 rounds, which detects bit flips only and is therefore not a below-threshold result for a full code, plus a post-selected [[4,2,2]] at 0.95 logical fidelity D[190]. It conflicts with crossbar addressing, calibration being per pair. Derived round 8.5 µs on dot spins and 7.7 µs on donors, readout-limited, against the ~100–300 µs typically run: the gate is not the bottleneck. Neighbouring empty slot: an all-pairs, same-chip result past eight qubits.
Evidence — how the numbers were measured
HRL's headline figures and the 80% calibration split are vendor-reported and unreplicated D[190]. Diraq and imec's 99.04–99.56% is a population statistic over foundry devices, not an all-pairs same-chip result; imec's eight-qubit device validates exchange on one of four pairs D[197]. Nature's July 2026 spin-qubit feature was corrected on 2026-08-04, revising single-qubit error rates attributed to HRL and QuTech P[450]. No below-threshold logical memory exists on any spin platform as of 2026-09-04.
SQC's fidelities in [192] read 99.5–99.99%, with Bell states beyond 99%, in the arXiv abstract, and 99.10–99.99%, with Bell states up to 99.5%, in the Nature version; the main report's single 99.90% donor nuclear CZ does not appear in the abstract. Diraq's total raised (">USD 100 M") comes from trade press, not a company release. Not published: the financial terms of IBM's acquisition of HRL, and a dated patent-family count for exchange gates.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Diraq | developer | Australia | 300 mm foundry two-qubit gates, 99.04–99.56% | D[189] |
| HRL Laboratories (IBM) | developer | US | 18 exchange-only qubits, sequenced at 4 K | D[190] |
| QuTech | research | Netherlands | Shuttled-spin CZ, mobile-ancilla parity checks | D[193] |
| Silicon Quantum Computing | developer | Australia | Donor registers linked by electron exchange | D[192] |
| Quantum Motion | developer | UK | Full-stack 22FDX system at the UK NQCC | C[355] |
| Quantum Machines | supplier | Israel | Control stack under most published spin results | C[449] |
Money.
- 2025-11-06 · DARPA · QBI Stage B · ≤USD 15 M each · Diraq, Quantum Motion, SQC of eleven · awarded G[65]
- 2026-05-07 · Quantum Motion · Series C · USD 160 M · DCVC, Kembara · closed C[355]
- 2026-05-21 · Diraq · CHIPS letter of intent · up to USD 38 M · US Commerce · LOI, not an award G[300]
- 2026-08-26 · IBM · M&A, HRL Laboratories · terms undisclosed · closed C[204]
Market & supply chain. No lasers, no vacuum: the equipment is a CMOS line plus baseband electronics, so the supply chain is four foundry lines and one control vendor — a cost argument and a concentration risk at once. Diraq's "<USD 1 per qubit by 2031" is a target, not a cost R[211]. It sells G1 and G2 devices; IBM's purchase bets it carries to G3 and G4.
IP & standards. The foundational results — Loss–DiVincenzo 1998 and exchange-only universality in 2000 S[416] — are published, not proprietary, so defensible IP sits in device geometry, cryogenic control silicon and calibration software. No dated patent-family count specific to this gate was found as of 2026-09-04.
Roadmaps & track record. Diraq (promised 2026-08-27 · 150 k physical, 1 k logical by 2029 · six weeks earlier the same company said "thousands by 2029") R[211] — inconsistent. Intel (promised 2026-01 · Tunnel Falls scaling to "hundreds of dots" · no dated follow-up) C[207] — unscorable. IBM (promised 2026-07-23 · HRL close by end Q3 2026 · closed 2026-08-26) C[10], [204] — met.
Strategic reading. If exchange gates reach fault-tolerant fidelity, the winners are the foundries and whoever owns the cryogenic controller — the qubit becomes a process option, not a product — and the losers are platforms whose cost base is optics and vacuum. IBM's acquisition turns HRL into a hyperscaler's spin programme and forces Diraq, Quantum Motion and Quobly to compete on balance sheet. If calibration burden persists, spins stay a G1/G2 curiosity.
Outlook & open questions
Falsifiable in 12–24 months: confirm/demote that a foundry device publishes all-pairs fidelity past eight qubits, and that IBM places a dated spin milestone on a public roadmap. Best case by 2029: a cryogenically sequenced foundry chip shows below-threshold logical memory with a full code. Worst case: uniformity stalls past ten qubits and roadmaps stay two orders ahead of hardware. Open: can calibration error fall without importing the controller's own error budget; does shuttled CZ displace static exchange; what IBM does with HRL's silicon.
References
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הטקסט בעברית נטען…
Mølmer–Sørensen / light-shift laser gate
Bichromatic-laser spin-dependent force that entangles trapped ions through a geometric phase on a shared motional mode, which the gate leaves as it found it.
Verdict. Still the entangling mechanism under every deployed laser-gate ion system, but gate time scales with chain length (1.6 µs on a pair, 672 µs median on 30 ions) and its floor is laser noise plus photon scattering — the two terms electronic gates delete.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two laser tones detuned symmetrically about a motional sideband drive a spin-dependent force; the pair traces a closed loop in the phase space of a shared vibrational mode and acquires a geometric phase set by the enclosed area, so the spins entangle and the motion returns to its start. The phase depends on loop area, not mode occupation, so a hot bus is tolerated — why this, not Cirac–Zoller, became the production mechanism. Mølmer and Sørensen proposed it in 1999–2000; the light-shift (σzσz geometric-phase) variant, a state-dependent optical dipole force, shares the error budget and dates the deployed line to about 2003.
Attributes: natural trapped-ion carrier; deterministic entangling at ≈63 µs (10^−4.2 s) over a shared motional bus.
Optical control from room temperature; error coherent, leakage, Pauli; manufacturing is optical assembly.
Physics & limits
Gate duration follows the detuning δ from the addressed sideband — one closed loop takes 2π/δ — and δ cannot be opened freely, because the beat note must stay clear of every spectator mode. In an N-ion chain the axial spectrum crowds, δ shrinks and the pulse lengthens: 1.6 µs on a pair D[441] against a 672 µs median on one 30-ion chain D[100], roughly 400× for 15× the ions. Two floors remain. Off-resonant Raman scattering is incoherent, no pulse shape cancels it, and it falls only as the Raman detuning is pushed past the fine-structure splitting. Laser noise and motional heating supply the rest: a 2026 perturbative model weights noise spectral density by a position-dependent sensitivity function and finds distant pairs ~10× more sensitive at ~25 kHz than neighbours, while ~1 kHz noise costs percent-level infidelity independently of position S[442]. The residue is coherent and leakage-like, not depolarising, so averaged benchmarks understate what a code sees.
Engineering state of the art
Best demonstrated: 99.8% at 1.6 µs on a ⁴³Ca⁺ pair, entanglement still generated at 480 ns — under one motional oscillation period (Oxford, 2018) D[441], still the fastest published laser gate. At scale, Helios logs 7.9×10⁻⁴ error in ≈70 µs across 98 Ba⁺ in eight zones D[97]; IonQ's single 30-ion chain, benchmarked over all 435 pairs, gives 550–883 µs, median 672 µs D[100].
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2018 | 99.8% at 1.6 µs; entanglement at 480 ns | Oxford (Schäfer et al.) | D[441] |
| 2023-08 | 550–883 µs, median 672 µs, 30-ion chain | IonQ Forte | D[100] |
| 2025-11 | 7.9×10⁻⁴ error in ≈70 µs, 98 ions | Quantinuum Helios | D[97] |
| 2026-05 | Quantum volume 32,768, gate undisclosed | Alpine Quantum Technologies | C[128] |
Manufacturing, materials & supply chain
Nothing here is fabricated into the trap: the gate is delivered by stabilised lasers, acousto- and electro-optic modulators and beam optics, covered as its own node. Helios needs at least seven wavelengths against 1,228 trap electrodes D[97] — the optical half is the larger bill of materials. Traps by contrast are merchant goods (Infineon, Villach); Honeywell makes Quantinuum's in-house C[320]. Export exposure is at system level — the 2024-09-06 BIS rule created ECCN 4A906 for quantum computers above qubit-count and error-rate thresholds, but no ECCN names ion traps or beam optics G[301].
Control, readout & I/O burden
The two global tones do not scale with ion count; individual addressing does, at ~one modulator channel and beam path per ion. The pulse is the cheap part of the cycle: a full-width Helios layer runs ≈55 ms once sorting, transport and re-cooling are counted — three orders above the 70 µs gate — transport alone was ~60% of runtime on H2 D[97]. At 10³ ions, power and crosstalk trade addressing quality against zone count; at 10⁴–10⁶, gate time growing with chain length makes any single-bus design trade throughput for connectivity, which is why every roadmap subdivides the trap.
Role in the stack
Entangling mechanism of two trapped-ion architectures — QCCD (Quantinuum) and the linear Paul trap with individual laser addressing (IonQ's Aria, Forte and Tempo, Alpine Quantum Technologies, Qudoor, Quantum Art) — and the historical one for lines migrating to laser-free, microwave-driven electronic control (IonQ with Oxford Ionics, eleQtron). It requires a trapped-ion carrier and a laser subsystem delivering phase-stable bichromatic beams to a chosen pair, and provides the entangling layer zoned architectures assume. Its substitute is the near-field electronic gate at 8.4×10⁻⁵ D[102]; switching writes off the optics stack but deletes photon scattering and laser noise. It conflicts with any single-bus design. Derived clock on the QCCD architecture = sum of the syndrome round: gate layers + transport + readout + reset ≈ 9.7 ms, transport 9.0 ms of it, against a measured ~55 ms full-width layer D[97]. No neighbouring empty slot is flagged.
Evidence — how the numbers were measured
Headline numbers are benchmarking averages over a zone or chain; no vendor publishes pair-resolved error against chain position, and the ~10× neighbour-versus-distant gap remains theory S[442]. Quantum-volume claims need the same care: AQT's 32,768 is 2¹⁵ against 2²⁵ published for Quantinuum's 56-qubit H2 C[98] — a record inside the rack-mounted class, not at the frontier. Neither 7.9×10⁻⁴ nor 8.4×10⁻⁵ has an independent replication as of 2026-09-04.
Randomised benchmarking over a native gate set built from two Mølmer–Sørensen gates, MS(π/2, 0) and MS(π/2, π/4) (a 192-element group), is not multiplicity-free: three irreducible representations occur two or three times and give matrix-valued rather than single-exponential decays, so a fidelity robust to state-preparation and measurement (SPAM) errors needs benchmarking against a larger 'lifting' group, here SU(4) P[895]. The demonstration is numerical; a native-gate benchmarking figure for MS gates should be read with its protocol named.
The 480 ns entangling result in [441] carries no fidelity in its abstract; only the 1.6 µs / 99.8% pair is a complete figure of merit. Not published: the gate time and fidelity of AQT's LYNX behind quantum volume 32,768, so its noise-desensitisation claim has no physical number to be checked against.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US-UK | Helios: 98 ions, eight zones | D[97] |
| IonQ | developer | US | Forte's 30-ion chain, 550–883 µs | D[100] |
| Oxford Ionics (IonQ) | developer | UK | Laser-free electronic gate, the substitute | D[102] |
| Alpine Quantum Technologies | developer | Austria | Rack-mounted LYNX, noise-desensitised variant | C[128] |
| Leibniz Supercomputing Centre | user | Germany | 20-qubit AQT system, the only public price | C[323] |
| DARPA | funder | US | QBI Stage B funds both large roadmaps | fact |
Money.
- 2023-12-05 · Alpine Quantum Technologies · sale to Leibniz Supercomputing Centre · ≈EUR 9.8 M, 20 qubits · closed C[323]
- 2025-09-04 · Quantinuum · equity · USD 600 M at USD 10 B pre-money · NVentures, Quanta, QED · closed C[122]
- 2025-09-17 · IonQ · M&A, Oxford Ionics · USD 1.075 B · closed C[18]
- 2026-06-03 · Quantinuum · IPO · USD 1.68 B gross, Nasdaq QNT · closed C[123]
Market & supply chain. Optics are integrated in-house at Quantinuum and IonQ, so no outside vendor holds pricing power; the ion stack's one merchant chokepoint is trap fabrication, which this gate does not use. Q-CTRL sells pulse-optimisation tooling C[443]. Unit economics: EUR 9.8 M for a turnkey 20-qubit rack ≈ EUR 0.5 M per qubit C[323], the only publicly quotable trapped-ion price as of 2026-09-04. Q2-2026 revenue: USD 8.0 M at Quantinuum, USD 80.1 M at IonQ C[123], [326]. G2 and G3 pay for it; the ≈55 ms layer routes G4 elsewhere.
IP & standards. PatSnap's 2026 landscape lists 9+ IonQ families filed across JP/EP/IL in 2025–2026, including "universal gate pulse for two-qubit gates" (JP, 2025), and two pending Quantum Art filings (IL, KR) on ion-array reconfiguration P[375] — not cross-checked elsewhere. No standards body covers this gate.
Roadmaps & track record. Quantinuum (promised 2024-09-10 · Helios 2025, Sol 2027, Apollo 2029 · Helios on schedule 2025-11-05) R[118] — the only met dated promise here. IonQ (promised 2025-06-13 · 256 qubits at 99.99% in 2026 · slipped to H1 2027); its 2020 roadmap missed 4,000 qubits by 2026 by ~40× R[132] — dates are directional. AQT (promised 2026-05-05 · LYNX units Q4 2026 · unscored) C[128].
Strategic reading. If laser gates hold, the vertically integrated optics teams win and no one buys an ion computer as components. If electronic gates win, IonQ with Oxford Ionics takes the cost curve and AQT and Quantum Art lose their optical differentiation. Exposure is asymmetric: Quantinuum, listed since June 2026, is the largest laser-gate incumbent, with Sol and Apollo still laser-driven — a laser-free gate at product scale is its biggest technical risk.
Outlook & open questions
Falsifiable in 12–24 months: confirm/demote that Sol ships in 2027 with laser gates; that a vendor publishes pair-resolved error against chain position; that AQT discloses LYNX gate time and fidelity at the Q4-2026 rollout. Best case by 2029: pulse engineering and zone subdivision hold laser gates at ≈10⁻⁴ with transport still the clock. Worst case: electronic gates reach product scale first and this becomes legacy. Open: does the AQT variant generalise beyond quantum-volume circuits; can scattering-limited error go below 10⁻⁴ at usable power; which binds first at 10⁴ ions, power or transport.
References
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Русский текст загружается…
הטקסט בעברית נטען…
Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter)
Driven SQUID/SNAIL couplers and transmon ancillas mediate beamsplitter and entangling gates between superconducting bosonic cavity modes, for cat, GKP and dual-rail encodings.
Verdict. Dual-rail cavity CZ reaches 0.029% post-selected Pauli error at 500 ns with ~80% of gate error heralded as erasure; no bias-preserving cat-cat entangling gate exists as of 4 Sep 2026.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two bosonic cavity modes are never coupled directly. A nonlinear element between them — a driven DC-SQUID or SNAIL (superconducting nonlinear asymmetric inductive element) coupler, or a dispersively coupled transmon ancilla — is pumped at the mode-frequency difference, turning pump photons into a bilinear exchange (beamsplitter) or a conditional phase. Yale set the pattern in 2018 with an rf-driven 50:50 beamsplitter between two microwave memories D[471]; gate fidelities follow from 2023 D[472].
- b/e: entangling time ≈500 ns (10⁻⁶·³ s), deterministic; microwave drives from room-temperature electronics.
- d/g: modes linked through a shared coupler acting as a bus; 3D-machined cavity hardware, not planar chips.
Physics & limits
The parametric beamsplitter rate reaches a few MHz, hence ~100 ns swaps D[472]; a conditional phase accumulates through a dispersive shift χ/2π ≈ 0.1–1 MHz, hence ~500 ns entangling gates D[84]. The floor is the ancilla, not the cavity: at ancilla T1 ≈ 50–100 µs against a 0.5-µs gate, ancilla error is ~10⁻² unless it is kept virtual or relabelled. Relabelling is the point: dual-rail does not lower total gate error but moves ~80% of it into heralded erasure (0.400(4)% control, 0.096(4)% target), leaving 0.029(6)% unheralded Pauli error and bit-flips at 2.8(4)×10⁻⁶ D[84]; located erasures buy ~5× more tolerable Pauli error at code level than depolarising noise P[402]. Failure modes: ancilla decay mid-gate (an erasure in dual-rail, a phase error elsewhere), ancilla dephasing, higher-Fock leakage no check sees, and for cats any gate term failing to commute with the two-photon dissipation. Moving the floor needs higher-coherence ancillas, virtual-ancilla or dissipative coupling, or a bias-preserving cat Hamiltonian — still theory P[81].
Engineering state of the art
Best demonstrated: dual-rail cavity CZ, ~500 ns, erasure ≈0.5%/gate, post-selected Pauli 0.029(6)%, SPAM ≈0.02% D[84]fact. D-Wave markets it as "approximately 99.9%" C[473], neither the raw nor the post-selected value. Typical at scale lags: AWS's transmon check runs 384 ns, erasure 2.54(1)×10⁻²/check, residual 6.0(2)×10⁻⁴, bias 42(1) D[85]. No cat–cat CNOT exists on hardware P[81]. Dominant error term: unheralded Pauli error surviving post-selection, plus the check's false negatives.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2018-02 | RF-driven 50:50 beamsplitter between two cavity memories | Yale | D[471] |
| 2023-03 | Cavity swap >99.98%, ~100 ns, DC-SQUID coupler | Yale | D[472] |
| 2026-04 | Erasure check 384 ns, residual 6.0(2)×10⁻⁴, bias 42(1) | AWS | D[85] |
| 2026-08 | Dual-rail cavity CZ ~500 ns, post-selected Pauli 0.029(6)% | Quantum Circuits | D[84] |
Trapped ions realise the same qubit-conditioned bosonic primitive outside circuit QED: driving the red and blue motional sidebands together gives a spin-dependent conditional displacement of a motional mode, and free-boson rotations are applied as laser phase shifts; a three-ion ¹⁷¹Yb⁺ chain used them to simulate the dynamics of a Yukawa field model D[884].
Manufacturing, materials & supply chain
Ancilla and coupler are aluminium-junction circuits in aluminium or tantalum films on silicon or sapphire; at Yale the modes are machined high-purity aluminium 3D cavities, etched to 10⁷–10⁸ Q, at D-Wave/Quantum Circuits 3D λ/4 coaxial cavities whose material and making are not published, while AWS's Ocelot holds its modes in thin-film coplanar-waveguide resonators on chip and Alice & Bob in thin-film tantalum circuits on sapphire D[80]fact. No merchant cavity supplier exists — Yale machines its own, D-Wave/Quantum Circuits name no supplier — so surface treatment is lab craft, not a qualified process. Below that, the generic superconducting chain: Bluefors, which absorbed pulse-tube maker Cryomech in 2023, and Oxford Instruments fact. Export exposure is the 2024 BIS rule: ECCN 4A906 (machines whose qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact), 3A904 (refrigerators ≥600 µW at 0.1 K), 3A901 (cryogenic amplifiers) G[301]. No per-cavity cost or yield is public.
Control, readout & I/O burden
Each cell needs a cavity drive, an ancilla drive and a dispersive ancilla readout, so lines run ahead of mode count. Erasure conversion adds latency: AWS resolves a check in 384 ns D[85], the cavity gate in ≈0.4–1 µs D[84]. That fits an FPGA-local loop but nothing off-chassis: NVQLink's 3.84 µs round trip suits syndrome processing, not heralding Cfact. The wall is geometric before electrical: a machined cavity is a cubic-centimetre object, so 10³ modes is a fridge-volume problem and 10⁶ needs planar or transmon variants.
Role in the stack
The shared entangling primitive of two competing superconducting architectures, cat/GKP encoding and dual-rail erasure encoding. It requires a cavity mode plus an ancilla and replaces ancilla-free cat-CNOT schemes: hardware bought for erasure-convertibility or bias, a trade only dual-rail has cashed. It reaches the superconducting branch only. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 1.44 µs on the cat-and-GKP architecture, whose largest term is two 500 ns gate layers, and ≈ 2.8 µs on the dual-rail one, with four. Empty neighbouring slots: a bias-preserving cat entangling gate, a merchant high-Q cavity process.
Evidence — how the numbers were measured
Headline figures come from randomised benchmarking on the composite two-mode system with post-selection on ancilla readout; the erasure fraction comes from that same readout, so false negatives fold into the "residual Pauli" bucket. A transmon-qutrit erasure design reports false positives ~2%, false negatives 6–8% P[405] — the order of what may be misattributed here. Theory keeps the surface-code threshold at least twice the Pauli value under imperfect checks, but only when the check is short against the cycle D[395]. Conflict: 0.029(6)% vs the 0.12% bound at depth D[84] vs "≈99.9%" C[473]; of the three, the measured decomposition is the best supported. SUSTech replicates the architecture, not the fidelity D[406]. Discard rates go unreported.
Not published: the amount of Alice & Bob's May-2026 Series B extension, and the post-selection discard rates of the dual-rail CZ and the beamsplitter swap.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Quantum Circuits Inc. | developer | USA | Built the 500-ns dual-rail CZ; ships 8-qubit Seeker | D[84] |
| D-Wave Quantum | developer | USA | Owner since Jan 2026; funds and markets it | C[14] |
| Yale University | research | USA | Originated ancilla-mediated cavity gates | D[471] |
| AWS | developer | USA | Transmon erasure checks; Ocelot; CNOT theory | D[85] |
| Alice & Bob | developer | France | Cat gates; 18-cat Helium, no logical data | C[87] |
| Nord Quantique | developer | Canada | GKP bosonic gates; QBI Stage B | C[89] |
Money.
| Date | Actor | Event | Amount | Programme / lead | Status |
|---|---|---|---|---|---|
| 2025-01-28 | Alice & Bob | Series B (extension 2026-05-22, undisclosed) | €100M | AVP, Bpifrance | closed Cfact |
| 2025-11-04 | US DOE | centre renewal naming dual-rail | $125M | C2QA/NQISRC | awarded G[474] |
| 2025-11-06 | DARPA | Stage B, 11 teams, Alice & Bob cut | ≤$15M | QBI | official G[65] |
| 2026-01-20 | D-Wave | M&A: Quantum Circuits | $550M | — | closed C[14] |
| 2026-05-18 | Nord Quantique | equity at $1.4B valuation | $30M | — | closed C[89] |
| 2026-08-06 | D-Wave | H1-2026 revenue | $5.9M (−67% YoY) | — | reported C[15] |
Market & supply chain. Nobody sells into this mechanism: it rides the refrigerator and junction chains common to all superconducting qubits, plus one unshared step, 3D cavity machining, which is the single point of failure. Helium's ~40 kW is the family's only public power figure C[87]. It pays for G2 and is a credible G3 candidate via dual-rail, not G4: the cat resource case rests on a phase-flip rate two orders below measurement, and D-Wave's Λ = 27 is a simulation of its own error model Sfact.
IP & standards. Amazon Technologies holds US 11,748,652 B1 (heralding of amplitude-damping decay, granted 2023-09-05), reading directly on heralded-decay dual-rail embodiments G[336] — awkward for rivals, since AWS alone needs no licence. No Yale or Quantum Circuits family surfaced in a dual-rail patent search fact. No litigation, no standards body.
Roadmaps & track record. D-Wave/Quantum Circuits (2026-06, for 2032: 100 logical at Λ = 10, via 17 qubits in 2026) — gate published, no system delivered as of 4 Sep 2026 Pfact; best physics, unproven as product. Alice & Bob (2023, for 2030: 2,000 cats, 100 logical, 10⁻⁶) — Helium shipped without logical data, no Stage B slot; unverified. Nord Quantique (2024, for 2029: 100+ logical at 1:1) — capitalised, unproven. AWS — Ocelot delivered, cat–cat CNOT still theory; claims have not outrun measurements.
Strategic reading. If erasure conversion scales the winners own large superconducting fabs, not bosonic specialities: the mechanism is portable, and IBM, Google or Rigetti could bolt an ancilla check onto existing transmons without 3D cavities P[405]. That is the substitution threat to D-Wave's $550M purchase, which concentrates Yale-lineage IP but buys no fab moat. Losers if it fails: the cat roadmaps, whose economics rest on a 100× resource reduction the measured phase-flip rate does not support.
Outlook & open questions
Confirm/demote in 12–24 months: a cat–cat CX on hardware; a dual-rail gate below 0.01% post-selected Pauli outside Quantum Circuits; a delivered 17-qubit system with its promised 2× logical-versus-physical error reduction; a published discard rate. Best case 2029: erasure conversion becomes a standard transmon add-on. Worst case: cat–cat gates stay theory and 3D cavities stall on volume. Open: does the erasure fraction hold at depth 10³; the true false-negative rate; can it be planarised without losing Q; does D-Wave fund Quantum Circuits through 2028 on $5.9M half-year revenue. Watch QBI Stage C.
References
- [14] D-Wave Quantum Inc., “D-Wave Announces Agreement to Acquire Quantum Circuits Inc., Establishing World's Leading Quantum Computing Company,” Jan. 7, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-to-acquire-quantum-circuits-inc-establishing-world-s-leading-quantum-computing-company/ - [15] D-Wave Quantum Inc., “D-Wave Reports Second Quarter 2026 Results,” Aug. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-reports-second-quarter-2026-results/ - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [81] Y. Ye et al., “Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter,” arXiv:2607.22852, Jul. 2026. P
- [84] N. Mehta et al., “An entangling gate for dual-rail erasure qubits,” Nature, vol. 656, no. 8126, pp. 47–53, Aug. 2026, doi: 10.1038/s41586-026-10822-y. arXiv:2503.10935. D
- [85] J. S.-C. Hung et al., “Fast, High-Fidelity Erasure Detection of Dual-Rail Qubits with Symmetrically Coupled Readout,” arXiv:2604.16292, Apr. 2026. D
- [87] N. Coppola, “Alice & Bob Unveils First Quantum System, Helium,” Alice & Bob, Jun. 10, 2026. [Online]. Available: https://alice-bob.com/
newsroom/ Calice-bob-unveils-first-quantum-system/ - [89] Nord Quantique, “Nord Quantique Reaches $1.4 Billion USD Valuation with Latest Investment,” Business Wire, May 18, 2026. [Online]. Available: https://www.businesswire.com/
news/ Chome/ 20260518358351/ en/ Nord-Quantique-Reaches-$1.4-Billion-USD-Valuation-with-Latest-Investment - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [336] A. M. Kubica and A. Retzker, “Heralding of amplitude damping decay noise for quantum error correction,” Google Patents, Sep. 5, 2023. [Online]. Available: https://patents.google.com/
patent/ GUS11748652B1/ en - [395] K. Chang et al., “Surface Code with Imperfect Erasure Checks,” PRX Quantum, vol. 6, no. 4, Art. no. 040355, Dec. 2025, doi: 10.1103/d1v7-nctj. D
- [402] M. Violaris et al., “Developments in superconducting erasure qubits for hardware-efficient quantum error correction,” arXiv:2601.02183, Jan. 2026. P
- [405] B.-J. Liu et al., “Hardware-Efficient Erasure Qubits With Superconducting Transmon Qutrits,” arXiv:2604.08672, Apr. 2026. P
- [406] W. Huang et al., “Logical multi-qubit entanglement with dual-rail superconducting qubits,” Nat. Phys., vol. 22, no. 4, pp. 591–597, Mar. 2026, doi: 10.1038/s41567-026-03211-9. arXiv:2504.12099. D
- [471] Y. Y. Gao et al., “Programmable interference between two microwave quantum memories,” Phys. Rev. X, vol. 8, no. 2, Art. no. 021073, Jun. 2018, doi: 10.1103/PhysRevX.8.021073. arXiv:1802.08510. D
- [472] Y. Lu et al., “High-fidelity parametric beamsplitting with a parity-protected converter,” arXiv:2303.00959, Mar. 2023. D
- [473] K. Chou, J. Teoh, and N. Mehta, “Why D-Wave's New Two-Qubit Gate is a Breakthrough for Quantum Error Correction,” D-Wave Quantum Blog, Aug. 5, 2026. [Online]. Available: https://www.dwavequantum.com/
learn/ Cblog/ posts/ why-d-wave-s-new-two-qubit-gate-is-a-breakthrough-for-quantum-error-correction/ - [474] US Department of Energy, “Energy Department Announces $625 Million to Advance the Next Phase of National Quantum Information Science Research Centers,” Energy.gov, Nov. 4, 2025. [Online]. Available: https://www.energy.gov/
articles/ Genergy-department-announces-625-million-advance-next-phase-national-quantum-information - [884] A. T. Than et al., “Quantum field theory dynamics on a spin–phonon quantum computer,” Nat. Phys., Sep. 2026, doi: 10.1038/s41567-026-03402-4. arXiv:2509.11477. D
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הטקסט בעברית נטען…
Bias-preserving cat–cat CNOT
A direct entangling gate between two dissipative cat qubits that keeps the exponential bit-flip suppression intact through the interaction — theory only.
Verdict. Undemonstrated as of 2026-09-04; demote every cat-code qubit-count estimate if no two-cat gate shows measured bias preservation by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An entangling gate acting directly between two dissipative cat qubits, no transmon ancilla in the middle, preserving the bit-flip/phase-flip asymmetry through the interaction. Every cat CX in hardware is cat–transmon; the cat–cat version is what cat-code resource estimates silently assume. The first coherent (unitary) scheme, a "vacuum-conditional beam-splitter", was posted 2026-07-24 by Ye et al. (AWS Center for Quantum Computing / Caltech) S[81]. Entangling is intended deterministic, gate time unmeasured; control is room-temperature microwave, bus connectivity.
Physics & limits
The difficulty is geometric: a cat CNOT rotates the target's coherent amplitude through π conditioned on the control, briefly leaving the stabilised two-lobe manifold; any non-adiabatic drive term then leaks population between lobes as plain bit-flips, no longer exponentially suppressed in photon number. Dissipative schemes pin the state but pay in gate-induced phase-flips. The unitary scheme drops the dissipator and claims logical memory below 10⁻⁶ from a distance-7 repetition code of 13 cats — from assumed lifetimes and nonlinearity precision, not measurement S[81]. The floor is structural: one residual bias-breaking term turns the exponential into a polynomial and takes the qubit-count case with it S[95].
Engineering state of the art
No cat–cat entangling gate exists in hardware as of 2026-09-04.
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2025-02 | Cat–transmon CX at n̄ = 2: bit-flip 3.5(4)×10⁻³, phase-flip 9.6(4)×10⁻² → bias > 25 under the gate, > 30 idle | AWS/Caltech (Ocelot) | D[80] |
| 2026-07 | Unitary cat–cat CNOT proposed; <10⁻⁶ logical memory claimed, distance 7 / 13 cats | Ye et al. | S[81] |
| 2030 | 2,000 cats → 100 logical at 10⁻⁶, requiring ≥13-min bit-flip during a CNOT | Alice & Bob | R[412] |
The neighbour shows the budget's shape: Ocelot's 2.8 µs cycle moved logical error only from 1.75(2)% at distance 3 to 1.65(3)% at distance 5, because per-CX phase-flip is already ~10⁻¹ D[80].
The <10⁻⁶ logical-memory claim in [81] rests on assumed component lifetimes and nonlinearity precision, with no independent replication and no measured gate as of 2026-09-04. The roadmap page [412] attaches the "13 minutes" bit-flip requirement to the Graphene chip without saying whether it holds idle or under a gate. No experimental group has reported an attempt at a cat–cat entangling gate.
Manufacturing, materials & supply chain
No dedicated process: the gate reuses existing cavity bodies, junction lithography and room-temperature microwave stacks. Dropping the ancilla removes one transmon and readout chain per gate pair — Ocelot spends four ancillas on five cats — but adds a parametric tone per cat: lines per qubit are re-allocated, not reduced. At 10³ cats the wall is coax density and pump crosstalk in one dilution unit; at 10⁴–10⁶ it is the generic microwave wiring wall, no cryogenic-CMOS multiplexing of cat pump tones having been demonstrated.
Role in the stack
On the superconducting bosonic (cat/GKP) architecture; requires two cat-encoded qubits and provides nothing downstream until it exists. It replaces the ancilla-mediated bosonic CX, trading a non-bias-preserving transmon channel for an unproven direct interaction; not switching leaves the ancilla's bit-flips setting the code floor. It does not move the derived clock, a 1.44 µs round here inside the measured 2.8 µs cycle, set by CX plus dispersive ancilla readout D[80]. Verification: the sole evidence is a proposal — no replication, no hardware attempt, and <10⁻⁶ is a code-level projection, not a measured fidelity S[81].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| AWS | developer | US | Authored the unitary scheme; owns the cat CX hardware | S[81] |
| Alice & Bob | developer | FR | 2030 rung, 2,000 cats → 100 logical, presumes it | R[412] |
| DARPA | investor | US | Stage B funds Nord Quantique, not Alice & Bob | fact |
Money.
2025-01-28 · Alice & Bob · Series B · €100 M · — · closed fact
2026-05-22 · Alice & Bob · Series B extension · undisclosed · NVentures lead · closed C[88]
2026-06-17 · GENCI · buys first "Helium" · undisclosed · French HPC agency · closed C[87]
2025-11-06 · Nord Quantique · QBI Stage B · $5 M, up to $15 M · DARPA · announced G[65]
Market & supply chain. No supplier is specific to this gate; it reuses cat vendors' fabrication and pays for G3 alone.
IP & standards. No dated patent family specific to a bias-preserving cat–cat gate was found as of 2026-09-04.
Roadmaps & track record. AWS: promised 2026-07, no experimental date S[81]. Alice & Bob: promised on the live roadmap, for 2030 — Boson 4 (2024) and Helium (2026-06) landed, but every rung past Lithium (48 cats, 4 logical, 10⁻³) presumes this gate R[412].
Strategic reading. If measured, cat codes keep their qubit-count argument and surface-code transmon vendors lose; if still theory past 2028, dual-rail erasure takes the hardware-efficient slot.
Outlook & open questions
Confirm by 2028 if a measured two-cat gate holds bit-flip time within 10× of idle; demote if 2028 passes with only ancilla-mediated gates, since the 2030 rung and the 126,133-cat class of estimates lose their premise S[95]. Best case 2029: bias above 10³ under drive. Worst case: cat logic runs through ancillas indefinitely. Open: does the scheme survive junction-nonlinearity spread; can the gate be characterised without ancilla contamination; who attempts hardware first? Watch Ocelot follow-ups and the Lithium chip.
References
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [81] Y. Ye et al., “Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter,” arXiv:2607.22852, Jul. 2026. S
- [87] N. Coppola, “Alice & Bob Unveils First Quantum System, Helium,” Alice & Bob, Jun. 10, 2026. [Online]. Available: https://alice-bob.com/
newsroom/ Calice-bob-unveils-first-quantum-system/ - [88] N. Coppola, “Alice & Bob announces Series B Extension,” Alice & Bob, May 22, 2026. [Online]. Available: https://alice-bob.com/
newsroom/ Calice-bob-announces-series-b-extension/ - [95] É. Gouzien, D. Ruiz, F.-M. Le Régent, J. Guillaud, and N. Sangouard, “Performance Analysis of a Repetition Cat Code Architecture: Computing 256-bit Elliptic Curve Logarithm in 9 Hours with 126133 Cat Qubits,” Phys. Rev. Lett., vol. 131, Art. no. 040602, Jul. 2023, doi: 10.1103/PhysRevLett.131.040602. arXiv:2302.06639. S
- [412] Alice & Bob, “Roadmap,” Jun. 23, 2026. [Online]. Available: https://alice-bob.com/
roadmap/ R
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הטקסט בעברית נטען…
Multi-photon resource-state generator (RSG; 6-ring etc.)
The source-plus-fusion subsystem that must mass-produce encoded multi-photon graph states at code rate to feed fusion-based fault tolerance; nothing runs near that rate.
Verdict. Real: 8 photons fused into 6-rings and 7-trees at 0.4–2.3 coincidences/minute. Unproven: any generator within nine orders of magnitude of the needed rate. Demote if no fused state above 16 photons by 2029.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The source-plus-fusion subsystem that must manufacture, at code rate, the encoded graph states — canonically the 6-ring — that fusion-based fault tolerance consumes and destroys. Browne–Rudolph type-II fusion (2005) made it possible; Bartolucci et al. fixed the 6-ring as reference resource and set its loss budget S[179]. Best instance: MPQ Garching fused deterministically emitted photons into 6-rings and 7-trees, 8 photons, 0.4–2.3 coincidences/minute D[688]. Attributes: flying photons from fabricated emitters, heralded entangling, no fixed clock; electro-optic room-temperature control, pure-loss errors, photonic-IC fabrication.
Physics & limits
An n-photon graph from k-photon primitives costs ~n/k fusions, each 50% unboosted or 75% boosted; failure is heralded and erases one of the two measured outcomes, but every attempt burns a photon that must be indistinguishable and lossless. Yield is brightness × indistinguishability × fusion success × transmission over the whole state — the exponent is photon count, not depth. Hence the code's tolerance: 2.7% loss per photon with 6-rings, ~17% only with 168-photon states nobody can build S[179]. A 2026 re-analysis sharpens this: fusion failure alone sets a logical-error floor at zero loss, forcing very large distance for 10⁻¹⁰, while emitter-mediated fusion raises the threshold to 7.0–7.3% against an unencoded 6-ring's 0.38–0.82% S[264]fact.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2024-05 | 8 photons fused into 6-ring/7-tree graphs, 0.4–2.3/min, fidelity 0.34–0.85 | MPQ | D[688] |
| 2025-02 | Fusion Bell fidelity 99.22% (component only) | PsiQuantum | D[169]fact |
| 2025-05 | Reconfigurable 4-photon graph states, one QD, ~0.5 Hz | C2N Paris-Saclay | D[824] |
| 2026-06 | Emitter-fusion loss threshold 7.0–7.3% vs 0.38–0.82% | Sparrow | S[264] |
Rate is the gap: components clear 99%, but optical fusion has not passed eight photons since 2024.
In the microwave domain, fusion is already deterministic: a superconducting circuit fused on-demand time-bin cluster states by non-destructive Bell projection of flying microwave photons, with qubit reset and reuse, into graph states with genuine multipartite entanglement across 13 photonic qubits D[885]. Those photons cannot leave the cryostat without a microwave–optical transducer, itself an empty slot, so the result does not fill this optical slot.
Quandela's 12-qubit Belenos/Lucy delivery to CEA is dated 2025-10 and the Lucy/Joliot-Curie HPC launch 2026-04-14; no single source reconciles the two. No independent group has replicated the 2024 MPQ 8-photon record as of 4 Sep 2026.
Manufacturing, materials & supply chain
No commercial resource-state generator exists; the nearest base is 300 mm photonic IC — GlobalFoundries' Quantum Technology Solutions Cfact and PIXEurope fact. Deterministic sources are the single point of failure: Sparrow Quantum, sole merchant vendor as of 4 Sep 2026, ships 20–35% system efficiency against its own 55.3% best device and USTC's 71.2% record Dfact; no cost or yield per state is public. I/O scales with photon count, not qubit count: a pump, switch tree and detectors per source, feed-forward within the photon's flight time per fusion — ~0.1–0.2 dB per switch against a ~0.5 dB budget at multiplexing depth ~10 D[169]. At 10³ states/s the wall is switch loss; at 10⁶, thousands of cryogenic detector channels under GHz feed-forward. ECCN 4A906 catches the machine; none names photon sources fact.
Role in the stack
In the photonic fusion-based architecture (PsiQuantum, Quandela, QuiX): requires linear-optical fusion and single photons, provides the only input fusion-based fault tolerance accepts. It sets the architecture's clock — on a fusion architecture there is no syndrome round (gate layers + transport + readout + reset); its place is taken by generation at ~0.4–2.3 min⁻¹ D[688] against the ~10⁹ s⁻¹ a teraquop machine (10¹² reliable operations) needs; the 24–168-photon slot next door is empty. Verification: the record is coincidence-counted tomography with fidelity 0.34–0.85 by graph type, unreplicated; nearest independent work is 4-photon states D[824]. Every threshold quoted is simulation.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | In-house fusion and generation | Dfact |
| Quandela | developer | FR | QD sources; Lucy on Joliot-Curie, running post-selected gates, not resource states | Cfact |
| Sparrow Quantum | supplier | DK | Sole merchant source vendor | Dfact |
| MPQ Garching | research | DE | Holds the 8-photon record | D[688] |
Money.
2025-04-10 · Sparrow Quantum · Series A · EUR 21.5 M · lead undisclosed · closed Pfact
2025-09 · PsiQuantum · Series E · USD 1 B at USD 7 B · closed Pfact
2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · USD 125 M · definitive fact
Market & supply chain. No merchant product; money goes to the inputs — source chips (Sparrow, a chokepoint) and fusion-capable PICs. Unit economics unquotable; only G3/G4 pay.
IP & standards. No dated patent family specific to resource-state generation as of 4 Sep 2026; the adjacent grant is ORCA's US 12,437,225 fact. No throughput standard exists.
Roadmaps & track record. (2025-07 · QuiX error-corrected generation 2027 · pending); (2025 · Quandela first logical qubit · missed; QBIT Stage A entered 2026-06-16 fact). No dated rate milestone exists.
Strategic reading. Generation rate, not fidelity, decides fusion photonics; a source vendor that also owns fusion gains leverage over integrators building sources in-house. If it fails, the architecture loses to CV/GKP and to matter qubits.
Outlook & open questions
Confirm by 2028: a fused state above 16 photons published with fidelity and rate; demote if still single digits. Best case 2029: merchant emitters plus on-chip fusion reach ≥10³ states/s. Worst case: the subthreshold floor holds and all-linear-optics 6-rings are abandoned. Open: can multiplexed sources beat emitters per useful state; does Sparrow close its 20–35%-to-55% gap. Watch: any rate figure in DARPA Stage C V&V.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. S
- [264] M. C. Löbl, L. A. M. Pettersson, J. Dragašević, S. X. Chen, and O. A. D. Sandberg, “The subthreshold issue of fusion-based quantum computing,” arXiv:2606.28490, Jun. 2026. S
- [688] P. Thomas, L. Ruscio, O. Morin, and G. Rempe, “Fusion of deterministically generated photonic graph states,” Nature, vol. 629, no. 8012, pp. 567–572, May 2024, doi: 10.1038/s41586-024-07357-5. D
- [824] H. Huet et al., “Deterministic and reconfigurable graph state generation with a single solid-state quantum emitter,” Nat. Commun., vol. 16, no. 1, Art. no. 4337, May 2025, doi: 10.1038/s41467-025-59693-3. D
- [885] Y. Li et al., “Deterministic and programmable fusion for the scalable generation of photonic graph states,” Nat. Phys., Sep. 2026, doi: 10.1038/s41567-026-03471-5. D
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הטקסט בעברית נטען…
Linear-optical fusion (heralded)
Probabilistic Bell-basis measurement on two photons — 50% unboosted, 75% with ancillae — whose failure is heralded and erases one of the two measured outcomes; the entangling primitive of fusion-based photonics.
Verdict. Real: single fusions at 99.22% Bell fidelity on chip, 99.72% chip-to-chip (PsiQuantum, 2025-02). Unproven: any chained fusion network with an end-to-end success rate. Demote if no multi-fusion result is published by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A Bell-basis measurement — beamsplitter, phase shifters, number-resolving detectors — projecting two photons onto a Bell state or destroying both and saying so, handing the code erasure rather than Pauli error. Browne and Rudolph introduced type-I/II fusion in 2005 to grow cluster states without a deterministic gate S[451]; linear optics caps unambiguous discrimination at 50%, unentangled ancillae lift it to 75% S[419]. Attributes: flying photons, heralded entangling at ~100 ns; electro-optic room-temperature control, loss-dominated errors, photonic-IC fabrication.
Physics & limits
The 50% ceiling is a linear-optics bound (Calsamiglia & Lütkenhaus 2001): passive optics with vacuum ancillae distinguishes at most two of the four Bell states, and the ancilla photons that raise it to 75% and beyond must themselves survive. The operating figure is success probability × transmission²; loss turns a success into heralded failure at best, an undetected error at worst. The gate is not the problem: 99.22 ± 0.12% on chip, 99.72 ± 0.04% chip-to-chip over 42 m at ~2 K D[169]fact. The floor is the path around it — SiN 1.8 ± 0.2 dB/m, BTO switch 100 mdB, fibre-to-chip 52 mdB, on-chip SNSPD 93.4% median D[169] — and failure itself: a 2026 re-analysis puts a logical-error floor at zero loss, so all-linear-optics designs need very large distance, while emitter-mediated fusion tolerates 7.0–7.3% S[264]fact.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2005 | Type-I/II fusion, 50% success, proposed | Browne & Rudolph | S[451] |
| 2014 | 75% Bell measurement with unentangled ancillae | Ewert & van Loock | S[419] |
| 2025-02 | Bell fidelity 99.22 ± 0.12% on chip; 99.72 ± 0.04% chip-to-chip, 42 m | PsiQuantum | D[169] |
| 2026-06 | Fusion-failure noise floor at zero loss; 7.0–7.3% threshold | Sparrow | S[264] |
Every dated fidelity is one fusion measured alone; no chained-fusion success rate is public.
No second group has replicated PsiQuantum's 99.22%/99.72% fusion fidelities as of 4 Sep 2026. Quandela's Lucy is described by its sources only as a 12-photonic-qubit machine, not as a fusion-based system. The main report's PsiQuantum waveguide loss of 0.5 dB/m conflicts with the Nature paper's 1.8 ± 0.2 dB/m for single-mode SiN, the figure used here.
Manufacturing, materials & supply chain
No fusion-specific materials: the gate reuses the platform stack — SiN waveguides, BTO switches, on-chip SNSPDs on 300 mm silicon at GlobalFoundries Cfact. Manufacturing decides loss per element, and every element sits inside the attempt: switch 100 mdB, fibre-to-chip 52 mdB D[169]; best packaged coupling is Xanadu's 0.085 dB/facet Cfact. I/O is channels and latency: 2–4 number-resolving detectors per fusion plus feed-forward within the photon's flight time; Aurora runs 12 modes on a 1 MHz cycle D[173]. At 10³ fusions/s the constraint is accumulated switch loss; at 10⁴–10⁶, cryogenic channel count and GHz feed-forward, unbuilt. ECCN 4A906 covers the machine, 3A901 sub-4.5 K electronics fact.
Role in the stack
Requires single photons, single-photon detection for heralding and electro-optic switching for feed-forward; provides the fusion measurements consumed by resource-state generation and fusion-based fault tolerance (PsiQuantum, Quandela, QuiX). It replaces CV Gaussian combination on the continuous-variable photonic GKP architecture (Xanadu), where it is an alternate — switching changes detectors, encoding and error model together. Clock contribution ~1.0 × 10⁻⁷ s per attempt, divided by success probability and multiplexing depth, so generation, not the gate, dominates the derived clock. Verification: the headline numbers are tomography of one fusion; no protocol reports success-at-depth, and no second group has replicated them.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | Highest published fusion fidelity, 300 mm line | Dfact |
| Quandela | developer | FR | Fielded linear-optical hardware | Cfact |
| QuiX Quantum | developer | NL | MBQC hardware at DLR | Cfact |
| Sparrow Quantum | research | DK | Threshold case against linear-optics fusion | Sfact |
| DARPA | investor | US | Funds PsiQuantum Stage C, Quandela QBIT | fact |
Money.
2025-09-10 · PsiQuantum · Series E · USD 1 B at USD 7 B · BlackRock, Temasek · closed fact
2026-06-16 · Quandela · DARPA QBIT Stage A · undisclosed · announced fact
2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · USD 125 M · definitive fact
Market & supply chain. No separate market: fusion ships inside a photonic IC, so the foundry and packaging house set its usable success probability. Concentration risk sits with GlobalFoundries; only G3/G4 pay.
IP & standards. No dated patent family specific to the fusion gate as of 4 Sep 2026; nearest is ORCA's US 12,437,225 fact.
Roadmaps & track record. (2025-02 · Omega component metrics · delivered); (2026-07 · Stage C V&V of switches, packaging, cryogenics · in progress, funding validation not publication). Component credibility good, system-level fusion untested.
Strategic reading. Component fidelity is table stakes; the contest is success rate at depth, where the 2026 threshold argument favours emitter-mediated fusion — a challenge to PsiQuantum and QuiX, an opening for quantum-dot vendors. If linear optics holds, foundries capture the value.
Outlook & open questions
Confirm by 2027: a published network of ≥3 chained fusions with end-to-end success rate and erasure statistics; demote if only single-fusion figures exist by 2028. Best case 2029: boosted fusion above 75% on chip. Worst case: the zero-loss failure floor holds and linear-optical fusion survives only inside emitter hybrids. Open: how correlated failures are across a chip; whether 93%-efficient number resolution supports boosting.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [264] M. C. Löbl, L. A. M. Pettersson, J. Dragašević, S. X. Chen, and O. A. D. Sandberg, “The subthreshold issue of fusion-based quantum computing,” arXiv:2606.28490, Jun. 2026. S
- [419] F. Ewert and P. van Loock, “3/4-Efficient Bell Measurement with Passive Linear Optics and Unentangled Ancillae,” Phys. Rev. Lett., vol. 113, no. 14, Art. no. 140403, Sep. 2014, doi: 10.1103/PhysRevLett.113.140403. arXiv:1403.4841. S
- [451] D. E. Browne and T. Rudolph, “Resource-Efficient Linear Optical Quantum Computation,” Phys. Rev. Lett., vol. 95, no. 1, Art. no. 010501, Jun. 2005, doi: 10.1103/PhysRevLett.95.010501. S
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הטקסט בעברית נטען…
Measurement-based Majorana gate
Clifford gates generated by sequences of joint fermion-parity measurements instead of physical braiding; specified since 2008, never operated.
Verdict. Falsified as a gate mechanism unless a joint (X-basis) parity measurement with a stated error and any two-tetron operation both appear by end-2027; as of 4 Sep 2026 the count of gate operations is zero.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Braiding is replaced by a schedule of projective joint fermion-parity measurements. Bonderson, Freedman and Nayak showed in 2008 that an anyonic teleportation identity lets topological-charge measurements produce the braiding transformations S[475]; Karzig et al. made it hardware in 2017 — Cliffords read as differential-capacitance shifts of dots tunnel-coupled to Majorana zero modes (MZMs) S[421]. Every published measurement here is single-wire (Z-type); the two-wire joint measurement that is the gate has never been reported D[21].
a fabricated (1.0) · b gate time unmeasured, deterministic by intent · c no readout of its own
d static · e low-frequency control at room temperature · f error structure unknown · g MBE wire stack
Physics & limits
Fidelity is joint-measurement time over the lifetime of the basis projected, and that ratio is where the mechanism fails. The tetron's Z-loop parity lives 12.4 ms, the X loop, which a gate repeatedly projects, 14.5 µs, ~1000× shorter D[20], attributed to the larger quasiparticle-capture cross-section of the two-loop configuration: poisoning, not dephasing. At SNR 1 in 3.6 µs D[13] one X projection eats a fifth of that window, so a Clifford sequence has no margin. Operation is adaptive (next basis from last outcome), so feed-forward must close inside the same window; none has been published. Over trivial Andreev levels, meanwhile, a measurement sequence implements no braid at all D[23].
Engineering state of the art
table
No row is a gate: the 2026 result measured one nanowire of a multi-tetron array: no braid, no joint parity, no two-qubit operation, no entanglement, no T1/T2 D[21].
The arXiv HTML of [20] also gives an X loop of ~4 µs and a Z loop of ~9.3 ms for other tunings; the ~1000× ratio holds for both readings, the 14.5 µs / 12.4 ms point values do not. Not published: a dollar figure for DARPA's US2QC award to Microsoft, and any feed-forward latency, dot–wire coupling switching time or projected gate time for this mechanism.
Manufacturing, materials & supply chain
Nothing is fabricated for this mechanism alone: it consumes the InAs–Pb stack and the readout below it. The unbuilt part is control: per-tetron tunable dot–wire couplings, an rf loop per measurable parity, and a demodulator-to-bias path that must resolve inside the X window. At 10³ tetrons the line budget resembles transmon readout; the wall is latency, unquantified because no adaptive sequence has been attempted.
Role in the stack
Requires the Majorana-parity carrier (two wires per tetron) and quantum-capacitance readout; it would supply the topological architecture's entire Clifford layer. The only substitute is braiding in T-junction networks, geometry nobody is building. No derived clock: with no gate operated and no code on the architecture, sum of the syndrome round: gate layers + transport + readout + reset reduces to its readout term, ~3.6 µs D[13], reset unpublished. Verification is telegraph statistics, not benchmarks: no randomised benchmarking, tomography or Bell test exists. QuTech's independent single-shot parity readout (Nature 650, 2026-02-11) replicates the method on InSb dot chains, limited protection stated D[216]; Legg's Matters Arising (2026-06-24) argues the readout regions are disordered and gapless, so the signals may be trivial, and Microsoft's same-day reply concedes nothing D[23].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Sole builder; tetrons, no gate | D[21] |
| DARPA | investor | US | US2QC final Validation & Co-Design stage since 2025-02-06, AFRL and Johns Hopkins APL evaluating; not a QBI Stage B performer | fact |
| QuTech | research | NL | Independent parity readout, not this gate | D[216] |
Money. 2025-02-06 · Microsoft · US2QC advances to its final Validation & Co-Design stage · undisclosed · DARPA · announced fact. 2026-01-23 · Microsoft · Quantum Pioneers Program · ≤ USD 200,000 per academic proposal for measurement-based topological computing · announced Pfact.
Market & supply chain. No market and no unit economics; only G3/G4 fault tolerance would pay, and only after a two-qubit result. Supply is internal to one company: concentration risk is total.
IP & standards. Microsoft's own published lineage S[421]; no dated patent count specific to this gate found as of 4 Sep 2026.
Roadmaps & track record. ("years not decades", promised 2025-02, for fault tolerance → restated as 2029 in 2026-06; status 4 Sep 2026: no joint measurement, no gate) C[215]; DARPA's utility-scale horizon is 2033 fact. Every annual Microsoft result has been readout; 2029 carries no X-measurement milestone.
Strategic reading. If measurement-only Cliffords work, Microsoft skips T-junction fabrication and owns the architecture; if not, the encoding, readout and epitaxy nodes below lose their only consumer.
Outlook & open questions
Falsifiable in 12–24 months: a first joint (X-basis) parity measurement with a stated assignment error; any operation or entanglement between two tetrons; a published X/Z ratio below 100×. Confirm on the first two; demote to theory if none lands by end-2027. Best case 2029, measurement-only Cliffords on a small array; worst case, X-basis poisoning is intrinsic to the two-loop geometry and the line closes. Open: is the asymmetry geometric or material; does anyone outside Microsoft attempt a joint measurement.
References
- [13] Microsoft Azure Quantum, “Interferometric single-shot parity measurement in InAs–Al hybrid devices,” Nature, vol. 638, no. 8051, pp. 651–655, Feb. 2025, doi: 10.1038/s41586-024-08445-2. D
- [20] M. Aghaee et al., “Distinct Lifetimes for X and Z Loop Measurements in a Majorana Tetron Device,” arXiv:2507.08795, Jul. 2025. D
- [21] M. Aghaee et al., “20 Second Parity Lifetime in an InAs–Pb Tetron Device,” arXiv:2606.03884, Jun. 2026. D
- [23] Microsoft Quantum, “Reply to: On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E27–E28, Jun. 2026, doi: 10.1038/s41586-026-10568-7. D
- [215] C. Nayak, “Majorana 2 – Microsoft's Scalable Quantum Processor With Reliable, Long-Lasting Qubits,” Microsoft Quantum. [Online]. Available: https://quantum.microsoft.com/
en-us/ Cinsights/ blogs/ majorana-2-scalable-quantum-processor - [216] N. van Loo et al., “Single-shot parity readout of a minimal Kitaev chain,” Nature, vol. 650, no. 8101, pp. 334–339, Feb. 2026, doi: 10.1038/s41586-025-09927-7. D
- [421] T. Karzig et al., “Scalable designs for quasiparticle-poisoning-protected topological quantum computation with Majorana zero modes,” Phys. Rev. B, vol. 95, no. 23, Art. no. 235305, Jun. 2017, doi: 10.1103/PhysRevB.95.235305. arXiv:1610.05289. S
- [475] P. Bonderson, M. Freedman, and C. Nayak, “Measurement-Only Topological Quantum Computation,” Phys. Rev. Lett., vol. 101, no. 1, Art. no. 010501, Jun. 2008, doi: 10.1103/PhysRevLett.101.010501. arXiv:0802.0279. S
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הטקסט בעברית נטען…
Analogue Rydberg Hamiltonian evolution
Global laser fields drive a programmable Rydberg Ising Hamiltonian on a whole tweezer array at once: the waveforms Ω(t), Δ(t), a fixed local-detuning pattern and the atom geometry are the program, and there is no discrete gate.
Verdict. Demonstrated to 256–289 atoms and productive for many-body physics, but graded by observables, not gate error: the reference many-body fidelity benchmark reports 0.095 at 60 atoms on an academic Sr machine, the register holds no fidelity figure for Aquila or Fresnel as of 2026-09-26, and the mode admits no error correction.
Λ = error-suppression factor per code-distance step; MIS = maximum independent set; SA = simulated annealing; Fd = cross-entropy-type many-body fidelity estimator; MPS = matrix-product state (χ = bond dimension); AHS = analog Hamiltonian simulation, Amazon Braket's program type; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The array evolves under one Hamiltonian, H/ℏ = Σᵢ (Ω(t)/2) σˣᵢ − Σᵢ [Δ(t) + hᵢ Δ_loc(t)] nᵢ + Σ_{i<j} C₆ r_ij⁻⁶ nᵢ nⱼ: global waveforms, one static site pattern hi, couplings fixed by atom positions C[262]C[429]. Technology g_ryd uses the same blockade for a two-atom CZ inside a circuit; here it acts on all pairs for the whole run, and the output is a bit-string sample. Technology g_anneal, the rf-SQUID flux annealer, sets couplings with programmable on-chip couplers D[430]; here geometry is the coupling matrix, and blockade confines the dynamics to independent sets of a unit-disk graph, the basis of MIS encoding D[431]. Lineage: 51 atoms in 1D, Harvard/MIT, 2017 D[384]; Pasqal's 2020 architecture naming analogue "Hamiltonian sequences" beside circuits D[385]; Aquila on Amazon Braket C[262].
Attributes: natural carrier; no step time (one evolution, ≤4 µs on Aquila); readout inherited; no mobility during the program; optical control at room temperature; coherent and loss errors; optics manufacturing.
Physics & limits
Aquila: Ω ≤ 15.8 rad/µs, |Δ| ≤ 125 rad/µs, C6 = 5,420,503 µm⁶ rad/µs (70S), spacing ≥4 µm, program ≤4 µs, T2* 5.8 µs, driven T2 7.5 µs C[262]: a blockade radius (C6/Ω)1/6 ≈ 8.4 µm at full drive, and a program of ~half the driven T2, ~10 Rabi periods S. Named error terms: laser amplitude and phase noise; thermal motion (Doppler, 0.200 µm position spread); scattering via the intermediate state, which continues with the drive off; detuning inhomogeneity, 0.37 rad/µs RMS across the field and 0.18 rad/µs shot-to-shot C[262]. Via r⁻⁶ the position spread gives ~30% shot-to-shot spread of a 5.5 µm bond (δV/V = 6δr/r) S — harmless deep in blockade, decisive where V ≈ Ω, which selects the ordered phase. Local detuning is a fixed pattern with a waveform ≤0, and programs using it decohere faster than the listed T2 C[429]. Errors integrate coherently over a run with no point to measure a syndrome, so no code acts S; erasure detection on Sr raised a Bell-pair fidelity bound from ≥0.9971 to ≥0.9985 by discarding flagged shots D[143] — post-selection, not correction.
Interaction time, not atom number, caps analog Rydberg programs at a few microseconds. Two laser-trapped circular Rydberg atoms (long-lived states of maximal angular momentum) at Laboratoire Kastler Brossel, Paris, sustained spin exchange for more than 60 µs and 40 oscillation periods, with a decay time of 59 µs, about ten times the previous record; the oscillation contrast is post-selected (79% against 33% raw) P[899].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2017-11 | 51 atoms, 1D; Z₂ order, oscillations after quench | Harvard/MIT | D[384] |
| 2021-07 | 64–256 atoms, 2D; (2+1)D Ising transition | Harvard/MIT | D[432] |
| 2021-07 | Up to 196 atoms, square and triangular antiferromagnets | Institut d'Optique | D[433] |
| 2021-12 | 219 atoms on kagome links; topological spin liquid | Harvard/MIT | D[434] |
| 2022-06 | Up to 289 atoms; MIS, superlinear speed-up vs SA | Harvard-led | D[435] |
| 2024 | 60 Sr atoms; Fd = 0.095(11) at saturated entanglement | Caltech | D[436] |
| 2025-06-04 | (2+1)D string breaking on Aquila | QuEra et al. | D[226] |
Above ~100 atoms nothing is checked exactly: the 196-atom work matched numerics only to ~100 D[433]. The 2022 speed-up did not survive: classical solvers reach optimality on the same Union-Jack-like instances to thousands of nodes within minutes D[431]. Pasqal offers a 100-qubit analogue QPU on Google Cloud (2025-05-13) C[437]; no Fresnel datasheet like Aquila's was found as of 2026-09-26.
Manufacturing, materials & supply chain
No wafer; optical assembly shared with the digital atom architectures. Orion Gamma: 140 qubits, room temperature, 3 kW average, 5 µm minimum spacing C[438]. The analogue-specific addition is a site-resolved detuning field whose hardware QuEra has not described C[439]; nothing else in the sources separates the analogue bill of materials from the digital one S.
Control, readout & I/O burden
Control is independent of N: a few waveforms, one pattern and a geometry C[262]. The cost moves to readout and repetition. Aquila misreads 8% of Rydberg and 1% of ground atoms and leaves 0.7% of sites empty C[262], so a 256-site snapshot, half excited, reads error-free with probability 0.92¹²⁸×0.99¹²⁸ ≈ 6×10⁻⁶, and ~17% of shots have a defect-free register S. Shots run below 10 Hz on Aquila C[262] and at ≥0.25 Hz effective on Orion Gamma C[438]: 10⁴ shots take ≥17 min to ~11 h S.
Role in the stack
Slot 3 of the "Neutral-atom analogue simulator (Rydberg arrays, lattice gases)" architecture (alkali atom → ground–Rydberg analogue qubit → this technology → AOD transport → laser + AOD/SLM control → fluorescence imaging; layers 7–9 empty; optical assembly), serving G1. It requires the alkali atom, the ground–Rydberg encoding and global Rydberg lasers; it provides nothing upward; it replaces nothing and is replaced by g_ryd when a machine turns digital. Register: Aquila (QuEra, 256 sites) and Fresnel/Fresnel 2 (Pasqal, 100 qubits) carry it as primary, both ✅; Pasqal's Orion line carries it as alternate on the "Rydberg tweezer array — alkali (Rb/Cs)" architecture, 🔎. The gap ledger proposed the alkali and alkaline-earth(-like) array architectures; the technology got its own architecture, and no alkaline-earth(-like) register machine runs it, though the fidelity benchmark above used Sr D[436] — the requires-alkali edge is narrower than the physics.
Evidence — how the numbers were measured
With no gate error, fidelity comes from observables: order parameters against numerics, valid to ~100 atoms D[433]; Fd, which weights measured bit-strings by simulated probabilities — 0.095(11) at 60 atoms, where a lightcone MPS at χ* = 3400 (~110 GB, ~180 core-days) keeps pace D[436]; and problem output such as MIS size, cheap to validate but not to prove optimal D[431]. Fd needs classical probabilities, so what it certifies can be simulated. Λ is undefined. The Orion cell stays 🔎: its cited page (2026-01-29) mentions local detuning for materials simulation and a 2026 Vela with over 256 qubits, but not analogue mode, MIS, Orion or ≤100 qubits C[390].
Aquila's continued Braket service is inferred from QuEra's 2026-06-15 release, which does not state it. Not published: the hardware mechanism of Aquila's local detuning (light-shift beam or otherwise), whose magnitude, resolution and per-site calibration error appear only as Braket SDK device properties; a Rydberg lifetime or atom-loss rate during evolution for Aquila; and a Fresnel datasheet (Ω, Δ, T2, detection errors).
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| QuEra Computing | developer | US | Aquila, 256 sites, on Braket since 2022 | C[162] |
| Pasqal | developer | FR | 100-qubit analogue QPU; analogue mode on Orion | C[437] |
| Amazon Web Services | cloud channel | US | Aquila local detuning by request, 2024-04-11 | C[440] |
| Harvard/MIT | research | US | 51- to 289-atom experiments | D[435] |
| Caltech | research | US | Fd benchmark, 60 Sr atoms | D[436] |
Money.
- 2025-09-09 · QuEra · Series B extended, NVentures joins · USD 230 M · announced; aimed at fault tolerance C[153]
- 2026-08-28 · Pasqal · SPAC merger, Nasdaq PSQL · ~USD 360 M cash · closed P[156]
Market & supply chain. Two vendors, two cloud channels. Pasqal reports seven QPUs deployed and markets its platform as analogue today P[156]; QuEra's analogue offer is one machine. It pays into G1 only.
IP & standards. No analogue-specific patent count as of 2026-09-26; the program format is cloud-defined (Braket AHS) C[429]; no standards body.
Roadmaps & track record. Pasqal promised 10,000 physical qubits for 2026 (2024-03-13) R[167]; its 2026 launch is Vela, over 256 qubits R[390] — ~39× short S — and its brochure says delivery 2027, 200+ C[438]. QuEra's Libra (2028) is digital, with no analogue specification R[162].
Strategic reading. Analogue is both vendors' revenue bridge while g_ryd matures. With certified advantage above ~100 atoms it stays a G1 instrument; without, it becomes a mode of digital machines, as on Orion.
Outlook & open questions
Confirm if, by 2027-12-31, a commercial analogue machine publishes a many-body fidelity at ≥60 atoms, or an analogue result survives a year of classical challenge; demote if Vela and QuEra's next systems ship without analogue specifications. Open questions. (1) Can Fd certify beyond the size where MPS keeps pace? (2) What are per-site local-detuning calibration errors? (3) How does driven-T2 loss split between phase noise, Doppler and scattering? (4) Can erasure excision post-select many-body runs at tolerable shot cost? (5) Will the requires-alkali edge survive alkaline-earth(-like) analogue machines?
A benchmark that needs no per-atom addressing has been proposed for it: prepare U†AU with a global y-rotation A and probe with a collective z-rotation; the quantum Fisher information (how sharply the output responds to the probe angle) grows with the number of atoms for Haar-random-like dynamics and is exactly zero for Clifford circuits, so circuit randomness can be graded without computing ideal output probabilities, provided the evolution can also be run backwards (U†) P[892]. It is a theory proposal, not yet run on an analog array.
References
- [143] P. Scholl, A. L. Shaw, R. B.-S. Tsai, R. Finkelstein, J. Choi, and M. Endres, “Erasure conversion in a high-fidelity Rydberg quantum simulator,” Nature, vol. 622, p. 273, 2023, doi: 10.1038/s41586-023-06516-4. arXiv:2305.03406. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [167] J. Russell, “PASQAL Issues Roadmap to 10,000 Qubits in 2026 and Fault Tolerance in 2028,” HPCwire, Mar. 13, 2024. [Online]. Available: https://www.hpcwire.com/
2024/ R03/ 13/ pasqal-issues-roadmap-to-10000-qubits-in-2026-and-fault-tolerance-in-2028/ - [226] D. González-Cuadra et al., “Observation of string breaking on a (2 + 1)D Rydberg quantum simulator,” Nature, vol. 642, no. 8067, pp. 321–326, Jun. 2025, doi: 10.1038/s41586-025-09051-6. D
- [262] J. Wurtz et al., “Aquila: QuEra's 256-qubit neutral-atom quantum computer,” arXiv:2306.11727, Jun. 2023. C
- [384] H. Bernien et al., “Probing many-body dynamics on a 51-atom quantum simulator,” Nature, vol. 551, pp. 579–584, Nov. 2017, doi: 10.1038/nature24622. arXiv:1707.04344. D
- [385] L. Henriet et al., “Quantum computing with neutral atoms,” Quantum, vol. 4, Art. no. 327, Sep. 2020, doi: 10.22331/q-2020-09-21-327. arXiv:2006.12326. D
- [390] L. Garbini, “Inside Pasqal's 2026 Vision on Quantum for Industry and Research,” Pasqal, Jan. 29, 2026. [Online]. Available: https://www.pasqal.com/
blog/ Cinside-pasqals-2026-vision-on-quantum-for-industry-and-research/ - [429] Amazon Web Services, “Explore Experimental Capabilities - Amazon Braket,” Amazon Braket Developer Guide. [Online]. Available: https://docs.aws.amazon.com/
braket/ Clatest/ developerguide/ braket-access-local-detuning.html - [430] P. I. Bunyk et al., “Architectural considerations in the design of a superconducting quantum annealing processor,” arXiv:1401.5504, Jan. 2014. D
- [431] R. S. Andrist et al., “Hardness of the Maximum Independent Set Problem on Unit-Disk Graphs and Prospects for Quantum Speedups,” Phys. Rev. Research, vol. 5, no. 4, Art. no. 043277, 2023, doi: 10.1103/PhysRevResearch.5.043277. arXiv:2307.09442. D
- [432] S. Ebadi et al., “Quantum Phases of Matter on a 256-Atom Programmable Quantum Simulator,” Nature, vol. 595, p. 227, Jul. 2021, doi: 10.1038/s41586-021-03582-4. arXiv:2012.12281. D
- [433] P. Scholl et al., “Programmable quantum simulation of 2D antiferromagnets with hundreds of Rydberg atoms,” Nature, vol. 595, p. 233, Jul. 2021, doi: 10.1038/s41586-021-03585-1. arXiv:2012.12268. D
- [434] G. Semeghini et al., “Probing Topological Spin Liquids on a Programmable Quantum Simulator,” Science, vol. 374, p. 1242, Dec. 2021, doi: 10.1126/science.abi8794. arXiv:2104.04119. D
- [435] S. Ebadi et al., “Quantum Optimization of Maximum Independent Set using Rydberg Atom Arrays,” Science, vol. 376, p. 1209, Jun. 2022, doi: 10.1126/science.abo6587. arXiv:2202.09372. D
- [436] A. L. Shaw et al., “Benchmarking highly entangled states on a 60-atom analog quantum simulator,” Nature, vol. 628, pp. 71–77, 2024, doi: 10.1038/s41586-024-07173-x. arXiv:2308.07914. D
- [437] Pasqal, “Pasqal's Neutral-Atom Quantum Computer Available on Google Cloud Marketplace,” May 13, 2025. [Online]. Available: https://www.pasqal.com/
newsroom/ Cpasqals-neutral-atom-quantum-computer-available-on-google-cloud-marketplace/ - [438] Pasqal and O. Q.-C. P. brochure, “The Power of Neutral Atom Quantum Processors by Pasqal — Unlock Quantum Computing for Real-World Solutions,” Pasqal, product brochure (PDF). [Online]. Available: https://www.pasqal.com/
wp-content/ Cuploads/ 2025/ 11/ 2509_Pasqal_Quantum-Computing-Processor_Brochure-RVB-V8.pdf - [439] QuEra Computing, “Local Qubit Control Brings New Capabilities to QuEra's Quantum Computer,” Apr. 17, 2024. [Online]. Available: https://www.quera.com/
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about-aws/ Cwhats-new/ 2024/ 04/ amazon-braket-experimental-capabilities-quera-device-braket-direct/ - [892] S. Cavazzoni and C. Oh, “Metrological benchmarking of random quantum circuits,” arXiv:2609.39226, Sep. 2026. P
- [899] A. Durán-Hernández et al., “Spin-exchange interactions between circular Rydberg atoms over long times,” arXiv:2609.37766, Sep. 2026. P
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הטקסט בעברית נטען…
Programmable linear-optical interferometer (no entangling primitive)
A programmable passive unitary on N optical modes — a beamsplitter/phase-shifter mesh or time-bin fibre loops — that scatters squeezed light or single photons into detectors for sampling, with no entangling gate and no feed-forward.
Verdict. A working sampler, not a gate: 8,176 modes and up to 3,050 detected photons (Jiuzhang 4.0, 2026). Every earlier advantage claim was matched on its own benchmarks by a published classical sampler; as of 2026-09-26 none was found for Jiuzhang 4.0, and ORCA publishes no mode, loss or clock figure for PT-2.
GBS = Gaussian boson sampling; MZI = Mach–Zehnder interferometer; EOM = electro-optic modulator; PNR = photon-number-resolving; SNSPD = superconducting nanowire single-photon detector; TES = transition-edge sensor; MPS = matrix-product state (a tensor network); USTC = University of Science and Technology of China; NQCC = UK National Quantum Computing Centre; G1–G7 = the report's goal classes (G1: analogue and NISQ simulation).
Identity & lineage
A passive network maps input modes onto outputs, a†ᵢ → Σⱼ Uⱼᵢ a†ⱼ, with U an N×N unitary. Reck et al. factorised any U into N(N−1)/2 beamsplitter–phase-shifter pairs G[452]; Clements et al. halved the footprint and balanced the loss G[453]; loops reuse one interference point on every time bin G[454]. A six-mode, 15-MZI chip set 100 Haar-random unitaries at fidelity 0.999 ± 0.001 D[455]. Machines on this technology use the network only to sample — single photons after Aaronson and Arkhipov G[456], squeezed light after Hamilton et al. G[268]. Attributes: flying carrier, no gate time or determinism class, loss-dominated error, electro-optic room-temperature control, bulk or photonic-IC fabrication.
Physics & limits
Output probabilities are permanents of n×n submatrices of U; exact polynomial-time classical sampling would collapse the polynomial hierarchy, and approximate hardness rests on two conjectures G[456]. With squeezed inputs they are hafnians, also #P-hard G[268]. The mesh entangles modes when fed squeezed light D[270] but has no entangling gate on encoded qubits: linear optics without ancilla photons distinguishes Bell states with at most 50% probability G[457], and universality needs detector feed-forward G[337]. The limits are loss and distinguishability. Transmission compounds with depth: at 0.99 per MZI, a 100-mode Clements mesh passes ~0.37 S[453]. Noisy GBS is efficiently simulable once squeezing, transmission and detector quality satisfy an inequality S[269]; tensor networks are likely efficient when surviving photons scale as √N for N inputs S[458]; at fixed partial distinguishability, simulation cost grows only polynomially with photon number S[459].
Coarse-grained outputs of a linear-optical interferometer are classically reproducible. Any linear statistic of the output — an integer-weighted sum of the photon counts per mode, which covers mode binning, molecular vibronic spectra and the 'most probable bin' one-way function — can be estimated classically to the same additive error as the experiment, in time polynomial in the number of modes, for single-photon and Gaussian inputs P[889]. An advantage or application claim for this mechanism must rest on fine-grained sampling or on a non-linear statistic; hash-function and proof-of-work variants remain open.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2015-05 | Six-mode universal chip, fidelity 0.999 ± 0.001 | Carolan et al. | D[455] |
| 2020-12 | 50 squeezed states, 100 modes, up to 76 clicks | USTC, Jiuzhang 1.0 | D[460] |
| 2021-09 | Workstation samplers beat Jiuzhang 1.0/2.0 on marginal distances | Google Quantum AI | S[461] |
| 2022-06-01 | 216 time-bin modes, three loops, up to 219 photons, ~33% transmittance | Xanadu, Borealis | D[270] |
| 2023-10-10 | Up to 255 clicks; 1.27 µs per sample vs ~600 years on Frontier | USTC, Jiuzhang 3.0 | D[462] |
| 2024-06-25 | MPS sampler beats Jiuzhang 2.0/3.0 and Borealis on correlations; 288 GPUs, ~72 min for 10⁷ samples | Univ. of Chicago / Argonne | S[463] |
| 2026-05-13 | 1,024 squeezed states, 8,176 modes, up to 3,050 photons, 25.6 µs per sample | USTC, Jiuzhang 4.0 | D[175] |
Jiuzhang 4.0 answers the MPS attack with efficiency — 92% at the source, 51% end to end — which by the authors' estimate needs bond dimension above 8×10²¹, over 10⁴² years on El Capitan S[175]; validation is on subsystems, with a margin growing with size, not at full scale D[175].
Manufacturing, materials & supply chain
Borealis is fibre and bulk optics: three delays with EOM-driven variable beamsplitters from QUBIG GmbH, 16 TES detectors at 95% behind a 1-to-16 demultiplexer D[270]. Jiuzhang 4.0 cascades three 16-mode interferometers through two delay-loop arrays onto 16 SNSPDs at 93% D[175]. ORCA builds rack-mounted room-temperature systems from telecom-grade fibre components C[464]. Only detectors are cryogenic. No per-element loss of a fielded sampling mesh is published as of 2026-09-26; the 99.8% transmission and >40 dB extinction quoted for Jiuzhang 4.0 belong to its squeezed-light filter D[175].
Control, readout & I/O burden
Borealis sets every loop beamsplitter per 167 ns time bin and samples at 10 kHz between loop stabilisations D[270]. Jiuzhang 4.0 tunes its meshes thermally and loop phases with piezo stretchers; no per-bin electro-optic setting is reported D[175], so the technology's electro-optic attribute fits Borealis best. Readout is terminal; nothing is fed forward. Time multiplexing decouples detectors from modes: 16 detectors read 216 or 8,176 modes D[175], [270]. The heavy I/O is classical: checking a sample exactly means computing hafnians G[268].
Role in the stack
The gate slot of the Boson sampler architecture (ph_sampler, goal G1). It requires photon (single photons or squeezed light in the mesh) and ct_eo (phase shifters and switches); it provides no edge — its output is a sample; it replaces nothing, and g_fusion replaces it (fusion vs sampling interferometer): the same optics become a gate only when heralded Bell outcomes (g_fusion) or homodyne results (g_cv) are fed forward. This answers gap G-lointer — samplers had a gate layer with nothing gate-like in it — with an architecture of their own rather than the proposed technology on ph_cv and ph_fusion. Register machines, all primary: Borealis (Xanadu, deployed 2022-06), Jiuzhang 4.0 (USTC, demonstrated 2026-05-13), PT-2 (ORCA, deployed 2024–2026). The clock is a sample period: 36 µs (Borealis), 25.6 µs (Jiuzhang 4.0) D[175], [270].
Evidence — how the numbers were measured
No gate exists to benchmark; samples are compared with the ideal distribution, and the benchmarks used — low-order correlations, marginal distances — were matched or beaten classically S[461], [463]. The Borealis ✅ and Jiuzhang 4.0 ✅ cells hold against their papers, the latter with the filter correction above. PT-2 stays 🔎: its evidence page gives no architecture C[465]. The one description found is third-party — fibre delay loops with variable beamsplitters, capable of two loops where that paper puts the classically hard regime at three, sampling photon-subtracted squeezed states with a PNR detector P[271] — not the single photons the register records. An ORCA co-authored PT-1 study used one delay line D[466].
ORCA's release of 2025-06-11 names the NQCC system only as "PT Series"; the PT-2 page lists the NQCC testbed as a 2025 deployment. No classical rebuttal of Jiuzhang 4.0 has appeared as of 2026-09-26. Not published: the PT-2 input state in any ORCA primary source.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| USTC | developer | CN | Jiuzhang series; 4.0 joins 16-mode meshes with delay-loop arrays, SNSPD readout | D[175] |
| Xanadu | developer | CA | Borealis: three EOM-programmed fibre loops | D[270] |
| ORCA Computing | developer | UK | PT-series time-bin loop samplers, rack-mounted | C[465] |
| QUBIG GmbH | supplier | DE | EOMs in the Borealis loops | D[270] |
| Google Quantum AI; Univ. of Chicago / Argonne | classical challengers | US | Marginal-matching and MPS samplers | S[461], [463] |
Money.
- 2024-02-05 · NQCC · £30 M testbed competition, ORCA one of seven winners · per-company value undisclosed · awarded G[467]
- 2024-06-05 · Montana State University · two PT-1 systems, US Air Force-funded · undisclosed · contracted C[468]
- 2025-06-11 · ORCA · NQCC testbed installed under the UK's £121 M initiative · undisclosed · delivered C[469]
Market & supply chain. Of the register's seven machines only ORCA's PT-1 and PT-2 are sold as systems; USTC is academic, and the register marks Borealis superseded by Aurora. ORCA does not publicise most of its fundraising P[470].
IP & standards. No sampler-specific patent count or benchmark standard found as of 2026-09-26.
Roadmaps & track record. NQCC testbeds were due by March 2025 G[467]; ORCA announced its installation on 2025-06-11, a quarter later C[469]. PT-3 is "due for release later in 2026" with three switchable modules, claimed to beat classical solvers on up to 25,000-variable problems R[470].
Strategic reading. A contest between loss and classical simulation, not a route to computation; what lasts are the loops, squeezers and number-resolving detectors that fusion and CV machines also need. If PT-3 reaches the three-loop regime with published loss, ORCA holds the only commercial sampler beyond easy simulation; if not, the technology stays academic.
Outlook & open questions
Confirm if, by 2027-12-31, no classical sampler matches Jiuzhang 4.0 on its subsystem benchmarks and ORCA publishes PT-3 modes, loops and loss with a classical comparison; demote if one matches Jiuzhang 4.0 by then, or PT-3 ships in 2026 without those figures. Open questions. (1) What is the per-element loss of Jiuzhang 4.0's programmable meshes? (2) Does subsystem validation extrapolate to full scale? (3) What does PT-2 inject, and through how many loops? (4) Does any GBS application keep a speed-up at 33–51% transmission? (5) Can a loop sampler become a fusion machine by adding heralding and feed-forward?
References
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- [268] C. S. Hamilton et al., “Gaussian Boson Sampling,” Phys. Rev. Lett., vol. 119, no. 17, Art. no. 170501, Oct. 2017, doi: 10.1103/PhysRevLett.119.170501. arXiv:1612.01199. G
- [269] H. Qi, D. J. Brod, N. Quesada, and R. García-Patrón, “Regimes of Classical Simulability for Noisy Gaussian Boson Sampling,” Phys. Rev. Lett., vol. 124, no. 10, Art. no. 100502, Mar. 2020, doi: 10.1103/PhysRevLett.124.100502. arXiv:1905.12075. S
- [270] L. S. Madsen et al., “Quantum computational advantage with a programmable photonic processor,” Nature, vol. 606, no. 7912, pp. 75–81, Jun. 2022, doi: 10.1038/s41586-022-04725-x. D
- [271] J. Park, S. Stepney, and I. D'Amico, “Benchmarking the ORCA PT-2 Boson Sampler using Minimum Dominating Set Problems,” arXiv:2605.30935, May 2026. P
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- [454] K. R. Motes, A. Gilchrist, J. P. Dowling, and P. P. Rohde, “Scalable Boson Sampling with Time-Bin Encoding Using a Loop-Based Architecture,” Phys. Rev. Lett., vol. 113, no. 12, Art. no. 120501, Sep. 2014, doi: 10.1103/PhysRevLett.113.120501. arXiv:1403.4007. G
- [455] J. Carolan et al., “Universal Linear Optics,” arXiv:1505.01182, May 2015. D
- [456] S. Aaronson and A. Arkhipov, “The Computational Complexity of Linear Optics,” Theory of Computing, vol. 9, pp. 143–252, 2013, doi: 10.4086/toc.2013.v009a004. arXiv:1011.3245. G
- [457] J. Calsamiglia and N. Lütkenhaus, “Maximum efficiency of a linear-optical Bell-state analyzer,” Appl. Phys. B, vol. 72, no. 1, pp. 67–71, Jan. 2001, doi: 10.1007/s003400000484. arXiv:quant-ph/0007058. G
- [458] M. Liu, C. Oh, J. Liu, L. Jiang, and Y. Alexeev, “Simulating lossy Gaussian boson sampling with matrix-product operators,” Phys. Rev. A, vol. 108, no. 5, Art. no. 052604, Nov. 2023, doi: 10.1103/PhysRevA.108.052604. arXiv:2301.12814. S
- [459] J. J. Renema et al., “Efficient Classical Algorithm for Boson Sampling with Partially Distinguishable Photons,” Phys. Rev. Lett., vol. 120, no. 22, Art. no. 220502, May 2018, doi: 10.1103/PhysRevLett.120.220502. arXiv:1707.02793. S
- [460] H.-S. Zhong et al., “Quantum computational advantage using photons,” Science, vol. 370, no. 6523, pp. 1460–1463, Dec. 2020, doi: 10.1126/science.abe8770. arXiv:2012.01625. D
- [461] B. Villalonga et al., “Efficient approximation of experimental Gaussian boson sampling,” arXiv:2109.11525, Sep. 2021. S
- [462] Y.-H. Deng et al., “Gaussian Boson Sampling with Pseudo-Photon-Number-Resolving Detectors and Quantum Computational Advantage,” Phys. Rev. Lett., vol. 131, no. 15, Art. no. 150601, Oct. 2023, doi: 10.1103/PhysRevLett.131.150601. arXiv:2304.12240. D
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- [467] National Quantum Computing Centre, “Science Minister Andrew Griffith announces the results of the £30m quantum computing testbed competition,” NQCC, Feb. 5, 2024. [Online]. Available: https://www.nqcc.ac.uk/
updates/ Gscience-minister-andrew-griffith-announces-the-results-of-the-30m-quantum-computing-testbed-competition/ - [468] ORCA Computing, “Montana State University Selects ORCA Computing to Advance Distributed Quantum Computing and Communications,” Jun. 5, 2024. [Online]. Available: https://orcacomputing.com/
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p/ Rorca-aims-to-beat-classical-computers - [889] B. Seron, H. Thomas, E. Araujo, A. Arkhipov, C. Oh, and L. Novo, “Efficient classical algorithm for estimating linear statistics of Boson Sampling,” arXiv:2609.35447, Sep. 2026. P
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הטקסט בעברית נטען…
Quantum annealing (analogue evolution)
Continuous-time Hamiltonian evolution (coherent quench, 3.6–27 ns) driving Ising or Rydberg spins toward a ground state; not a discrete gate.
Verdict. No platform has an unchallenged advantage claim as of 4 Sep 2026; falsified if one survives a full classical-rebuttal round by 2028, confirmed non-advantage if erosion keeps repeating.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Continuous-time Hamiltonian evolution — sweeping a transverse field, laser detuning or blockade radius — carrying a many-body system toward a ground state with no discrete gate. Kadowaki–Nishimori (1998) and Farhi et al. (2000) gave it its form; D-Wave commercialised it from 2011, and Rydberg arrays run it with optics instead of flux.
Fabricated carriers; ~4 ns characteristic quench, no deterministic entangling operation; no readout of its own — a mechanism, not a qubit.
Long-range interaction; low-frequency or optical control at mK or in vacuum; coherent plus Pauli error; superconducting lithography or tweezer optics.
Physics & limits
Two clocks bound the schedule. From below, control bandwidth — DAC slew for flux, AOM switching for Rydberg: D-Wave's fastest coherent quenches run 3.6–27 ns across 1,222–5,627 qubits D[221]. From above, decoherence. Between them sits the adiabatic condition, which for hard instances demands time scaling inversely with the square of a gap that itself closes exponentially — so the useful regime is a fast diabatic quench whose output is a sample, not a certified minimum. Rydberg adds spontaneous emission, flux adds 1/f noise. The floor moves not with faster electronics but with a way to certify the sample.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-03 | Coherent quench 3.6–27 ns, up to 5,627 qubits; beyond-classical claim | D-Wave | D[221] |
| 2025–26 | Claim eroded by tensor networks and t-VMC | Tindall; Mauron & Carleo | D[222], [223] |
| 2025 | 69-qubit analogue-digital simulator, beyond-classical on XEB only | D[225] | |
| 2025 | Aquila, 256 atoms, analogue Rydberg evolution: gauge-theory string breaking, no claim | QuEra | D[226] |
Dominant limitation: no accepted certificate that analogue output matches the Hamiltonian.
QuEra's cumulative funding (">$250 M") and its fuller investor list (Valor Equity, Rakuten, Commonwealth of Massachusetts) appear only in secondary reporting; the primary release of 2025-09-09 names Google, SoftBank Vision Fund 2 and NVentures. Pasqal's 2025 revenue of €16.5 M is from trade press, not a filed statement. Not published: the date of Pasqal's Aeponyx acquisition, in any primary source, and a further classical test of D-Wave's "most frustrated instances" beyond Tindall and Mauron/Carleo.
Manufacturing, materials & supply chain
Two supply chains carry one mechanism: Nb/Al superconducting lithography (D-Wave) and vacuum/laser/AOM tweezer stacks (QuEra, Pasqal). The I/O burdens scale oppositely: flux annealers push everything through one mK stage on multiplexed on-chip DACs, while tweezer machines add laser power, deflectors and imaging per atom — the optical table is the constraint. Pasqal has begun displacing bulk optics with a silicon-nitride photonic IC: four traps from one chip, atom lifetime ~27.5 s Cfact. No export rule names analogue evolution: exposure is inherited from the carrier — ECCN 4A906 and 3A904 for the flux line, nothing for tweezer optics.
Role in the stack
Architecture: quantum annealer — flux qubits, where it is the only gate mechanism. The register lists 4 machines using it, among them D-Wave's Advantage2 and Advantage and Qilimanjaro's AQPU. It runs on the flux-qubit carrier only — Rydberg arrays use the separate analogue Rydberg Hamiltonian evolution — and provides nothing to a gate-model stack; the field's standard error is reading an analogue sampling claim as gate-model advantage. Quantinuum's magnetism result is quoted alongside these but is Trotterised digital simulation competing for the same budget D[227]. No derived clock applies; the figure is quench time, ~4 ns to µs, plus one measurement. Verification is comparison against classical solvers, never randomised benchmarking, and the target moves: D-Wave's March 2025 claim was eroded within weeks [222], [223], its counter arguing the tensor-network scaling used against it is unvalidated P[224]. Unresolved as of 4 Sep 2026.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| D-Wave Quantum | developer | US/Canada | Coherent-quench annealer; the disputed claim | D[221] |
| QuEra Computing | developer | US | Aquila Rydberg on Braket (analogue Rydberg evolution, not annealing); Libra 2028 | D[226] |
| Pasqal | developer | France | Analogue Rydberg arrays; Nasdaq since 2026-08 | P[156] |
| Google Quantum AI | developer | US | Analogue-digital simulator; atom track 2026-03 | fact |
Money. 2025-09-09 · QuEra · Series B expansion · $230 M+ USD · Google, SoftBank Vision Fund 2, NVentures · closed C[153]. 2026-08-28 · Pasqal · SPAC merger · ~$360 M USD cash · Nasdaq PSQL · closed P[156]. 2026-08-06 · D-Wave · H1-2026 revenue $5.9 M (−67% YoY) · reported Cfact.
Market & supply chain. Rydberg buys lasers, deflectors, vacuum and cameras from a thin supplier base; flux buys foundry runs and refrigerators. Money here is G1 instrument spend plus D-Wave's hybrid-solver G5 line; G3/G4 pay nothing.
IP & standards. No mechanism-specific patent family or standards body apart from the carrier hardware.
Roadmaps & track record. (2024-01 · for 2026 · QuEra 100 logical qubits · missed, replaced by Libra 2028 at >256 logical) R[162]; (2024 · for 2026 · Pasqal 10,000 physical · missed, restated to 2028) P[156]; (2025-05 · for 2029 · D-Wave 20,000 qubits · open) Rfact. Both atom vendors slipped a flagship target by two years; only D-Wave delivers on schedule.
Strategic reading. If one analogue claim survives a full classical round, the tweezer vendors capture the value, holding a path to digital; otherwise this is a bridge product and whoever reaches gate operation fastest wins. Laser and cryoplant suppliers keep the pricing power.
Outlook & open questions
Confirm if any platform defends an unchallenged claim through 2028; demote if erosion repeats. Best case 2029: Rydberg vendors convert analogue arrays into error-corrected digital machines. Worst case: analogue stays a physics instrument. Open: does Pasqal reach 10,000 physical by 2028; does Libra hold at >256 logical?
References
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [221] A. D. King et al., “Beyond-classical computation in quantum simulation,” Science, vol. 388, pp. 199–204, 2025, doi: 10.1126/science.ado6285. arXiv:2403.00910. D
- [222] J. Tindall, A. Mello, M. Fishman, M. Stoudenmire, and D. Sels, “Dynamics of disordered quantum systems with two- and three-dimensional tensor networks,” Science, vol. 392, pp. 868–872, 2026, doi: 10.1126/science.adx2728. arXiv:2503.05693. D
- [223] L. Mauron and G. Carleo, “Challenging the Quantum Advantage Frontier with Large-Scale Classical Simulations of Annealing Dynamics,” arXiv:2503.08247, Mar. 2025. D
- [224] A. Nocera, J. Raymond, W. Bernoudy, M. H. Amin, and A. D. King, “Evaluating classical simulations with a quantum processor,” arXiv:2508.15759, Aug. 2025. P
- [225] T. I. Andersen et al., “Thermalization and criticality on an analogue–digital quantum simulator,” Nature, vol. 638, no. 8049, pp. 79–85, Feb. 2025, doi: 10.1038/s41586-024-08460-3. D
- [226] D. González-Cuadra et al., “Observation of string breaking on a (2 + 1)D Rydberg quantum simulator,” Nature, vol. 642, no. 8067, pp. 321–326, Jun. 2025, doi: 10.1038/s41586-025-09051-6. D
- [227] R. Haghshenas et al., “Digital quantum magnetism on a trapped-ion quantum computer,” Nature, vol. 653, pp. 56–62, 2026, doi: 10.1038/s41586-026-10445-3. arXiv:2503.20870. D
Русский текст загружается…
הטקסט בעברית נטען…
Cross-resonance (fixed-frequency, all-microwave)
All-microwave entangling gate driving one fixed-frequency transmon at its neighbour's frequency through a static bus; no flux line, no tunable coupler.
Verdict. Superseded on IBM's own fleet at Heron (2023-12) yet still the only two-qubit gate needing zero coupler control; it returns only if post-fabrication frequency trimming beats a flux DAC per coupler on cost.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Driving a control transmon at its neighbour's frequency through a fixed bus produces a ZX interaction (Z on the control, X on the target); Chow, Córcoles, Gambetta et al. (IBM), 2011 D[425]. Kandala et al. reached CNOT 99.77(2)% in a single 180 ns pulse in 2021 by suppressing the static ZZ intrinsically, two fixed-frequency coupling elements retuning the dressed levels rather than extra cancellation drives D[287].
Attributes: fabricated carrier, static connectivity, microwave control at room temperature; deterministic entangling at 10^-6.5 s (~320 ns typical, 180 ns best).
Coherent plus Pauli error; standard superconducting lithography, no added process.
Physics & limits
The ZX rate is second order, ∝ JΩ/(Δ(Δ+α)), fastest in the straddling regime −α < Δ < 0, so the detuning must sit inside a band of order the anharmonicity, ~300 MHz. The static ZZ, ∝ 2J²α/(Δ(Δ+α)), never switches off, so coherent error dominates the budget. The floor is not one pair but frequency targeting: every neighbour adds a collision constraint inside that band, and junction spread as fabricated is of order a per cent, so collision-free yield collapses with lattice size. What moves the floor is post-fabrication trimming — annealing junctions to target, 97.4% success D[294] — not better pulses.
Engineering state of the art
table
No fleet-average cross-resonance (CR) number was ever published; IBM's EPLG today (3.7×10⁻³ D[34]) is Heron hardware, which replaced CR in 2023-12 C[72]. The painful reference is Oxford/OQC's fixed-coupling CZ, 99.8% in 25 ns C[423] — no coupler control either, seven times faster.
The PRL by Kandala et al. reports intrinsic ZZ suppression through two fixed-frequency coupling elements, not active cancellation. Not published: a fleet-average CR fidelity for IBM's pre-Heron generations (Falcon to Condor), beside the isolated-pair 99.77(2)%, and a dated CR-specific patent count.
Manufacturing, materials & supply chain
No process of its own. The cost lands in binning and trimming: a collision cannot be detuned away after fabrication, only masked in software or annealed out, so frequency targeting — laser annealing at IBM, alternating-bias annealing at Rigetti D[294] — is the supply-chain item CR drives. Its advantage is the I/O ledger: one drive line per qubit and nothing per coupler, where tunable couplers add a flux line and a DAC channel each, roughly 1.5–2× the lines. At 10³ that is a crowded fridge against an impossible one; at 10⁴–10⁶ it is the whole wiring budget. Export exposure is the carrier's (ECCN 3A901).
Role in the stack
The fixed-frequency branch of the transmon-lattice architecture — IBM Falcon through Condor, 2019–2023 C[72], and Lawrence Berkeley National Laboratory's Advanced Quantum Testbed (AQT) to date — providing entanglement with no coupler control; its alternative is the tunable coupler, and switching is a chip redesign, not firmware. On the derived clock it loses: 180–500 ns against ~50 ns for a tunable-coupler CZ, so every QEC cycle pays 3–7× on the gate layer. Verification: 99.77% is interleaved RB on an isolated pair, blind to spectators; CR error is coherent, so RB understates it and gate-set tomography is the honest measurement.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| IBM | developer (ex-user) | US | Invented and scaled CR to Condor; retired it at Heron | D[287] |
| Hanyang University | research | KR | Fixed-frequency lattice-patch design reviving CR | S[426] |
| OQC | developer | UK | Fixed-frequency coaxmons with a fixed-coupling CZ, not CR | C[423] |
Money.
2026-06-02 · IBM · investment commitment · > $10 B over five years · announced G[57]fact
2026-06-03 · OQC · Series C · £260 M · Bullhound lead · closed C[60]fact
No funding event or QBI stage names cross-resonance.
Market & supply chain. No incremental supplier: the same lithography, cryostat and coax chain, minus per-coupler flux electronics. It paid for G1 and early G2 only.
IP & standards. IBM holds the foundational family (Chow 2011, Kandala 2021); no dated CR-specific patent count was found as of 2026-09-04. Qiskit still ships CR as a native two-qubit template.
Roadmaps & track record. IBM (2022-05-10 · no long-term CR commitment · retired on schedule at Heron, 2023-12 fact). Hanyang (2026-06-25 · simulation only · nothing fabricated). IBM's record is good precisely because it dropped CR when yield turned.
Strategic reading. Nobody wins from CR's supersession except tunable-coupler and cryogenic-control vendors. Its residual value is cheap wiring: if annealing reaches near-unity frequency-targeting yield, a fixed-frequency chiplet undercuts a tunable-coupler chip on cost. Power now sits with the control-electronics vendors — what CR was designed to avoid.
Outlook & open questions
Confirm by 2028: a fabricated fixed-frequency processor above eight qubits with CR fidelity published under simultaneous operation, or the Hanyang patch measured above 98%; else demote to legacy. Best case 2029: a cheap fixed-frequency chiplet; worst case, CR survives only as a Qiskit compilation target. Does anyone outside IBM run CR in production? Does frequency targeting reach collision-free yield past ~100 qubits? Would a foundry pick CR on cost rather than physics?
References
- [34] IBM Quantum, “What's new at IBM Quantum - Q2 2026.” [Online]. Available: https://www.ibm.com/
quantum/ Dblog/ whats-new-q2-2026 - [57] IBM Quantum, “Why IBM is investing $10 billion into quantum computing,” Jun. 2, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Gblog/ 10-billion-investment-faq - [60] A. Curbison, “OQC raises £260m in Europe's largest ever private quantum computing funding round,” OQC, Jun. 2, 2026. [Online]. Available: https://oqc.tech/
company/ Cnewsroom/ series-c - [72] IBM, “Quantum Roadmap.” [Online]. Available: https://www.ibm.com/
roadmaps/ Cquantum/ - [287] A. Kandala et al., “Demonstration of a High-Fidelity CNOT Gate for Fixed-Frequency Transmons with Engineered ZZ Suppression,” Phys. Rev. Lett., vol. 127, no. 13, Art. no. 130501, Sep. 2021, doi: 10.1103/PhysRevLett.127.130501. D
- [294] D. P. Pappas et al., “Alternating-bias assisted annealing of amorphous oxide tunnel junctions,” Communications Materials, vol. 5, no. 1, Art. no. 150, Aug. 2024, doi: 10.1038/s43246-024-00596-z. D
- [423] A. Curbison, “Oxford research group demonstrate fundamental speed-up of two-qubit gate,” OQC, Mar. 21, 2025. [Online]. Available: https://oqc.tech/
company/ Cnewsroom/ oxford-research-group-demonstrate-fundamental-speed-up-of-two-qubit-gate - [425] J. M. Chow et al., “Simple All-Microwave Entangling Gate for Fixed-Frequency Superconducting Qubits,” Phys. Rev. Lett., vol. 107, no. 8, Art. no. 080502, Aug. 2011, doi: 10.1103/PhysRevLett.107.080502. D
- [426] C. Kim, J. Kang, and Y. Kwon, “Lattice patch structure for fixed-frequency transmon quantum computer with high-fidelity CNOT gates,” arXiv:2606.27017, Jun. 2026. S
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הטקסט בעברית נטען…
CV Gaussian gates + GKP-assisted non-Gaussian operations
Beamsplitters, squeezers and homodyne feed-forward on optical modes, with GKP grid states supplying the non-Gaussian resource fault tolerance requires.
Verdict. On-chip GKP effective squeezing is 0.62 dB against the ~10 dB the architecture needs — an ~8.7× grid-noise-variance gap. If Xanadu's 2028–29 fault-tolerance milestone slips, this is the slowest photonic track.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Gates act on optical quadratures — beamsplitters, phase shifts, squeezers — closed by homodyne feed-forward. Gaussian operations with homodyne detection are classically simulable, so universality needs a non-Gaussian resource: the Gottesman–Kitaev–Preskill grid state, 2001 S[413]. Time-domain multiplexing predates the companies — the University of Tokyo entangled over 10,000 modes in 2013 D[821]; Xanadu added the modular chip version D[173] and the first integrated GKP source D[174]. Attributes: flying carrier, partly fabricated, ~1 µs deterministic step, Gaussian-noise and loss-dominated error; electro-optic control at room temperature, photonic-IC fabrication.
Physics & limits
Loss acts as a Gaussian random-displacement channel on the grid, blurring the GKP peaks until modular-quadrature measurement cannot resolve the logical value; the floor is effective squeezing, not gate count. Xanadu's on-chip source reports 0.62 dB D[174] — grid-noise variance ~0.87 of vacuum against ~0.10 at the ~10 dB assumed, an ~8.7× reduction still to find S, a different quantity from Xanadu's 24.1× loss factor above threshold C[178]. Only lower per-element loss, better sources and deeper multiplexing move it. Feed-forward adds a second floor: electronics must act inside the ~1 µs clock, and the published CV loop is 196 ns P[822].
Engineering state of the art
table
No GKP logical qubit exists; Aurora ran two hours without error correction and reported no logical fidelity, so it shows stability, not computation D[173].
The date, platform and room-temperature operation of the 0.62 dB GKP result come from the publisher's press coverage [642], and no independent group has replicated it. Published GKP threshold estimates vary with decoder and architecture, so the ~10 dB figure is not a single authoritative value. The 0.87→0.10 variance conversion is derived, not quoted. Xanadu's 24.1× loss factor and the 0.62 dB effective squeezing are different quantities that no source reconciles.
Manufacturing, materials & supply chain
Fabrication is silicon-nitride lithography on 300 mm-class wafers, shared with the discrete-variable sector; the CV-specific additions are squeezers and high-efficiency homodyne receivers rather than switches, and the GKP source runs at room temperature D[174]. Packaging is Corning fibre arrays and DISCO singulation C[172]. Control is the heavy part: every mode needs a homodyne receiver, an ADC and a loop closing inside the clock, scaling linearly with no published shortcut. At 10³ modes that is a rack of receivers, at 10⁴ the analogue front end dominates, and nothing addresses 10⁶. ECCN 4A906 applies to the machine fact.
Role in the stack
The continuous-variable architecture's gate layer, requiring squeezed sources and room-temperature feed-forward. It substitutes for rather than complements discrete-variable fusion: CV measures quadratures where fusion detects single photons, so switching architectures replaces sources, detectors and decoders together. Derived clock 1.0 MHz D[173]. Verification is thin: the 0.62 dB is single-group, unreplicated, and routinely confused with raw quadrature squeezing — the 1.4 dB in periodically poled TFLN P[345] is a different quantity.
Actors & economics
Who.
Money.
2025-11-06 · Xanadu · DARPA QBI Stage B selection · up to USD 15 M · DARPA · announced fact
2026-03-26 · Xanadu · SPAC merger with Crane Harbor · ~USD 302 M gross, ~40% below plan · closed Cfact
2026-08-28 · Xanadu · Toronto factory funding · CAD 195 M · Government of Canada · announced C[178]
2026-08-31 · Xanadu · liquidity · ~USD 686 M at 2026-06-30 · reported Cfact
Market & supply chain. One commercial actor, so no market — only Xanadu's supply relationships and the packaging concentration it shares with photonics generally. CV pays for G1 today; G3/G4 only if squeezing closes, G6 the natural adjacency.
IP & standards. No dated CV/GKP patent count from a named database as of 2026-09-04; Strawberry Fields/Blackbird is the only CV-native open-source stack, used by no other vendor.
Roadmaps & track record. The 2026-08-31 release is Xanadu's first quantified schedule (promised 2026-08: fault tolerance 2028–29, 200 logical qubits 2029, 1,000+ by 2031) — too new to score C[178]; against it stands one miss, the SPAC closing ~40% below plan Cfact. Its physics claims are self-critical; its financing claims are not.
Strategic reading. If effective squeezing improves an order of magnitude, CV's flying room-temperature carrier is the natural networking substrate and G6 is Xanadu's to lose. If not, no second actor exists to inherit the track, and its suppliers are worth more than its architecture.
Outlook & open questions
Confirm by 2027: effective squeezing above 3 dB on chip; demote the 2028–29 milestone if it stays below 1 dB. Best case 2029: a small GKP logical qubit at low distance. Worst case: uncorrected demonstrations continue and the schedule slips as the financing did. Open: how much of the gap is loss versus fabrication; do homodyne front-ends scale.
References
- [172] Xanadu, “Xanadu sets new industry benchmark in photonic chip packaging,” PR Newswire, Jun. 10, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cxanadu-sets-new-industry-benchmark-in-photonic-chip-packaging-302796562.html - [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [174] M. V. Larsen et al., “Integrated photonic source of Gottesman–Kitaev–Preskill qubits,” Nature, vol. 642, no. 8068, pp. 587–591, Jun. 2025, doi: 10.1038/s41586-025-09044-5. D
- [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [345] X. Shi et al., “Squeezed Light Generation in Periodically Poled Thin-Film Lithium Niobate Waveguides,” arXiv:2508.08599, Aug. 2025. P
- [413] D. Gottesman, A. Kitaev, and J. Preskill, “Encoding a qubit in an oscillator,” Phys. Rev. A, vol. 64, no. 1, Art. no. 012310, Jun. 2001, doi: 10.1103/PhysRevA.64.012310. arXiv:quant-ph/0008040. S
- [642] Xanadu, “Xanadu Unveils 1st On-Chip Error-Resistant Photonic Qubit,” HPCwire, Jun. 5, 2025. [Online]. Available: https://www.hpcwire.com/
off-the-wire/ Pxanadu-unveils-1st-on-chip-error-resistant-photonic-qubit/ - [821] S. Yokoyama et al., “Ultra-large-scale continuous-variable cluster states multiplexed in the time domain,” Nat. Photon., vol. 7, no. 12, pp. 982–986, Dec. 2013, doi: 10.1038/nphoton.2013.287. D
- [822] D. Duggan et al., “FPGA Based Feedforward System for Photonic Quantum Computing Applications,” arXiv:2606.03500, Jun. 2026. P
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הטקסט בעברית נטען…
Microwave / optical spin gates (defect centres, 1Q spins)
Resonant microwave rotation of a defect electron spin, hyperfine-conditional rotation of its neighbouring nuclei, and optical pulses for initialisation and readout.
Verdict. Sub-0.1% single-node gate error, but the optical cycles that initialise and read the spin are also its dominant decoherence source, and no benchmark in use separates the two.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Resonant microwave drive rotates a colour centre's electron spin between ground-state sublevels — 2.87 GHz at zero field for NV, a Zeeman-split pair for the group-IV centres. Hyperfine coupling to ¹³C or ¹⁴N neighbours makes them addressable by conditional rotations — a register from one defect. Optical pulses do the initialisation and readout microwaves cannot. Coherent single-defect Rabi driving dates to 2004; the benchmark is Fujitsu/QuTech gate-set tomography below 0.1% P[208].
Attributes: engineered placement of a natural defect, static, entangling near 1 µs (electron) and milliseconds (nuclear); microwave plus optical control; Pauli and coherent error.
Physics & limits
Two rates set the architecture: megahertz electron Rabi gives gates of tens to hundreds of nanoseconds, while hyperfine-conditional nuclear gates run at kilohertz — three orders slower, so the long-lived memory is the slow one. The floor is optical duty cycle, not microwave power: every initialisation or readout pulse drives the defect through an excited state that can ionise it and shifts the local charge environment, so the error of the next gate depends on how many photons the last one scattered. Isotopic ¹²C purity lengthens T2 but does nothing about that; only fewer optical cycles per operation move the floor, which is why Delft's ~10× collection gain is a gate result as much as a link result D[359].
Engineering state of the art
table
| year | figure | who | tag+key |
|---|---|---|---|
| 2025-03-28 | NV 1Q and 2Q gate error below 0.1% by gate-set tomography | Fujitsu with QuTech | P[208] |
| 2025-11-27 | resonant photon collection ~0.05% → ~0.5%, echo coherence above 100 µs kept | QuTech | D[359] |
| 2026-05-26 | unconditional teleported CNOT between cryostats, 63(4)% | QuTech | D[360] |
Dominant term: optically induced charge instability, not microwave control.
On germanium hole spins, a geometric form of the electric-dipole spin resonance (EDSR) pulse — a non-adiabatic, three-segment loop whose rotation is set by the loop's geometry rather than by the pulse's dynamics — kept X/2 and Y/2 above 99% at ±2.5 MHz microwave detuning and the idle gate at ±1.2 MHz, peaking at 99.98% (idle), 99.80% (X/2) and 99.97% (Y/2) by gate-set tomography P[888]. The price is four to six times the duration of the ordinary gate, and which loop works best depends on the dominant noise.
The below-0.1% NV gate-set-tomography figure rests on a joint Fujitsu/QuTech press release relayed by trade press [208], with no peer-reviewed paper giving error bars or an error budget; it is tagged P here and D in the main report and the graph record. Not published: nuclear-spin gate durations alongside the NV fidelities, so the kilohertz Rabi rate is a mechanism, not a measured device figure; dates for Quantum Brilliance's named deployment sites [823] and any funding after its January 2025 Series A; and a dated roadmap with qubit counts from any defect-gate actor.
Manufacturing, materials & supply chain
The gate inherits diamond's constraints: CVD growth from Element Six, implanted defects, per-device nanophotonics. Nothing in the drive chain multiplexes: each addressed defect needs its own resonant laser line, microwave feed and detector channel, so hardware scales linearly with sites — the opposite of a shared microwave plant. Control latency is set by the link, not the gate: the teleported CNOT needed feed-forward inside the memory lifetime D[360]. At 10³ sites the wall is laser count and optical fan-out, with no published plan. No export rule names colour centres.
Role in the stack
Requires the colour-centre carrier and provides the gate the defect-node architecture uses; it is also the alternate gate on the silicon / germanium quantum-dot spin and donor-spin architectures. The register lists 5 machines using it, among them SaxonQ's QC2026 Dual Core, Quantum Brilliance's Quoll / QB-QDK 2.0 and Fujitsu's Diamond-spin quantum computer prototype. Its clock contribution never binds: ~10⁻⁷–10⁻⁶ s electron gates against ~100 µs readout and links six to nine orders slower; no code runs on the defect architecture, so sum of the syndrome round: gate layers + transport + readout + reset has no value here and the link rate is the clock. Verification: the sub-0.1% figure is one collaboration, published through a press release, and gate-set tomography as applied does not separate microwave error from optically induced charge-state error — a composite that will not transfer to another readout duty cycle. The teleported CNOT is unconditional, unlike the post-selected T-centre result at Bell 0.60(8) P[363].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuTech | developer | Netherlands | Cavity NV control, remote gate | D[359], [360] |
| Fujitsu | user | Japan | Joint NV gate programme | P[208] |
| Quantum Brilliance | developer | Australia | Room-temperature units | P[823] |
| Photonic Inc. | developer | Canada | T-centre spin control | P[363] |
| Element Six | supplier | UK | Merchant CVD diamond | P[364] |
Money. 2026-05-12 · Photonic Inc. · equity · USD 200 M at USD 2 B · Microsoft returning · closed Cfact. 2026-07 · QuantumDiamonds · EUR 91 M, EUR 76 M of it EU Chips Act · closed P[364]. 2025-01 · Quantum Brilliance · Series A · USD 20 M · ~USD 58 M cumulative · closed P[364]. No QBI stage names this gate mechanism.
Market & supply chain. One merchant diamond supplier and a thin detector base are the concentration risks; microwave hardware is shared with every modality. Pays into G6 and sensing; no G3 or G4 money reaches this gate.
IP & standards. No dated patent family from a named database as of 4 Sep 2026; no standards body covers defect-spin control.
Roadmaps & track record. Quantum Brilliance (units at three laboratories · delivered, sites undated) P[823]. SaxonQ (QC2026 Dual Core · shipped) P[364]. Photonic Inc. (fault tolerance "within five years" of 2023-11 · unmet). Credibility is inverted: the smallest actors ship, the best-funded promises.
Strategic reading. This gate wins only inside a networking or edge thesis, not the fault-tolerance budget. Suppliers hold leverage: no vendor sells an integrated defect-control stack.
Outlook & open questions
Confirm/demote (12–24 months): a peer-reviewed sub-0.1% gate-set result with an explicit charge-state error term confirms; two more years of press-release fidelities demotes it. Best case 2029: a small error-detected multi-node register. Worst case: excellent gates that never enter a code. Open: (1) can optical addressing be multiplexed; (2) does anyone report nuclear-gate times with fidelities; (3) does a defect platform reach a logical qubit.
References
- [208] M. Swayne, “Fujitsu And QuTech Realize High-Precision Quantum Gates,” The Quantum Insider, Mar. 28, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P03/ 28/ fujitsu-and-qutech-realize-high-precision-quantum-gates/ - [359] J. Fischer et al., “Spin-photon correlations from a Purcell-enhanced diamond nitrogen-vacancy center coupled to an open microcavity,” Nat. Commun., vol. 16, no. 1, Art. no. 11680, Nov. 2025, doi: 10.1038/s41467-025-66722-8. D
- [360] M. Iuliano et al., “Unconditionally teleported quantum gates between remote solid-state qubit registers,” Nat. Commun., vol. 17, no. 1, Art. no. 4694, May 2026, doi: 10.1038/s41467-026-72818-6. D
- [363] F. Afzal et al., “Distributed Quantum Computing in Silicon,” arXiv:2406.01704, Jun. 2024. P
- [364] M. U. Rehman, “Top Diamond NV-Centre Quantum Computing Companies in 2026,” The Quantum Insider, Jul. 10, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P07/ 10/ 8-quantum-computing-companies-working-with-nv-centre-in-diamond-technology/ - [823] Oak Ridge National Laboratory, “Quantum Brilliance, ORNL pioneer quantum-classical hybrid computing,” ORNL News, Sep. 2, 2025. [Online]. Available: https://www.ornl.gov/
news/ Also https://www.iaf.fraunhofer.de/quantum-brilliance-ornl-pioneer-quantum-classical-hybrid-computing en/ . Also https://quantumbrilliance.com/media-library/ press-releases/ first-room-temperature-quantum-accelerator-in-europe.html news/ . Psupercomputer-with-quantum-accelerator-pawsey-commissions-first-room-temperature-on-premises-quantum-computer-in-supercomputing-center/ - [888] Y.-C. Zhou et al., “High-fidelity geometric quantum gates exceeding 99.9% in germanium quantum dots,” arXiv:2609.33251, Sep. 2026. P
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הטקסט בעברית נטען…
Long-range on-chip couplers (c-couplers, mm-scale)
Waveguide- or resonator-extended tunable couplers that entangle fixed superconducting qubits millimetres apart, buying the degree-6 graphs that qLDPC codes need.
Verdict. One 2 mm CZ at 99.81% (IQM, 2023) and IBM's Loon components without numbers; demote if no coupler of ≥ 5 mm reports a CZ ≥ 99.5% with error bars by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A long-range on-chip coupler is a microwave element — an extended capacitor, a transmission-line section, a resonator or a chain of them, usually with a flux-tunable transmon or SQUID in the middle — that mediates an exchange or ZZ interaction between superconducting qubits that are not lattice neighbours, millimetres apart, by virtual-photon exchange through the structure's detuned mode. Yale's cavity bus of 2007-09 moved quantum information between qubits "on opposite sides of a chip" through a cavity "a few millimetres long" D[477]; MIT's giant atoms, coupled to one waveguide at several points, gave distant qubits decoherence-free exchange in 2020-07 D[478]; Caltech's metamaterial bus gave ten qubits a tunable hopping range in 2023 D[479]. The graph record dates the node to 2023, when IQM published a CZ of 99.81 ± 0.02% between transmons 1.96 mm apart through a floating transmon coupler whose two "waveguide extenders" carry both the qubit–coupler and the direct qubit–qubit coupling D[480]. IBM's "c-coupler" (2025-06 vocabulary; "l-couplers" link chips C[481]) is the same object built for a code, and Loon (2025-11) the first chip claiming a lattice of them C[49].
Attributes (legend: a = affinity natural↔fabricated; b = time, deterministic/heralded; c = readout; d = mobility; e = control @ placement; f = error structure; g = manufacturing), quoting the graph record:
- a = 1.0: a fully fabricated carrier.
- b = no characteristic time, determinism not applicable: the link sets no clock; the CZ it hosts is deterministic, 33 ns in the record device D[480].
- c = no readout function.
- d = long-range: connectivity beyond nearest neighbour without moving the qubit.
- e = no control modality at no placement: the flux line is booked under the qubits joined.
- f = coherent: residual ZZ, phase miscalibration, crosstalk.
- g = superconducting lithography.
Rank 2 of 111; shared by the superconducting and annealing architectures; it pairs a fabricated carrier with far-range mobility.
Physics & limits
At 4 GHz on silicon the guided wavelength is about 30 mm, so IQM's 2 mm extenders are electrically short capacitors; the coupler idles at 3.195 GHz below qubits at 4.10 and 3.89 GHz, with qubit–coupler couplings of 51.5 and 53.9 MHz against a direct 3.7 MHz, the net exchange being their difference D[480]. The gate is a coupler flux excursion that turns on the |11⟩↔|20⟩ interaction for 22 ns plus 11 ns idle; the separation also cuts next-nearest-neighbour coupling below 30 kHz D[480]. Beyond a few millimetres the extender's own standing-wave modes enter the qubit band (a 1 cm half-wave line resonates near 6 GHz), so the coupling must come from a hybridised resonator–transmon mode: Nanjing's 1 cm coupler measures 23.5 MHz of XX coupling and up to 100 MHz of ZZ, switchable by more than 10² and 10⁴ respectively D[482]. Links of 1 cm to 0.5 m exist only in simulation S[483]–[485].
Four floors. Loss: a coupler mode with T1 > 40 µs D[480] costs at most 33 ns/40 µs ≈ 8×10⁻⁴ per gate, ~10⁻⁵ at dispersive participation — below the record's 1.9 ± 0.2 ×10⁻³, attributed "mostly" to one qubit's T1 falling to 14 µs during the flux excursion D[480]. Crowding: each extra mode is a frequency collision, and a degree-6 vertex holds six couplers off resonance at once. Coherent error: residual ZZ under 2 kHz D[480] is 0.013 rad of conditional phase per microsecond of idling per pair, correlated rather than stochastic. Geometry: degree above four needs crossings, hence routing layers; the bivariate bicycle Tanner graph is "a degree-6 graph that consists of two edge-disjoint planar subgraphs" D[248], so two suffice topologically. The floor moves with lower-loss routing layers — Loon claims "multiple high-quality, low-loss routing layers" C[49] — and qubits whose T1 survives flux tuning.
Engineering state of the art
Best demonstrated: 99.81(2)% CZ at 1.96 mm in 33 ns (IQM, published 2023-02) D[480]. Typical at scale, as of 3 Sep 2026: none — no multi-qubit processor with mm-scale couplers has published gate fidelities; Loon shows "6-way qubit connections" without numbers C[49], [486], and IQM's resonator-hub Star devices reach "above 99.3%" on a MOVE–CZ–MOVE sequence C[487].
table
| Year | Figure | Who | Tag | Src |
|---|---|---|---|---|
| 2007-09 | Two qubits on opposite sides of a chip coupled through a few-mm cavity bus | Yale | D | [477] |
| 2023-02 | CZ 99.81(2)% across 1.96 mm, 33 ns, ZZ < 2 kHz | IQM | D | [480] |
| 2025-03 | 6-qubit star resonator: [[4,2,2]] logical error per cycle 0.25(2)–0.91(3)% | IQM | D | [488] |
| 2025-05-20 | Advantage2 GA, 4,400+ qubits at degree 20 (16 internal + 2 external + 2 odd couplers) | D-Wave | C | [489] fact |
| 2025-06 | 1 cm hybrid-mode coupler, XX 23.5 MHz, ZZ contrast > 10⁴, no gate | Nanjing | D | [482] |
| 2025-11-12 | Loon: 6-way connections, longer couplers, multilayer routing, no numbers | IBM | C | [49], [486] |
Dominant error term today: qubit relaxation during the flux excursion (T1,eff 14 µs on one qubit, 43 µs on the other) D[480]; for degree-6 lattices the budget is unpublished.
Manufacturing, materials & supply chain
Standard Nb/Al Josephson lithography plus multilayer, low-loss routing so couplers can cross qubit rows. IBM builds Loon on 300 mm wafers at Albany NanoTech and credits the line with "a ten-fold increase" in chip complexity C[49], [486]; D-Wave's 10-K describes "a multilayer integrated circuit process" G[490]. Each tunable coupler adds a junction and a flux line: a 288-qubit gross-code module at degree 6 D[248] carries 864 couplers if all are tunable, three per qubit against 1.8 on Nighthawk (218 couplers, 120 qubits) C[49]. Yield per coupler is unpublished.
Supply chain: IBM fabricates in-house with NY CREATES C[49]; IQM in Espoo D[480]; D-Wave uses "existing third-party foundries", demonstrated a second source with the 2000Q LN G[491], and its 10-K filings mention SkyWater (nine full-text hits, 2023–2026) G[492] — a foundry that IonQ, a platform competitor, has owned since 2026-07-31 C[493] fact. The single points of failure are the three or four fabs with qualified low-loss multilayer processes. Export exposure: the BIS rule of 2024-09-06 G[301] fact controls dilution refrigerators (3A904) and quantum computers only where qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906), not coupler designs.
Control, readout & I/O burden
A tunable long-range coupler needs one flux line and a 22 ns-class flux pulse D[480]; a fixed resonator hub needs none but pays with MOVE operations C[487], [494]. At degree 6 the coupler flux lines alone are three per qubit, on top of drive, qubit flux and multiplexed readout — five to six lines per qubit. At 10³ qubits that is 5,000–6,000 lines and cold multiplexing; at 10⁴ it is the 40,000 lines QuantWare promises for 2028 C[536] fact; at 10⁶ only on-chip flux generation (cryo-CMOS or SFQ, SEEQC's mK control being the published pointer fact) closes the gap. Loop latency is unchanged: a bivariate bicycle round is "a depth-7 circuit composed of nearest-neighbor CNOT gates" D[248]; what the coupler moves is the decoder, since bicycle codes lack the matching decoders that keep surface-code decoding within a microsecond.
Role in the stack
Two architectures: superconducting transmons and quantum annealing. It requires superconducting lithography with multilayer routing and provides the degree-6 long-range checks bivariate bicycle codes consume: 12 logical qubits in 288 physical where a surface code needs "nearly 3000" at 0.1% physical error D[248], and 121 logical qubits from a 5,000-qubit gross system at p = 10⁻³ in IBM's architecture study, whose degree "does not exceed seven" S[496]. It replaces nearest-neighbour couplers at the price of one junction and flux line per added edge, two or more routing layers, and a coupler whose T1 and spurious modes enter the budget — paid per design, not per gate. Across families: a fabricated carrier that buys in lithography the far-range mobility atoms and ions get from motion. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: on the transmon architecture the round is 0.65 µs with readout 282 ns its largest term, and the 33 ns long-range CZ D[480] is 5% of the round, binding only if a MOVE–CZ–MOVE sequence outruns the readout term; on the annealing architecture the anneal schedule is the clock. Neighbouring empty slots: the chip-to-chip l-coupler promised for IBM's Cockatoo in 2027 R[481], and the spin-qubit resonator link, where Delft showed iSWAP oscillations between spins 250 µm apart D[497] without a gate fidelity.
Evidence — how the numbers were measured
The 99.81% is interleaved randomised benchmarking, its 1.9(2)×10⁻³ error decomposed by simulation into a coherence-limited part dominated by one qubit's T1,eff of 14 µs; ZZ < 2 kHz is measured at the idle point D[480]. Nanjing's figures are spectroscopic couplings, not gates D[482]. IQM's star results are logical-state fidelities of a [[4,2,2]] code, folding in readout and idling D[488]; its "above 99.3%" is a company figure without protocol C[487]. Loon's claims are release text C[49], [486].
Not captured: crosstalk on shared extenders when several couplers of one vertex fire together; T1 at the flux points every coupler forces on its qubits; leakage into extender modes; drift of the ZZ null. Independent replications of a mm-scale CZ with error bars: none as of 3 Sep 2026. Conflicts: degree 6 D[248] against "does not exceed seven" S[496] — the seventh edge is the logic-unit adapter, so both hold; the graph record's "≥ 2 mm" is the paper's 1.96 mm D[480]; IQM's 99.3% (Constellation cell) and 99.81% (isolated pair) are different operations, not a regression.
D-Wave's reliance on SkyWater rests on nine EDGAR full-text hits G[492]; D-Wave's own text says "existing third-party foundries", with a second source demonstrated on the 2000Q LN G[491]. IQM's Constellation "above 99.3%" carries no protocol or error bar C[487]. Nanjing's 1 cm coupler has a measured XX of 23.5 MHz, while its 100 MHz ZZ is stated without saying whether it is measured or simulated D[482]. The 282 ns readout behind the derived clock is the superconducting architecture's typical value, not a figure specific to long-range couplers. Patent metadata for [498] comes from Justia's index, not USPTO full-text records. Not published: IBM Loon's qubit count, c-coupler length and any gate fidelity C[49], [486]; the cost, energy and yield per coupler, from any actor; a patent-family count for long-range couplers; and whether IQM's shipped Crystal products use the 2 mm extended coupler of [480].
Actors & economics
Who.
| Organisation | Role | Country | What it does with this technology | Evidence |
|---|---|---|---|---|
| IBM | developer | US | c-couplers on Loon; Kookaburra qLDPC module (2026); Starling (2029) | C[49], [481] fact |
| IQM Quantum Computers | developer | Finland | 2 mm coupler record; Star hubs; Constellation 2030+ | D[480] C[70], [487], [494] |
| D-Wave Quantum | developer | US | Zephyr degree-20 annealers | C[489] fact |
| Nanjing University | research | China | 1 cm hybrid-mode coupler; long-range ZZ theory | D[482] S[484] |
| QuTech | research | Netherlands | Resonator link between spins 250 µm apart | D[497] |
| SkyWater Technology | supplier | US | Foundry named in D-Wave's 10-Ks; IonQ-owned since 2026-07-31 | G[492] C[493] |
| QuantWare | supplier | Netherlands | 3D-routed chips; VIO-40K roadmap | P[495] |
| DARPA | funder | US | QBI Stage B includes IBM (up to $15 M) | G[65] fact |
Money.
- 2025-09-03 · IQM · Series B · $320 M · closed fact
- 2025-11-06 · DARPA QBI Stage B · IBM among eleven teams · up to $15 M each · official G[65] fact
- 2026-05-21 · IBM/Anderon; D-Wave; GlobalFoundries · US DoC CHIPS letters of intent · $1 B (+ $1 B IBM cash); $100 M; $375 M · LOI, non-binding G[300] fact
- 2026-06-02 · IBM · quantum investment commitment · > $10 B over five years · announced C[57] fact
- 2026-07-02 · IQM · Nasdaq and Helsinki listing · pro-forma cash €337 M; H1-2026 revenue €8.9 M · closed C[58] fact
- 2026-07-31 · IonQ · acquisition of SkyWater · ~$1.8 B · closed C[19] fact
- 2026-08-06 · D-Wave · Q2-2026 results · H1 revenue $5.9 M (Q2 $3.1 M), cash $546.2 M · reported C[15] fact
Market & supply chain. Nobody sells a long-range coupler; it is a design block inside a vendor's chip, and the market is the three or four fabs that can print it — Albany C[49], IQM's own D[480], D-Wave's third-party foundries G[491], [492], GlobalFoundries under its LOI fact — plus QuantWare as the only merchant seller of 3D-routed chips P[495]. The structural cost is 1.5–3 extra couplers per qubit against a 10× saving in physical qubits per logical qubit D[248]. Who pays: G4 (IBM's Starling), G3 if Kookaburra runs, G5 on the annealing architecture C[489], G1/G2 through fewer SWAPs on Star hubs C[494].
IP & standards. IBM: US 12,517,856 (filed 2022-09-28, granted 2026-01-06) on modular connectivity levels, US 12,587,192 (granted 2026-03-24) on resonator chains with tunable inductive couplers, US 2024/0169232 A1 (filed 2022-11-18) on fluxonium long-range coupling G[498]. D-Wave: US 10,268,622 (granted 2019-04-23), US 11,507,871 and US 11,494,683 (both 2022-11) on long-range couplers G[498]. No litigation found; no standard. PatSnap's landscape published on 2026-06-30 counts IBM at 4,388 quantum families, 783 in superconducting devices Pfact; no count exists for long-range couplers.
Roadmaps & track record.
- IBM: promised 2025-06-10 · Loon in 2025 with c-couplers · delivered 2025-11-12 as components without performance numbers C[49], [481].
- IBM: promised 2025-06-10 · Kookaburra 2026, Cockatoo 2027 (l-couplers), Starling 2029 (200 logical, 10⁸ gates) · Kookaburra not delivered as of 2026-09-03, the rest pending R[481] C[72] fact.
- IQM: promised 2026-01-05 · 2Q fidelity above 99.94% in 2025–26; qLDPC demonstrators 2027–28; Constellation with long-range couplers 2030+ · pending R[70].
- D-Wave: described 2021-09-22 · Zephyr topology · delivered with Advantage2 GA 2025-05-20 C[489] fact.
Credibility: IBM ships the processor it names in the year it names (Nighthawk delivered 2025-12 fact) but has published no coupler number ten months after Loon; IQM delivered its 2023 physics and ships Star systems, with a roadmap that carries no qubit counts; D-Wave delivered its topology at scale, for annealing only.
Strategic reading. If mm-scale couplers reach nearest-neighbour fidelity at degree 6, physical qubits per logical qubit fall by an order of magnitude D[248]; the winners are the vendors owning both coupler and code — IBM and, later, IQM — plus the fabs holding multilayer processes; the losers are surface-code roadmaps on nearest-neighbour lattices, Google's included fact. Substitution threats: chip-to-chip l-couplers R[481]; atoms and ions, which get connectivity from motion; better nearest-neighbour gates with SWAP networks. Bargaining power sits with platform vendors on design and with the few fabs on routing layers; IonQ–SkyWater is the first platform vendor owning a rival's named foundry G[492] fact.
Outlook & open questions
Confirm within 12–24 months if: IBM publishes c-coupler CZ fidelities ≥ 99.5% with error bars at ≥ 5 mm and a gross-code memory experiment on Kookaburra by end-2027 fact; any group demonstrates a ≥ 1 cm on-chip CZ at ≥ 99.5% D[482]; IQM shows a Constellation cell at ≥ 99.9% C[487]. Demote if by end-2027 no mm-scale coupler reports ≥ 99.9% or no code with long-range checks on superconducting hardware reports Λ > 1. Best case by 2029: Starling-class modules of 288-qubit gross codes with couplers at 99.9% D[248] R[481]. Worst case: couplers stay at 99.8% on isolated pairs, qLDPC codes migrate to atoms and ions, and IBM's 2029 machine becomes a surface-code machine.
Open questions: (1) does a qubit's T1 survive the flux points six couplers force on it? (2) what is the parallel-gate crosstalk on a vertex whose extenders share a routing layer? (3) which decoder runs bicycle codes within the cycle time? Watch: any IBM coupler paper, Kookaburra's 2026 status, IQM's Constellation product date, Nanjing's 1 cm gate.
References
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news/ Cquantware-announces-scaling-breakthrough-with-vio-40k
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הטקסט בעברית נטען…
Spin shuttling (conveyor mode)
Coherent transport of a spin qubit along a gate-defined conveyor, buying distance and layout sparsity with a dephasing budget rather than with wiring.
Verdict. Transport is no longer the limiting error in a shuttling circuit; the static exchange gates are. Demote if no 300 mm foundry conveyor link reaches 99% per 10 µm by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Conveyor-mode spin shuttling moves a single spin along a gate-defined channel on a travelling potential wave: overlapping clavier gates driven with fixed phase offsets by four sinusoids (eight two-tone), the carrier riding the moving minimum. Bucket-brigade shuttling needs one pulsed control per hop; a conveyor needs a control count set by the number of phases, not by distance. That is the node's whole economic case, and this brief is its price. Bluhm's group at RWTH Aachen and Forschungszentrum Jülich introduced it as the QuBus: 420 nm channel, four sinusoids, 99.42 ± 0.02% single-electron shuttling — charge, not spin D[510]. Spin coherence at length followed at Delft D[196].
Attributes. a — affinity: fully fabricated, an electron in a lithographic ²⁸Si/SiGe well. b — time: ~2 × 10⁻⁷ s per 10 µm transit (cumulative, shuttled back and forth) D[196]; entangling not applicable, this is transport. c — readout: none of its own, it borrows the register's charge sensor. d — mobility: transport, the node's entire function. e — control: no modality or placement of its own, one shared radio-frequency drive. f — error as the code sees it: coherent, dephasing and position-dependent rotations, no loss channel. g — manufacturing: CMOS, the same 300 mm line as the dots.
Physics & limits
Gates at 180 nm pitch driven to 300 MHz make a moving confinement minimum; the carrier follows adiabatically at 36 m/s single-tone, 64 m/s two-tone D[196]. Adiabaticity bounds transit time from below through orbital and valley splittings, spin coherence from above. Spin–orbit coupling and micromagnet gradients make transport a deterministic, position-dependent rotation — coherent, hence calibratable in principle — and motion also helps, Delft attributing the improved coherence of moving spins to motional averaging D[193]. Charge noise and disorder pin the carrier and excite it at valley–orbit anticrossings S[511]. Nothing thermodynamic bounds any of this, so the floor is materials: valley-splitting uniformity along a line, and charge noise. Moving it takes interface engineering, quieter gate stacks, echo during transport (in germanium, echo lifted the characteristic shuttle number from 64–77 to above 300 D[512]) or confinement modulation S[513]. Surface-code simulation gives a dephasing threshold of several percent and moderate overhead to ~1% error per shuttle S[514] — forgiving, but conditional on gates and readout already sitting below threshold, which on spins they do not.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2021-08 | 420 nm conveyor, four controls, 99.42 ± 0.02% single-electron (charge) shuttling | RWTH Aachen | D[510] |
| 2024-07-08 | Germanium holes, bucket-brigade: 99.97% per shuttle, basis states only, 312 µm effective | QuTech | D[512] |
| 2025-06-09 | Conveyor: 10 µm effective (back and forth) in under 200 ns at 99.54 ± 0.03% spin fidelity | QuTech | D[196]fact |
| 2026-05-06 | Controlled-phase gate between two moving spins: 98.86 ± 0.29%, 240 nm, 58 ns | QuTech | D[193] |
| 2026-07-29 | Weight-four parity, mobile ancilla: 97.7(1)% per 1.2 µm round trip; Z-parity 72.2(6)% | QuTech | D[349] |
The dominant error term is counter-intuitive: in the five-qubit parity device the limit is incoherent noise in the exchange interaction, dephasing during shuttling and idling being about a quarter of the total D[349]. Transport has stopped being the worst thing in a shuttling circuit; the static gates are, and the route past 99% is gate-stack change, not faster conveyors. Typical-at-scale does not exist: every result above is on a research-fab heterostructure, and no conveyor link has been published on a 300 mm device.
Bucket-brigade hopping (a spin passed from dot to dot by sequential gate pulses, as opposed to conveyor-mode transport in a moving potential well) now crosses a two-dimensional array: in QuTech's 6×6 germanium hole-dot grid with one shared barrier gate, a spin crossed 26 dot-to-dot transitions over 5.2 µm, with lower bounds of 99.96 ± 0.01% per hop for basis states and 99.68 ± 0.04% for superpositions; the same shuttling tuned 30 of the 36 dots P[898].
Manufacturing, materials & supply chain
Three overlapping gate layers at ~180 nm pitch over an enriched ²⁸Si/SiGe well, 7 nm thick at Delft D[196] — nominally 300 mm-compatible, and the node's hard dependency is exactly that: uniform conveyor gates on a CMOS line. Dots need only resemble each other; a bus must be uniform along its whole length, because one pinning defect breaks the channel and a conveyor carries no redundancy. No yield or uniformity statistic has been published for conveyors, conspicuous beside Intel's 24,000-plus spin devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766]. Supply: enriched ²⁸Si from a handful of isotope separators, the single point of failure the silicon-spin architecture already shares, and SiGe epitaxy and overlay at imec, Intel, GlobalFoundries and STMicroelectronics. Cost per bus is not quotable; no ECCN mapping of the quantum dual-use regime is asserted here.
Control, readout & I/O burden
Four or eight shared radio-frequency lines drive an arbitrarily long bus, so line count scales with the number of buses, not with distance or stops served; a bucket-brigade link of equal reach needs one pulsed line per hop. Sparsity is what makes co-located electronics fit — the argument HRL's 4 K controller makes from the other end at ≤3.5 W and 366 DACs for 18 qubits D[190]fact. The node has no readout; a mobile ancilla is measured at a dedicated site D[349]. Latency is not the binding constraint: 4 ns hops and 58 ns moving-spin gates sit two to three orders below spin readout at 1–100 µs, so shuttling does not lengthen the syndrome cycle. The walls: at 10³ qubits, channel uniformity on 300 mm; at 10⁴, phase calibration across thousands of drifting conveyors; at 10⁶, the dephasing budget — at 10⁻³ per µm, one micron of travel per syndrome extraction is affordable and one hundred is not.
Role in the stack
The node belongs to the silicon and germanium quantum-dot spin architecture (Intel, Diraq, Quantum Motion, HRL under IBM, QuTech, Quobly). It requires gate-defined dot spins to move and a 300 mm CMOS foundry for uniform conveyor gates, and provides nothing downstream: its value is realised inside the architecture it serves, which is why it will never be sold as a product. It replaces static nearest-neighbour exchange, which costs no transport error; a shuttled link buys distance with a dephasing budget and a calibration burden, worth paying only when control and readout electronics must be interleaved among the qubits. The node sits far from the fabrication cluster it depends on, its physics set by disorder in research heterostructures and its economics by a 300 mm line it has never run on. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: transport contributes 2.0 × 10⁻⁷ s and gates 5.8 × 10⁻⁸ s each, so the architecture stays readout-limited at 8.5 × 10⁻⁶ s, readout 6.3 µs of it and reset 1 µs. Empty neighbouring slots: transport across a die boundary, and a link with in-flight leakage detection.
Evidence — how the numbers were measured
The silicon figure comes from interleaved randomised benchmarking of a shuttle "gate" over a 10 µm effective path, shuttled back and forth D[196]; the germanium figure from exponential fits to a characteristic shuttle number D[512]. Different observables, routinely quoted side by side: 99.97% per shuttle in germanium is basis-state only, 99.54% in silicon a spin fidelity over a path. Benchmarking a shuttle also assumes twirlability, questionable for a deterministic position-dependent rotation, since motional averaging can flatten the benchmark below the physical error at any single point. Neither protocol reports leakage out of the valley or orbital subspace, and no shuttling result has been cycle- or mirror-benchmarked, so the correlated error a code would see is unmeasured. Conveyor transport is shown at charge level by RWTH Aachen, at spin level by Delft; the 10 µm figure has no independent replication as of 3 Sep 2026.
The germanium "99.97% per shuttle" [512] is a basis-state figure, not comparable with the silicon conveyor spin fidelity [196]. Not published: ARQUE Systems' funding round, amount and investors [515], its headcount and a dated installation milestone at Jülich Supercomputing Centre; and yield, channel-uniformity or per-bus cost data for conveyor structures on any 300 mm line.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuTech | research | NL | Every conveyor spin record: 10 µm effective shuttle, moving-spin gate, mobile ancilla | D[193], [196], [349] |
| RWTH Aachen | research | DE | Invented conveyor mode; SpinBus architecture | D[510]S[514] |
| Forschungszentrum Jülich | research | DE | Conveyor co-parent; hosts ARQUE's first system | C[515] |
| ARQUE Systems | developer | DE | Sells patented shuttling paths; five-qubit processor | C[515] |
| IBM | developer | US | Acquired HRL: exchange-only silicon plus 4 K cryo-CMOS | G[10] |
| Diraq | developer | AU | 300 mm silicon MOS with imec; sparse layouts underpin its cost claim | D[189] |
| Quantum Motion | developer | UK | 22FDX CMOS, full-stack system at NQCC | C[355] |
| imec | supplier | BE | 300 mm spin line; would fabricate any foundry conveyor | D[189] |
Money.
- 2022-09 · ARQUE Systems · spin-off founded by Bluhm and three colleagues · undisclosed · Jülich, RWTH Aachen · announced C[515]
- 2025-11-06 · DARPA QBI Stage B · eleven teams including Diraq, Quantum Motion · up to $15 M each · announced G[65]fact
- 2026-05-07 · Quantum Motion · Series C · $160 M · DCVC, Kembara · closed C[355]fact
- 2026-05-21 · Diraq · CHIPS letter of intent · up to $38 M · US Commerce · LOI G[300]fact
- 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · closed C[350]fact
- 2026-07-23 · IBM · acquisition of HRL Laboratories · undisclosed · announced; closed 2026-08-26 G[10]factfact
None of these is financing for shuttling as such: it is a feature funded inside spin-qubit companies, not a fundable line item, with ARQUE the sole exception — and its funding undisclosed.
Market & supply chain. Nobody sells a shuttle. Enabling supply is 300 mm lithography and overlay, SiGe epitaxy, enriched ²⁸Si substrates and multi-channel waveform generation. G3 and G4 pay for it, since sparsity only earns its dephasing cost at code scale; G7 marginally, through the Jülich installation; G1 and G5 nothing.
IP & standards. The conveyor family originates with RWTH Aachen and Forschungszentrum Jülich; ARQUE commercialises a patented shuttling mechanism C[515]. No dated family count from a named database exists for this node, so none is quoted, and no standards body covers spin transport.
Roadmaps & track record. (promised 2021-08 · conveyor as a scalable bus · status 2026-09-03: single-channel level only, never on a foundry wafer). (ARQUE Systems, promised 2026 · five-qubit shuttling processor at Jülich · status: installation under way, no acceptance data C[515]). (QuTech, promised 2026-07 · above-99% shuttled parity via gate-stack change · status: 97.7% per shuttle D[349]). (Diraq, promised 2026-08-27 · 150 k physical and 1 k logical qubits by 2029 · status: eight-qubit foundry device with one working pair, its own July release saying "thousands by 2029" Cfactfact). QuTech is the strongest actor here; ARQUE is unproven but the only vehicle with a delivery date; Diraq's numbers move faster than its devices.
Strategic reading. If the conveyor reaches foundry uniformity, the winners are the CMOS spin vendors whose thesis is density-through-sparsity — IBM with HRL, Diraq, Quantum Motion, Quobly — and the cryogenic control suppliers, since sparse lattices are what make co-located electronics fit. Losers: dense nearest-neighbour exchange architectures, and foundries selling dot uniformity rather than line uniformity. Bargaining power sits with the 300 mm lines and the enriched-silicon suppliers; a transport primitive with no standalone product will be absorbed as an IP position, which is what the Aachen and Jülich patents already are.
Outlook & open questions
Falsifiable milestones for 12–24 months. Confirm: a conveyor spin link on a 300 mm foundry device at ≥99% per 10 µm by 2027-09; a shuttled-ancilla parity check above 99%, the target the Delft authors set themselves D[349]; independent replication by a group other than Delft. Demote: if shuttled-ancilla parity stays below ~90% through 2027, the sparse-architecture argument loses its only experimental leg; or if valley-splitting variation along channels proves irreducible on foundry material. Best case by 2029, a distance-3 to distance-5 surface-code patch on a sparse spin lattice with shuttled syndrome extraction; worst case, shuttling stays a Delft and Aachen speciality on research heterostructures.
Open questions. (1) Is benchmarking of a shuttle a meaningful fidelity, or an artefact of motional averaging? (2) Does motional averaging survive foundry-level charge disorder, or invert into pinning? (3) What is the leakage rate at valley anticrossings? (4) Can conveyor phase calibration be automated across thousands of buses? (5) Can a spin cross a die boundary? Watch: any 300 mm shuttling result from imec, Intel, GlobalFoundries or STMicroelectronics; ARQUE's acceptance data at Jülich; QuTech's follow-up to the weight-four parity device.
References
- [10] IBM, “IBM to Acquire HRL Laboratories to Power the Future of Quantum,” Jul. 23, 2026. [Online]. Available: https://newsroom.ibm.com/
2026-07-23-ibm-to-acquire-hrl-laboratories-to-power-the-future-of-quantum G - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fidelity,” Nature, vol. 646, no. 8083, pp. 81–87, Sep. 2025, doi: 10.1038/s41586-025-09531-9. D
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [193] Y. Matsumoto et al., “Two-qubit logic and teleportation with mobile spin qubits in silicon,” Nature, vol. 653, no. 8114, pp. 391–397, May 2026, doi: 10.1038/s41586-026-10423-9. D
- [196] M. De Smet et al., “High-fidelity single-spin shuttling in silicon,” Nat. Nanotechnol., vol. 20, no. 7, pp. 866–872, Jun. 2025, doi: 10.1038/s41565-025-01920-5. D
- [199] H. C. George et al., “12-spin-qubit arrays fabricated on a 300 mm semiconductor manufacturing line,” Nano Lett., vol. 25, no. 2, pp. 793–799, Dec. 2024, doi: 10.1021/acs.nanolett.4c05205. arXiv:2410.16583. D
- [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
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Русский текст загружается…
הטקסט בעברית נטען…
Static nearest-neighbour lattice
A coupling graph fixed at mask level in which each qubit interacts only with lithographic neighbours; the default topology under every fielded superconducting and spin processor.
Verdict. Not a design choice but the residue of planar lithography. It caps codes at the surface/colour family by geometry, and every announced escape from it is roadmap, not hardware.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A connectivity primitive, not a qubit type: the interaction graph is frozen at mask level, each site coupling only to lithographic neighbours, because capacitive/inductive and exchange couplings decay over microns and nanometres. The anchor is Barends et al. (Google/UCSB, 2014-02): five Xmon qubits in a linear nearest-neighbour array, 2Q up to 99.4%, at the surface-code threshold D[284]. IBM's heavy-hex arrived in 2019 as a code construction — a surface/Bacon–Shor hybrid with flag qubits, cutting fixed-frequency collisions "by several orders of magnitude" at the cost of coordination number S[476]; the flagship has since returned to a square lattice C[49].
Attributes: fully fabricated affinity; no time constant, readout or control of its own — a topology, not a device; static, lithographic, coherent error: "heavy-hex (degree 2.3) or square lattice (degree 3.5–3.6) with on-chip couplers; ZZ crosstalk is the tax" (graph record).
Physics & limits
The floor is not a coherence floor. Always-on coupling leaves residual ZZ; tunable couplers null the static part but add a flux line, a leakage path and flux-noise susceptibility S[476]. In the only published full error budget at code scale — Google's d=7 run on Willow — CZ crosstalk contributes 5.5×10⁻⁴ D[1]. The binding constraint is geometric: a stabiliser code with 2D-local checks obeys the Bravyi–Poulin–Terhal bound kd² ≲ n, so this topology hosts only the surface/colour family at order 2d² physical qubits per logical one — a rate no better qubit can raise. The second tax is routing: an arbitrary interaction on a degree-2.3–3.6 graph costs SWAP depth scaling with lattice diameter. Only breaking 2D locality moves the floor.
For digital simulation of time-independent, finite-range lattice Hamiltonians in a fixed dimension, nearest-neighbour connectivity is near-optimal: a nearest-neighbour circuit reaches depth O(T log(nT/ε)) with O(nT log(nT/ε)) gates and O(n) ancilla qubits, for n qubits, evolution time T and error ε, against an unconditional lower bound of Ω(log n / log log n) depth for uniform XXZ dynamics at fixed time P[894]. The count assumes exact single-qubit rotations; synthesis over a finite gate set adds a polylogarithmic factor.
Engineering state of the art
Best demonstrated is an isolated pair: IQM's flux-tunable-coupler CZ at 99.93% over 40 hours, with 99.98% 1Q and >99.94% simultaneous readout on the same device D[38]. Typical at scale is IBM's fleet error per layered gate, 3.7×10⁻³ typical and 1.9×10⁻³ best (July 2026), measured full-width D[33]. That ≈5× gap between a characterised pair and a full-width layer is the lattice tax; inside it the two-qubit gate dominates, about 40% of Google's colour-code budget D[41]. Foundry spin arrays sit a generation behind, 2Q 99.04–99.56% D[189].
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2014-02 | Five-qubit linear array, 2Q up to 99.4% | Google/UCSB | D[284] |
| 2024-12 | d=7 surface code, 105 q, Λ=2.14; CZ crosstalk 5.5×10⁻⁴ | Google Quantum AI | D[1] |
| 2025-11 | Nighthawk: 120 q, 218 couplers, 5,000 2Q gates per circuit | IBM | C[49] |
| 2026-04 | Twelve chiplets tiled into 108 q, median 2Q 99.1% (99.5% at 36 q) | Rigetti | C[36] |
Manufacturing, materials & supply chain
Superconducting lattices are Nb/Al junction films patterned by DUV or e-beam; EUV is not required and no fielded transmon lattice uses it — IBM runs 300 mm at Albany, Google in-house. Spin dot arrays are foundry-native and EUV-dependent: Intel 300 mm, >24,000 devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766]; GlobalFoundries 22FDX for Quantum Motion; STMicroelectronics FD-SOI for Quobly Cfact. Uniformity, not peak fidelity, limits that branch: imec's eight-qubit device had a validated two-qubit gate on one of four pairs D[197]. Export exposure attaches to the machine, not the topology (ECCN 4A906, 3A904, 3A901.a) G[301].
Control, readout & I/O burden
The lattice buys no wiring saving. Nighthawk carries 218 tunable couplers for 120 qubits: the coupler count — roughly 1.8 flux lines per qubit above drive and readout — sets the harness C[49]. At 10³ the harness is buildable; at 10⁴ it binds on cryostat area and heat load, which IBM's 0.53 m² wiring area and 2.75 m³ vacuum volume per modular cell are sized against C[50]; at 10⁶ nothing at room temperature closes. Both mitigations sit far below lattice scale: SEEQC's millikelvin SFQ control flip-chip-integrated with qubits, 1Q up to 99.9% D[304], and HRL's 4 K cryo-CMOS sequencer running 18 qubits with no room-temperature real-time electronics D[190].
Role in the stack
It underlies the transmon architecture (IBM, Google, Rigetti, IQM, Fujitsu), the bosonic and dual-rail superconducting architectures, the silicon and germanium quantum-dot spin architecture (Intel, Diraq, Quantum Motion, HRL→IBM), the silicon donor-spin architecture, defect-spin nodes and the topological tetron (Majorana) architecture. It provides the 2D-local checks the rotated surface and colour codes need, and is the alternative to long-range on-chip couplers, shuttled spins and shared-line crossbars; switching costs a mask redesign. It conflicts with degree-≥6 qLDPC codes, all-to-all high-rate codes, transversal-permutation schemes and cm-scale 3D cavities. Having no transport step it adds zero to the transport term of the derived clock (= sum of the syndrome round: gate layers + transport + readout + reset); its cost hides in the gate term as SWAP depth. The neighbouring empty slot is a degree-≥6 static lattice at parity fidelity with degree-3.5.
Evidence — how the numbers were measured
Crosstalk and coupler figures come from randomised or cross-entropy benchmarking on pairs or small subsets. The 5.5×10⁻⁴ CZ crosstalk is a fitted component of Google's device-wide error budget, not an independent measurement; no vendor publishes full-lattice simultaneous crosstalk. Error per layered gate is the only full-width metric in fleet use and only IBM reports it, so cross-vendor comparison of the lattice tax is impossible today. Rigetti's 99.5%→99.1% median drop across its 36→108-qubit tiling is unattributed C[36].
The PatSnap patent counts come from secondary sources.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| IBM | Developer | US | Heavy-hex then square lattices; Nighthawk 120 q | C[49] |
| Google | Developer | US | Square lattices; d=7 code on 105 qubits | D[1] |
| Rigetti | Developer | US | Tiles chiplets into 108 qubits | C[36] |
| IQM | Developer | FI | Transmon line; isolated-pair CZ 99.93% | D[38] |
| GlobalFoundries | Supplier | US | 22FDX spin-dot wafers | Cfact |
Money.
- 2026-05-21 · US Dept of Commerce · CHIPS letters of intent, nine firms (IBM/Anderon $1 B, GlobalFoundries $375 M, Diraq ≤$38 M) · $2.013 B · LOI, non-binding fact
- 2026-06-02 · IBM · five-year quantum commitment · >$10 B · announced Cfact
- 2026-07-02 · IQM · Nasdaq/Helsinki listing · cash €337 M pro-forma · closed Cfact
- 2026-08 · Rigetti · Q2-2026 results · revenue $5.1 M, cash $541.3 M · reported Cfact
Market & supply chain. Transmon lattices consume DUV/e-beam tooling, flip-chip bonders, TWPA amplifiers and control racks; spin lattices consume ASML EUV inside Intel, GlobalFoundries and STMicroelectronics — a single point of failure the superconducting branch does not share. G1–G3 pay for the lattice; G4 is the goal it cannot reach unaided.
IP & standards. The IP is coupler-level: IBM US 11,727,297 B2 (granted 2023-08-15) claims an opposite-sign second coupling path cancelling coherent error Pfact. Aggregate quantum families in PatSnap's landscape published on 2026-06-30: IBM 4,388, Google 2,385 P[312]. No topology standard exists.
Roadmaps & track record. IBM Nighthawk (promised 2025-06-10, for 2025, delivered 2025-12) Cfact; Kookaburra, the first step off pure nearest-neighbour connectivity (promised 2022-05-10 for 2025, redefined for 2026, undelivered as of 2026-09-04) Rfact; Rigetti median 99.5% at 108 q (promised for end-2025, slipped to "later 2026", unmet) Rfact. IBM ships the base lattice on time and misses every date beyond it.
Strategic reading. If this topology stays the only manufacturable one, the winners own 2D-local decoding and yield — IBM and Google in superconductors, CMOS foundries in spins — and the losers are high-rate-code startups betting on connectivity nobody can fabricate. If degree rises, leverage moves to coupler and packaging IP — what IBM's coupler patents and the HRL purchase buy.
Outlook & open questions
Confirm or demote within 12–24 months: does Kookaburra ship a qLDPC memory on c-coupled hardware or slip again; does Rigetti reach median 99.5% at 108 qubits; does any vendor publish a full-lattice simultaneous-crosstalk number. Best case by 2029: degree-6 on-chip routing ships without a fidelity penalty and a planar lattice hosts a high-rate memory. Worst case: coordination stays near 3.5 and scale is bought with 2d² overhead. Open: whether the pair-to-full-width gap is intrinsic.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [33] IBM, “IBM Quantum Computing — Hardware and roadmap.” [Online]. Available: https://www.ibm.com/
quantum/ Dhardware - [36] Rigetti Computing, Inc., “Rigetti Announces General Availability of 108-Qubit System,” Apr. 7, 2026. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ rigetti-announces-general-availability-108-qubit-system - [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
- [41] N. Lacroix et al., “Scaling and logic in the color code on a superconducting quantum processor,” Nature, vol. 645, no. 8081, pp. 614–619, May 2025, doi: 10.1038/s41586-025-09061-4. arXiv:2412.14256. D
- [49] IBM, “IBM Delivers New Quantum Processors, Software, and Algorithm Breakthroughs on Path to Advantage and Fault Tolerance,” Nov. 12, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance C - [50] C. Dundon, S. Hall, M. Hollister, and A. Lindler, “IBM's new modular architecture for cryogenic systems,” IBM Quantum Computing Blog, Aug. 19, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ modular-cryogenics - [189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fidelity,” Nature, vol. 646, no. 8083, pp. 81–87, Sep. 2025, doi: 10.1038/s41586-025-09531-9. D
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
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Русский текст загружается…
הטקסט בעברית נטען…
Ion shuttling (QCCD, junctions, grid traps)
Moving trapped ions between zones through junctions or grid traps so a small gate-able crystal inherits all-to-all connectivity.
Verdict. Sorting, splitting and re-cooling — not the hop, not the gate — set the ion clock (~55 ms per full-width layer on Helios). Without a 10× cut by 2028 ion QCCD stays high-fidelity and low-throughput.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
QCCD, proposed by Kielpinski, Monroe and Wineland in 2002 D[499], splits the register into zones and uses time-varying electrode voltages to move ions between memory and interaction zones, so no chain need be both long and gate-able — routing bought with trap area. Junctions make it two-dimensional; grid traps permute ions like a sliding-tile puzzle.
Mobility and time: the carrier itself moves, at 1.7–4 m/s measured D[114], [117], so connectivity is a schedule, not a coupler map; move-plus-re-cool ~2 ms, entangling determinism inapplicable. Error and fabrication: coherent motional excitation plus ion loss, seen as raised two-qubit infidelity and leakage; MEMS surface-electrode chips on DC waveforms.
Physics & limits
Ramping neighbouring segment voltages drags a potential well, and its ion, along the axis — and the move need not be slow: NIST moved ⁹Be⁺ 370 µm in 8 µs, excitation peaking at 1.6 quanta and returning to 0.2 by waveform design D[500]. The millisecond cost is therefore not the hop but splitting and recombining crystals (two ions split in 55 µs kept ~2 quanta each D[500]) and the sideband cooling that restores the gate modes.
At a junction the rf null is discontinuous: the ion crosses a pseudopotential bump with excess micromotion, which sets transit speed and heating. Beneath that is anomalous heating from electrode-surface noise, steep as the ion nears the surface, so tighter confinement cannot buy adiabaticity. What moves the floor is a gate tolerant of a warm crystal: the electronic (laser-free, microwave-driven) gate reached 8.4×10⁻⁵ error without ground-state cooling D[102], deleting the re-cool term rather than shrinking it.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2022-06 | X-junction round trip, 4 m/s average, 0.013(1)–0.030(2) quanta | Quantinuum | D[114] |
| 2023-02 | Chip-to-chip matter link, 2,424 transfers/s, loss infidelity < 7×10⁻⁸ | Universal Quantum | D[117] |
| 2024-03 | Grid-trap ion exchange at 2.5 kHz | Quantinuum | D[113] |
| 2025-11 | 55 ms per full-width layer, 98 ions, 8 zones | Quantinuum | D[97] |
The gap between primitive and product is the finding: a Helios two-qubit gate takes ~70 µs against ~55 ms per layer, and on H2 transport was ~60% of runtime D[97], [110]. The dominant term is the schedule — sorting, split/merge, re-cooling, serialisation across eight zones.
Manufacturing, materials & supply chain
Traps are segmented-electrode chips. Honeywell is Quantinuum's captive fab and made Sol's 2D grid chip, in validation as of Q2 2026 C[124]. Infineon Villach is the merchant line — 6–12 inch wafers, Generation-3 out-of-plane electrodes claimed to raise confinement ~10× — serving Oxford Ionics, eleQtron, Innsbruck and ETH at once C[320]. IonQ broke that duopoly by buying SkyWater for ~$1.8 B, closed 2026-07-31: the first ion vendor to own fabrication G[19]. Sandia's MESA stays research-only G[501]. No yield figure is public; the only price is AQT's EUR 9.8 M 20-qubit turnkey system, ≈ EUR 0.5 M per qubit C[323]. Single points of failure: Infineon's one line, and UV lasers, where TOPTICA dominates and 369 nm for Yb⁺ is constrained P[322]. No ECCN names ion traps, but a finished machine falls under 4A906, effective 2024-09-06 G[301].
Control, readout & I/O burden
A move is a synchronised DC waveform across tens of electrodes at µs update, then cooling and, for laser gates, beam re-addressing. Helios carries 1,228 electrodes for 98 ions D[97]: electrode count is what scales, and updates fit three orders inside the 55 ms layer, so electronics is not the wall. At 10³ ions it is ~10⁴ filtered DC channels, which Oxford Ionics would cut to ~200 external sources by putting switching electronics on-chip — a design study, no chip built S[325]. At 10⁴–10⁶ the constraint is routing cooling and gate light to many zones at once (Helios needs ≥7 wavelengths): none drives more than a few dozen concurrently.
Role in the stack
Shuttling serves two of the three trapped-ion architectures — QCCD (Quantinuum), where it is primary, and electronic qubit control (IonQ/Oxford Ionics, eleQtron), where it is the alternate — providing the arbitrary-pair connectivity that bivariate bicycle qLDPC memories and high-rate transversal codes assume: Quantinuum's [[80,48,4]] demonstration pays for it in transport, while IonQ's qLDPC break-even ran on a static 40-ion chain without it. It replaces the static long chain, whose mode spectrum crowds as ions are added; the price is that connectivity becomes scheduling and the clock moves from gate to move — derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 9.7 ms, transport 9.0 ms of it, against the measured ~55 ms full-width layer D[97]. Neighbouring empty slot: more than two linked modules — the two-module link exists D[117], nothing larger.
Evidence — how the numbers were measured
Transport has no stand-alone benchmark. It is inferred from sideband thermometry around a move — the 0.013(1)–0.030(2) quanta figures D[114] — and from two-qubit fidelity after a transport sequence, which folds transport into gate error. Neither captures cumulative heating over a deep circuit, junction loss at scale, or zone crosstalk. The 55 ms layer and 2.5 kHz exchange rate are vendor-reported and externally unreplicated as of 2026-09-04; AQT's quantum volume 32,768 is not a transport measurement and discloses no timing C[128].
The EUR 0.5 M per qubit figure is a 2023 turnkey system price, not a chip cost. Not published: the grid-site count of the grid trap [113]; AQT LYNX's architecture (junction or linear-only) and its transport and gate times; and the yield, uniformity or per-die cost of any ion-trap fab line.
Actors & economics
Who.
| Organisation | Role | Country | What they do here | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US/UK | Ring-junction QCCD, grid trap for Sol | D[97] |
| Honeywell | supplier | US | Captive fab, made Sol's chip | C[124] |
| IonQ | developer | US | Junction traps, owns SkyWater | G[19] |
| Infineon | supplier | AT | Merchant trap foundry, Gen-3 | C[320] |
| Universal Quantum | developer | UK | Only chip-to-chip matter link | D[117] |
| AQT | developer | AT | LYNX module, units Q4 2026; architecture undisclosed | C[128] |
| Quantum Art | developer | IL | Optical ion-array reconfiguration | P[125] |
Money. 2022-11-02 · Universal Quantum · DLR contract · EUR 67 M · undelivered P[328]. 2025-09-04 · Quantinuum · round · $600 M at $10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed G[122]. 2025-11-06 · Quantinuum and IonQ · QBI Stage B · ≤$15 M each · active fact. 2026-05-05 · eleQtron · Series A · EUR 57 M G[129]. 2026-06-03 · Quantinuum · IPO · $1.68 B gross, Nasdaq QNT, cash $2.1 B G[124]. 2026-07-31 · IonQ · SkyWater M&A · ~$1.8 B, after Oxford Ionics at $1.075 B G[18], [19].
Market & supply chain. Trap fabrication was one captive plus one merchant line; SkyWater adds a vertically integrated third — the year's most consequential supply-chain event C[320]G[19]. UV lasers stay the harder chokepoint P[322]. Shuttling is paid for by G2 and is prerequisite to G3 and G4.
IP & standards. No shuttling-specific family count is published. Nearest dated: IonQ filed 9+ trapped-ion families across JP/EP/IL in 2025–26; Quantum Art holds two pending IL/KR patents on optical reconfiguration of ion arrays P[375]. No open-source shuttling stack exists.
Roadmaps & track record. Quantinuum: Helios (promised 2024-09-10, launched 2025-11-05 — met); Sol (2027, chip in validation Q2 2026 — on track); Apollo (2029 — unscored) R[118]C[124]; credible. IonQ: 10,000 physical on one chip by 2027, 2 M by 2030, no published 2D-trap heating or transport data, and a 2020 roadmap that missed 4,000 qubits by ~40× — intent, not plan R[132]. Universal Quantum has delivered nothing since 2022 P[502].
Strategic reading. Cut layer time 10× and ions convert a fidelity lead into throughput-competitive fault tolerance; fail, and they win logical-qubit headlines while losing on shots per second. Winners either way: Infineon and Honeywell, who sell the scarce object. Substitution threat: neutral-atom tweezers and superconducting long-range couplers — connectivity with no transport.
Outlook & open questions
Confirm/demote in 12–24 months: Sol ships in 2027 with a published per-layer time; any vendor publishes a full-width layer below 10 ms; Universal Quantum links more than two modules. Best case 2029: sub-10 ms layers put the ion logical clock within ~10× of superconducting. Worst case: layer time stays within 2× of 55 ms and ions stay a platform that demonstrates codes rather than running algorithms. Open: does anomalous heating force cryogenic traps at 10⁴ ions; can split/merge be made quanta-free by optimal control; do warm-crystal gates delete re-cooling; does a second merchant fab appear. Watch: Sol validation, Infineon capacity, IonQ's first SkyWater trap.
References
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news/ Gionq-completes-acquisition-of-oxford-ionics-rapidly-accelerating-its-quantum - [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Gionq-completes-acquisition-of-skywater-technology - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
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- [113] R. D. Delaney et al., “Scalable Multispecies Ion Transport in a Grid-Based Surface-Electrode Trap,” Phys. Rev. X, vol. 14, Art. no. 041028, Nov. 2024, doi: 10.1103/PhysRevX.14.041028. arXiv:2403.00756. D
- [114] W. C. Burton, B. Estey, I. M. Hoffman, A. R. Perry, C. Volin, and G. Price, “Transport of multispecies ion crystals through a junction in an RF Paul trap,” Phys. Rev. Lett., vol. 130, Art. no. 173202, Apr. 2023, doi: 10.1103/PhysRevLett.130.173202. arXiv:2206.11888. D
- [117] M. Akhtar et al., “A high-fidelity quantum matter-link between ion-trap microchip modules,” Nat. Commun., vol. 14, no. 1, Art. no. 531, Feb. 2023, doi: 10.1038/s41467-022-35285-3. D
- [118] Quantinuum, “Quantinuum Unveils Accelerated Roadmap to Achieve Universal, Fully Fault-Tolerant Quantum Computing by 2030,” Sep. 10, 2024. [Online]. Available: https://www.quantinuum.com/
press-releases/ Rquantinuum-unveils-accelerated-roadmap-to-achieve-universal-fault-tolerant-quantum-computing-by-2030 - [122] Honeywell, “Honeywell Announces $600 Million Capital Raise for Quantinuum at $10B Pre-Money Equity Valuation to Advance Quantum Computing at Scale,” Sep. 4, 2025. [Online]. Available: https://www.honeywell.com/
us/ Gen/ news/ press-releases/ 2025/ 09/ honeywell-announces-600-million-capital-raise-for-quantinuum-at-10b-pre-money-equity-valuation-to-advance-quantum-computing-at-scale - [124] Quantinuum, “Quantinuum Reports Second Quarter 2026 Results,” Aug. 11, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Cquantinuum-reports-second-quarter-2026-results - [125] M. Abdel-Kareem, “Quantum Art Extends Series A to $140M to Scale Trapped-Ion Architecture,” Quantum Computing Report, Apr. 27, 2026. [Online]. Available: https://quantumcomputingreport.com/
quantum-art-extends-series-a-to-140m-to-scale-trapped-ion-architecture/ P - [128] Alpine Quantum Technologies GmbH, “AQT Sets New European Industry Standard: Introducing the ‘LYNX’ Series with Record-Breaking Quantum Volume,” AQT, May 5, 2026. [Online]. Available: https://www.aqt.eu/
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Atom transport by AOD tweezers (zoned architecture)
Crossed acousto-optic deflectors move tweezers to shuttle atoms between storage, entangling and readout zones at ~99.95% per move.
Verdict. Real: 610 µm in 1.6 ms at 99.95% survival; 448 atoms under fault-tolerant control. Unverified: AOD channel bandwidth past 10⁴ atoms. Demote if no >10³-atom zoned system runs long-memory QEC by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An rf tone in a crystal makes an acoustic grating whose first-order diffraction angle tracks the tone, so sweeping the rf sweeps a tweezer and the atom in it; crossed x/y deflectors turn a comb of tones into a grid of movable traps. The zoned architecture partitions the plane into storage, entangling and readout regions, taking connectivity from moving atoms rather than fixed couplings — introduced by Bluvstein et al.'s 2022 coherent-transport processor (Harvard/MIT).
Attributes. Mobility: transport — atoms relocate hundreds of µm between zones, the platform's only long-range coupling. Time ~10⁻³ s per move, classical repositioning, neither deterministic nor heralded entanglement; the error is loss, not phase.
Physics & limits
Two clocks bound a move: acoustic transit across the beam aperture sets how fast a tone can change (µs for millimetre apertures), and trap radial frequency sets how fast the atom can accelerate without heating out. The second dominates — transport error is release-and-recapture loss driven by trajectory jerk, so minimum-jerk profiles and deeper transit traps, not faster electronics, buy fidelity. Measured: 610 µm in 1.6 ms at 99.95%, 270 µm in 400 µs at 99.8% D[138].
Coherence is not binding here: hyperfine T2 is 12.6 s in the same 6,100-atom array D[138] and 1.09(3) s under dynamical decoupling in a continuously reloaded 3,000-atom system D[144]. So the signature is loss — detectable by imaging, hence erasure-convertible, and over 80% of all leakage; used as a supercheck with ML decoding it gave 2.14(13)× suppression at d=3→5 D[4]fact. What moves the floor: minimum-jerk trajectories, deeper transit traps, and an acousto-optic lens adding the axial axis — so far a design study with no atoms S[503].
Engineering state of the art
Best demonstrated: 610 µm in 1.6 ms at 99.95% D[138]. Typical at scale is the 448-atom zoned processor, where transport is interleaved with gates, not benchmarked alone D[4].
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-03 | 6,100-atom Cs array, hyperfine T2 12.6 s; moves 610 µm/1.6 ms at 99.95% | Caltech | D[138] |
| 2025-09 | 3,217 atoms at 99.3% filling held >2 h, 30,000 initialised qubits/s | Harvard | D[144] |
| 2025-11 | 448 atoms under fault-tolerant control, up to 96 logical qubits active | Harvard/MIT/QuEra | D[4] |
Dominant error term: atom loss at release and recapture — the channel that makes the platform erasure-friendly.
Manufacturing, materials & supply chain
No fab here — free-space optics bolted to a vacuum cell, so "yield" is array filling fraction: 99.3% after rearrangement D[144], 60.5% before it in a metasurface array D[145]. Named hardware in the 448-atom system: crossed AODs (DTSX-400, AA Opto-Electronic), Hamamatsu modulator and camera, Spectrum Instrumentation AWGs (arbitrary waveform generators), Rohde & Schwarz microwave sources D[4]; Gooch & Housego supplies deflectors in the 3,000- and 6,100-qubit papers P[504]. That is the concentration risk: two acousto-optics houses serve the published field — Gooch & Housego, quoted on the London Stock Exchange's AIM market, and the privately held AA Opto-Electronic. Cost per channel is not quotable. Export exposure is nil — the BIS rule of 2024-09-06 names no tweezer optics or deflectors fact; it controls only the resulting machines (4A906), and those only when qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact.
Control, readout & I/O burden
The burden is one rf tone per trap per axis, synthesised by AWG; count scales with atoms, not zones, and intermodulation between tones — not laser power — caps simultaneous traps. The cycle is the real cost: transport 0.4–1.6 ms plus imaging 0.5–1 ms gives QEC rounds of 1–4.5 ms, ~10³× a superconducting cycle, with the decoder obliged to keep up. At 10³ atoms a few AWG channels suffice; at 10⁴ the wall is beam steering — a deflector resolves as many spots as its rf bandwidth times the acoustic transit across the beam, a transit that also bounds how fast it re-points — a trade no source consulted here quantifies against atom number; at 10⁶ the only design point puts RSA-2048 at 19 M atoms and 5.6 days at 1 ms cycles S[31].
Role in the stack
It requires laser plus AOD/SLM optical control and provides for bivariate bicycle qLDPC codes, high-rate concatenated codes with transversal gates, and algorithmic fault tolerance — none reachable with fixed nearest-neighbour coupling, so it is a prerequisite, not a convenience. Architectures served: the alkali (Rb/Cs) and alkaline-earth(-like) (Yb/Sr) Rydberg tweezer arrays and the neutral-atom analogue simulator. Nothing replaces or conflicts with it in the graph; pressure comes from other transport physics — the 3,000-qubit continuous system moves atoms 0.5 m on optical-lattice conveyor belts, using tweezers only for local rearrangement D[144]. Contribution to the derived clock: dominant, at ~2.0×10⁻⁴ s per move it is 0.80 ms of the 1.31 ms sum of the syndrome round: gate layers + transport + readout + reset on both gate-model architectures, since CZ runs at 270 ns.
Evidence — how the numbers were measured
Move fidelity is post-recapture survival by fluorescence imaging: a loss metric, not a state fidelity, so 99.95% certifies the atom arrived, not that its phase did. No source isolates transport-only error at the logical level; the 448-atom results fold transport, gates and readout together D[4]. The sharpest negative evidence is Atom Computing's toric-code run, where suppression over four cycles vanished once continuous reloading was included (0.63% versus 0.64% per cycle over 90 rounds) D[148] — reloading and transport are the operations this node owns. Harvard and Caltech report 99.8–99.95% survival on different deflector hardware, consistent but not a replication.
The axial range, speed and survival in [503] come from an optical design study with no trapped atoms, not from an experiment. Not published: the channel count, or the deflector's trade between spot count and re-pointing speed, against atom number; a dated patent family (assignee and year) for AOD-based zoned atom transport; and the capacity and scale-up plans of AA Opto-Electronic and Gooch & Housego.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Harvard | research | US | Originated zoned transport; 448-atom and 3,000-qubit systems | D[4] |
| QuEra | developer | US | Commercialises the zoned architecture; QBI Stage B | C[153] |
| Caltech | research | US | 6,100-atom array, move-fidelity records | D[138] |
| Atom Computing | developer | US | Alkaline-earth(-like) zoned system; reloading-with-QEC data | D[148] |
| Pasqal | developer | FR | AOD/SLM systems; photonic-chip trap alternative | C[330] |
| Infleqtion | developer | US | NYSE-listed neutral-atom vendor | G[332] |
| AA Opto-Electronic | supplier | FR | Crossed AODs (DTSX-400) in the 448-atom system | D[4] |
| Gooch & Housego | supplier | UK | Deflectors in the 3,000- and 6,100-qubit papers | P[504] |
Money.
- 2025-07-17 · QuNorth · order for Magne (Atom Computing/Microsoft, 50 logical) · €80 M · EIFO + Novo Nordisk Foundation · delivery turn of 2026/27 G[11]
- 2025-09-09 · QuEra · financing round · $230 M+ · Google, SoftBank Vision Fund 2, NVentures · closed C[153]
- 2026-06-16 · Atom Computing · Series C plus CHIPS LOI · >$300 M total · Third Point · closed + LOI C[154]fact
- 2026-08-12 · Infleqtion · Q2 revenue, FY guidance · $12.6 M, ~$43 M FY2026 · — · reported G[332]
- 2026-08-28 · Pasqal · SPAC merger completed (Nasdaq PSQL) · ~$360 M cash · — · closed P[156]
Market & supply chain. The equipment is generic photonics with one exception: crossed AODs, where AA Opto-Electronic and Gooch & Housego are the only vendors named in sourced material D[4]P[504]. Deflector-channel demand grows linearly with atom count, so a small supplier could gate a platform. Unit economics are not quotable. G3 and G4 pay directly; G1 partly; G2, G5, G6, G7 indirectly.
IP & standards. No dated patent family with assignee and year was found for AOD-based zoned transport, and no standards body governs tweezer hardware. The one vendor specification with numbers is QuEra's Gemini page: 260 physical qubits, 99.2% global two-qubit fidelity, one shot per second Cfact.
Roadmaps & track record. QuEra (promised Jan 2024 · 100 logical qubits in 2026 · status 2026-09-03: replaced by Libra 2028, >256 logical — a two-year slip) R[162]. Atom Computing/Microsoft (2025-07 · Magne, 50 logical, turn of 2026/27 · installing) G[11]. Pasqal (2024 · 10,000 physical in 2026 · slipped to 2028) C[156]. Google entered March 2026 with no hardware result C[9]. Experimental groups deliver what they publish; vendor logical-qubit dates have slipped about two years each.
Strategic reading. If zoned transport scales, Harvard's lineage companies and the two deflector houses win, and fixed-connectivity Rydberg machines lose the code families that matter. The substitution threat is other optics, not another node: metasurface arrays (11,022 atoms, no gates) D[145] and photonic-chip trap delivery (4 atoms, 27.5 s, claimed 50× footprint cut) C[330] would displace bulk AOD/SLM stacks if they reach gate quality.
Outlook & open questions
Confirm by end-2027 a zoned system holding >1,000 atoms under fault-tolerant control; demote if by end-2028 no group shows long-memory suppression (Λ > 2) with continuous reloading — the case where suppression has already vanished once D[148]. Best case by 2029: transport loss cut several-fold and the axial axis in use, unlocking 10⁴-atom zones. Worst case: channel count and deflector bandwidth cap zones near 10³–10⁴ atoms. Open questions: does move fidelity hold at QEC duty cycles under reloading; can channel count scale past the deflector's bandwidth–transit limit; who else supplies deflectors at volume?
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [9] H. Neven, “Building superconducting and neutral atom quantum computers,” Google, Mar. 24, 2026. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ neutral-atom-quantum-computers/ - [11] Novo Nordisk Foundation, “New quantum computer with great potential to boost Nordic research and innovation,” Novo Nordisk Fonden, Jul. 17, 2025. [Online]. Available: https://novonordiskfonden.dk/
en/ Gnews/ new-quantum-computer-with-great-potential-to-boost-nordic-research-and-innovation/ - [31] H. Zhou et al., “Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays,” Proc. 52nd Annu. Int. Symp. Comput. Archit. (ISCA), 2025, doi: 10.1145/3695053.3731039. arXiv:2505.15907. S
- [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [145] Y. Wang et al., “Trapping 11,000 Atoms in a Tweezer Array Generated by a Single Metasurface,” arXiv:2606.02715, Jun. 2026. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [330] Pasqal, “Pasqal brings qubit control on-chip, advancing the path to fault-tolerant quantum computing at scale,” Aug. 10, 2026. [Online]. Available: https://www.pasqal.com/
news/ Cpasqal-brings-qubit-control-on-chip-advancing-the-path-to-fault-tolerant-quantum-computing-at-scale/ - [332] Infleqtion, “Infleqtion Reports Record Q2 Revenue, Raises 2026 Outlook as Quantum Commercialization Accelerates,” Aug. 12, 2026. [Online]. Available: https://ir.infleqtion.com/
news-events/ Gpress-releases/ detail/ 201/ infleqtion-reports-record-q2-revenue-raises-2026-outlook-as-quantum-commercialization-accelerates - [503] Z. Guo, R. A. van Herk, E. J. Vredenbregt, and S. J. Kokkelmans, “Acousto-optic lens for 3D shuttling of atoms in a neutral atom quantum computer,” arXiv:2510.09398, Oct. 2025. S
- [504] Gooch & Housego (G&H), “G&H Acousto-Optic Deflectors Referenced in Nature Papers Demonstrating 3,000 & 6,100 Qubit Quantum Systems,” G&H, Mar. 2026. [Online]. Available: https://gandh.com/
news-and-resources/ Pg-and-h-acousto-optic-deflectors-in-nature-papers
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Photonic switching / routing (electro-optic, feed-forward)
Electro-optic and MEMS switches route photons between waveguides on a real-time heralding decision, the loss-dominated transport layer every photonic architecture shares.
Verdict. Best published in-line switch loss is 100 mdB (PsiQuantum BTO), ~14× the ~7 mdB fault-tolerance budget as of 4 Sep 2026; non-volatile devices fix static power, not loss.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An electro-optic or mechanical element inside a Mach–Zehnder interferometer sets its splitting ratio, so a mesh implements any unitary and, driven by an earlier heralding click, routes photons in real time. The lineage is Carolan's six-mode, 15-MZI chip of 2015 D[455] — thermo-optic, reconfigurable "in seconds", the opposite end of the speed and power axis from what fusion needs. Everything since has tried to keep that programmability while stripping its loss and static power.
- b/e: switching in ns–µs (10⁻⁶·⁰ s), electro-optic, room-temperature drivers; not itself entangling.
- d/g: flying photons routed in photonic-IC waveguides; every stage taxes the loss budget.
Physics & limits
Loss is multiplicative, so the architecture fixes a per-stage budget the device meets or the machine does not exist: against a total photon budget of order 0.5 dB across a fusion network's depth, the per-switch allowance is ≈7 mdB D[173]. Fusion-based fault tolerance tolerates 2.7% per-photon loss with 6-ring resource states, 17% only with 168-qubit states nobody can build D[179]. The families trade differently: thermo-optic shifters are low-loss but dissipate milliwatts each and switch in µs, unusable at 2 K across 10⁴ channels; barium titanate and thin-film lithium niobate switch in ns at low power but add material and transition loss. The second failure mode is finite extinction: amplitude leaked to the wrong port is an unheralded error, not a loss. Moving the floor needs higher electro-optic coefficients (barium titanate's effective r is ~30× lithium niobate's, so shifters shorten and lose less), lower-loss material transitions and non-volatility.
Engineering state of the art
Best published in-line switch: PsiQuantum's barium titanate at 100 mdB insertion, with 52(12) mdB fibre-to-chip coupling at ~2 K D[169]fact. Aurora is the only system-scale figure: 35 chips, 0.19 dB per MZI, ~14 dB total loss, no error-corrected computation D[173]. The 2026 non-volatile barium-titanate array switches in 80 ns at 1.48 dB per cell with zero static power once set D[516] — a static-power result, not a loss one. Dominant error: cumulative insertion loss, then coupling.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-01 | 0.19 dB/MZI; ~14 dB system loss; ≈7 mdB requirement | Xanadu | D[173] |
| 2025-02 | BTO switch 100 mdB; fibre-to-chip 52(12) mdB | PsiQuantum | D[169] |
| 2026-06 | Non-volatile BTO cell: 80 ns, 1.48 dB, zero static power | UPV iTEAM | D[516] |
| 2026-08 | Foundry-compatible MEMS switch, <1.5 dB, >30 dB extinction, ~20 nW | UC Berkeley | P[517] |
Manufacturing, materials & supply chain
Silicon nitride or thin-film lithium niobate waveguides, barium titanate for the active element, superconducting nanowire detectors on the same 300 mm wafer; PsiQuantum's runs at GlobalFoundries, which launched a quantum manufacturing unit on 2026-05-21 against a $375M CHIPS letter of intent C[353]. Barium titanate on silicon is a deposition few lines can do; the merchant thin-film-lithium-niobate base is two venture-scale suppliers, HyperLight and Lightium P[518]. Packaging is the second chokepoint: Xanadu's coupling result needed Corning fibre arrays and DISCO singulation C[172]. No yield figure is public; no export-control category names photonic switches, the 2024 BIS rule reaching them only via ECCN 4A906 fact.
Control, readout & I/O burden
Feed-forward means the photon waits in a delay line while a cryogenic detector click is classified and the switch driven, which couples latency to loss — brutally on chip. At silicon-nitride propagation loss one nanosecond of on-chip delay costs a few tenths of a dB, more than the whole per-stage budget, while the same nanosecond in fibre at ≈0.2 dB/km is free: feed-forward lives in fibre and must resolve in nanoseconds. QuiX names feed-forward electronics as one of two problems its 2026 system must solve C[177]. I/O scales with network depth, not qubit count; at 10⁴–10⁶ modes the binding constraints are detector channel count and the cryogenic power holding each switch in state.
Role in the stack
Transport for all three photonic architectures: fusion-based discrete-variable machines (PsiQuantum, Quandela, QuiX), the continuous-variable/GKP architecture (Xanadu) and the boson sampler. It requires a photonic-IC foundry process and provides the routing that turns heralded fusion outcomes into a cluster state; nothing substitutes for it. Every actor in the branch depends on the same number, making it the branch's single point of failure. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset — undefined here, the fusion architecture running no syndrome round; the ~1 µs floor is set by feed-forward and detector recovery, not the switch. Empty neighbouring slot: a sub-10 mdB non-volatile switch.
Evidence — how the numbers were measured
Switch loss and extinction come from direct insertion-loss characterisation against on-chip reference paths — harder numbers than gate fidelities, and the least comparable, each vendor quoting a different boundary. Aurora's 0.19 dB is per MZI including interconnect; PsiQuantum's 100 mdB is the switch element alone; Xanadu's 0.085 dB/facet is fibre-to-chip, marketed as an industry benchmark C[172] though PsiQuantum published 52(12) mdB for that interface a year earlier D[169]. None should be summed or ranked without a common protocol, and none is replicated outside its originating group. System verification is a loss budget, not a logical-fidelity witness.
The main report's "waveguide loss 0.5 dB/m" for Omega conflicts with the paper's single-mode silicon-nitride figure of 1.8(2) dB/m fact; neither is a switch figure.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | USA | BTO switches at 100 mdB, under DARPA V&V | D[169] |
| Xanadu | developer | Canada | Aurora switch network; coupling and packaging | D[173] |
| QuiX Quantum | developer | Netherlands | Feed-forward hardware; Carina at DLR | C[177] |
| Quandela | developer | France | 12-qubit switched system at CEA | C[176] |
| GlobalFoundries | supplier | USA | 300 mm line; $375M CHIPS letter of intent | C[353] |
| DARPA | investor | USA | Stage C money buys BTO switch validation | P[181] |
Money.
| Date | Actor | Event | Amount | Programme / lead | Status |
|---|---|---|---|---|---|
| 2025-09-10 | PsiQuantum | Series E | $1B at $7B | BlackRock, Temasek | closed C[519] |
| 2026-03-26 | Xanadu | SPAC merger | ~$302M, 40% below plan | Crane Harbor | closed C[178] |
| 2026-05-21 | US Commerce | CHIPS letters of intent | $375M, $100M | GlobalFoundries, PsiQuantum | LOI fact |
| 2026-07-22 | PsiQuantum | QBI Stage C expanded | $125M after $31.8M | DARPA | official P[181] |
| 2026-08-28 | Xanadu | Toronto factory funding | CAD 195M | Government of Canada | closed C[178] |
Market & supply chain. The enabling equipment is not quantum: 300 mm CMOS (GlobalFoundries), fibre-array assembly (Corning), wafer singulation (DISCO), a thin-film-lithium-niobate base of two small suppliers P[518]. Concentration sits in mainstream chains where a photonic quantum company has no bargaining power and no second source for fibre-array attach. G3 and G4 pay for this component — no photonic logical qubit exists without closing the loss gap — G1/G5 do not.
IP & standards. No patent family specific to quantum photonic switching surfaced; the nearest adjacent grant is ORCA Computing's US 12,437,225 on linear-optical encoded GHZ measurements (2025-10-07) fact. Classical MZI-switch IP is extensive and non-quantum; PatSnap's counts are not disaggregated to this layer Pfact. No standards body, no litigation, no shared feed-forward interface.
Roadmaps & track record. PsiQuantum (2024-04, for a useful machine by end-2027) — as of 4 Sep 2026 groundbreaking only on 2026-06-17 after a site change P[183], its Linde cryoplant due for delivery in 2H 2027 Cfact, no 2026 hardware publication; strong components, unevidenced system. Xanadu (2026-08-31, for 1.0× threshold loss in 2030 from 24.1×) — the field's first quantified roadmap, naming this component's gap. QuiX (2025-07, for a 2026 universal system) — Carina delivered July 2026, commissioning pending. Quandela — Lucy delivered, 2025 logical-qubit milestone missed.
Strategic reading. Whoever first ships a non-volatile sub-10 mdB switch owns the chokepoint for both photonic architectures at once, the requirement being encoding-agnostic; hence DARPA's Stage C buys validation of switches, packaging and cryogenics, not an algorithm. If the gap fails to close the branch loses together — no photonic fallback avoids switching — while matter-based modalities face no equivalent single-number gate. Leverage sits with GlobalFoundries, Corning and DISCO.
Outlook & open questions
Confirm/demote in 12–24 months: a sub-50 mdB non-volatile switch; independent replication of the 100 mdB figure; PsiQuantum's Moreton Bay cryoplant delivered in 2H 2027 as promised; a feed-forward loop published under 100 ns. Best case 2029: single-digit-mdB non-volatile switching, Xanadu's 24.1× closing as promised. Worst case: loss plateaus near 100 mdB and photonic fault tolerance slips past 2031 for the whole branch. Open: does barium titanate yield at 300 mm; can fibre-array attach be second-sourced; does extinction bind once loss falls. Watch Xanadu's 2027 loss number.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [172] Xanadu, “Xanadu sets new industry benchmark in photonic chip packaging,” PR Newswire, Jun. 10, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cxanadu-sets-new-industry-benchmark-in-photonic-chip-packaging-302796562.html - [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [176] Quandela, “Quandela delivers Lucy, the most advanced photonic quantum computer worldwide, to EuroHPC and GENCI at CEA's TGCC,” Oct. 23, 2025. [Online]. Available: https://www.quandela.com/
about-us/ Cnewsroom/ quandela-delivers-lucy-the-most-advanced-photonic-quantum-computer-worldwide-to-eurohpc-and-genci-at-ceas-tgcc/ - [177] QuiX Quantum, “QuiX Quantum Delivers Carina Core Hardware Platform to DLR QCI, Advancing Europe's Universal Photonic Quantum Computing Roadmap,” Jul. 14, 2026. [Online]. Available: https://www.quixquantum.com/
news/ Cquix-quantum-delivers-carina-core-hardware-platformto-dlr-qci - [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. D
- [181] M. Abdel-Kareem, “PsiQuantum Secures $125 Million Expanded Agreement with DARPA under QBI Program,” Quantum Computing Report, Jul. 22, 2026. [Online]. Available: https://quantumcomputingreport.com/
psiquantum-secures-125-million-expanded-agreement-with-darpa-under-qbi-program/ P - [183] D. Van Boom, “PsiQuantum ditches Brisbane Airport plan in bid to break ground on supercomputer,” Forbes Australia, May 20, 2026. [Online]. Available: https://www.forbes.com.au/
news/ Pinnovation/ psiquantums-stalled-quantum-plant-to-break-ground-after-location-switch/ - [353] GlobalFoundries, “GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing,” May 21, 2026. [Online]. Available: https://gf.com/
gf-press-release/ Also https://investors.gf.com/globalfoundries-launches-quantum-technology-solutions-to-scale-us-quantum-manufacturing/ news-releases/ . Cnews-release-details/ globalfoundries-launches-quantum-technology-solutions-scale-us - [455] J. Carolan et al., “Universal Linear Optics,” arXiv:1505.01182, May 2015. D
- [516] C. Català-Lahoz et al., “High-speed non-volatile barium titanate field-programmable photonic gate array,” Nat. Photon., vol. 20, no. 8, pp. 932–940, Aug. 2026, doi: 10.1038/s41566-026-01934-y. D
- [517] A. Roy et al., “Zero-change foundry compatible silicon photonics MEMS optical switch,” arXiv:2608.03146, Aug. 2026. P
- [518] optics.org, “Lithium niobate in vogue as thin-film developers raise cash,” Sep. 24, 2024. [Online]. Available: https://optics.org/
news/ Plithium-niobate-in-vogue-as-thin-film-developers-raise-cash - [519] PsiQuantum, “PsiQuantum Raises $1 Billion to Build Million-Qubit Scale, Fault-Tolerant Quantum Computers,” Sep. 10, 2025. [Online]. Available: https://www.psiquantum.com/
news-import/ Cpsiquantum-1b-fundraise
Русский текст загружается…
הטקסט בעברית נטען…
Continuous atom reloading (reservoir + optical conveyor belt)
A continuously fed atom reservoir (optical-lattice conveyor belts from a distant MOT, a cavity-enhanced lattice or a molasses-stopped beam) from which tweezers extract fresh atoms into the array while the stored qubits keep their coherence.
Verdict. Demonstrated as an enabler: Harvard/MIT held over 3,000 atoms for over 2 h and sort 15,000 qubits/s, the authors' own sufficiency figure for a ~10,000-qubit processor; as of 2026-09-26 the largest published QEC run with reservoir reloading found is 64 atoms, and the register's only primary carrier has no entangling result.
MOT = magneto-optical trap; AOD = acousto-optic deflector; DD = dynamical decoupling (XY16 = its 16-pulse sequence); T2 / T2* = echo / Ramsey coherence time; ³P₀ = metastable clock state of Sr and Yb; QEC = quantum error correction; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A tweezer array is normally loaded once and sorted by AOD moves — Caltech's 6,100 atoms fill about half of ~12,000 sites D[138] — and then only loses atoms. This technology adds a reservoir refilled during the computation, from which tweezers extract fresh atoms without disturbing stored qubits. Feeds: lattice conveyor belts from a MOT 0.5 m away (Harvard/MIT, Rb) D[144]; a repetitively filled cavity-enhanced lattice (Atom Computing, ¹⁷¹Yb) D[505]; a molasses-stopped reservoir several hundred µm from the qubits (Princeton, ¹⁷¹Yb) D[506].
Attributes: natural carrier; transport mobility; removes loss; optical control at room temperature; optics manufacturing.
Physics & limits
N atoms of lifetime τ are lost at N/τ: the first loss comes after ~τ/N, and one lifetime leaves e⁻¹ ≈ 37 % of the array S. At Harvard's ~60 s storage lifetime D[144], 3,000 atoms lose 50 per second; at Caltech's 23 min D[138], the first of 10⁴ atoms goes after ~0.14 s S. Operations lose more: entangling errors and readout join trap lifetime as loss sources D[144], and loss is "a significant fraction of all errors" D[506]. Chiu et al. estimate that 15,000 rearranged qubits/s replenish ~10,000 qubits at ~99.5 % gate fidelity and 1 ms per layer S[144] — 1.5 × 10⁻³ replacements per qubit per layer, ~1 % of them due to a 60 s lifetime S. Cryogenic lifetimes of 5,000–6,000 s D[507]D[146] remove only that 1 %.
Light constrains refilling: MOT and imaging light is near-resonant for Rb qubits, so Harvard adds distance, a differential pumping tube tilted ~4° and a 1529 nm light shift of 5P₃/₂ that suppresses scattering >10⁴-fold D[144]. The Yb ³P₀ qubit is isolated from cooling and imaging light D[506]; stored ⁸⁸Sr is shelved in ³P₀ (13 s lifetime) with the MOT repumper off D[259].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2021-06 | Tweezers at ~4 K, lifetime >6,000 s | Institut d'Optique | D[507] |
| 2024-01 | 1,225 Yb sites, 99 % filled from a lattice reservoir | Atom Computing | D[505] |
| 2024-02 | >1,000 Sr atoms, ~130 refilled per 2.5 s cycle, >1.5 h | MPQ | D[259] |
| 2024-03 | >6,100 atoms, single load, 23 min lifetime | Caltech | D[138] |
| 2025-06 | 7.3 × 10⁴ atoms/s extracted; 1 ms per replacement | Princeton | D[506] |
| 2025-09 | 3 × 10⁵ atoms/s into tweezers; >3 × 10⁴ qubits/s; >3,000 atoms for >2 h | Harvard/MIT | D[144] |
| 2026-04 | 1,024-atom defect-free arrays at 4 K, ~5,000 s | Lim et al. | D[146] |
| 2026-06 | Toric code, 90 cycles with reservoir reloading | Atom Computing/Microsoft | D[148] |
Harvard/MIT sort 15,000 qubits/s in 600-qubit batches D[144], one per ~40 ms S; one of six 540-site storage subarrays is refilled every ~80 ms D[144], so each atom is replaced about every 0.5 s — 6.75 × 10³ atoms/s over >2 h, the ~5 × 10⁷ reported S. The run proves throughput and 99.3 % filling D[144], not hours-long qubit survival S.
Manufacturing, materials & supply chain
Vacuum and optics, not a fabricated part: a second MOT chamber behind a differential pumping tube and two lattice stages, ~39 cm and ~17 cm, delivering ~2.5 × 10⁶ atoms every ~150 ms D[144]; Atom Computing's MOT sits 30 cm below its array D[148]. Delivery, ~1.7 × 10⁷ atoms/s, exceeds tweezer loading ~50-fold, so extraction bounds the flux S. Optical access to the science region, shared with tweezers, Rydberg beams and imaging, is the scaling limit S.
Control, readout & I/O burden
Three synchronised loops — reservoir delivery (~150 ms), batch extraction, imaging and sorting, storage refill (~80 ms) — interleave with XY16 DD on stored qubits D[144]. Every fresh atom is imaged: 25–50 camera frames and rearrangement solutions per second S. Yb needs no shield; Princeton prepares 30 complete arrays per second D[506].
Role in the stack
Slot 4 of Rydberg tweezer array — alkali (Rb/Cs) and Rydberg tweezer array — alkaline-earth(-like) (Yb/Sr), erasure-native, beside cx_aod. It requires ct_laser (lattice and tweezer light) and fab_optics (second MOT region, conveyor optics, vacuum). It replaces one-shot loading (the edge from cx_aod), though every machine keeps AOD tweezers for extraction and sorting. The gap ledger holds: AOD moves span hundreds of micrometres in 0.4–1.6 ms; a conveyor carries a ~10⁶-atom reservoir half a metre D[144]. Filed by function: a lattice reservoir or a molasses-stopped beam does the same job. Conflicts with alkali (scattered MOT light) and ae_atom (repumper depleting stored atoms) are mitigated (2025-09; 2024-02). It provides reload flux and run length: >2 h, >5 × 10⁷ atoms through 3,000 sites D[144].
Reload closes the loop erasure conversion opens: converting 98 % of ¹⁷¹Yb errors to erasures raised the simulated threshold from 0.937 % to 4.15 % S[8]; Atom Computing corrected on average 1.8 lost atoms across 24 logical qubits D[149]; delayed-erasure decoding uses loss of unknown timing S[508]. Each converted error is a hole that mid-circuit imaging locates and the reservoir fills D[148]; without reload, conversion shortens the run.
Register: two machines — the continuously reloaded 3,000-atom machine (Harvard/MIT, primary, demonstrated Sep 2025), cell ✅ verified (arXiv:2506.20660, Fig. 1a), two-qubit error n/a — an enabler without an entangling result; and Phoenix (Gen-1) and Gen-2 (Atom Computing, alternate), cell ✅.
Evidence — how the numbers were measured
The discriminating test is stored-qubit coherence with reload on versus off. Harvard (Rb, XY16): T2 1.34(4) s reference, 1.15(3) s with the MOT, 1.09(3) s adding imaging and shielding D[144] — 14–19 % lower, ~4–5σ S. Princeton (Yb): echo T2 5.4(9) versus 7(1) s, T2* 0.73(2) versus 0.69(2) s, unchanged within 1.5σ D[506]. No gate fidelity on stored qubits during reload is published, as of 2026-09-26. The one logical figure: 0.63(3) % and 0.64(4) % error per cycle over up to 90 cycles with reloading, on 32- and 64-atom toric codes, cycle time unstated D[148]. Flux is quoted as atoms, initialised or sorted qubits, a tenfold spread; the Atlas uses initialised qubits/s.
The Harvard/MIT batch cadence is derived from flux and batch size, not quoted by the source.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Harvard University / MIT | research | US | Two-stage lattice conveyor, 3,000-atom continuous array | D[144] |
| QuEra Computing | developer | US | Libra roadmap with a reloading reservoir | R[509] |
| Atom Computing (with Microsoft) | developer | US | Lattice reservoir; toric code with reloading | D[505]D[148] |
| Princeton University | research | US | Yb metastable reservoir | D[506] |
| MPQ | research | DE | Refilled Sr lattice array | D[259] |
| Caltech | research | US | Single-load reference array | D[138] |
Money. No dated financial item is specific to continuous reloading as of 2026-09-26.
Market & supply chain. No separate market: makers build reservoirs from the laser, modulator and vacuum classes they already buy. The technology pays into G1, G3 and G7 by lifting the depth bound.
IP & standards. No patent count was checked; no standard defines how reload flux or coherence during reload is reported, as of 2026-09-26.
Roadmaps & track record. (for 2028 · QuEra Libra · >10,000 physical, 256 logical qubits at 10⁻⁶, fresh qubits loaded "mid-circuit from Libra's reloading reservoir") R[509]; Chiu et al.: ~99.9 % fidelity with 80,000 qubits/s could run several hundred surface-code logical qubits at 10⁻⁸ S[144]. Flux is ahead of plan; integration is behind — gates plus reload are published only at 64 atoms.
Strategic reading. Reload makes loss the cheapest error to correct, as both atom architectures' QEC plans assume. The flux record comes from a group whose senior authors co-founded QuEra D[144]; only Atom Computing's reservoir has run inside QEC. If coherence and gate fidelity hold under reload at 10³–10⁴ atoms, depth stops being the atom platform's weakness; if not, runs stay bounded by τ/N.
Outlook & open questions
Confirm if, by 2027-12-31, a published experiment runs gates or QEC rounds on ≥1,000 atoms while reloading, with logical error flat across reload events; demote if QuEra's 2028 reservoir has no such precursor by then. Open questions. (1) Does flux scale with array area, or do extraction and imaging cap it? (2) What gate-fidelity tax do stored qubits pay beside an active preparation zone? (3) What does re-cooling fresh atoms cost in time? (4) Can a conveyor share optical access with a zoned architecture at 10⁴ sites? (5) At 5,000–6,000 s cryogenic lifetimes, is operation-induced loss the whole budget?
References
- [8] Y. Wu, S. Kolkowitz, S. Puri, and J. D. Thompson, “Erasure conversion for fault-tolerant quantum computing in alkaline earth Rydberg atom arrays,” Nat. Commun., vol. 13, Art. no. 4657, 2022, doi: 10.1038/s41467-022-32094-6. arXiv:2201.03540. S
- [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [146] D. Lim et al., “Defect-free arrays at the thousand-atom scale in a 4-K cryogenic environment,” PRX Quantum, vol. 7, Art. no. 033032, Apr. 2026, doi: 10.1103/45t1-vl5y. arXiv:2604.07205. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [149] B. W. Reichardt et al., “Fault-tolerant quantum computation with a neutral atom processor,” arXiv:2411.11822, Nov. 2024. D
- [259] F. Gyger et al., “Continuous operation of large-scale atom arrays in optical lattices,” Phys. Rev. Research, vol. 6, no. 3, Art. no. 033104, Feb. 2024, doi: 10.1103/PhysRevResearch.6.033104. arXiv:2402.04994. D
- [505] M. A. Norcia et al., “Iterative assembly of ¹⁷¹Yb atom arrays with cavity-enhanced optical lattices,” PRX Quantum, vol. 5, no. 3, Art. no. 030316, Jan. 2024, doi: 10.1103/PRXQuantum.5.030316. arXiv:2401.16177. D
- [506] Y. Li, Y. Bao, M. Peper, C. Li, and J. D. Thompson, “Fast, continuous and coherent atom replacement in a neutral atom qubit array,” arXiv:2506.15633, Jun. 2025. D
- [507] K.-N. Schymik et al., “Single Atoms with 6000-Second Trapping Lifetimes in Optical-Tweezer Arrays at Cryogenic Temperatures,” Phys. Rev. Appl., vol. 16, no. 3, Art. no. 034013, Jun. 2021, doi: 10.1103/PhysRevApplied.16.034013. arXiv:2106.07414. D
- [508] G. Baranes et al., “Leveraging Qubit Loss Detection in Fault-Tolerant Quantum Algorithms,” Phys. Rev. X, vol. 16, no. 1, Art. no. 011002, Jan. 2026, doi: 10.1103/ycwc-3myc. arXiv:2502.20558. S
- [509] QuEra Computing, “Our Quantum Roadmap,” Sep. 15, 2026. [Online]. Available: https://www.quera.com/
our-quantum-roadmap R
Русский текст загружается…
הטקסט בעברית נטען…
Crossbar shared-line control (spins)
Row- and column-shared plunger and barrier lines address a two-dimensional dot array with line count scaling as the square root of dot count, trading addressing granularity for wireability.
Verdict. Removes the I/O wall on paper and in a 1,058-site chip, but no crossbar array has published a two-qubit gate, a crosstalk figure or an independent replication.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A crossbar shares gate lines across rows and columns of a dot array: an n×m grid needs O(n+m) lines, not O(nm), at the price that every pulse reaches every dot on the line. Selectivity comes from cross-capacitance compensation and the operating-point spread between tiles: addressing becomes calibration. Proposed for spin qubits by Li et al. (QuTech, Sci. Adv. 2018); first demonstrated by Borsoi et al. (Veldhorst group, QuTech/TU Delft): 16 germanium dots on 23 lines, published January 2024 D[520]. Attributes: connectivity — shared row/column addressing, carrier immobile; control and error — low-frequency drive from room temperature, coherent shared-line crosstalk over ordinary charge noise, CMOS fabrication.
Physics & limits
Line count follows a Rent exponent near 0.5: T = 6√g − 1 terminals for g dots D[520], and n+m+7 = 53 lines for the 23×23 QARPET array, capacity 1,058 sites at 2×10⁶ tiles/mm² D[521]. The binding constraint is uniformity, not wiring: one shared voltage must land inside every tile's operating window at once, so threshold spread sets how many tiles a line serves. QARPET's 38-of-40 addressable tiles show T2* 4.43–5.75 µs and Hahn-echo T2 10.11–12.69 µs, comparable to individually wired germanium devices: sharing lines costs no coherence D[521]. What it adds is coherent error correlated along a whole row or column, the structure decoders assume away. On-chip demultiplexing would move the floor.
Engineering state of the art
table
Dominant term: addressing coverage. Neither device published a two-qubit gate on a shared line.
Not published: a shared-line crosstalk figure for any crossbar array; the conflict with per-pair exchange calibration follows from the addressing scheme, not from a measurement.
Manufacturing, materials & supply chain
Both devices are Ge/SiGe heterostructures made in a university cleanroom, not on a 300 mm line, and no foundry has announced a crossbar process step as of 4 Sep 2026 — GlobalFoundries' Quantum Technology Solutions unit, with cryogenic control ICs and packaging, is the closest named capability C[353]. Control burden is the whole point, and its cost reappears as sequencing: one row and one column select at a time, so at 10³ tiles parallel operation needs on-chip decoding, and at 10⁴–10⁶ the wall is addressing bandwidth, not connector count. No demultiplexer has been demonstrated inside an array.
Role in the stack
Requires a gate-defined quantum-dot spin carrier; replaces one-line-per-electrode wiring; conflicts with per-pair exchange calibration, since a shared barrier cannot deliver an independently tuned pulse to every pair at once. Belongs to the silicon and germanium quantum-dot spin architecture. Its clock contribution is a sequencing multiplier on derived clock = sum of the syndrome round: gate layers + transport + readout + reset (8.5 µs here, readout-set), unquantified in any publication. Verification: 1,058 is a site capacity, not a qubit count, and no crossbar has published a two-qubit fidelity, a crosstalk figure or a replication. The "only some pairs work" result often cited here — one of four pairs gated on imec's eight-qubit 300 mm device D[197] — is individually wired, not a crossbar.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| QuTech/TU Delft | research | Netherlands | Built both crossbar devices, including QARPET | D[521] |
| Groove Quantum | developer | Netherlands | Commercialises the germanium dot platform | fact |
| GlobalFoundries | supplier | USA | Cryogenic control ICs and packaging | C[353] |
| Quantum Machines | supplier | Israel | Sequencing hardware for shared-line addressing | C[449] |
Money. 2026-04-30 · Groove Quantum · venture round · €16 M · investors undisclosed · €26 M cumulative · closed fact. 2026-05-21 · GlobalFoundries · CHIPS letter of intent · $375 M · US Commerce · non-binding fact.
Market & supply chain. No crossbar-specific equipment vendor exists; the scheme sets how many fridge lines an array needs, making cryogenic control ICs the contested layer C[353]. Pays into G3 and G4 only — below ~10³ dots individual wiring is cheaper and better characterised.
IP & standards. No dated crossbar patent family found in a named database as of 4 Sep 2026; the shared-line principle is commodity-memory word-line addressing, long out of patent.
Roadmaps & track record. QuTech (2026-02-12 · QARPET as a shared benchmarking chip · delivered, no scaling roadmap) D[521]. Diraq's 2029 roadmap names no wiring scheme Rfact. The demonstrations are modest and honestly stated; no vendor has committed to a crossbar.
Strategic reading. If crossbars scale, leverage shifts from rack-electronics vendors to whichever foundry can put demultiplexers at millikelvin; if uniformity blocks them, per-qubit wiring with cold multiplexing — the HRL/IBM route — wins and the rack vendors keep their position.
Outlook & open questions
Confirm or demote in 12–24 months: two tiles gated independently through one shared line; a published crosstalk figure; a foundry crossbar step by 2027. Best case 2029: on-chip demultiplexing addresses >10⁴ dots with hundreds of lines. Worst case: crossbars stay a wireability demonstration while cold per-qubit multiplexing wins. Open: (1) what fraction of tiles stays addressable as arrays grow; (2) whether row-correlated error breaks decoder assumptions; (3) whether demultiplexers fit the millikelvin power budget.
References
- [197] A. Nickl et al., “Eight-qubit operation of a 300 mm SiMOS foundry-fabricated device,” Nat. Commun., vol. 17, no. 1, Art. no. 5878, Jul. 2026, doi: 10.1038/s41467-026-74597-6. D
- [353] GlobalFoundries, “GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing,” May 21, 2026. [Online]. Available: https://gf.com/
gf-press-release/ Also https://investors.gf.com/globalfoundries-launches-quantum-technology-solutions-to-scale-us-quantum-manufacturing/ news-releases/ . Cnews-release-details/ globalfoundries-launches-quantum-technology-solutions-scale-us - [449] Quantum Machines, “Semiconductor Spin Qubits,” Aug. 11, 2026. [Online]. Available: https://www.quantum-machines.co/
qubit-types/ Csemiconductor-spin-qubits/ - [520] F. Borsoi et al., “Shared control of a 16 semiconductor quantum dot crossbar array,” Nat. Nanotechnol., vol. 19, no. 1, pp. 21–27, Jan. 2024, doi: 10.1038/s41565-023-01491-3. D
- [521] A. Tosato et al., “A crossbar chip for benchmarking semiconductor spin qubits,” Nat. Electron., vol. 9, no. 3, pp. 324–333, Mar. 2026, doi: 10.1038/s41928-026-01569-5. D
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הטקסט בעברית נטען…
Ion-chain motional bus (all-to-all in chain)
A shared collective motional mode entangles any pair in one trap, giving genuine all-to-all connectivity at the price of gate time growing with chain length.
Verdict. Real all-to-all to ~30 benchmarked ions and ~100 claimed; IonQ's 10,000-ions-on-one-chip target for 2027 has no published heating, gate-time or mode-spectrum data behind it.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Ions in one trap share collective motional modes; a spin-dependent force through a shared mode entangles any pair without moving them, so connectivity is all-to-all by construction. Cirac–Zoller (1995) and Mølmer–Sørensen (1999) gave the mechanism; chain gates date from 2003.
Bus mobility, one shared mode, no transport; MEMS-adjacent trap fabrication.
No control modality or readout of its own; coherent error — mode addressing and heating, not loss.
Physics & limits
N ions carry N motional modes in a fixed bandwidth, so mode spacing falls as ~1/N: a gate must resolve one mode spectrally, costing time, or close all with shaped pulses, costing power and calibration. Gate time therefore rises with chain length — 550–883 µs, median 672 µs, on a 30-ion chain against 110 µs for one qubit D[100]. Electrode noise heats the shared mode, and error grows with N as every pair borrows the same excitation. Above a critical anisotropy the chain buckles into a zigzag: long chains need weak axial confinement, hence lower frequencies and slower gates. The floor moves with laser-free electronic gates (2Q 8.4×10⁻⁵ D[102]) and shaped pulses.
Engineering state of the art
table
| Date | Figure | Who | Tag+key |
|---|---|---|---|
| 2023-08 | 30-ion chain, 435 pairs benchmarked; MS 550–883 µs | IonQ Forte | D[100] |
| 2024 | 512-ion 2D crystal, analogue only | Tsinghua | D[121] |
| 2025-10 | 2Q error 8.4×10⁻⁵, electronic gate, no cooling | IonQ/Oxford Ionics | D[102] |
| 2026-06 | qLDPC memory break-even within error bars, 3.95±0.68 s (one code) vs 3.84±0.48 s physical (revised Sep 2026) | IonQ | D[109] |
Tempo: 100 ions, #AQ 64, no gate time C[101]. Dominant term: gate time, not fidelity.
The chain's motional modes can also serve as a bosonic register rather than only as a gate bus. A three-ion ¹⁷¹Yb⁺ chain encoded a scalar field in one set of transverse modes (2.80–3.05 MHz) and evolved it with spin–phonon gates, avoiding the truncation of bosons into qubits, while Mølmer–Sørensen gates used the other transverse set so that the two do not interfere; measured phonon occupations matched simulation up to eight quanta per mode, and a fourth bosonic mode had to run in a separate circuit D[884]. The register is short-lived: motional coherence is ≲ 10 ms against ≈ 1.5 s of idle spin coherence D[884].
The 100-ion Tempo chain is a company claim; the largest independently benchmarked chain is 30 ions. Not published: Tempo's two-qubit gate time and per-pair fidelity, beyond #AQ 64 and a "99.9% fidelity" headline; KISTI's Tempo-100 contract value; and any heating, mode-spectrum or interconnect data that reconciles IonQ's 10,000-ions-on-one-chip 2027 target with the chain-length trade-off.
Manufacturing, materials & supply chain
IonQ closed its SkyWater acquisition on 2026-07-31, naming microfabricated-trap fabs in Minnesota, Florida and Texas, no wafer size or node disclosed Cfact. Control splits two ways: laser MS gates need several wavelengths and per-ion optics; electronic gates use on-chip current and microwave lines. At 10³ ions the wall is the mode spectrum, not wiring: the answer is many short chains joined by shuttling or photonics — IonQ's first two-system entanglement (2026-04-14) disclosed no rate or fidelity Cfact. Export exposure sits with the finished machine: ECCN 4A906 controls it only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact; no rule names ion traps G[301].
Role in the stack
It is the primary connectivity of two trapped-ion architectures: the linear Paul trap with individual laser addressing and electronic qubit control (laser-free, microwave-driven gates). Requires nothing; provides the non-local checks bivariate bicycle qLDPC and high-rate transversal codes assume, as IonQ's eight codes on one 40-ion chain show, run without hardware reconfiguration, one of them at break-even within error bars D[109]. It competes with QCCD shuttling, which buys chain length with transport time: Helios gets all-to-all from a ring plus junction at ~55 ms per full-width layer D[97], and on H2 transport took ~60% of circuit time on average D[110]. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 1.5×10⁻³ s, gate layers 1.4 ms of it. Verification: Forte's figure is an all-pairs benchmark over 435 pairs, so position effects are visible; Tempo publishes #AQ 64 and "99.9% fidelity" with no gate time or per-pair data — a disclosure gap, not a dispute.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| IonQ | developer | US | Forte and Tempo chains; owns SkyWater | C[101] |
| Oxford Ionics | developer | UK | Electronic laser-free gates; IonQ unit | D[102] |
| Quantinuum | developer | US/UK | Rival transport architecture | D[97] |
| eleQtron | developer | Germany | MAGIC microwave ion control | C[129] |
Money. 2025-09-17 · IonQ · M&A, Oxford Ionics · $1.075 B USD · closed fact. 2025-10-12 · IonQ · equity · $2.0 B USD at $93/share · closed fact. 2025-11-06 · DARPA · QBI Stage B · up to $15 M each · IonQ and Quantinuum among eleven G[65]. 2026-05-05 · eleQtron · Series A · €57 M · closed C[129]. 2026-07-31 · IonQ · M&A, SkyWater · ~$1.8 B USD · closed fact. 2026-08 · IonQ · Q2-2026 revenue $80.1 M (+287% YoY), cash $3.0 B C[326].
Market & supply chain. The bus buys a trap chip, lasers or microwave lines and one vacuum system; concentration risk sits with narrowband laser and AOM vendors, whom electronic gates remove. It pays into G3 and G5.
IP & standards. PatSnap names IonQ the filing leader on motional-mode engineering Pfact; no standards body.
Roadmaps & track record. (2025-06 · for 2026 · 256 qubits at 99.99% · slipped to H1 2027); (for 2027 · 10,000 on one chip · no heating data); (for 2030 · 2 M physical) R[132]. Fidelity claims land, scale dates do not: the 2020 roadmap promised 4,000 qubits by 2026, missed ~40×.
Strategic reading. If chain all-to-all holds to a few hundred ions, ion vendors keep the connectivity advantage that makes high-rate codes cheap, and IonQ's owned fabs speed trap iteration. If not, the bus is a module-internal detail and value moves to interconnects.
Outlook & open questions
Confirm if IonQ publishes Tempo gate times and per-pair fidelities, or ships 256 qubits in H1 2027; demote if disclosure stays headline-only. Best case 2029: electronic gates on owned-fab traps carry chains past 100 ions. Worst case: chains stall near 30–50 ions. Open: how does mode heating scale at 100 ions?
References
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [100] J.-S. Chen et al., “Benchmarking a trapped-ion quantum computer with 30 qubits,” Quantum, vol. 8, Art. no. 1516, Nov. 2024, doi: 10.22331/q-2024-11-07-1516. arXiv:2308.05071. D
- [101] IonQ, “IonQ Tempo: 100-Qubit Quantum Computer (#AQ 64).” [Online]. Available: https://ionq.com/
quantum-systems/ Ctempo - [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [109] E. Tham et al., “Breakeven demonstration of quantum low-density parity-check codes,” arXiv:2606.06455, Jun. 2026. D
- [110] S. A. Moses et al., “A Race Track Trapped-Ion Quantum Processor,” Phys. Rev. X, vol. 13, Art. no. 041052, Dec. 2023, doi: 10.1103/PhysRevX.13.041052. arXiv:2305.03828. D
- [121] S.-A. Guo et al., “A site-resolved two-dimensional quantum simulator with hundreds of trapped ions,” Nature, vol. 630, no. 8017, pp. 613–618, May 2024, doi: 10.1038/s41586-024-07459-0. D
- [129] A. Cordes, “Quantum computing scale-up eleQtron secures €57 million in one of the largest Series A funding rounds worldwide,” eleQtron, May 5, 2026. [Online]. Available: https://eleqtron.com/
en/ Cquantum-computing-scale-up-eleqtron-secures-57-million-in-one-of-the-largest-series-a-funding-rounds-worldwide/ - [132] IonQ, “IonQ's Accelerated Roadmap: Turning Quantum Ambition into Reality,” Jun. 13, 2025. [Online]. Available: https://www.ionq.com/
blog/ Rionqs-accelerated-roadmap-turning-quantum-ambition-into-reality - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [326] IonQ, “IonQ Announces Record Second Quarter 2026 Revenues, Growing 287% YoY,” Aug. 5, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-announces-record-second-quarter-2026-revenues-growing-287-yoy - [884] A. T. Than et al., “Quantum field theory dynamics on a spin–phonon quantum computer,” Nat. Phys., Sep. 2026, doi: 10.1038/s41567-026-03402-4. arXiv:2509.11477. D
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הטקסט בעברית נטען…
Cryo-CMOS controller (4 K / mK)
Commercial CMOS ASICs inside the cryostat that synthesise qubit control waveforms and bias next to the qubits, replacing room-temperature racks and their coaxial lines.
Verdict. Proven end-to-end on 18 spin qubits and at room-temperature parity on 156 transmons for flux only; the binding constraint is milliwatts per qubit against a 2 W 4 K plant. Demote if nothing drives >50 qubits end-to-end by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A cryo-CMOS controller is a silicon ASIC on a cold plate in the refrigerator, generating microwave, flux and gate-bias waveforms next to the qubits. Nothing quantum happens in it: the gain is thermal and topological. It became hardware with Horse Ridge (Intel/QuTech, 22 nm FinFET, 4 K, 2019–2020) C[548] and Gooseberry (Microsoft/Sydney, 100 mK) D[549].
Attributes (a affinity; b time; c readout; d mobility; e control @ placement; f error structure; g manufacturing):
- a = 1.0, wholly fabricated; a foundry part, not a carrier.
- b = none; it holds no quantum state.
- c = none; it serves the host's readout.
- d = none; fixed to a cold plate.
- e = microwave @ 4 K; placement is the technology.
- f = coherent: amplitude, phase, timing, crosstalk.
- g = CMOS, 130 nm to 14 nm.
Rank 5 of 111; shared by the superconducting and spin architectures.
Physics & limits
The floor is a heat budget, not a coherence time. Plants are small: 2 W at 4 K (Bluefors XLD1000sl), 24 W (IBM Goldeneye concept), 200 W (Fermilab Colossus) S[550]. The only power attached to a working two-qubit gate is IBM's 23 mW per qubit D[296]; the same review's optimistic case is 5 mW, its lowest demonstrations under 2 mW S[550]. A 2 W plant thus holds ~87 qubits at 23 mW, ~1,000 at 2 mW.
At millikelvin the regime changes kind: baseband, duty-cycled cells that hold a gate voltage and refresh it — 18 nW per cell for 100 mV pulses at 100 mK D[549], ~20 nW MHz⁻¹ per cell at 7 mK D[551].
Failure is coherent: drift and quantisation become rotation-angle error — a Delft converter drifted 60 µV/s to 18 mV/s C[552] — jitter becomes over-rotation, finite isolation crosstalk. The stochastic channel is back-action, worth 0.07% of single-qubit fidelity D[551]. The floor moves with a cold-characterised process C[553] or superconducting logic at ~1.6 µW/qubit S[550].
Engineering state of the art
Best demonstrated: HRL's 130 nm RF CMOS controller at 4 K — ≤3.5 W, 366 DACs, a 250 MHz sequencer — driving 54 dots as 18 exchange-only qubits at mean single-qubit error 2×10⁻⁴ and mean CNOT 3×10⁻³ (best reproducible 9×10⁻⁴), closing a distance-5 repetition code at 5.0×10⁻³ over 200 rounds, Λ₅/₃ = 4.7, with nothing warm in the loop D[190] fact. IBM ran 14 nm flux-bias ASICs on a 156-qubit Heron R2 at median two-qubit error ≈2.3×10⁻³, parity with warm electronics on the same processor C[527]. Typical at scale: none — everything else above ~10 qubits runs from warm racks Dfact.
table
| Year | Figure | Who | Tag | Src |
|---|---|---|---|---|
| 2021-01-25 | 100 mK, 18 nW/cell, 100 mV pulses | Microsoft | D | [549] |
| 2024-02-14 | Gate from 4 K: 23 mW/qubit, 1Q 8×10⁻⁴ | IBM | D | [296] |
| 2025-06-25 | 7 mK, ~20 nW MHz⁻¹/cell, 0.07% fidelity cost | Sydney | D | [551] |
| 2026-03-16 | Flux ASICs, 156 qubits, median 2Q 2.3×10⁻³ | IBM | C | [527] |
| 2026-07-29 | ≤3.5 W, 366 DACs, 18 qubits, Λ₅/₃ = 4.7 | HRL | D | [190] |
Dominant term: channel-to-channel non-uniformity — mean CNOT 3×10⁻³ against best reproducible 9×10⁻⁴, ~80% of it extrinsic, from control and calibration D[190].
Manufacturing, materials & supply chain
No exotic process; the difficulty is a commercial node run 300 K outside its qualified range: 130 nm RF CMOS (HRL) D[190], 14 nm FinFET (IBM) D[296], 22 nm FinFET (Horse Ridge, Delft converters) C[548], [552], 28 nm FD-SOI (Gooseberry, Sydney) D[549], [551], 22FDX (Equal1) C[273]. The scarce input is the model, not the wafer: design kits stop at −40 °C, so actors keep private cryogenic models or buy a cryo-optimised process — SemiQon quotes 0.32 mV/dec subthreshold swing at 420 mK against ~60 mV/dec at 300 K C[553]. Yield and cost per channel are unpublished. Concentration sits in foundries willing to run unqualified corners and in dilution refrigerators Cfact. Export exposure is direct: the BIS rule of 2024-09-06 created ECCN 3A901.a for CMOS circuits "designed to operate at an ambient temperature equal to or less (better) than 4.5 K", catching this node by design intent rather than performance, beside controls on refrigerators and cryogenic probers G[301] fact. The controlled item can therefore be a design file.
Control, readout & I/O burden
HRL removed warm waveform generation, but the cable count did not fall: 296 lines for 18 qubits, ~16 each — the win was the rack, not the wiring D[190]. The wiring win is a millikelvin one, where demultiplexing turns N terminals into ~log N inputs: Pando Tree's 64 terminals at 10–20 mK C[272], Delft's 648 devices from 96 voltages under 120 µW C[552]. Latency is the second argument: 200 code rounds closed with nothing warm in the loop D[190], against 3.84 µs mean round trip on a warm GPU link fact. The walls follow the heat budget: 10³ qubits needs the sub-2 mW class on a 2 W plant; 10⁴ needs Goldeneye- or Colossus-class cooling at ≤5 mW/qubit; 10⁶ means ~90 modules of 10,000 qubits dissipating 50 W each at 4 K — outside anything sold in 2026 S[550].
Role in the stack
Two architectures: superconducting transmons (IBM, Google, IQM) and silicon or germanium quantum-dot spins (Intel, Diraq, Quantum Motion, HRL, Quobly, Equal1). It requires a 300 mm CMOS foundry — a dependency spins already carry, so they get cryo-CMOS as a by-product while superconducting vendors fund it separately. It provides the cold digital substrate a cryogenic decoder needs: a 4 K predecoder costed under 0.56 mW for 3,780× syndrome-bandwidth reduction Sfact. It replaces room-temperature control, the only part of this layer with revenue, and competes with single-flux-quantum control, published above 99% at millikelvin Dfact; switching buys cold silicon on an 18–24-month tape-out loop, paid for in cooling budget that would otherwise buy qubits. The node is a non-quantum object whose only distinguishing attribute is placement at 4 K. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset; this node does not bind it — 4.0 ns sequencer granularity D[190] against a 0.65 µs round whose largest term is 282 ns of readout. Empty slots next door: a cryogenic readout digitiser and a standard cold digital interface.
Evidence — how the numbers were measured
Every headline number is measured through the qubit, never on the controller: interleaved randomised benchmarking, whose 1.71 and 17.51 instructions per Clifford (single- and two-qubit) must accompany any comparison D[296]; repetition-code Λ scaling across distances 3 and 5 for HRL D[190]; and, for IBM's 2026 flux result, an A/B comparison against warm electronics on the same processor — the right design, and the rarest.
Randomised benchmarking averages over Cliffords and is blind to slow coherent drift, so converter drift C[552] appears in no RB number; back-action, duty-cycle transients, channel non-uniformity and cold reliability need bespoke measurements D[551]. Replication is reasonable at 4 K (IBM, HRL) and at millikelvin (Microsoft, Sydney, Delft, QuTech C[554]).
Conflicts: IBM's 23 mW per qubit D[296] against 5 mW and under 2 mW S[550] are different quantities — active versus idle, drive-only versus full chain — with no common definition; 23 mW is used here as the only figure tied to a working gate. Equal1's fidelity figures are product-page claims C[273] against a published six-qubit device at 0.3 K fact.
On HRL's 54-dot exchange-only chip run by its 4 K CMOS controller, the measured error per exchange in a 12-spin cross-entropy benchmark (1.54×10⁻⁴) was more than ten times what component-level noise predicts (1.15×10⁻⁵) and mostly coherent; the authors suspect the cryo-controller and the signal lines. The controller's memory holds only about 1,000 unique pulse instructions once state preparation and measurement are loaded, so deep sequences had to be built from recursive subroutines P[900].
Gooseberry's 18 nW per cell D[549] and the Sydney chip's ~20 nW MHz⁻¹ per cell D[551] are different quantities. The cooling powers of the Bluefors XLD1000sl, IBM Goldeneye and Fermilab Colossus come from the resource review S[550], not from the makers' specifications. IBM's 2026 cryo-CMOS flux result, including its 14 nm FinFET attribution, exists only as conference abstracts as of 2026-09-03 C[527]. SEEQC's S-1 amendment of 2026-08-28 gives $4.2 M revenue in 2025 and $18.1 M cash at 2026-06-30 C[556] P[557] fact; the $1 B enterprise value and $65 M PIPE describe the terminated Allegro merger. Quantum Machines' ">50% of companies developing quantum computers" is a company claim C[528]. Not published: the cooling power at 4 K of IBM's modular cryogenics; SemiQon's process node, fab location and the size of its 2026-07 PostScriptum investment; SEEQC's offering size; the revenue of Quantum Machines and any comparable figure from Zurich Instruments, Keysight or QBLOX, so the warm-control market cannot be sized; the power, channel count and process node of the QuTech/Fujitsu diamond cryo-CMOS ISSCC 2026 paper beyond its institutional release C[554]; a dated cryo-CMOS patent-family count — PatSnap gives only regional tallies with a completeness disclaimer P[563]; and HRL's controller cost, tape-out schedule and whether IBM retains the 130 nm design, after the acquisition that closed on 2026-08-26 C[10] fact.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with it | Evidence |
|---|---|---|---|---|
| HRL Laboratories | developer | US | 4 K controller sequencing 18 qubits | D[190] fact |
| IBM Quantum | developer | US | 14 nm flux ASICs; acquired HRL | D[296] C[10], [527] fact |
| Intel | developer | US | Horse Ridge, Pando Tree | C[272] fact |
| Microsoft | research | US | Gooseberry at 100 mK; charge-lock patent | D[549] G[555] |
| University of Sydney | research | AU | mK CMOS driving Diraq spins | D[551] |
| Equal1 | developer | IE | Qubits and control on one die | C[273] fact |
| Quantum Machines | supplier | IL | Warm racks this node displaces | C[528] |
Money.
- 2025-02-25 · Quantum Machines · Series C · $170 M · PSG Equity · $280 M cumulative C[528]
- 2025-11-06 · DARPA QBI Stage B · up to $15 M each · eleven teams incl. IBM, Diraq fact
- 2026-05-21 · GlobalFoundries; Diraq · CHIPS letters of intent · $375 M; $38 M · LOI fact
- 2026-06-29 · SEEQC · S-1 for Nasdaq beside an Allegro merger · $1 B enterprise value, $65 M PIPE C[556] P[557]; SPAC merger terminated 2026-08-25, S-1 continues, IPO unpriced as of 30 Sep 2026 fact
- 2026-07-23 · IBM · acquires HRL Laboratories · undisclosed · closed 2026-08-26 C[10] factfact
Market & supply chain. Nobody sells a cryo-CMOS controller as of 3 Sep 2026; the layer's revenue is warm racks from Quantum Machines, Zurich Instruments, Keysight and QBLOX, and Quantum Machines alone has raised $280 M C[528], [558]. Cryo-CMOS itself is captive R&D; merchant offers are pre-revenue: SemiQon, FrostByte (€1.3 M) and Rhonexum ($1 M) C[553], [559] P[560]. G3, G4 and G7 pay for it; G1, G2 and G5 do not.
IP & standards. Microsoft Technology Licensing holds US 11,838,022 on the cryogenic-CMOS qubit interface (granted 2023-12-05), the charge-lock architecture behind Gooseberry G[555]; MIT holds US 12,705,525 on baseband pulsing (2026-08-11) G[561]; Intel's closed-loop calibration filing is an application only G[562]. No database publishes a dated family count P[563]. Standards: none, and no agreed power-per-qubit definition.
Roadmaps & track record.
- Intel: 2020-12-03 · Horse Ridge II for scaled spin systems · no successor fact.
- Microsoft: 2021-01-27 · Gooseberry to "thousands of qubits" · not delivered C[564].
- IBM: 2024-02-14 · cryo-CMOS as the route to scalable control · partly delivered, flux only D[296] C[527].
- HRL: 2026-04-17 · a processor with no warm waveform generators · delivered D[190].
Credibility: HRL alone named a dated deliverable and shipped it, and IBM bought it; IBM publishes A/B comparisons, not headline claims; Intel has no peer-reviewed fidelity on a Horse Ridge part; Microsoft's line is five years dormant.
Strategic reading. Winners if cold control becomes standard: integrated CMOS houses — IBM with HRL, Intel if it re-engages — and spin companies whose qubits and controllers share a line. Losers: warm-rack vendors, protected only while nobody below a thousand qubits needs an ASIC. The other cold route, SFQ control, is projected to draw less power per qubit S[550] and has no two-qubit gate yet; its developer, SEEQC, has filed for a Nasdaq listing, offering size undisclosed P[557]. Bargaining power stays with platform vendors; the scarce supplier is the refrigerator maker.
Outlook & open questions
Confirm within 12–24 months if IBM publishes a peer-reviewed full chain — drive, flux and readout — on ≥100 superconducting qubits at warm-rack parity; if the HRL controller reappears inside IBM above 18 qubits; if anyone reports a defined power per qubit below 5 mW at 4 K under load. Demote if by end-2027 nothing drives more than about fifty qubits end-to-end in a peer-reviewed result and Heron-class systems still ship warm racks. Best case by 2029: cold control standard on spin machines and IBM's flux path, a 10,000-qubit module on one 4 K plant at ≤5 mW/qubit. Worst case: the budget stays binding, superconducting machines keep warm racks, and cryo-CMOS survives only as millikelvin biasing for spins.
Open questions: (1) a defensible power-per-qubit definition? (2) will a foundry qualify a cryogenic corner? (3) does controller drift dominate below 10⁻⁴ qubit error? (4) must per-qubit power fall, or can the plant grow tenfold? (5) will IBM keep HRL's 130 nm design? Watch ISSCC 2027, IBM's post-acquisition disclosures, and any 4 K plant marketed above 20 W.
References
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2026-07-23-ibm-to-acquire-hrl-laboratories-to-power-the-future-of-quantum C - [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [272] S. Subramanian and S. Pellerano, “Intel's Millikelvin Quantum Research Control Chip Provides Denser Integration with Qubits,” Intel Community, Jun. 20, 2024. [Online]. Available: https://community.intel.com/
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technology C - [296] D. Underwood et al., “Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate,” PRX Quantum, vol. 5, no. 1, Art. no. 010326, Feb. 2024, doi: 10.1103/PRXQuantum.5.010326. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [527] A. Noori et al., “A Cryo-CMOS Control System for Large-Scale Superconducting Qubit Quantum Computing: Part 2,” IBM Research, Mar. 16, 2026. [Online]. Available: https://research.ibm.com/
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- [552] J. van Staveren et al., “Cryo-CMOS Bias-Voltage Generation and Demultiplexing at mK Temperatures for Large-Scale Arrays of Quantum Devices,” IEEE Trans. Quantum Eng., vol. 6, pp. 1–18, 2025, doi: 10.1109/TQE.2025.3580377. C
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הטקסט בעברית נטען…
SFQ digital control (4 K / mK)
Quantised flux pulses from a niobium digital chip flip-chipped onto the qubit die drive gates at millikelvin, replacing per-qubit microwave coax.
Verdict. Real: one five-qubit module at 1Q > 99%. Unproven: two-qubit gates, readout, flux bias, robustness to quasiparticle poisoning beyond five qubits. Demote if no >20-qubit SFQ module by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Single-flux-quantum (SFQ) logic stores a bit as one flux quantum Φ₀ = h/2e in a superconducting loop; a switching junction emits a pulse of area Φ₀, about 1 mV for 2 ps. Rapid single-flux-quantum (RSFQ; Likharev & Semenov, 1991) logic was built for classical computing at 4 K. For qubit control, a pulse train locked to the qubit period adds coherently into a Rabi rotation S[565]. In the 2026 form the controller is flip-chipped to the qubits at 10 mK D[304]. The wider superconductor-electronics field is tracked in the Superconductor Electronics Monitor P[56].
Attributes. Carrier affinity: fully fabricated control layer. Time / entangling: not applicable. Readout: none demonstrated C[53]. Mobility: none, bump-bonded. Control modality @ placement: microwave drive synthesised digitally at millikelvin. Error structure as the code sees it: Pauli plus correlated poisoning bursts D[249]. Manufacturing: multi-layer niobium lithography.
Physics & limits
Each Φ₀ pulse gives the qubit a fixed phase kick, so gate angle is set by pulse count, not analogue amplitude. Switching costs only ~I_cΦ₀ ≈ 10⁻¹⁹ J per event; within a mixing-chamber budget of tens of µW at 20 mK, RSFQ's static bias power and bias distribution bind first.
The floor is pair-breaking: switching junctions radiate photons above the aluminium gap (2Δ ≈ 90 GHz) that break Cooper pairs in the qubit film — quasiparticle poisoning — causing T1 decay and correlated bursts. Limiting the driver's pulse bandwidth is projected to remove it, bringing gate error toward 0.1% for resonant sequences D[249]. Other levers: quasiparticle traps, gap engineering, millimetre-wave absorbers.
Engineering state of the art
Best demonstrated (3 Sep 2026): SEEQC's five-qubit module at 10 mK, single-qubit fidelity above 99%, one digital input demultiplexed to several qubits D[304]C[53]. No SFQ result exceeds five qubits or includes a two-qubit gate or a QEC cycle.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2014 | 4,544 on-chip flux DACs for 512 qubits via 56 wires | D-Wave | D[430] |
| 2019 | First SFQ gate on a transmon, ≈ 95% | Wisconsin / Syracuse | D[566] |
| 2023 | Separate-die driver: 1.2(1)% error/Clifford, 0.96(2)% from poisoning | Wisconsin, Syracuse, NIST | D[249] |
| 2026-03 | Five qubits, SFQ control at 10 mK; 1Q > 99%, peak 99.9% | SEEQC | D[304] |
| 2026-03 | Fluxon time-delay readout, no fidelity reported | preprint | S[568] |
Dominant error term: quasiparticle poisoning in the 2023 module D[249]; undisclosed for SEEQC's.
Manufacturing, materials & supply chain
The control die is multi-layer Nb/AlOx/Nb — eight or more planarised niobium layers, 10⁴–10⁶ junctions — unlike the aluminium qubit process D[569]. Foundries are few: MIT Lincoln Laboratory (SFQ5ee line, SQUILL qubit foundry) C[570], AIST's niobium process and cell libraries D[571], and SEEQC's commercial foundry in Elmsford, NY C[572]. Yield needs critical-current spreads of a few per cent across thousands of junctions. Export exposure (BIS rule of 2024-09-06): ECCNs 3A904, 3B904 and 4A906; 3A901.a, read literally, covers cryogenic CMOS only G[301]. Single points of failure: dilution refrigerators, indium-bump bonding, niobium sputter and CMP tools.
Superconductor electronics integrate 1–10 million junctions per cm² against more than 10 billion transistors per cm² in advanced CMOS (figures from the MIT Lincoln Laboratory process papers the authors cite). Design gains such as clock-free xSFQ cells with built-in fan-out amplifiers — 2.7–3.4× fewer junctions on standard benchmark circuits, one cell fabricated in MIT Lincoln Laboratory's SFQ5ee process (critical current density 10 kA/cm²) and verified at 4.2 K — raise functional density, not integration density P[897].
Control, readout & I/O burden
Room-temperature control needs about one drive coax and one flux line per transmon, so fridge cross-section and heat load set its limit; a KIDE-class platform offers > 4,000 rf lines for "over 1000 qubits" Cfact. SFQ control needs a clock plus a low-rate instruction stream D[304]. SFQ readout exists only as a preprint scheme S[568]; SEEQC lists flux bias as future work C[53].
Role in the stack
Architecture: the superconducting transmon lattice. It requires superconducting-qubit lithography and flip-chip modules; it provides cold digital logic for a cryogenic decoder and D-Wave's flux DACs D[430]. The cold routes for control are cryo-CMOS or SFQ: cryo-CMOS reuses commercial foundries and design tools; SFQ needs a niobium ecosystem whose commercial tools stop at physical verification. The conflict with the transmon — switching photons poisoning the qubit — is open: its mitigation is projected D[249], and SEEQC's 2026 report of no detectable poisoning is press coverage C[53]. Contribution to the derived clock: neutral — the syndrome round stays at 0.65 µs against the measured 1.1 µs QEC cycle D[1]. Neighbouring empty slots: SFQ flux bias, SFQ readout.
Evidence — how the numbers were measured
Every headline number is a randomised-benchmarking (RB) Clifford average D[566]D[249]D[304]. RB assumes Markovian, gate-independent errors, so rare correlated bursts average into a slightly worse mean, and a module can pass at 99.9% yet emit correlated errors that decoders do not model. SEEQC's "absence of detectable quasiparticle poisoning" is reported only in press C[53]. Not reported: charge parity under continuous clocking, T1 with the clock on and off. No independent replication: the 2026 authors are all from SEEQC D[304]. Conflicts: "exceeding 99%" in the abstract D[304] against "exceeding 99.5%" in press C[53]; "nanowatts per qubit" C[53] against ~1.6 µW per qubit in a 2026 estimate S[550]fact.
The five-qubit count, 10 mK and "nanowatts per qubit" come from press [53], not from the paper's abstract [304]. SEEQC's S-1 filings give $4.2 M revenue in 2025 and $18.1 M cash at 2026-06-30 fact; its enterprise value comes from trade press. SkyWater's superconducting capability is inferred from mentions in D-Wave's 10-K [492]. Not published: a dated 2025–26 Chinese SFQ qubit-control result, an SFQ-control patent-family count, and SEEQC's offering size (blank in the S-1 amendment of 2026-09-11).
Actors & economics
Who.
| Organisation | Role | Country | What they do with it | Evidence |
|---|---|---|---|---|
| SEEQC | developer / foundry | US | mK SFQ control module; commercial Nb foundry | D[304]C[572] |
| IBM | integrator | US | SFQ integration with SEEQC (QBI); own cryo-CMOS control | P[54]C[527] |
| Wisconsin–Madison, Syracuse, NIST Boulder | research | US | Resonant SFQ control; poisoning study | S[565]D[249] |
| MIT Lincoln Laboratory | foundry | US | SFQ5ee process; SQUILL qubit foundry | C[570] |
| D-Wave | developer (adjacent) | CA | On-chip SFQ flux DACs in annealers | D[430] |
| AIST, NEC | research / foundry | JP | Nb cell libraries; 4.2 K multiplexed controller | D[571]C[567] |
Money.
- 2020-09-16 · SEEQC · Series A · $22.4 M · EQT Ventures (lead) · closed C[572]
- 2025-01-16 · SEEQC · growth round · $30 M · SIP Global and others · closed P[573]
- 2025-06-12 · SEEQC + IBM · SFQ integration under DARPA QBI, IBM the performer G[65] · undisclosed · announced P[54]fact
- 2026-06-29 · SEEQC · S-1 for a Nasdaq IPO, alongside an Allegro Merger Corp SPAC agreement ($1 B enterprise value) · filed C[556]fact
- 2026-08-25 · SEEQC / Allegro · SPAC merger ended by settlement: Allegro gets $6 M in stock at a $1.3 B pre-money valuation on a future IPO, sale or ≥ $100 M raise · terminated G[574]
Market & supply chain. No SFQ control market exists yet: one vendor, one demonstration. SkyWater, the merchant foundry named in D-Wave's 10-K filings G[492], has belonged to IonQ since July 2026 C[19]. G3 and G4 pay for it; G7 secondarily.
IP & standards. SEEQC holds the Hypres RSFQ and niobium-process patents, transferred at its 2019 spin-out C[572]. No SFQ-control standards exist; shared design bases are AIST's cell library D[571] and MIT-LL's kits C[570].
Roadmaps & track record. SEEQC: millikelvin SFQ control (promised 2021–22 · delivered 2026-03 at five qubits) D[304]; on-die flux control and readout (announced 2026-03 · undated) C[53].
Strategic reading. Niobium process capability sits with SEEQC and, via Lincoln Laboratory, the US government. Of the cold routes, cryo-CMOS or SFQ, cryo-CMOS has the stronger record: a QEC demonstration under a 4 K cryo-CMOS controller D[190] and parity with warm electronics on an IBM processor C[527]; SFQ has single-qubit gates on five qubits from one group D[304].
Outlook & open questions
Confirm if by end-2027 a group publishes an SFQ-driven two-qubit gate below 1% error, an SFQ-controlled device above ten qubits, or hours of charge-parity data free of clock-correlated bursts. Demote if by end-2028 no SFQ module exceeds twenty qubits, or a decomposition shows poisoning above 0.1% per Clifford. Open questions: does "no detectable poisoning" survive continuous clocking at QEC duty cycles? Can SFQ flux bias hold the DC stability transmons need?
References
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הטקסט בעברית נטען…
Chip-integrated microwave control (ions)
Ion gate drive synthesised as electrical signals and delivered by conductors inside the trap chip instead of by laser beams.
Verdict. Fidelity records are real but two-ion; the ~200-sources-per-1,000-qubits wiring claim remains a 2023 design study, with no multi-zone chip-integrated microwave device published as of 2026-09-03.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The control layer of the laser-free ion machine: the electronics generating the qubit drive, the chip conductors radiating it, and the wiring between. Hyperfine splittings sit at 1–13 GHz, so the wavelength exceeds the whole trap and nothing is focused. Addressing is geometric, via the near field of a trace tens of micrometres from the ion, or spectral, when a static magnetic gradient gives each ion its own resonance. One family descends from NIST Boulder's near-field gates of the early 2010s, carried today by Oxford Ionics inside IonQ; the other is Wunderlich's magnetic-gradient-induced coupling from Siegen, commercialised by eleQtron as MAGIC.
Attributes: carrier affinity 1.0, fully fabricated — the ion is natural, everything this node owns is lithographic; no characteristic time and no entangling action of its own; no readout, fluorescence stays optical; no mobility, the structure is static and ions are transported past it; microwave modality at room-temperature placement, only routing on-chip; Pauli error structure, no leakage channel of its own; MEMS-class manufacturing, a multilayer surface-electrode metal stack. The node dates from 2024, when the sub-part-per-million single-qubit gate D[103] and the first fielded MAGIC demonstrator C[590] arrived.
Physics & limits
A 10 GHz photon carries ~40 µeV against an optical Raman photon's ~2 eV. Driving through a virtual excited state costs spontaneous scattering, which floors laser gates near 10⁻⁴ and converts part of that error into leakage; a microwave drive touches no excited state, so the term vanishes. What remains is classical — source amplitude and phase noise, magnetic-field noise, calibration drift — hence a floor of 1.5(4)×10⁻⁷ per Clifford on a ⁴³Ca⁺ clock qubit, T2 ≈ 70 s, at room temperature, unshielded, calibration error below 10⁻⁸ D[103].
The bill arrives in current: spin–motion coupling, the entangling ingredient treated in the sibling gate brief, needs a gradient, and a gradient at the ion means amperes microns away. Three consequences follow. Ohmic dissipation, since the 10 GHz copper skin depth is sub-micrometre and the heat lands in the chip holding the ion; global reach, since every ion sees a drive whose wavelength dwarfs the trap, so selectivity must be built from routing or frequency separation; and drive-induced motional heating, which shows up not as a control error but as a degraded entangling gate later. Superconducting traces and on-chip switching that keeps unselected zones cold would move the floor.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2023-05-22 | 1,000 fully connected qubits from ~200 signal sources (design) | Malinowski, Allcock, Ballance (Oxford Ionics) | S[325] |
| 2023-05-22 | ~40–2,600 gate layers per second projected | Oxford Ionics | S[325] |
| 2024-05-30 | First MAGIC demonstrator delivered, 10 qubits, Hamburg | eleQtron / NXP / ParityQC | C[590] |
| 2024-12-05 | 1Q error 1.5(4)×10⁻⁷ per Clifford, no magnetic shielding | Oxford (Lucas group) | D[103] |
| 2025-10-20 | 2Q error 8.4(7)×10⁻⁵, no ground-state cooling | Oxford Ionics / IonQ | D[102] |
Every record above was taken on one or two ions in a laboratory trap; no public device drives eight or more zones from chip-integrated conductors. The largest ion machine in service, the 98-ion Helios, is laser-driven with 1,228 electrodes and ≥7 wavelengths, and spends ~55 ms per full-width layer on transport, sorting and cooling against a ~70 µs gate D[97]. The dominant Oxford error term is decoherence plus leakage and measurement, not the drive electronics D[103]; at system scale it should be crosstalk and drive-induced heating, neither published.
Manufacturing, materials & supply chain
The chip is an rf circuit that happens to trap ions: metal levels with a top layer sized for ~1 A at gigahertz frequencies, vias moving the DC fan-out off the ion-facing surface, and — in WISE — switching devices integrated in a form "compatible with its fabrication and operation constraints", synthesis left outside S[325]. That is a semiconductor-fab specification, not an optics-shop one, and it explains capital allocation better than any roadmap slide. IonQ bought Oxford Ionics for $1.075 B (closed 2025-09-17) fact, then the 200 mm foundry SkyWater for ~$1.8 B (closed 2026-07-31) fact, while disclosing only a "semiconductor-based approach to manufacturing" C[19]. In Germany the split is contractual: eleQtron builds trap and MAGIC hardware, NXP the control and regulation electronics, ParityQC the architecture layer G[327].
No yield, uniformity or cost-per-qubit figure is public for a microwave trap chip as of 2026-09-03. The one quotable ratio is 0.2 signal sources per qubit at 1,000 qubits S[325], against a laser system's per-zone beam path and ≥7 wavelengths D[97]. Single points of failure sit in trap fabrication — Sandia, Infineon, Honeywell in-house, IonQ's captive SkyWater — not in the commodity microwave chain; export exposure runs through the September 2024 US quantum controls, ECCN unverified.
Control, readout & I/O burden
Per qubit: one tone at 1–13 GHz with sub-milliradian phase control, plus trap DC voltages and a stable magnetic environment. The naive build gives one synthesiser, amplifier and coaxial feedthrough per zone, and it is feedthrough count and heat load, not qubits, that stops the machine at a few hundred. WISE answers with demultiplexing — synthesis at room temperature, simple switches on the chip, one shared high-power signal fanned out to the selected zone — yielding ~200 sources for 1,000 qubits at 40–2,600 layers per second S[325]. That is the move superconducting digital control makes when one digital input feeds several qubits D[304].
At 10³ qubits the binding question is whether an on-chip switch can sit micrometres from an ion without charging dielectrics or adding electric-field noise: unpublished, and the load-bearing unknown here. At 10⁴ the wall is thermal — parallel gates dissipating tens of milliwatts to watts each cannot run together in a 4 K trap with a one-watt cooling budget, so parallelism trades against clock rate, which the record's room-temperature operation avoids at the price of higher anomalous heating D[103]. At 10⁶ nothing published applies; it needs gigahertz synthesis on-chip. Latency stays comfortable: 10–1,000 µs gates leave FPGA control three orders of magnitude of headroom, the inverse of the superconducting case.
Role in the stack
The node sits on the architecture Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (IonQ/Oxford Ionics, eleQtron) and is the alternate control of Trapped ions — QCCD (transport between zones) (Universal Quantum). The register lists 8 machines using it, among them JION, QSea I, QUARTET and iQPU / UQConnect. It requires surface-electrode ion-trap microfabrication, specifically the current-carrying traces; it provides the signal sources for the electronic near-field microwave gate; it replaces laser control of ions. The switching price is precise: gate lasers go, but cooling, state-preparation and readout lasers stay, so a "laser-free" machine still carries optics, the trap chip becomes a microwave design problem, and the species choice narrows to hyperfine ions with a usable clock transition. Here a natural carrier is driven by a wholly fabricated control structure — the manufacturing burden moves off the qubit onto the chip around it.
Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 1.5×10⁻³ s — seven gate layers of today's electronic gate plus readout and reset, no transport — against ~5.5×10⁻² s on a transport-based machine of the Helios type D[97]. Neighbouring empty slots: cryogenic on-chip microwave synthesis; a trap-qualified on-chip current switch with a published electric-field-noise spectrum; superconducting current traces in an ion trap.
Evidence — how the numbers were measured
The 10⁻⁷ figure is a randomised-benchmarking number whose per-Clifford decay is comparable to slow drift, so it states as much about long-run stability and the leakage and SPAM model as about the gate D[103]. Benchmarking here does not capture spectator crosstalk from the global far field, a.c. Zeeman shifts on neighbours, or drive-induced heating, which surfaces only in a later entangling gate. No simultaneous randomised benchmarking, crosstalk-RB or cycle benchmarking exists for a chip-integrated microwave device, and the 8.4(7)×10⁻⁵ two-qubit result has no independent replication as of 2026-09-03 D[102]. Two source issues: the main report attributes gate durations of 225.8 µs (2025) and ≈120 µs (2024) to a paper whose abstract states neither, so those are carried as reported; and WISE's source count and layer rate are architectural estimates S[325], not measurements.
Not published: Universal Quantum's DLR contract value, funding and 2025–2026 status; the QSea I and QSea II contract values in EUR; patent counts for the three families; and per-qubit cost or yield for microwave trap chips.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IonQ (incl. Oxford Ionics) | developer | US / UK | Chip-integrated microwave control; electronic 2Q gate at 8.4(7)×10⁻⁵; owns WISE | D[102], S[325] |
| eleQtron | developer | DE | MAGIC static gradient plus global microwave; builds the QSea processor | C[590] |
| NXP Semiconductors | supplier | NL / DE | Control and regulation electronics for the QSea demonstrators | G[327] |
| ParityQC | supplier | AT | Architecture and algorithm layer for QSea | G[327] |
| DLR Quantum Computing Initiative | user / funder | DE | QSea I, 2023-03-01 → 2027-02-28, demonstrator in Hamburg | G[327] |
| SkyWater Technology | supplier (captive) | US | 200 mm foundry acquired by IonQ, closed 2026-07-31 | fact |
| Oxford (Lucas group) | research | UK | 1Q record 1.5(4)×10⁻⁷ with an on-chip microwave resonator | D[103] |
| Universal Quantum | developer | UK | Global microwave plus magnetic gradients; no dated figure verified | — |
| Quantinuum | competitor | US | Laser control at scale, 1,228 electrodes, ≥7 wavelengths | D[97] |
| DARPA (QBI) | funder | US | Stage A included Oxford Ionics; Stage B includes IonQ | fact |
Money.
- 2023-03-01 · DLR QCI with eleQtron, NXP, ParityQC · QSea I contract to 2027-02-28 · value not disclosed · active G[327]
- 2024-05-30 · eleQtron, NXP, ParityQC · QSea I demonstrator delivered, Hamburg · no amount · delivered C[590]
- 2025-06-09 · IonQ · M&A, Oxford Ionics · $1.075 B · closed 2025-09-17 fact
- 2025-07-08 / 2025-10-12 · IonQ · equity · $1.0 B then $2.0 B at $93/share · cash $3.0 B, Q2-2026 revenue $80.1 M · closed fact
- 2025-11-06 · DARPA · QBI Stage B incl. IonQ · up to $15 M each · announced fact
- 2026-01-26 · IonQ · M&A, SkyWater · ~$1.8 B ($15.00 cash + 0.4883 shares per share) · closed 2026-07-31 fact
- 2026-05-05 · eleQtron · Series A · €57 M, €54 M backlog · closed C[129]fact
Market & supply chain. The enabling equipment is microwave synthesis and amplification — AWG (arbitrary waveform generator) and direct-digital sources, GaN/GaAs amplifiers, coaxial feedthroughs — a commoditised dual-use base with almost no vendor bargaining power, unlike the narrow-linewidth-laser oligopoly the optical machines need. Concentration risk migrates upstream into multilayer trap fabrication, the segment IonQ has internalised; unit economics are undisclosed. G3 (early fault tolerance) pays through gate fidelity and G7 (deployable systems) through removal of the gate-laser optical table; G4 pays later, G1 and G6 not at all.
IP & standards. The relevant families are Oxford Ionics' electronic-qubit-control filings (Ballance/Malinowski lineage from 2019, now IonQ-assigned), the Siegen magnetic-gradient family behind MAGIC, and Universal Quantum's modular-microwave filings. No dated patent-database query was run, so no count is claimed; no litigation, standard or open-source stack is specific to microwave ion control.
Roadmaps & track record. IonQ (promised 2025-06-13 · for 2026 · 256 qubits at 99.99% · slipped to commissioning H1 2027); IonQ (promised 2025-06-13 · for 2027 · 10,000 physical qubits on one chip · no multi-zone chip-integrated microwave data as of 2026-09-03); IonQ (promised 2025-06-13 · for 2030 · 2 M physical / 40–80 k logical) Rfact; eleQtron with DLR (promised 2023-03 · for year one · a MAGIC demonstrator in Hamburg · delivered 2024-05-30), QSea II (for 2027-02-28 · industry-ready successor · no public target) G[327]C[590]. IonQ's gate physics leads the world and its component claims have held; its scale claims have not, the 2020 roadmap having missed 4,000 qubits by 2026 roughly 40-fold, and the architecture behind the 10,000-qubit promise is still a paper. eleQtron is small and has delivered what it contracted for, where the deliverable was a demonstrator rather than a fidelity record.
Strategic reading. If this works at 10³ ions, value accrues to whoever owns a qualified multilayer trap line plus an rf design team; IonQ has bought both, and NXP gives the European line the same pairing without vertical integration. The losers are the laser supply chain and the integration advantage of the optical incumbents, since Helios's 1,228 electrodes and seven wavelengths do not transfer to a microwave chip D[97]. The substitution threat runs the other way with equal force — laser control has run 98 ions with all-to-all connectivity, microwave control 30, in JION, with no gate fidelity disclosed — so the node trades proven scale for a better error floor and a better wiring asymptote.
Outlook & open questions
Confirm if a device with ≥8 zones driven by chip-integrated conductors is published with simultaneous-RB crosstalk figures before 2027-12, if IonQ commissions 256 qubits at 99.99% in H1 2027 on full-register rather than pairwise benchmarking, or if eleQtron publishes a QSea II fidelity before 2027-02-28. Demote if no multi-zone device appears by end-2027, or if the first one reports drive-induced heating forcing one source per zone, since the wiring advantage then evaporates. Best case by 2029: a 10³-ion register wired by on-chip switching at ~200 sources, two-qubit error near 10⁻⁴, no gate lasers. Worst case: the records stand, the architecture does not, and microwave control survives as the single-qubit layer of an optically entangled machine.
Open questions. (1) How much anomalous heating do drive currents inject at entangling-gate gradients? (2) Can an on-chip switch operate micrometres from an ion without dielectric charging? (3) Room temperature or 4 K, given that lower heating buys no headroom for parallel drive? (4) Does frequency addressing scale past ~10 ions per chain? (5) In a static register, is the derived clock gate- or transport-limited?
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [103] M. C. Smith, A. D. Leu, K. Miyanishi, M. F. Gely, and D. M. Lucas, “Single-qubit gates with errors at the 10⁻⁷ level,” Phys. Rev. Lett., vol. 134, no. 23, Art. no. 230601, Jun. 2025, doi: 10.1103/42w2-6ccy. arXiv:2412.04421. D
- [129] A. Cordes, “Quantum computing scale-up eleQtron secures €57 million in one of the largest Series A funding rounds worldwide,” eleQtron, May 5, 2026. [Online]. Available: https://eleqtron.com/
en/ Cquantum-computing-scale-up-eleqtron-secures-57-million-in-one-of-the-largest-series-a-funding-rounds-worldwide/ - [304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at millikelvin temperature,” Nat. Electron., vol. 9, no. 3, pp. 287–294, Mar. 2026, doi: 10.1038/s41928-026-01576-6. D
- [325] M. Malinowski, D. Allcock, and C. Ballance, “How to Wire a 1000-Qubit Trapped-Ion Quantum Computer,” PRX Quantum, vol. 4, no. 4, Art. no. 040313, Oct. 2023, doi: 10.1103/PRXQuantum.4.040313. arXiv:2305.12773. S
- [327] German Aerospace Center (DLR), “QSea I – Quantum computer demonstrator with 10 ion trap qubits,” DLR Quantum Computing Initiative. [Online]. Available: https://qci.dlr.de/
en/ Gqsea-i/ - [590] NXP Semiconductors, “NXP, eleQtron and ParityQC Reveal their First Quantum Computing Demonstrator for the DLR Quantum Computing Initiative,” NXP Newsroom, May 30, 2024. [Online]. Available: https://www.nxp.com/
company/ Cabout-nxp/ newsroom/ NW-NXP-ELEQTRON-AND-PARITYQC-FIRST-QUANTUM
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הטקסט בעברית נטען…
PIC-generated tweezers / integrated optics for atoms
Generating, routing and collecting the light that traps, addresses and images single atoms from a photonic integrated circuit instead of free-space optics.
Verdict. Four atoms trapped from a chip, fifty addressed through a chip, zero gates through either. Until a PIC holds atoms far enough from its surface to run Rydberg gates, this is packaging, not a scaling path.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Move the optics that hold and address single atoms — lenses, modulators and deflectors on a metre-scale breadboard — onto a photonic chip. Two functions hide under one node and only the first is trap generation: emitting tweezer light from the chip (Pasqal, four rubidium atoms, ~27.5 s lifetime, August 2026 C[330]), and coupling trapped atoms to on-chip photonics for imaging and collection (Chicago, 64 free-space tweezers over >100 nanophotonic cavities D[579]; a 50-atom, 784-channel glass waveguide array D[580]). Reconfiguring traps on chip, nobody has shown.
Control and fabrication: room-temperature optical control from a photonic IC, wrapping a natural carrier it never becomes. Error structure: coherent — coupling loss, crosstalk (0.4% measured D[580]) and surface-induced light shifts, not decoherence.
Physics & limits
A rubidium tweezer needs roughly a millikelvin of depth: several milliwatts focused to a micron waist at high numerical aperture. A grating or metasurface emitter can do that, and Pasqal's lifetime matches its own bulk systems C[330], so coupling loss is not the first wall. Power is next: a thousand traps is watts on chip, where scattered light and coupler heating bind first.
The first wall is the surface. Rydberg states are enormously polarisable, so adsorbate-induced stray fields and blackbody radiation from a nearby dielectric shift and broaden the line every neutral-atom two-qubit gate depends on. Chicago holds atoms a few hundred nanometres above the chip for cavity coupling D[579] — excellent for photon collection, hopeless for a blockade gate. A trap-generating chip must project its focus tens to hundreds of microns clear of itself, spending much of the footprint advantage. The second wall is reconfiguration: crossed deflectors sweep continuously and are already the bandwidth limit above ~10⁴ atoms, while on-chip switching is thermo-optic (microseconds to milliseconds, milliwatts dissipated each) or electro-optic in lithium niobate (nanoseconds, lossier, not trap-grade yet). What moves the floor: surface passivation letting atoms sit closer, and a low-loss switch fabric beating deflector rates.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-07 | 64 tweezers over >100 nanophotonic cavities, 99.2% imaging fidelity, atoms a few hundred nm above the surface | University of Chicago | D[579] |
| 2026-08 | 4 Rb atoms trapped by light from a SiN chip, ~27.5 s lifetime, stated as matching bulk optics | Pasqal | C[330] |
| 2026-08 | 50 addressed ⁸⁷Rb atoms through a glass waveguide array: 0.4% crosstalk, 2.9 dB insertion loss, 93% fill, 118 Hz loss repair, 784-channel chip | USTC | D[580] |
Two to three orders below free-space systems on atom count, and no gate or transport has run through a chip-generated trap anywhere. The 784-channel chip is the strongest scaling evidence, and it addresses atoms rather than trapping them.
On the light-source side, a hybrid-integrated 780 nm microcomb (Si₃N₄ resonators from 150 mm wafers, self-injection-locked III–V laser diodes) referenced to ⁸⁵Rb drove an optical lattice and a Raman coupling in an ⁸⁷Rb Bose–Einstein condensate in 2026 P[886]. The light was chip-generated but delivered through free space, and it controlled a quantum gas, not qubits: no chip-generated trap or gate was involved.
Manufacturing, materials & supply chain
Silicon nitride photonic-IC processes; the 50-atom array uses glass waveguides D[580]. Pasqal's photonics came from Aeponyx at an undisclosed price under 18 months before the August 2026 release, and no foundry partner is named C[581]. Nearest merchant capacity: imec's PIXEurope pilot line (~EUR 400 M, 2024-11-24) and GlobalFoundries' Quantum Technology Solutions ($375 M CHIPS letter of intent, 2026-05-21) — both name photonics as an output, neither names atom traps G[582]G[353]. Thin-film lithium niobate vendors HyperLight and Lightium are the candidates if fast switching becomes the requirement P[518]. No yield, per-channel cost or export-control category for atom-trap photonics was found as of 2026-09-04.
Control, readout & I/O burden
The claim is footprint: Pasqal states up to 50× smaller optics once trap light is routed on chip C[330]. At four atoms the burden is a few fibre couplings; the question starts at hundreds, where it becomes power per channel, fibre count into vacuum and switching bandwidth — none of which is published. The 784-channel chip at 2.9 dB insertion loss is the only channel-count datum D[580]. A chip removes an optical table's alignment and drift burden and adds a fixed geometry unless switches are integrated.
Role in the stack
It replaces free-space tweezer and addressing optics on the alkali neutral-atom architecture (Pasqal, QuEra, Infleqtion) and requires a photonic-IC process underneath, providing no connectivity, gate or code of its own. Contribution to the derived clock is nil today; at scale, on-chip switching could become a new clock term if it cannot match deflector reconfiguration — the opposite of the intended effect. The same pattern runs on the ion side, where Sandia supplies Quantinuum integrated photonics for laser delivery G[501]. Neighbouring empty slots: a gate through a chip-generated trap, and on-chip transport.
Evidence — how the numbers were measured
Pasqal's lifetime and 50× footprint projection are company-reported without replication, and "matching bulk optics" is measured against its own systems, not an external reference C[330]. The Chicago and USTC results carry no vendor roadmap and neither reports a gate fidelity, because neither has run a gate. Nothing published measures what matters most — trap depth, position stability and Rydberg-line shift against distance from the chip surface.
The millikelvin trap depths and milliwatt-per-trap powers are standard tweezer scalings, not values quoted by the chip sources. Not published: the Aeponyx acquisition price and closing date (only "less than 18 months" before 2026-08-10 is stated); the numbers behind Pasqal's 50× footprint projection; and the yield, per-channel cost and export-control classification of atom-trap photonics.
Actors & economics
Who.
| Organisation | Role | Country | What they do here | Evidence |
|---|---|---|---|---|
| Pasqal | developer | FR | Only chip-generated atom traps demonstrated | C[330] |
| Aeponyx | supplier | CA | SiN photonics behind Pasqal's chip; acquired | C[581] |
| University of Chicago | research | US | Atom array over nanophotonic cavities, background-free imaging | D[579] |
| USTC | research | CN | 50-atom addressing array, 784-channel chip | D[580] |
| GlobalFoundries | supplier | US | Quantum unit naming photonics as an output | G[353] |
| HyperLight | supplier | US | Lithium niobate for fast switching | P[518] |
Money. 2024-09 · HyperLight and Lightium · Series B and seed · $37 M and $7 M · Summit Partners; Vsquared and Lakestar · closed Pfact. 2025 (undated) · Pasqal · M&A of Aeponyx · undisclosed · closed, stated as under 18 months before 2026-08 C[581]. 2026-08-28 · Pasqal · SPAC merger · ~$360 M cash · Nasdaq PSQL · closed fact.
Market & supply chain. The supply base is the general photonic-foundry ecosystem, not scarce; the scarce asset is trap design know-how, and Pasqal's arrived with one acquired startup — a single point of failure if that team disperses. What it threatens is the incumbent free-space chain: deflectors from AA Opto-Electronic and Gooch & Housego, the only vendors named in published tweezer work D[4]. It pays for G3 and G4 by cutting footprint and alignment labour, nothing for G1, G2 or G5.
IP & standards. Aeponyx's pre-acquisition silicon-nitride portfolio is the core asset; Pasqal has disclosed nothing of its contents. No dated patent-family count for chip-generated atom tweezers was found as of 2026-09-04, and no standards activity addresses trap-grade photonics.
Roadmaps & track record. Pasqal states >10,000 atoms and 100 logical qubits by this route with no date attached R[330], against one slip already on the free-space side — 10,000 physical moved from 2026 to 2028, 100 logical to 2029 R[156]fact. First demonstration August 2026: no delivery record to score, and no rival chip-trap roadmap exists.
Strategic reading. If on-chip generation scales past the dozens it undercuts the free-space chain every tweezer and ion machine depends on and moves bargaining power to photonic foundries selling into datacom volumes; Pasqal wins by leading in a component competitors must then buy or build. If crosstalk, power and the surface problem cap channel counts in the tens, it stays packaging and the incumbent vendors keep their position — the likelier outcome on today's evidence.
Outlook & open questions
Confirm/demote in 12–24 months: anyone runs a two-qubit gate through a chip-generated trap; chip-trapped atom count reaches the hundreds; a second vendor enters. Best case 2029: chip tweezers hold hundreds to thousands of atoms at free-space fidelity, shrinking a rack enough to change system cost. Worst case: the surface constraint forces long working distances, the footprint gain evaporates, and integrated optics stays confined to imaging and collection, where it already works. Open: how far from the chip must atoms sit for a clean Rydberg line; can on-chip switching beat deflector reconfiguration. Watch: Pasqal's next update and any gate through a chip trap.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ R08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [330] Pasqal, “Pasqal brings qubit control on-chip, advancing the path to fault-tolerant quantum computing at scale,” Aug. 10, 2026. [Online]. Available: https://www.pasqal.com/
news/ Cpasqal-brings-qubit-control-on-chip-advancing-the-path-to-fault-tolerant-quantum-computing-at-scale/ - [353] GlobalFoundries, “GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing,” May 21, 2026. [Online]. Available: https://gf.com/
gf-press-release/ Also https://investors.gf.com/globalfoundries-launches-quantum-technology-solutions-to-scale-us-quantum-manufacturing/ news-releases/ . Gnews-release-details/ globalfoundries-launches-quantum-technology-solutions-scale-us - [501] T. Rummler, “In the Mountain West, a quantum computing collaboration announces major results,” Sandia Lab News, Aug. 27, 2026. [Online]. Available: https://www.sandia.gov/
labnews/ G2026/ 08/ 27/ in-the-mountain-west-a-quantum-computing-collaboration-announces-major-results/ - [518] optics.org, “Lithium niobate in vogue as thin-film developers raise cash,” Sep. 24, 2024. [Online]. Available: https://optics.org/
news/ Plithium-niobate-in-vogue-as-thin-film-developers-raise-cash - [579] S. G. Menon, N. Glachman, M. Pompili, A. Dibos, and H. Bernien, “An integrated atom array–nanophotonic chip platform with background-free imaging,” Nat. Commun., vol. 15, no. 1, Art. no. 6156, Jul. 2024, doi: 10.1038/s41467-024-50355-4. D
- [580] Y.-D. Hu et al., “A scalable chip-integrated single-photon source array based on 50 individually addressable neutral atoms,” arXiv:2608.15637, Aug. 2026. D
- [581] M. U. Rehman, “Pasqal Demonstrates Photonic Chip-Based Control for Neutral-Atom Quantum Computers,” The Quantum Insider, Aug. 10, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ C08/ 10/ pasqal-photonic-chip-control-neutral-atom-quantum-computers/ - [582] imec, “The European Commission and Chips JU select the PIXEurope consortium to lead the European Pilot Line on Advanced Photonic Integrated Circuits,” Nov. 24, 2024. [Online]. Available: https://www.imec-int.com/
en/ Gpress/ european-commission-and-chips-ju-select-pixeurope-consortium-lead-european-pilot-line - [886] W. Sun et al., “A photonic integrated comb engine for ultracold quantum gases,” arXiv:2609.28294, Sep. 2026. P
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Baseband electrical control (spins, Majorana)
DC-to-few-GHz voltage pulses on lithographic gate electrodes drive exchange, tunnelling and parity in spin and Majorana devices, with no resonant drive.
Verdict. The physics is settled and the wiring is not. HRL attributes roughly 80% of its CNOT error to control and calibration rather than the qubit, so cold co-location — not faster pulses — is the lever.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Baseband control manipulates a qubit with DC-to-few-GHz voltage pulses on lithographic gates rather than a resonant drive: a pulse shifts the electrostatic potential, and with it the exchange coupling between dots or the tunnel coupling of a Majorana junction. The licence is old and precise: DiVincenzo, Bacon, Kempe, Burkard and Whaley showed in 2000 that the Heisenberg interaction alone suffices for universal computation, at about 3× more qubits and ~10× more two-qubit operations S[416]. Every exchange-only architecture since pays that bill to delete microwave hardware.
- Control and placement: low-frequency voltage pulses generated warm, routed to millikelvin gates.
- Error structure: coherent and correlated, not stochastic — miscalibration is what the code sees.
Physics & limits
Exchange coupling J depends exponentially on detuning and barrier height, so a rotation angle is the time integral of J and a small voltage error is a proportionally large angle error. There is no drive-frequency selectivity: 1/f charge noise modulates the same potential that carries the signal, and crosstalk from a neighbouring gate is indistinguishable from an intended pulse. Hence the field's most useful number — HRL measures ~80% of its CNOT error as extrinsic, in control and calibration rather than the qubit Dfact. The floor is waveform accuracy and recalibration cadence, not T2: foundry devices reach 1.31(4) ms echo coherence Dfact against 58 ns exchange gates Dfact. Moving it means a shorter electrical path — a controller on the cold stage, ideally on-die — plus automated recalibration.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-07 | Microwave-free hopping control, 2×2 array with a micromagnet gradient: hopping-gate fidelity lower bound 99.50(6)%, echo T2 up to ~49 µs | QuTech | Dfact |
| 2026-07-29 | 18 exchange-only qubits from 54 dots, sequenced by a 4 K controller: mean 1Q error 2×10⁻⁴, mean CNOT 3×10⁻³ (best 9×10⁻⁴) | HRL | Dfact |
| 2026-07-29 | Same device, distance-5 repetition code over 200 rounds: logical error 5.0×10⁻³, Λ₅/₃ = 4.7 — bit-flip only | HRL | Dfact |
Dominant term: extrinsic control and calibration, ~80% of the CNOT budget.
Baseband control can drop per-pair barrier pulsing: in a 6×6 germanium hole-dot array, one shared barrier gate held at a fixed voltage, with only the individual plunger gates pulsed, sufficed for electric-dipole spin resonance (EDSR) driving, shuttling and exchange tuning from about 20 kHz to about 80 MHz P[898].
Manufacturing, materials & supply chain
The node rides ordinary CMOS: Intel's 300 mm EUV line reports over 24,000 devices per wafer D[199], with 96% tune-up yield on 232 devices of one wafer D[766], and Quantum Motion characterises 1,024 dots in five minutes on GlobalFoundries 22FDX C[200]. That is the asset and the exposure: each developer sole-sources one foundry it does not own — Quobly to STMicroelectronics, Quantum Motion to GlobalFoundries, Diraq to imec — so a fab-side decision is a company-level failure mode. Room-temperature pulse generation is uncontrolled, but a controller "designed to operate at" ≤4.5 K falls under ECCN 3A901.a from the design file on fact: cold integration imports export control.
Control, readout & I/O burden
Baseband control costs about one line per gate and two to four gates per dot, so a naive 10³-qubit array wants 10³–10⁴ addressed lines from room temperature. HRL's counter-example is the number to hold: 296 lines and 366 DACs at ≤3.5 W driving 54 dots, with a 250 MHz on-chip sequencer and no room-temperature real-time electronics Dfact — ~20 DACs per qubit, cold multiplexing rather than wire elimination. At 10³ the harness is impractical without cold DACs; at 10⁴ per-qubit DAC count must fall an order of magnitude; at 10⁶ nothing exists. The binding constraint is recalibration cadence.
Role in the stack
It requires nothing upstream, provides the exchange gate directly, and reaches four architectures: quantum-dot spins (Intel, Diraq, Quantum Motion, HRL/IBM, QuTech, Quobly, Equal1), donor spins (Silicon Quantum Computing), colour-centre spin network nodes and Majorana devices, where gate voltages tune the dots that report parity. It competes with microwave and electric-dipole spin resonance, which buys frequency selectivity at the price of antennas and heating. Its clock contribution is negligible: exchange gates run at ~58 ns Dfact against 6.3 µs readout, so derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 8.5 µs here, set by readout with reset next.
Evidence — how the numbers were measured
Fidelities come from randomised benchmarking and gate-set tomography, and the headline QuTech number is a lower bound, not a point estimate Dfact. The 80% extrinsic share deserves most scrutiny: it is inferred from measured error against a modelled noise budget, not independently partitioned, and unreplicated. No spin device above 12 qubits has published all-pairs two-qubit fidelities, so simultaneous-operation crosstalk — this node's own failure mode — is uncharacterised at scale. HRL's Λ₅/₃ = 4.7 is a repetition code, bit-flip only, not below-threshold evidence, and its [[4,2,2]] fidelity of 0.95 is post-selected Dfact. On the Majorana side the control works but the qubit does not exist: parity readout is real, X-loop lifetimes ran ~1,000× shorter than Z-loop lifetimes, no two-qubit operation D[13].
Not published: a dated patent-family count for baseband gate-voltage control.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| HRL Laboratories | Developer | USA | Only self-sequenced baseband QEC demonstration; acquired by IBM | Dfact |
| Diraq | Developer | Australia | SiMOS exchange qubits on imec's 300 mm line | Dfact |
| Quantum Motion | Developer | UK | Full-stack 300 mm CMOS system at the UK NQCC | Cfact |
| QuTech | Research | Netherlands | Microwave-free hopping control, 2D array | Dfact |
| Microsoft | Developer | USA | Gate-voltage-tuned parity measurement in tetrons | D[13] |
Money. 2025-11-06 · Diraq, Quantum Motion, Silicon Quantum Computing · DARPA QBI Stage B · up to $15 M USD each · programme fact. 2026-05-07 · Quantum Motion · Series C · $160 M USD · DCVC, Kembara · closed Cfact. 2026-05-21 · Diraq · CHIPS letter of intent · up to $38 M USD · US Commerce · non-binding fact. 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicro · €134 M cumulative · closed Cfact. 2026-07-23 · IBM · acquires HRL · undisclosed · closed 2026-08-26 Cfactfact.
Market & supply chain. Nothing is sold as "baseband control"; what sells is foundry capacity, enriched ²⁸Si, and the warm waveform racks Quantum Machines dominates with over half of developers as customers Cfact. Cold integration threatens that rack business, and is why IBM bought HRL. Diraq's under-$1-per-qubit figure is a target, not a cost. This node pays for G3 and G4 on the spin architecture, G4 on the Majorana architecture if a qubit appears.
IP & standards. No patent family specific to baseband gate-voltage control was found in a named dated database as of 4 Sep 2026. The foundational exchange-only claim is a 2000 publication, long out of patent term S[416] — part of why this layer is crowded. IBM's HRL deal brings undisclosed controller IP in-house. No standards body governs gate-pulse interfaces today.
Roadmaps & track record. Diraq (2026-08-27 · 150 k physical, 1 k logical by 2029, > 2 M by 2031 · its 2026-07-09 release said "thousands by 2029") — low on messaging, real on devices fact. Quantum Motion (full-stack delivery · met, NQCC 2025-09-15) — the only met hardware date here. HRL/IBM (no public date · QPU delivered 2026-07-29) — strongest result here. Microsoft ("years not decades" → 2029 · no two-qubit operation) — no base.
Strategic reading. If baseband control scales, foundry-native platforms inherit decades of CMOS investment free while exotic-control platforms fund their own hardware forever — the argument IBM made by buying HRL. Losers are room-temperature control-rack vendors, displaced from inside the cryostat rather than out-competed on price. The live substitution question is warm versus cold placement, not baseband versus microwave drive. Bargaining power sits with the foundries: every developer above depends on a relationship it cannot replace within a product cycle.
Outlook & open questions
Confirm by 2027 if any developer publishes all-pairs two-qubit fidelities above 12 qubits, or an independent group reproduces the extrinsic/intrinsic split; demote if crosstalk caps arrays at ≤20 qubits through 2028. Best case 2029: cold self-sequenced control becomes default and two-qubit errors move from 3×10⁻³ toward 10⁻⁴. Worst case: calibration overhead outruns qubit count and the CMOS argument stalls at demonstration scale. Open questions: does the 80% figure survive independent measurement; can per-qubit DAC counts fall an order of magnitude; does recalibration keep pace with array size; does Majorana control ever get a qubit.
References
- [13] Microsoft Azure Quantum, “Interferometric single-shot parity measurement in InAs–Al hybrid devices,” Nature, vol. 638, no. 8051, pp. 651–655, Feb. 2025, doi: 10.1038/s41586-024-08445-2. D
- [199] H. C. George et al., “12-spin-qubit arrays fabricated on a 300 mm semiconductor manufacturing line,” Nano Lett., vol. 25, no. 2, pp. 793–799, Dec. 2024, doi: 10.1021/acs.nanolett.4c05205. arXiv:2410.16583. D
- [200] Quantum Motion, “Quantum Motion Delivers the Industry's First Full-Stack Silicon CMOS Quantum Computer,” Sep. 15, 2025. [Online]. Available: https://quantummotion.com/
quantum-motion-delivers-the-industrys-first-full-stack-silicon-cmos-quantum-computer/ C - [416] D. P. DiVincenzo, D. Bacon, J. Kempe, G. Burkard, and K. B. Whaley, “Universal quantum computation with the exchange interaction,” Nature, vol. 408, no. 6810, pp. 339–342, 2000, doi: 10.1038/35042541. arXiv:quant-ph/0005116. S
- [766] S. F. Neyens et al., “Probing single electrons across 300-mm spin qubit wafers,” Nature, vol. 629, no. 8010, pp. 80–85, May 2024, doi: 10.1038/s41586-024-07275-6. D
- [898] A. S. Ivlev et al., “Sparse qubit operation in a 6×6 quantum dot array,” arXiv:2610.07683, Oct. 2026. P
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On-chip flux-DAC multiplexing
SFQ on-chip flux digital-to-analogue converters that hold each qubit's or coupler's DC bias at the mK stage, replacing one room-temperature wire per bias with a multiplexed on-chip network.
Verdict. Proven at 200–300 bias wires for a several-thousand-qubit annealer; the January 2026 fluxonium result is one device with coherence but no gate fidelity, no crosstalk matrix and no peer review.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An on-chip flux DAC (Φ-DAC) is an SFQ circuit on the mK stage that latches the DC flux bias of one qubit or coupler. SFQ pulses push flux quanta (Φ₀ = h/2e) into a superconducting storage loop, which holds the bias indefinitely with no static dissipation and no room-temperature wire. D-Wave has shipped this in annealers for over a decade; the first gate-model application, a flip-chip fluxonium module, came in January 2026 D[316]C[281].
Attributes: fabricated control layer with no intrinsic gate or readout channel; low-frequency bias at the mK stage.
Error structure is coherent — bias-setting error, crosstalk, drift — not relaxation; fabrication is superconducting multilayer lithography.
Physics & limits
The scaling argument is about duty cycle, not power efficiency. Each switching event dissipates ~I_cΦ₀, but a flux bias is reprogrammed on a calibration cadence, not a gate cadence, so thousands of latched channels sit quiescent inside a millikelvin budget that could not host one continuously driven line — unlike SFQ gate control, which pulses at circuit rates. A resource review puts SFQ control at ~1.6 µW/qubit against 2–23 mW/qubit for 4 K cryo-CMOS S[550]fact.
The floor is bias resolution and stability, not coherence. The least significant flux step fixes a residual detuning; thermal cycling and trapped vortices move the working point; and every stored quantum couples magnetically to its neighbours, which is where crosstalk originates. Moving the floor needs low-power SFQ families (ERSFQ — energy-efficient rapid SFQ — and eSFQ) without static bias resistors, finer quantisation, and shielding that keeps the DAC network's fields off the qubit chip.
Engineering state of the art
table
| Year | Figure | Who | Tag/key |
|---|---|---|---|
| 2025-05-20 | Advantage2 GA: 4,400+ qubits, Zephyr degree-20, 12.5 kW | D-Wave | Cfact |
| 2026-01-06 | "200 bias wires" for tens of thousands of qubits and couplers; parts made at NASA JPL | D-Wave | C[281] |
| 2026-01-23 | Flip-chip fluxonium + Φ-DAC: T1 ≈ 200 µs, T2* ≈ 20 µs at 10 mK, no added decoherence resolved | D-Wave | D[316] |
| 2026-03-10 | SFQ control co-integrated with qubits, 1Q > 99% (peak 99.9%) — gate, not flux, control | SEEQC | D[304]fact |
| 2026-03-16 | 14 nm cryo-CMOS flux-bias ASICs on 156-qubit Heron R2, 2Q error ≈ 2.3×10⁻³ (rival) | IBM | C[527]fact |
The annealer ratio is deployed; the gate-model result is one qubit, with coherence but no gate fidelity.
Manufacturing, materials & supply chain
The package bump-bonds a "high-coherence, minimal fabrication" qubit chip to a multilayer control chip across a ~7 µm gap D[316]. The supply chain is the exposure: key components were fabricated at NASA's Jet Propulsion Laboratory C[281] — a government laboratory, not a merchant foundry. D-Wave's 10-Ks state fabrication at "existing third-party foundries" with a second source demonstrated; EDGAR search returns nine "SkyWater" hits in its 2023–2026 filings G[492]. Export exposure is asymmetric and favours SFQ: ECCN 3A901.a controls CMOS ICs designed for ≤4.5 K — a design-intent test capturing a cryo-CMOS design file — while no ECCN names superconducting digital logic; only the finished machine can be caught, under 4A906, and only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits G[301]fact.
Control, readout & I/O burden
The node breaks the one-wire-per-bias law: 200–300 bias wires serve several thousand annealer qubits and tens of thousands of couplers C[281], [316]. Annealer biases are set per program and structurally homogeneous, whereas a gate-model processor retunes per-qubit and per-coupler biases against a drifting calibration. Line count is not the only I/O: bump-bond count, readout and microwave drive are untouched. SFQ pulses are picosecond-scale, so updates are fast; settling time and neighbour disturbance are unpublished. At 10³ D-Wave already operates; at 10⁴ the ~200–300 lines is an annealer ratio, not a fluxonium one; at 10⁶ no path is described and bond density, not wire count, binds.
Role in the stack
This Control-layer node underlies the quantum-annealing architecture (D-Wave), is the alternate control of the dual-rail erasure architecture (D-Wave's gate-model line), and requires superconducting Nb/Al junction lithography and SFQ digital logic at the mixing-chamber stage — the DAC is an SFQ flux-storage loop, so the node hangs off SFQ digital control (ct_sfq) and gives that node its second carrier family; it shares cold-stage fabrication capacity. It replaces room-temperature control lines. The switching cost is a second die, flip-chip bond yield as a new failure mode, and loss of arbitrary waveform shaping on the biased node — bandwidth traded for wire count. Flux biases are quasi-static, so this node adds no term to derived clock = sum of the syndrome round: gate layers + transport + readout + reset; the annealing architecture runs no syndrome round in any case, its cadence being calibration, not circuit, and no figure is quotable. Its empty downstream fan-out understates the case: every superconducting roadmap above ~10³ qubits meets this wall.
Evidence — how the numbers were measured
T1 (relaxation) and T2 (Ramsey) were measured on the single Φ-DAC-controlled fluxonium against a conventional control-line baseline. The comparison has limited sensitivity: T2 ≈ 20 µs is already an order of magnitude below T1 ≈ 200 µs, so "no resolvable increase" bounds rather than measures the DAC's flux noise. Unpublished: any crosstalk matrix, bias drift across thermal cycles, or gate fidelity. The source is a company whitepaper, not peer-reviewed, and unreplicated. Value conflict: D-Wave says 200 bias wires (2026-01-06) C[281] and ~300 (2026-01-23) D[316]; the whitepaper's figure is tied to a described array.
The SkyWater–D-Wave foundry relationship rests on an EDGAR full-text hit count, not a quoted sentence. No ECCN names superconducting digital logic; whether an SFQ control die falls under a catch-all is untested. Not published: the Φ-DAC's settling time, and the scope, capacity or contract terms of JPL's role beyond "key components".
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| D-Wave | developer | CA | Originated Φ-DAC multiplexing; first fluxonium demo | D[316]C[281] |
| NASA JPL | supplier | US | Fabricated key components of the module | C[281] |
| SEEQC | developer | US | SFQ control chips; owns a multilayer superconductor foundry | D[304] |
| IBM | developer | US | Rival 14 nm cryo-CMOS flux-bias ASIC on Heron R2 | C[527] |
| US Dept of Commerce | regulator | US | $100 M CHIPS LOI to D-Wave; BIS sets 3A901.a and 4A906 | G[300], [301] |
Money.
2026-01-20 · D-Wave · M&A, Quantum Circuits Inc. · $550 M ($300 M stock + $250 M cash) · closed C[14]fact
2026-05-21 · D-Wave · CHIPS letter of intent · $100 M · US DoC, $2.013 B package · LOI G[300]fact
2026-05-26 · SEEQC · SPAC registration (Form S-4), Allegro Merger Corp. · $75 M offering + $65 M PIPE, ~$1 B EV · filed G[575]fact; merger terminated 2026-08-25 before closing fact
2026-08-06 · D-Wave · H1-2026 revenue $5.9 M (−67% YoY), cash $546.2 M · reported C[15]fact
Market & supply chain. The scarce input is multilayer niobium capacity: SkyWater as merchant option (quantum ATS revenue +30% YoY on FY2025 revenue $442.1 M G[576]), SEEQC's own Elmsford line, JPL as a government facility with no commercial throughput. No $/channel figure is disclosed. G7 pays most directly; G3/G4 only if the fluxonium route generalises.
IP & standards. No dated patent family specific to on-chip flux-DAC circuits was found; D-Wave's annealer control IP predates this window. SEEQC's SFQ portfolio descends from over $100 M of prior Hypres investment Pfact. No standards activity identified.
Roadmaps & track record. D-Wave gate model: 17 physical qubits (promised 2026-06-01 · for 2026 · reaffirmed 2026-08-06, undelivered as of 4 Sep 2026), then 49 (2027), 181 (2028), 100 logical (2032), Λ = 10 R[14]. Advantage2 GA (promised for 2025 · delivered 2025-05-20) is the clean delivery C[220]. Against that, H1-2026 revenue fell 67% C[15]: the pivot runs on cash, not the business. CFO John Markovich retired effective 2026-09-02; the 8-K of 2026-08-25 states the departure involved no disagreement with the company fact. SEEQC's SPAC merger was terminated on 2026-08-25; its separate S-1 IPO, filed 2026-06-29, had not priced by 30 Sep 2026 fact.
Strategic reading. Three answers compete for one I/O wall: on-chip SFQ Φ-DACs (D-Wave), 4 K cryo-CMOS DACs (IBM, HRL), and needing fewer lines at all — the Shenzhen unified XY+Z architecture drives both through one room-temperature channel per fluxonium at 99.99% 1Q fidelity on eight devices D[315]. That third route is the underrated threat: no cryogenic hardware, and it reports the gate metric the Φ-DAC work omits. If Φ-DACs generalise, D-Wave and Nb foundries gain and room-temperature rack vendors lose per-qubit channel revenue.
Outlook & open questions
Milestones (12–24 months): D-Wave publishes a multi-qubit Φ-DAC result with a crosstalk matrix and gate fidelity (confirm); the 17-qubit 2026 gate-model target ships (confirm); an outside group replicates the coherence result on a second device (confirm) — or the fluxonium line stays a single-device whitepaper through 2027 (demote). Best case 2029: Φ-DAC control of hundreds of independently tuned gate-model qubits, crosstalk below the gate-error budget, adopted outside D-Wave; worst case, proven only for a homogeneous annealer array while cryo-CMOS or line-reduction takes the gate-model market. Open: crosstalk and drift at scale; whether bump-bond density becomes the real wall. Watch: D-Wave's next fluxonium publication, SEEQC's IPO pricing, an SFQ-vs-cryo-CMOS comparison.
References
- [14] D-Wave Quantum Inc., “D-Wave Announces Agreement to Acquire Quantum Circuits Inc., Establishing World's Leading Quantum Computing Company,” Jan. 7, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-to-acquire-quantum-circuits-inc-establishing-world-s-leading-quantum-computing-company/ - [15] D-Wave Quantum Inc., “D-Wave Reports Second Quarter 2026 Results,” Aug. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-reports-second-quarter-2026-results/ - [220] M. Swayne, “D-Wave Announces General Availability of Advantage2 Quantum Computer,” The Quantum Insider, May 20, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ C05/ 20/ d-wave-announces-general-availability-of-advantage2-quantum-computer/ - [281] D-Wave, “D-Wave Demonstrates First Scalable, On-Chip Cryogenic Control of Gate-Model Qubits,” Jan. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-demonstrates-first-scalable-on-chip-cryogenic-control-of-gate-model-qubits/ - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at millikelvin temperature,” Nat. Electron., vol. 9, no. 3, pp. 287–294, Mar. 2026, doi: 10.1038/s41928-026-01576-6. D
- [315] X. Pan et al., “Unified Flux Control Architecture for Fluxonium Qubits,” arXiv:2605.25948, May 2026. D
- [316] D-Wave Quantum Inc., “Digital control of a high-coherence fluxonium qubit,” D-Wave Quantum Inc., Jan. 2026. [Online]. Available: https://www.dwavequantum.com/
media/ D41upubz2/ 14-1090a-a_fluxonium-dac-control.pdf - [492] U.S. Securities and Exchange Commission, “EDGAR full-text search: ‘SkyWater’ in D-Wave Quantum Inc. 10-K filings,” SEC EDGAR Full-Text Search, Feb. 26, 2026. [Online]. Available: https://efts.sec.gov/
LATEST/ Gsearch-index?q=%22SkyWater%22&forms=10-K&ciks=0001907982 - [527] A. Noori et al., “A Cryo-CMOS Control System for Large-Scale Superconducting Qubit Quantum Computing: Part 2,” IBM Research, Mar. 16, 2026. [Online]. Available: https://research.ibm.com/
publications/ Ca-cryo-cmos-control-system-for-large-scale-superconducting-qubit-quantum-computing-part-2 - [550] S. Kawabata, “Integration and Resource Estimation of Cryoelectronics for Superconducting Fault-Tolerant Quantum Computers,” arXiv:2601.03922, Jan. 2026. S
- [575] SeeQC, Inc., “Form S-4 Registration Statement (SeeQC, Inc. / Allegro Merger Corp.),” U.S. Securities and Exchange Commission, May 2026. [Online]. Available: https://www.sec.gov/
Archives/ Gedgar/ data/ 1779977/ 000121390026061108/ ea0278139-04.htm - [576] SkyWater Technology, “SkyWater Technology Reports Fourth Quarter and Full Fiscal Year 2025 Results,” U.S. Securities and Exchange Commission, Feb. 2026. [Online]. Available: https://www.sec.gov/
Archives/ Gedgar/ data/ 1819974/ 000181997426000005/ skyt-20251228xex991.htm
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Laser control with integrated photonics (ions)
On-chip waveguides route cooling, gate and readout light to trapped ions, replacing free-space beams with lithographically fixed optical paths.
Verdict. Proven in laboratory chips (two-ion entanglement at > 99.3% fidelity, 2020) but in no product: Helios still delivers its ≥7 wavelengths to 8 zones as free-space beams, and the best laser gate at scale (7.9×10⁻⁴) is an order of magnitude behind the laser-free electronic gate it competes with.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Light for cooling, state preparation, gates and readout runs in single-mode waveguides fabricated into or beside the trap chip, exiting at the ion through grating couplers instead of free-space beams aligned through vacuum viewports. ETH Zürich demonstrated waveguide-delivered multi-ion logic above 99.3% two-qubit fidelity in October 2020 D[583]. No product uses it yet: Quantinuum's Helios (≥7 wavelengths, 8 zones) delivers its light as focused free-space beams running parallel to the chip surface D[97], while Sandia's MESA complex designs and tests integrated-photonics components with Quantinuum for possible inclusion in future platforms, under a CRADA in force for four years and renewed in May 2026 G[501].
Attributes: optical control modality on a natural ion carrier, delivered inside the vacuum system; no intrinsic gate or readout channel.
Dominant error is coherent — crosstalk, stray-light shifts, phase noise; fabrication is a photonic-IC foundry process (SiN, BTO or thin-film lithium niobate).
Physics & limits
The gate physics is untouched — MS and light-shift gates run identically whether the beam arrives from a mirror or a waveguide, so gate times stay microsecond-scale. Optical power per site is capped by waveguide loss and coupler efficiency, and since gate rate scales with intensity, a loss budget becomes a gate-time budget. Stray light from the photonic layer ac-Stark-shifts and heats neighbouring zones — a coherent channel free-space delivery lacks, traded against the alignment drift it has. And the binding material constraint is the shortest wavelength in the set: Helios's Ba⁺ qubits run on visible and infrared lines (gates at 515 nm), but its Yb⁺ coolant ions are cooled at 369 nm D[97], where waveguide loss and photodarkening are worst and where the supply chain's constrained laser wavelength sits P[322] — the choice of species, coolant included, and photonic integrability are one decision. Moving the floor needs UV-transparent waveguide materials, better couplers, denser multiplexing, and on-chip modulators.
Engineering state of the art
table
| Year | Figure | Who | Tag/key |
|---|---|---|---|
| 2020-10 | Waveguide-delivered multi-ion 2Q gate > 99.3% | ETH Zürich | D[583] |
| 2024-07 | All-electronic 7-zone trap, 2Q 99.97(1)%, 10 qubits — no gate lasers | Oxford Ionics | D[257]fact |
| 2025-10 | Electronic 2Q error 8.4×10⁻⁵, no ground-state cooling | IonQ/Oxford Ionics | D[102] |
| 2025-11-05 | Helios: 98 Ba⁺, 8 zones, ≥7 wavelengths, all free-space; 2Q 7.9(2)×10⁻⁴, 1Q 2.5(1)×10⁻⁵, SPAM 4.8(6)×10⁻⁴ | Quantinuum | D[97] |
The uncomfortable comparison: the best laser gate at scale sits at 7.9×10⁻⁴ while the laser-free electronic gate reaches 8.4×10⁻⁵ D[97], [102]. Integrated photonics competes on stability, zone count and manufacturability, not fidelity; no vendor publishes a metric for the photonic layer itself.
Manufacturing, materials & supply chain
Waveguides (SiN or thin-film lithium niobate) come from photonic-IC foundries, and co-integrating them with trap electrodes is not confined to Sandia's MESA research complex: LioniX International, a merchant photonics foundry, built ETH Zürich's 2020 traps with electrodes, waveguides and couplers on one chip C[882], and MIT Lincoln Laboratory's chip of the same year delivered every wavelength a Sr⁺ qubit needs D[883]. The volume merchant trap fab is Infineon's Villach line (6–12 inch, anodic bonding, Gen-3 out-of-plane electrodes), serving Oxford Ionics/IonQ, eleQtron and Universal Quantum, while Honeywell fabricates Quantinuum's traps in-house C[320]fact. Sandia is therefore a process-development partner, not a supply bottleneck: the genuine single points of failure are UV laser supply (TOPTICA) and Infineon's fab P[322]. No ECCN names ion traps or ion-control photonics G[301]fact; only the finished machine can be caught, under 4A906, and only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact.
Control, readout & I/O burden
Helios sends several free-space beams to each of its 8 zones D[97]; the same trap carries 1,228 electrodes, so the electrical interface is already an order of magnitude larger — optical delivery is not today's binding I/O. Gate-loop latency is unchanged — microsecond-scale, set by the ion-light interaction — so the gain is reliability, not speed. At 10³ ions, beyond Helios's 8 zones, integrated delivery is a candidate for future platforms G[501]; at 10⁴ routing that many low-crosstalk channels is unproven, and neither Sandia partnership names a channel count — both cite scalability as their purpose G[501], [584]; at 10⁶ no path exists, and optical power per waveguide, not channel count, would bind.
Role in the stack
This node is the alternate light delivery of two trapped-ion architectures, "Trapped ions — QCCD (transport between zones)" (Quantinuum) and "Trapped ions — linear Paul trap with individual laser addressing"; it requires photonic-IC fabrication and feeds the Mølmer–Sørensen / light-shift gate. It replaces microwave and electronic ion control, and the switching cost is not a component swap but a fork: an entire laser system against an entire electrode system, with trap geometry, species and error budget downstream. IonQ owns both sides. The node shares the fabrication constraint of natural-carrier platforms needing photonic integration. Delivery does not enter the derived clock: Helios's 2Q gate is ~70 µs but the round is 9.66 ms and the measured full-width layer ~55 ms, dominated by transport, sorting and cooling.
Evidence — how the numbers were measured
The 2020 two-qubit figure is the fidelity of the entangled state the waveguide-delivered gate prepares D[583], not a benchmarked gate error; a paired comparison with free-space delivery on one trap is possible, but none is published. No vendor reports the photonic layer's crosstalk, stray-light heating or phase-noise contribution; Helios's numbers are system-level and free-space D[97], and Sandia's August 2026 announcement carries none G[501]. No independent replication of the 2020 ETH result was found. Reading caveat: AQT's "QV record" of 32,768 is 2¹⁵ against 2²⁵ for Quantinuum's H2 — a record within the rack-mounted class, with no gate time or fidelity disclosed C[128]fact.
No ECCN names ion traps or ion-control photonics. The Ba⁺-versus-Yb⁺ wavelength argument is an engineering inference from the sourced species and supply-chain facts, not a quoted claim. Not published: which Quantinuum system will first carry integrated delivery — Sandia's release names only "future platforms" and the Helios paper describes free-space beams; a dated patent family specific to integrated photonics for ion control; and whether, and on what timeline, SkyWater will fabricate trapped-ion photonics.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US/UK | Develops integrated photonics with Sandia for future platforms; Helios's 8 zones still take free-space beams | D[97], G[501] |
| Sandia National Laboratories | research | US | MESA designs and tests integrated photonics for future trapped-ion platforms; CRADA with Quantinuum, MOU with IonQ | G[501], [584] |
| IonQ | developer | US | Sandia MOU on photonics; owns Oxford Ionics and SkyWater | C[19], [584] |
| Infineon Technologies | supplier | AT | Merchant ion-trap fab at Villach | C[320] |
| TOPTICA Photonics | supplier | DE | Dominant laser supplier; UV is the constrained input | P[322] |
Money.
2025-09-17 · IonQ · M&A, Oxford Ionics (electronic gates) · $1.075 B · closed Cfact
2026-06-03 · Quantinuum · IPO, Nasdaq QNT · $1.68 B gross; Q2-2026 revenue $8.0 M, cash $2.1 B · closed C[123]fact
2026-07-31 · IonQ · M&A, SkyWater Technology (captive US fab) · ~$1.8 B · closed C[19]fact
2026-08-04 · IonQ / Sandia · MOU, quantum co-design for US security work · undisclosed · signed C[584]fact
Market & supply chain. Two upstream markets feed this node, both thin: PIC fabrication co-integrated with trap electrodes, shown at MESA, MIT Lincoln Laboratory and one merchant foundry, LioniX, with PIXEurope the only open-access capacity being built G[582], and UV-capable lasers, dominated by TOPTICA P[322]. No $/unit or $/channel figure is disclosed. G3 and G4 pay for this node — multi-zone delivery is what QCCD scaling requires — plus G7 for replacing field alignment with a fab step.
IP & standards. No dated patent family specific to integrated photonics for ion control was found. A 2026 PatSnap analysis puts IonQ first among trapped-ion assignees with 9+ filings on gate and beam-geometry techniques P[375]. No standards activity identified.
Roadmaps & track record. Quantinuum: Helios (promised 2024-09 · for 2025 · delivered 2025-11-05), Sol (2027, 2D grid trap, in validation), Apollo (2029) R[118]; the QV 10×/year commitment was met. IonQ: 4,000 qubits (promised 2020 · for 2026 · missed ~40×), 256 qubits at 99.99% slipped to H1 2027; both photonics commitments are under three months old as of 4 Sep 2026, with no published result.
Strategic reading. The rival here is not another photonics vendor but the removal of lasers from the gate entirely. The electronic gate leads on fidelity by an order of magnitude, laser delivery on demonstrated zone count; whichever closes its gap first takes the architecture. IonQ has bought both sides and can wait. Quantinuum cannot: it is committed to lasers, and its integrated photonics is being developed at a national laboratory that also serves its main competitor. Free-space alignment hardware is designed out either way; TOPTICA and Infineon keep bargaining power regardless.
Outlook & open questions
Milestones (12–24 months): Sol ships with integrated delivery in its zones and no fidelity regression (confirm); Sandia or Quantinuum publishes a photonic-layer metric (confirm); waveguide-delivered 2Q error reaches the 10⁻⁴ decade (confirm) — or Sol ships on free-space beams like Helios (demote). Best case 2029: integrated delivery is default across laser-gate platforms at 10³-zone scale, crosstalk below the gate-error budget; worst case, it stays in laboratory chips while electronic gates take the trapped-ion roadmap. Open: the photonic layer's isolated error contribution; whether a UV-capable waveguide platform exists for Yb⁺; whether MESA's process transfers to a production fab. Watch: Sol's 2027 delivery, the first Sandia–IonQ publication.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [118] Quantinuum, “Quantinuum Unveils Accelerated Roadmap to Achieve Universal, Fully Fault-Tolerant Quantum Computing by 2030,” Sep. 10, 2024. [Online]. Available: https://www.quantinuum.com/
press-releases/ Rquantinuum-unveils-accelerated-roadmap-to-achieve-universal-fault-tolerant-quantum-computing-by-2030 - [123] Quantinuum, “Quantinuum Announces Pricing of Upsized Initial Public Offering,” Jun. 3, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Cquantinuum-announces-pricing-of-upsized-initial-public-offering - [128] Alpine Quantum Technologies GmbH, “AQT Sets New European Industry Standard: Introducing the ‘LYNX’ Series with Record-Breaking Quantum Volume,” AQT, May 5, 2026. [Online]. Available: https://www.aqt.eu/
lynx-quantum-volume-record/ C - [257] C. Löschnauer et al., “Scalable, High-Fidelity All-Electronic Control of Trapped-Ion Qubits,” PRX Quantum, vol. 6, no. 4, Art. no. 040313, Oct. 2025, doi: 10.1103/h4wk-v31j. arXiv:2407.07694. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [320] Infineon Technologies AG, “Trapped ion quantum computing.” [Online]. Available: https://www.infineon.com/
promo/ Ctrapped-ions - [322] M. Ivezic, “The Optical Table's Hidden Supply Chain: Who Really Wins If Trapped-Ion Quantum Computing Wins,” PostQuantum.com, Oct. 1, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Ptrapped-ion-quantum-ecosystem/ - [375] PatSnap, “Trapped Ion Quantum Computing: Technology Landscape 2026,” Apr. 23, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ trapped-ion-quantum-computing-2026-patsnap-eureka/ - [501] T. Rummler, “In the Mountain West, a quantum computing collaboration announces major results,” Sandia Lab News, Aug. 27, 2026. [Online]. Available: https://www.sandia.gov/
labnews/ G2026/ 08/ 27/ in-the-mountain-west-a-quantum-computing-collaboration-announces-major-results/ - [582] imec, “The European Commission and Chips JU select the PIXEurope consortium to lead the European Pilot Line on Advanced Photonic Integrated Circuits,” Nov. 24, 2024. [Online]. Available: https://www.imec-int.com/
en/ Gpress/ european-commission-and-chips-ju-select-pixeurope-consortium-lead-european-pilot-line - [583] K. K. Mehta et al., “Integrated optical multi-ion quantum logic,” Nature, vol. 586, no. 7830, pp. 533–537, Oct. 2020, doi: 10.1038/s41586-020-2823-6. D
- [584] IonQ, “IonQ and Sandia National Laboratories Sign MOU to Accelerate Quantum Co-Design for National Security Applications,” Aug. 4, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-and-sandia-national-laboratories-sign-mou-to-accelerate-quantum-co-design-for-national-security-applications - [882] LioniX International, “A photonic integrated ion trap for scalable quantum computing,” Nov. 20, 2020. [Online]. Available: https://www.lionix-international.com/
about-us/ Cblog/ a-photonic-integrated-ion-trap-for-scalable-quantum-computing/ - [883] R. J. Niffenegger et al., “Integrated multi-wavelength control of an ion qubit,” Nature, vol. 586, no. 7830, pp. 538–542, Oct. 2020, doi: 10.1038/s41586-020-2811-x. arXiv:2001.05052. D
Русский текст загружается…
הטקסט בעברית נטען…
Room-temperature electronics + per-qubit coax/flex
One coherent line per drive, flux and readout port runs from room-temperature racks through attenuated coax or flex cable into the mixing chamber.
Verdict. Line count and mixing-chamber heat, not gate physics, cap qubits per fridge; falsifiable if one fridge runs >2,000 qubits on RT lines.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The incumbent control architecture for essentially every gate-model superconducting qubit: microwave drive, flux bias and readout tones synthesised at room temperature, carried down the dilution refrigerator on coax or flex cable, attenuated at each stage, reaching the chip at 10–20 mK. Every control degree of freedom is a conductor crossing a 300 K → 10 mK gradient — a thermal and mechanical problem, not a quantum one. In use since the first transmon setups (2007). Attributes: e = microwave control placed entirely at room temperature, no cryogenic amplification or demultiplexing; f = coherent error as the code sees it — crosstalk, phase noise, amplitude drift.
Physics & limits
The binding constraint is the cooling budget, not coherence. Each line carries a passive conduction load plus an active load from the ~60 dB of attenuation that brings 300 K Johnson noise down to the 10 mK photon floor, most of it dumped at 4 K and the still. Cooling power per stage is fixed — a Bluefors XLD400 gives roughly 1 W at 4 K, microwatts at the mixing chamber — so lines scale O(N) against a constant. Krinner et al.'s measured budget supports 50 qubits at 14 mK in that fridge, about 150 at most D[522]; every gain since is thinner cable and denser packing, not new physics. Failure is coherent — crosstalk and phase drift appear as control error, so these machines degrade by needing recalibration rather than by decohering. What moves the floor: multiplexing qubits per conductor, or moving synthesis into the fridge.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2019 | 50 qubits per XLD400 measured; ~150 thermal upper bound | ETH Zürich | D[522] |
| 2023-12 | 1,121 qubits on one fridge (Condor), largest ever wired this way | IBM | C[292] |
| 2025-11-10 | 8 channels per flex, +50% per port, 1,536 lines per XLDsl | Delft Circuits | C[523] |
| 2026-06-16 | KIDE specified at >4,000 rf lines, >1,000 qubits | Bluefors | C[303] |
Wiring sets the N at which errors are worth correcting, not the floor: the dominant term is still two-qubit infidelity — Willow, 105 qubits at 99.88% mean 2Q, 1.1 µs cycle D[1].
Manufacturing, materials & supply chain
Yield here is mechanical (connectors per port, flex delamination, thermal anchoring) and thermal, not lithographic; racks are near-COTS. Cryogenic wiring is the thin layer — Delft Circuits is the leading independent flex supplier and ships inside Bluefors systems C[523]. Refrigerators concentrate the risk: Bluefors absorbed Cryomech's pulse tubes and helium plants in 2023, taking the stage beneath the dilution unit in-house at combined revenue above EUR 160 M C[524]; Oxford Instruments is the only comparable merchant alternative, ULVAC a Japanese third source since 2025 C[525]. Export control cuts asymmetrically: refrigerators past the BIS threshold (≥600 µW at 0.1 K, 48 h) fall under ECCN 3A904, and 3A901.a controls CMOS designed to run at ≤4.5 K — catching the cryo-CMOS alternative — while RT racks are uncontrolled G[301].
Control, readout & I/O burden
Two to four lines per qubit: drive, flux, and readout feedlines multiplexing 5–10 qubits each. At 10³ the architecture works and fills most of a large fridge; KIDE's >4,000 lines is specified for >1,000 qubits, about four each C[303]. At 10⁴ the flex roadmap (40,000+ lines by 2029) is a projection with no interim demonstration R[523], and multiplexing depth rather than cable count becomes the limit. At 10⁶ no RT path exists; every roadmap past ~10⁴ assumes in-fridge control or multi-fridge partitioning. The RT round trip also adds cable delay plus rack processing at µs scale C[526] against Willow's 1.1 µs cycle D[1].
Role in the stack
Serves the transmon, bosonic cat/GKP and dual-rail erasure architectures — the whole superconducting tree — and requires nothing upstream, its commercial strength. It is also the alternate control of the silicon/germanium quantum-dot, silicon-donor and colour-centre spin architectures. Its substitutes (4 K cryo-CMOS, millikelvin SFQ, on-chip flux DACs) each cost a fresh cryogenic qualification burden, and none has displaced it at scale: SEEQC's millikelvin SFQ module reaches 1Q fidelity above 99% and up to 99.9% on five qubits D[304]; HRL's 4 K controller runs 18 silicon spin qubits at Λ₅/₃ = 4.7 D[190]; IBM reports cryo-CMOS flux ASICs at parity with RT electronics on a 156-qubit Heron R2, but as conference abstracts only C[527]. RT wiring adds no gate or readout time, so the derived round stays 0.65 µs, inside the measured 1.1 µs QEC cycle D[1]. Neighbouring empty slot: a multiplexed cryogenic control layer proven at array scale.
Evidence — how the numbers were measured
Every line count above 1,536 is product literature, not a wired system: Bluefors' >4,000 and Delft Circuits' 40,000-by-2029 have no named installation, and neither publishes crosstalk or phase-stability data at high channel count. No independent measurement of aggregate crosstalk above ~1,000 simultaneous lines exists as of 4 Sep 2026 — the gap that matters, since crosstalk is how this architecture fails.
The qubit itself can measure the control chain's noise. On one Jülich transmon line with 56 dB of attenuation, the modelled excitation rate was dominated by classical noise from the room-temperature drive instrument (−146 dBm/Hz above 4.6 GHz) and from the 1 K attenuator stage, while relaxation was set by quantum noise; the qubit's excitation spectrum served as an in-situ spectrometer of that noise P[890]. The result describes one set-up, not every line.
Bluefors' >4,000-line and Delft Circuits' 40,000-by-2029 figures are not demonstrated at system level. IBM's cryo-CMOS flux-bias parity result exists only as APS conference abstracts, with no preprint or paper as of 2026-09-04. No dated ECCN determination covers RT control racks; their uncontrolled status is read from the absence of a matching entry in the 2024 rule, not from an explicit BIS statement. Not published: a per-line or per-loom cost, and the revenue and customer counts of Delft Circuits and Zurich Instruments.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Bluefors | supplier | Finland | Refrigerators with integrated looms; KIDE at >4,000 lines | C[303] |
| Delft Circuits | supplier | Netherlands | Cri/oFlex ribbon, 8 channels per flex, inside Bluefors XLDsl | C[523] |
| Quantum Machines | supplier | Israel | OPX control racks and controller software | C[528] |
| Zurich Instruments | supplier | Switzerland | ZQCS racks on Fujitsu/RIKEN's 256-qubit system | C[526] |
| Qblox | supplier | Netherlands | Modular control stacks, lower price point | C[529] |
| IBM | developer | USA | Condor, 1,121 qubits on one fridge; cryo-CMOS challenger | C[292] |
| SEEQC | developer | USA | Millikelvin SFQ control, an in-fridge alternative | D[304] |
Money.
2023-03-28 · Bluefors · M&A, Cryomech · undisclosed, combined revenue > EUR 160 M · closed C[524]
2024-06-20 · Qblox · Series A · USD 26 M · Quantonation, Invest-NL Deep Tech · closed C[529]
2025-02-25 · Quantum Machines · Series C · USD 170 M · PSG Equity lead · USD 280 M cumulative · closed C[528]
2025-12-03 · Delft Circuits · Series A extension · EUR 8 M · DeepTech XL, HTGF, QuVest · EUR 15 M cumulative · closed P[530]
2026-06-17 · Quantum Machines · M&A, PCB Engineering (Hungary) · undisclosed · closed C[528]
Market & supply chain. Racks are competitive and commoditising: five vendors qualified for NVQLink C[531], Quantum Machines best capitalised at USD 280 M cumulative C[528], Qblox an order of magnitude smaller C[529]. Fridges and their wiring are concentrated, and Delft Circuits at EUR 15 M cumulative P[530] is the one significant independent flex supplier — a single point of failure. Pays for G2, G3, G7; not G4.
IP & standards. No dated patent-family count for cryogenic rf cabling or RT control was found in a named database — no dated fact found. No formal standard; the closest is NVQLink, which since 2025-10-28 defines a common GPU-side interface across five control vendors C[531] while each pulse stack stays proprietary.
Roadmaps & track record. Delft Circuits (2025-11-10, for 2029): 40,000+ lines per fridge, no interim milestone R[523]. Bluefors (2026-06-16, undated): KIDE at >4,000 lines, product page only C[303]. Zurich Instruments (2026-03-09, undated): "several thousand qubits" C[526]. Both cabling vendors have shipped every density step they announced; 2029 is nonetheless a straight-line projection.
Strategic reading. If RT wiring reaches 10⁴ qubits, the rack vendors and Bluefors keep the control budget and cryo-CMOS or SFQ control stays a research programme. If density stalls near 4,000–5,000 lines, bargaining power moves inside the fridge, where no RT vendor owns IP — and the strongest cryo-CMOS results sit with IBM and HRL, one company since 2026-08-26 fact. Export control favours the incumbent G[301].
Outlook & open questions
Confirm by end-2027 if one fridge runs >2,000 qubits on RT lines with published fidelity at that density; demote after another year of line-count specifications without a wired system. Best case by 2029: flex density plus deeper multiplexing reaches 10⁴ qubits, stack unchanged. Worst case: density plateaus near 4,000–5,000 lines while roadmaps beyond assume undelivered cryo-CMOS or SFQ. Open questions: does crosstalk grow faster than linearly past ~1,000 lines; do flex density and multiplexing compound or hit independent walls; will any vendor commit to in-fridge control before RT wiring visibly fails; does multi-fridge partitioning make the per-fridge ceiling irrelevant.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [292] J. Gambetta, “The hardware and software for the era of quantum utility is here,” IBM Quantum Computing Blog, Dec. 4, 2023. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ quantum-roadmap-2033 - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [303] Bluefors, “KIDE Cryogenic Platform — For Large-Scale Quantum Computing,” Jun. 16, 2026. [Online]. Available: https://bluefors.com/
products/ Ckide-cryogenic-platform/ - [304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at millikelvin temperature,” Nat. Electron., vol. 9, no. 3, pp. 287–294, Mar. 2026, doi: 10.1038/s41928-026-01576-6. D
- [522] S. Krinner et al., “Engineering cryogenic setups for 100-qubit scale superconducting circuit systems,” EPJ Quantum Technology, vol. 6, no. 1, Art. no. 2, Dec. 2019, doi: 10.1140/epjqt/s40507-019-0072-0. arXiv:1806.07862. D
- [523] Physics World (IOP Publishing), “Delft Circuits, Bluefors: the engine-room driving joined-up quantum innovation,” Nov. 10, 2025. [Online]. Available: https://physicsworld.com/
a/ Cdelft-circuits-bluefors-the-engine-room-driving-joined-up-quantum-innovation/ - [524] Bluefors, “Bluefors closes the acquisition of Cryomech,” Mar. 28, 2023. [Online]. Available: https://bluefors.com/
press-releases/ Cbluefors-closes-the-acquisition-of-cryomech/ - [525] ULVAC, “ULVAC Developing Next-Generation Dilution Refrigerator for Quantum Computing by 2026,” Nasdaq (JCN Newswire), Mar. 20, 2025. [Online]. Available: https://www.nasdaq.com/
press-release/ Culvac-developing-next-generation-dilution-refrigerator-quantum-computing-2026-2025-03 - [526] Zurich Instruments, “Zurich Instruments Launches the ZQCS Quantum Control System to Master the Long-Lived Logical Qubit Challenge,” Mar. 9, 2026. [Online]. Available: https://www.zhinst.com/
americas/ Cen/ news/ zurich-instruments-launches-zqcs-quantum-control-system-master-long-lived-logical-qubit/ - [527] A. Noori et al., “A Cryo-CMOS Control System for Large-Scale Superconducting Qubit Quantum Computing: Part 2,” IBM Research, Mar. 16, 2026. [Online]. Available: https://research.ibm.com/
publications/ Ca-cryo-cmos-control-system-for-large-scale-superconducting-qubit-quantum-computing-part-2 - [528] Quantum Machines, “Quantum Machines Raises $170M as Its Customer Base Exceeds 50% of Companies Developing Quantum Computers,” Feb. 25, 2025. [Online]. Available: https://www.quantum-machines.co/
press-release/ Cquantum-machines-raises-170-million-in-series-c-funding/ - [529] E. Flipse, “Qblox secures series A funding to accelerate quantum control stack development,” Qblox Newsroom, Jun. 20, 2024. [Online]. Available: https://qblox.com/
newsroom/ Cqblox-secures-series-a-funding-quantum-control-stack-development - [530] M. U. Rehman, “Delft Circuits Names Martin Danoesastro CEO and Extends Funding Round,” The Quantum Insider, Dec. 3, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P12/ 03/ delft-circuits-new-ceo-financing/ - [531] NVIDIA, “NVIDIA Introduces NVQLink — Connecting Quantum and GPU Computing for 17 Quantum Builders and Nine Scientific Labs,” Oct. 28, 2025. [Online]. Available: https://nvidianews.nvidia.com/
news/ Cnvidia-nvqlink-quantum-gpu-computing - [890] J. R. Guimarães et al., “Quantum environment afterglow from broadband excitation spectroscopy in superconducting qubits,” arXiv:2609.31280, Sep. 2026. P
Русский текст загружается…
הטקסט בעברית נטען…
Laser + AOD/SLM optical control (atoms)
Free-space lasers, holographic modulators and acousto-optic deflectors generate, move, image and drive the optical-tweezer arrays that hold neutral-atom qubits.
Verdict. This layer, not the 270 ns gate, sets the neutral-atom clock: imaging plus transport keep the QEC round at 1–4.5 ms as of 4 Sep 2026, and trap power scales linearly at ~0.67 mW per site.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A holographic modulator splits one beam into a static lattice of tweezer foci; crossed acousto-optic deflectors, driven by multi-tone rf, steer individual traps; further lasers cool, image and drive the hyperfine and Rydberg transitions. Modulators frame at tens of hertz, static within a shot, so fast motion belongs to the deflectors or to optical-lattice conveyors. Endres set the pattern in 2016 — real-time control of 100 tweezers building defect-free arrays of over 50 atoms in under 400 ms D[577] — and that measure-decide-move-verify loop is still the clock.
- e/f: entirely optical, room temperature, outside the vacuum cell; errors are coherent — pointing, hologram phase, rf intermodulation.
- d/g: connectivity comes from deflector transport, built of free-space optics.
Physics & limits
Two hard laws govern this layer. Trap power is linear in site count: Tsinghua's 18,225-site array takes 33 W incident, 12.2 W effective, ~0.67 mW per trap D[145], so 10⁶ sites implies about a kilowatt of trapping light before any imaging or Rydberg beam. And a deflector's resolvable-spot count is its rf bandwidth times the acoustic transit across the beam, while that transit lower-bounds how fast a trap is re-pointed: more sites and faster moves pull against each other in one device. Neither is a "refresh rate". The consequence is the clock: imaging at 0.5–1 ms and transport at hundreds of µs give QEC rounds of 1–4.5 ms against 270 ns gates D[4]. Failure modes are systematic: trap-depth non-uniformity, pointing drift, tone intermodulation. Faster imaging moves the floor — 17.6 µs readout at 99.89(5)% discrimination on ytterbium P[261], ~50× off the dominant term.
Engineering state of the art
Largest array: 11,022 rubidium atoms in an 18,225-site grid from a 19.8 mm metasurface outside the vacuum cell — no gates, no coherence, 60.5% filling before rearrangement D[145]. Best sustained operation: 3,217 atoms at 99.3% filling beyond two hours, reloading 300,000 atoms per second for 30,000 initialised qubits per second, moved by optical-lattice conveyors, not deflectors D[144]. Typical at scale is far smaller: the 448-atom architecture, where imaging and transport set a 1–4.5 ms round D[4]. Dominant limit: measurement and motion latency, not trap count or power.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-09 | 3,217 atoms, >2 h, 30,000 initialised qubits/s | Harvard | D[144] |
| 2026-06 | 18,225 metasurface traps, 11,022 atoms, 0.67 mW/site | Tsinghua | D[145] |
| 2026-07 | 2,000 tweezers from 20 W, 3.5 µm pitch, sub-100 nm | Fraunhofer ILT | P[578] |
| 2026-08 | 17.6 µs imaging, 99.89(5)% discrimination, 98.80(44)% survival | Kyoto | P[261] |
A chip-scale alternative to the frequency-reference chain was shown in 2026: a 780 nm Si₃N₄ microcomb (a chip resonator that turns one pump laser into a comb of evenly spaced, mutually coherent lines) locked to an ⁸⁵Rb transition held its pump drift to the 100 kHz level over 2,000 s, and because the comb is coherent the lock disciplines every line at once. One line, amplified to 102 mW and delivered through free space, formed an optical lattice 4.2 recoil energies deep and a Raman coupling of 0.7 recoil energies on an ⁸⁷Rb Bose–Einstein condensate P[886]. One channel was demonstrated; sharing the reference across many channels is the authors' projection.
Manufacturing, materials & supply chain
No wafer: commodity and semi-custom free-space optics integrated by hand — yet the concentration is severe. Only two deflector vendors appear in the sourced literature, AA Opto-Electronic (DTSX-400, in the 448-atom system) and Gooch & Housego Dfact, and Hamamatsu supplies both modulator and camera with no alternative identified Cfact — the two real single points of failure. A June-2026 alliance of Hamamatsu, NKT Photonics and Yaqumo is the first attempt to industrialise the tier, aimed at a sensing market projected at $3.5–7.9B P[335]. Tsinghua's metasurface points the other way: a lithographic element replacing the objective is the one step that could become semiconductor manufacturing D[145]. No export-control category names tweezer optics; exposure runs via ECCN 4A906 fact.
Control, readout & I/O burden
One optics chain serves the whole array, so the burden is bandwidth and optical power, not lines per qubit — the inverse of the superconducting problem, and why atom counts scale while clocks do not. At 10³ sites full fault-tolerant loops run today D[4]. At 10⁴ the binding constraint is the measure-rearrange-verify cycle: 11,022 atoms trapped against 448 under logical control. Nothing exists at 10⁶. The only end-to-end control-loop figure a vendor publishes is QuEra's Gemini repetition rate: one shot per second at 260 qubits C[137].
Role in the stack
This layer underlies all three neutral-atom architectures — the alkali (QuEra, Pasqal, Infleqtion, Google) and alkaline-earth(-like) (Atom Computing/Microsoft, Caltech) Rydberg tweezer arrays and the neutral-atom analogue simulator — supplying the Rydberg drive and deflector transport that the gate and zoned-connectivity mechanisms consume. It replaces photonic-integrated trap control, trading chip-scale integration for free-space flexibility. Nearly every neutral-atom mechanism sits on it. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 1.31 ms, transport 0.80 ms of it, against a measured 1–4.5 ms round — set entirely here. Empty neighbouring slot: an integrated optical control plane keeping deflector flexibility.
Evidence — how the numbers were measured
Trap counts and filling come from direct fluorescence imaging and are not disputed, but they are compared across incompatible boundaries: 11,022 trapped atoms and 448 qubits under fault-tolerant control measure different things, and filling is quoted before rearrangement (60.5% D[145]) or after (99.3% D[144]) unlabelled. Latency figures are architectural, measured inside one group's system and never reproduced, and the metasurface and 2,000-tweezer results are each single-group.
The €65k-per-atom figure is derived from one order, not a price list. Not published: named customers of the Hamamatsu, NKT Photonics and Yaqumo alliance; the vacuum lifetime and any coherence measurement for the 18,225-site metasurface array; and any cost breakdown below system level.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| QuEra Computing | developer | USA | Sells Gemini: 260 atoms, one shot per second | C[137] |
| Atom Computing | developer | USA | Ytterbium platform; builds Magne with Microsoft | C[154] |
| Pasqal | developer | France | Rydberg tweezer systems; SPAC-listed Aug 2026 | P[156] |
| Hamamatsu Photonics | supplier | Japan | Modulators and qCMOS cameras | P[335] |
| AA Opto-Electronic | supplier | France | Crossed AODs for tweezer transport | Dfact |
Money.
| Date | Actor | Event | Amount | Programme / lead | Status |
|---|---|---|---|---|---|
| 2025-07-17 | QuNorth | Magne order, 1,225 physical | €80M | Atom Computing, Microsoft | ordered Cfact |
| 2025-09-09 | QuEra | financing round | $230M+ | Google, SoftBank Vision Fund 2 | closed C[153] |
| 2025-11-06 | DARPA | QBI Stage B: Atom Computing, QuEra | ≤$15M | QBI | official fact |
| 2026-06-16 | Atom Computing | Series C plus CHIPS LOI | $100M + $100M | Third Point; US Commerce | closed+LOI C[154] |
| 2026-08-28 | Pasqal | SPAC close | ~$360M cash, 2025 revenue €16.5M | — | closed P[156] |
Market & supply chain. Two deflector vendors and one camera-and-modulator vendor against a laser field with real alternatives (NKT, TOPTICA, Coherent): the concentration sits in deflectors and cameras, small unlisted businesses under four venture-funded platforms. Unit economics are quotable at system level — QuNorth's €80M for 1,225 atoms is ~€65k per atom, two orders below a trapped-ion delivery per ion Pfact, because tweezer optics amortise across sites. It pays for G1, is a prerequisite for G3, blocks G4 until the millisecond cycle falls.
IP & standards. No patent family specific to tweezer control surfaced: the technique descends from open literature and the entrants are spin-outs of the groups that published it. Vendor IP sits in the deflector and modulator products, not quantum-specific; PatSnap's counts are not disaggregated here Pfact. No litigation, no standards body.
Roadmaps & track record. QuEra (2024, for 100 logical in 2026) — retargeted to "Libra" in 2028, a two-year slip, no control-hardware change announced. Atom Computing with Microsoft (2025-07, for 50 logical in Magne at the turn of 2026/27) — installing as of 4 Sep 2026, the field's only firm delivery date. Pasqal (2024, for 10,000 physical in 2026) — slipped to 2028, now funded. Infleqtion (2025-09, for 1,000 logical by 2030) — capitalised, no latency figure. Google (2026-03) — staffed, no milestone.
Strategic reading. If this layer industrialises the winner is whoever consolidates the optics tier, not a platform company: a supplier owning deflectors, modulators and cameras prices against every neutral-atom vendor at once, which is what the Hamamatsu alliance is positioned to become. The platforms' counter is integration — metasurfaces and trap chips pulling optics onto a wafer. If the millisecond cycle holds they lose together: atom counts already exceed what anyone can control, so latency is the differentiator, and superconducting rivals hold three orders on clock.
Outlook & open questions
Confirm/demote in 12–24 months: a QEC round below 1 ms above 10³ sites; a second group replicating the metasurface array or the 17.6 µs imaging; Magne benchmarked at 50 logical qubits. Best case 2029: fast imaging and conveyor transport cut the round to ~100 µs, removing the clock disadvantage. Worst case: latency stays at milliseconds, arrays large, cheap and slow. Open: is the deflector bandwidth-transit trade engineering or a hard limit; can fast imaging survive at 10⁴ sites; will anyone second-source the deflectors. Watch Magne's acceptance tests.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [137] QuEra Computing Inc., “Gemini-Class Gate-Model Quantum Computer.” [Online]. Available: https://www.quera.com/
gemini C - [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [145] Y. Wang et al., “Trapping 11,000 Atoms in a Tweezer Array Generated by a Single Metasurface,” arXiv:2606.02715, Jun. 2026. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [261] R. Yokoyama et al., “Minimally Destructive Fast Imaging of Single Atoms in an Optical Tweezer Array with Coherent Excitation,” arXiv:2605.24175, Jun. 2026. Also https://arxiv.org/
abs/ . P2605.24175 - [335] M. Abdel-Kareem, “Hamamatsu Photonics, NKT Photonics, and Yaqumo Form Alliance to Industrialize Cold-Atom Quantum Core Components,” Quantum Computing Report, Jun. 4, 2026. [Online]. Available: https://quantumcomputingreport.com/
hamamatsu-photonics-nkt-photonics-and-yaqumo-form-alliance-to-industrialize-cold-atom-quantum-core-components/ P - [577] M. Endres et al., “Cold Matter Assembled Atom-by-Atom,” arXiv:1607.03044, Jul. 2016. D
- [578] M. Swayne, “Fraunhofer ILT Develops Laser System for 2,000-Qubit Neutral-Atom Quantum Computer,” The Quantum Insider, Jul. 8, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P07/ 08/ fraunhofer-ilt-develops-laser-system-for-2000-qubit-neutral-atom-quantum-computer/ - [886] W. Sun et al., “A photonic integrated comb engine for ultracold quantum gases,” arXiv:2609.28294, Sep. 2026. P
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Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring
Control and readout lines from room-temperature electronics reach each superconducting qubit through the face of the chip — coaxial pins, contact probes, superconducting vias or a stacked signal die — instead of being routed in the chip plane to its edge.
Verdict. Carries a 256-qubit processor (RIKEN/Fujitsu) and a >500-qubit wafer-scale package (OQC); it removes the edge-routing wall but not the line count, and line crosstalk has been published only for a four-qubit device as of 2026-09-26.
TSV = through-silicon via; MXC = mixing chamber, the coldest refrigerator stage; T1, T2e = relaxation and echoed dephasing times; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Lines still start in room-temperature racks (ct_rt); only the last centimetre changes. Instead of a coplanar line routed to a wire-bond pad at the die edge, the signal enters through the chip's face — a spring-loaded or coaxial pin, a contact probe, a superconducting via, or a bump-bonded signal die. Waterloo's quantum socket (2016) pressed spring-mounted coaxial wires onto the chip D[532]; Oxford's coaxial circuit QED (2017) put qubit and resonator on opposite faces with all wiring perpendicular D[533], the root of OQC's coaxmon. RIKEN chose backside superconducting vias over flip-chip interfaces that still bring pads to the edge C[534] and reviewed the packaging this needs G[535].
Attributes: microwave control at room temperature; coherent error; superconducting-lithography fabrication.
Physics & limits
Edge routing. In an m × m lattice every line serving a qubit inside a ring crosses the ring's ~4m inter-qubit gaps; with k lines per qubit and c per gap, routing closes at m = 4c/k — for k = 2 and c = 3–5, N ≈ 36–100 S. That is the ~100-qubit plateau QuantWare cites C[536], with "almost 90% of the chip" spent on routing C[537]. A flip-chip signal die raises c, but lines still leave through a perimeter ∝ √N while their number grows ∝ N — polynomial, not the vendor's "exponential fan-out" S. Vertical entry keeps lines per unit area constant, so the lattice tiles.
The line. A vacuum coaxial hole is 50 Ω at a diameter ratio of 2.3 S. OQC's 50 ± 2.5 Ω pins end 0.9 mm (qubit) or 0.4 mm (resonator) from the circuit and couple evanescently below the hole's cutoff: control-line selectivity −40 to −60 dB at 2 mm pitch D[538]. Non-galvanic pins carry no DC, so flux-tuned qubits and couplers need probes, vias or bumps S.
Box modes. A 20 mm silicon die can resonate as low as ~3 GHz, inside the qubit band S; OQC's inductive pillar lifts the enclosure cutoff to 34.3 GHz and bounds parasitic coupling to |J|/2π < 250 kHz D[538].
Heat is set per line, not by the route: OQC's fully wired wafer-scale package is estimated at ≤~3 µW on the MXC against 25–30 µW of cooling at 20 mK D[311].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2016-05 | Spring-mounted coaxial wires, DC–8 GHz, contact ~150 mΩ, mismatch ~10 Ω | Univ. of Waterloo | D[532] |
| 2017-08 | Superconducting TSVs, zero via-to-via resistance below aluminium's critical temperature | Rigetti | D[539] |
| 2020 | 10 × 20 × 200 µm TSVs carry control and readout in a bump-bonded stack | MIT Lincoln Laboratory | D[540] |
| 2021-11 | 127 qubits, wiring on "multiple physical levels" | IBM Eagle | C[541] |
| 2022-04 | 2 × 2 coaxmons; T1 149(38) µs; single-qubit fidelity 99.982(4)% | Oxford / OQC | D[538] |
| 2023-03 | 64 qubits, 2 cm chip, contact probes, 96 input + 16 output lines | RIKEN consortium | C[542] |
| 2025-04 | 256 qubits; density ×4 in the same refrigerator | RIKEN / Fujitsu | C[51] |
| 2026-02 | >500 qubits on a 3-inch die; median T1 97 µs, T2e 129 µs | OQC | D[311] |
Among the register's carriers, beyond 256 gate-coupled qubits only claims exist: VIO-40K (VIO is QuantWare's vertical-wiring architecture), 40,000 lines for 10,000 qubits in chiplet modules, shipping 2028 C[536]. No Japanese machine has a two-qubit error in the register, and OQC's package reports coherence and readout, not gates D[311].
Manufacturing, materials & supply chain
Vias: MIT Lincoln Laboratory fabricates qubits on a TSV-bearing surface D[540]; Rigetti's sloped walls let evaporated or sputtered films coat the via D[539]. Pins: OQC's package manages differential thermal contraction across 3 inches with 0.5 mm pin gaps D[311]. Stacks: QuantWare integrates "all signal conditioning components" C[537] and opens KiloFab, Delft, in 2026 at 20× its 2025 capacity C[536]. Pin, via and bump yields at 10³–10⁴ contacts are unpublished as of 2026-09-26.
Control, readout & I/O burden
Vertical delivery moves lines; it does not remove them. RIKEN's 64 qubits take 112 lines C[542], 1.75 per qubit S; OQC's four-qubit device two per qubit D[538]; VIO-40K four C[536]. OQC's wafer-scale package shares each line among nine qubits, control riding on readout D[311] — ~0.11 per qubit S; the dimon, GENESIS's qubit C[543], drives both modes through one control line D[250]. At 10³ qubits that is 10²–4×10³ lines S; at 10⁴ QuantWare claims one cryostat C[537]; at 10⁶ only cold multiplexing — ct_cryocmos, ct_sfq — closes the gap S. Loop latency is unchanged S.
Role in the stack
Slot 5 of "Transmon lattice with tunable couplers" and "Dual-rail erasure qubits". It requires ct_rt's electronics behind the vertical wiring and fab_sc's vias, pins and interposers; it and ct_rt replace one another ("edge-routed vs vertical signal delivery"); no provides edge is recorded. What it frees is the die edge, for chip-to-chip links between edge qubits C[537] — a precondition for ic_multidie. Ten register machines carry it (10 as primary). RIKEN 64 and RIKEN–Fujitsu 256 are ✅ on vendor figures; Toshiko's ✅ rests on the four-qubit paper, GENESIS's on the dual-rail paper, VIO-40K's on its announcement. The Fujitsu 1,000-qubit machine is 🔎: the cited article names high-density packaging, not perpendicular wiring P[546]; the 10,000-qubit cell's wiring is undisclosed. Contralto-A17 and Tenor-D64 are not among them: the source presents Contralto-A as "a cost-efficient upgrade path to QuantWare's VIO-powered QPUs", not as one C[544], and the D-line page pictures "VIO 1K" and "VIO 40K" modules without naming a processor C[545]. Gap G-vio, answered: lines per qubit span 0.11–4; routing-layer count is undisclosed by every carrier.
Evidence — how the numbers were measured
Line crosstalk exists only as OQC's four-qubit selectivity matrix D[538]; RIKEN, Fujitsu and QuantWare publish none in the sources opened, as of 2026-09-26. OQC's package is the one many-qubit dataset: median T1, T2e ~100 µs over ~100 qubits, readout fidelity 97.5% and qubit temperature 36 mK over 54 D[311]. Missing: simultaneous benchmarks over >100 lines; contact yield across thermal cycles.
Not published: whether IBM's Eagle-generation signals enter through the chip face; Rigetti Ankaa's signal delivery; QuantWare's impedance, yield and heat-load data for VIO, and which processor carries "VIO 1K"; and, for OQC's package with nine-way sharing over 56 cells, the number of lines entering the package and whether its qubits are coupled.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| RIKEN | research | JP | Contact-probe package, 64 qubits | C[542] |
| Fujitsu | developer | JP | 256-qubit unit-cell tiling; 1,000 qubits listed for 2026 | C[51] |
| Oxford Quantum Circuits | developer | UK | Coaxmon on Toshiko and GENESIS; wafer-scale package | C[543]D[311] |
| QuantWare | supplier | NL | VIO chip stack; VIO-40K for 2028 | C[537] |
| MIT Lincoln Laboratory | research | US | TSVs in bump-bonded stacks | D[540] |
| Rigetti Computing | developer | US | Superconducting TSV process | D[539] |
| IBM | developer | US | Multi-level wiring (Eagle) | C[541] |
Money.
- 2026-05-05 · QuantWare · Series B led by Intel Capital and In-Q-Tel, naming VIO-40K and KiloFab · USD 178 M · announced C[547]
- 2026-06-02 · OQC · Series C led by Bullhound Capital, coaxmon not named · GBP 260 M · announced C[60]
Market & supply chain. RIKEN/Fujitsu and OQC build their own packages; QuantWare sells VIO to "scale the qubit chiplets and designs of third parties" C[547]. Serves G2–G4 (transmon) and G3–G4 (dual-rail).
IP & standards. OQC calls the coaxmon "patented" C[543], no number traced; QuantWare pitches VIO-40K as the standard of its Quantum Open Architecture P[495]. No standards body, as of 2026-09-26.
Roadmaps & track record. In July 2020 RIKEN aimed for a 64-qubit device "within the next three years" C[534] and opened it on 2023-03-27 C[542] — kept. Fujitsu still lists 1,000 qubits for 2026 C[75], no launch found as of 2026-09-26. QuantWare: VIO-40K 2028 C[536]; no interim VIO data, as of 2026-09-26.
Strategic reading. Past ~100 qubits vertical entry decides whether a die tiles, not whether a refrigerator can feed it; value moves to via, bump and pin capacity and to whoever first publishes crosstalk and yield at scale.
Outlook & open questions
Confirm if, by 2027-12-31, a vertically wired processor above 256 qubits publishes two-qubit errors with simultaneous crosstalk; demote if Fujitsu's 1,000-qubit machine passes 2026-12-31 undisclosed or VIO-40K slips past 2028. Open questions. (1) What pitch holds selectivity below −40 dB at 1 mm qubit spacing? (2) Can non-galvanic pins serve flux-tuned couplers? (3) What is contact yield per thermal cycle at 10⁴ pins? (4) Does nine-way line sharing survive coupled qubits and gates? (5) At what scale does the stack's own heat bind?
References
- [51] Fujitsu Limited and RIKEN, “Fujitsu and RIKEN develop world-leading 256-qubit superconducting quantum computer,” Fujitsu Global, Apr. 22, 2025. [Online]. Available: https://info.archives.global.fujitsu/
global/ Cabout/ resources/ news/ press-releases/ 2025/ 0422-01.html - [60] A. Curbison, “OQC raises £260m in Europe's largest ever private quantum computing funding round,” OQC, Jun. 2, 2026. [Online]. Available: https://oqc.tech/
company/ Cnewsroom/ series-c - [75] Fujitsu, “Fujitsu Quantum.” [Online]. Available: https://global.fujitsu/
en-global/ Ctechnology/ research/ quantum - [250] J. Wills, M. T. Haque, and B. Vlastakis, “Error-detected coherence metrology of a dual-rail encoded fixed-frequency multimode superconducting qubit,” arXiv:2506.15420, Jun. 2025. D
- [311] O. W. Kennedy et al., “Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits,” arXiv:2602.12773, Feb. 2026. D
- [495] M. Abdel-Kareem, “QuantWare Debuts VIO-40K™ Architecture to Enable 10,000-Qubit Superconducting Processors,” Quantum Computing Report, Dec. 10, 2025. [Online]. Available: https://quantumcomputingreport.com/
quantware-debuts-vio-40k-architecture-to-enable-10000-qubit-superconducting-processors/ P - [532] J. H. Béjanin et al., “The Quantum Socket: Three-Dimensional Wiring for Extensible Quantum Computing,” Phys. Rev. Appl., vol. 6, Art. no. 044010, 2016, doi: 10.1103/PhysRevApplied.6.044010. arXiv:1606.00063. D
- [533] J. Rahamim et al., “Double-sided coaxial circuit QED with out-of-plane wiring,” Appl. Phys. Lett., vol. 110, no. 22, Art. no. 222602, May 2017, doi: 10.1063/1.4984299. arXiv:1703.05828. D
- [534] RIKEN, “Wiring a new path to scalable quantum computing,” Jul. 3, 2020. [Online]. Available: https://www.riken.jp/
en/ Cnews_pubs/ research_news/ rr/ 20200703_2/ index.html - [535] S. Tamate, Y. Tabuchi, and Y. Nakamura, “Toward Realization of Scalable Packaging and Wiring for Large-Scale Superconducting Quantum Computers,” IEICE Trans. Electron., vol. E105.C, no. 6, pp. 290–295, Jun. 2022, doi: 10.1587/transele.2021SEP0007. G
- [536] QuantWare, “QuantWare announces scaling breakthrough with VIO-40K™, delivering 10,000 qubit Quantum Processors for the first time,” Dec. 8, 2025. [Online]. Available: https://quantware.com/
news/ Cquantware-announces-scaling-breakthrough-with-vio-40k - [537] QuantWare, “Technology — VIO™ 3D Scaling Architecture.” [Online]. Available: https://quantware.com/
technology C - [538] P. A. Spring et al., “High coherence and low cross-talk in a tileable 3D integrated superconducting circuit architecture,” Sci. Adv., vol. 8, no. 16, Art. no. eabl6698, Apr. 2022, doi: 10.1126/sciadv.abl6698. arXiv:2107.11140. D
- [539] M. Vahidpour et al., “Superconducting Through-Silicon Vias for Quantum Integrated Circuits,” arXiv:1708.02226, Aug. 2017. D
- [540] D.-R. W. Yost et al., “Solid-state qubits integrated with superconducting through-silicon vias,” npj Quantum Inf., vol. 6, Art. no. 59, 2020, doi: 10.1038/s41534-020-00289-8. arXiv:1912.10942. D
- [541] J. Chow, O. Dial, and J. Gambetta, “IBM Quantum breaks the 100‑qubit processor barrier,” IBM Quantum Computing Blog, Nov. 16, 2021. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ 127-qubit-quantum-processor-eagle - [542] NTT (joint release of RIKEN, AIST, NICT, Osaka University, Fujitsu and NTT), “Japanese joint research group launches quantum computing cloud service: Opening access to Japan's first superconducting quantum computer,” Mar. 24, 2023. [Online]. Available: https://group.ntt/
en/ Cnewsrelease/ 2023/ 03/ 24/ 230324a.html - [543] Oxford Quantum Circuits, “Devices – OQC,” OQC. [Online]. Available: https://oqc.tech/
tech/ Cdevices/ - [544] QuantWare, “Introducing Contralto-A: a QPU for quantum error correction,” Feb. 25, 2025. [Online]. Available: https://quantware.com/
news/ Cintroducing-contralto-a-qpu-for-quantum-error-correction - [545] QuantWare, “D-line QPUs — Build bigger, scale faster.” [Online]. Available: https://quantware.com/
product/ Cprocessors/ d-line - [546] M. Swayne, “How Fujitsu Is Tackling a 10,000-Qubit Quantum Computer for Practical Applications,” The Quantum Insider, Dec. 8, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P12/ 08/ how-fujitsu-is-tackling-a-10000-qubit-quantum-computer-for-practical-applications/ - [547] QuantWare, “QuantWare Raises $178 Million to Build World’s Most Powerful Quantum Processors at an Industrial Scale,” May 5, 2026. [Online]. Available: https://quantware.com/
news/ Cquantware-raises-178-million
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הטקסט בעברית נטען…
Free-space laser addressing of ions (AOM/AOD beams)
Gate light from a room-temperature optical bench is switched and steered onto individual ions of one chain by multi-channel acousto-optic modulators or acousto-optic deflectors and focused through bulk optics above the trap.
Verdict. The most common ion control in the register, published to 40 addressed ions per chain with neighbour crosstalk of 10⁻³–10⁻²; no per-pair benchmark of a longer free-space-addressed chain was found as of 2026-09-26, and IonQ's roadmap past Tempo rests on chips and photonic links.
AOM = acousto-optic modulator; AOD = acousto-optic deflector; MS = Mølmer–Sørensen gate; DRB = direct randomised benchmarking; ε = the neighbour's Rabi frequency over the target's; QV = quantum volume; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An optical bench sends gate light through viewports and a high-aperture objective; acousto-optics set which ion is lit and the light's amplitude, frequency and phase. A multi-channel AOM gives one rf channel per fixed beam — 32 at 355 nm in the 2016 five-qubit Maryland machine, the technology's origin D[585]; an AOD maps rf frequency to angle, so a steered beam reaches any ion D[100]. Hyperfine qubits take a Raman pair — 355 nm for ¹⁷¹Yb⁺ D[586], 532 nm for ¹³³Ba⁺ D[109]; ⁴⁰Ca⁺ optical qubits take one 729 nm beam D[253].
Attributes: optical control at room temperature; coherent errors; bulk optics; one assembly per chain.
Physics & limits
Crosstalk. A Gaussian field falls as exp(−d²/w²) — ~10⁻¹² at EURIQA's 0.85 µm waist and 4.43 µm pitch S — yet the neighbour sees up to 2.5% of the target's Rabi frequency D[254]: aberration and scatter set the floor. Published neighbour figures, in differing measures, fall from <4% in 2016 D[585] to <9×10⁻⁴ D[587]. For a Rabi ratio ε, a spectator rotated by εθ loses ≈(εθ/2)², 2.5×10⁻⁴ at ε = 10⁻² for a π pulse S; being coherent, the error compensates — intensity-scaling light-shift pulses cut the AQT demonstrator's 0.5% neighbour figure to 1.3×10⁻⁴ D[253].
Pointing and phase. Jitter δx shifts the Rabi rate by ~(δx/w)² S; Forte sizes its 1.5 µm waist against pointing noise D[100]. At 355 nm, 56 nm of path between counter-propagating arms is 1 rad of gate phase S; Forte configures two of its four paths for phase-insensitive single-qubit gates D[100].
The AOD. θ = λf/v; resolution is aperture time × bandwidth; thermal drift needs in-situ angle calibration G[588]. Duke's UV AOD deflects 6 mrad over a 100 MHz band D[587], i.e. v ≈ 5.9 km/s S. The rf also shifts the optical frequency with position; AQT's crossed AODs cancel it D[253]. ~50 beam diameters of steering D[587] span 25–50 ions at 3–4 µm spacing S. Pairs are served in sequence D[109]: 15 disjoint pairs at Forte's median 672 µs MS gate take ~10 ms S. Field of view and serialisation hold a chain near 30–40 ions S.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2016-08 | 5 ¹⁷¹Yb⁺; 32-channel UV AOM; crosstalk <4%; XX gate 235 µs | Univ. of Maryland | D[585] |
| 2019-11 | 11 qubits in 13 ions; global + addressed 355 nm beams; 2Q 97.5% | IonQ | D[586] |
| 2021-06 | Crossed AODs, 729 nm; neighbour crosstalk 0.5%; 24-ion GHZ 54.4(7)% | Innsbruck / AQT | D[253] |
| 2021-10 | 32 beams, 0.85 µm waist; 13 qubits in 15 ions; 2Q 98.5–99.3% | EURIQA (Maryland/Duke) | D[254] |
| 2023-08 | 4 AODs; 30 qubits in 36 ions; 2Q DRB median 4.64×10⁻³ | IonQ Forte | D[100] |
| 2026-01 | AOD module <1 ft²; crosstalk <9×10⁻⁴; 30-ion chain; 240 ns switching | Duke | D[587] |
| 2026-06 | 40 ¹³³Ba⁺; AOD-steered 532 nm Raman beams | IonQ | D[109] |
Above 40 ions, beyond Helios's 98 ions in a QCCD trap, only claims exist: Tempo's page lists 100 "target" qubits and 99.9% "target fidelity", with no addressing method C[101]. Tsinghua's 512-ion crystal runs global 411 nm beams — free space without addressing D[121].
Manufacturing, materials & supply chain
An assembly, not a wafer: a pulsed UV laser (EURIQA: Coherent Paladin 355-4000) D[254], acousto-optics — fused silica in the UV, TeO₂ in the visible G[588] — objectives and rf synthesis; Duke's module uses a Brimrose AOD D[587]. Gooch & Housego and AA Opto Electronic are also named P[322]; G&H deflectors steer 3,000- and 6,100-atom tweezer arrays too C[504], a supply shared with cx_aod. AQT fits 12 qubits in two 19-inch racks, 2 m², <2 kW C[382].
Control, readout & I/O burden
A multi-channel AOM needs one rf channel per ion at fixed pitch — EURIQA idles two end ions to keep the spacing uniform D[254]; Forte's four AODs, each behind an AOM that sets amplitude, frequency and phase, are designed to reach any of 40 ions — the benchmark ran 36, limited by its photon-detection channels — and free the trapping potential D[100]. Switching (~240 ns) D[587] is negligible; serialisation is the latency — Ba-testbed code cycles take 35–86 ms, all ions shelved to D₅/₂ during mid-circuit readout D[109]. At 10³ ions: ~25 benches plus photonic links S.
Role in the stack
Slot 5 of "Trapped ions — linear Paul trap with individual laser addressing" and "Trapped ions — QCCD (transport between zones)". It requires fab_optics (bulk optics above the trap), provides the free-space fields g_ms requires, and is replaced by ct_ionlaser (integrated delivery) and ct_ionmw (laser-free, microwave-driven electronic gates, two-qubit error 8.4(7)×10⁻⁵ D[102]). Sixteen register machines carry it (16 as primary), among them IonQ Aria, Forte, Tempo and the 40-ion Ba testbed; Quantinuum Helios, H1 and H2; AQT IBEX Q1 and LYNX; PIAST-Q; QSCOUT (Quantum Scientific Computing Open User Testbed); the FIAN / Rosatom 70-qubit ion machine; Tsinghua; Innsbruck; Maryland/Duke. Seven cells are ✅; Aria's is 🔎, its beam optics shown only for the 2019 predecessor D[586]; Tsinghua's is 🔎 and shows global beams; Tempo, PIAST-Q and the Rosatom machine are 🔎. Qudoor AbaQ is not among them: its control is undisclosed. AQT and Innsbruck are profiled as ⁴⁰Ca⁺ optical qubits, as their cited papers use D[253]D[255]. Gap G-ionaod is closed, with ion_chain in place of the proposed ion_elec.
Evidence — how the numbers were measured
Crosstalk is quoted as Rabi ratio, intensity ratio (ε²) or spectator error — Duke calls a Rabi ratio "intensity crosstalk" D[587] — and measured by moving one ion through the beam D[253], by flag ions D[254] or by simultaneous benchmarks D[109]. Forte's 435-pair DRB finds no significant dependence on ion distance but significant out-of-model errors D[100]. Of the vendor pages opened, only AQT's specifies crosstalk, neighbour <1.8×10⁻², as of 2026-09-26 C[382].
Not published: Tempo's species, gate time and addressing method, Aria's own architecture and Qudoor AbaQ's control; and any quantitative figure for rf power per tone, multi-tone intermodulation or AOD thermal pointing drift in ion systems.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IonQ | developer | US | AOD addressing on Forte and the 40-ion Ba testbed | D[100]D[109] |
| Alpine Quantum Technologies | developer | AT | Crossed-AOD 729 nm addressing, rack systems | D[253]C[382] |
| University of Innsbruck | research | AT | Steerable 729 nm beams, 16 ions | D[255] |
| Univ. of Maryland / Duke | research | US | 32-channel AOM; compact AOD module | D[254]D[587] |
| Tsinghua University | research | CN | 512-ion crystal, global beams | D[121] |
| Qudoor | developer | CN | In-house lasers and control; addressing undisclosed | P[302] |
| Gooch & Housego | supplier | UK | AODs, AOMs | C[504] |
Money.
- 2023-12-05 · AQT · 20-qubit two-rack computer for LRZ and Munich Quantum Valley, Bavarian funding · ~EUR 9.8 M · contracted C[323]
- 2025-09-17 · IonQ · acquisition of Oxford Ionics (chip-manufactured traps) · not stated in the release · closed C[18]
Market & supply chain. Lasers, acousto-optics, objectives and rf are merchant parts; ytterbium's UV lines demand expensive, power-limited lasers P[322]. Both architectures serve G2, G3, G6 and G7.
IP & standards. IonQ filings on compensating Raman beam-geometry errors (JP 2024, EP 2025) P[375]; no crosstalk-reporting standard found as of 2026-09-26.
Roadmaps & track record. IonQ (2025-06-13): Tempo, 100 qubits, 2025; 10,000 on one chip, 2027; >2,000,000 by 2030, naming Oxford Ionics 2D traps and photonic links as the means R[132]. Tempo's figures remain targets C[101]; the 2026-04-14 two-system photonic link gave no rate or fidelity C[589]. AQT's LYNX claims QV 32,768 and lower laser phase-noise sensitivity, no qubit count C[128].
Strategic reading. The fastest route to a working 30–40-ion machine and the yardstick for integrated and electronic delivery, but not a scaling path; value moves to trap chips and links.
Outlook & open questions
Confirm if, by 2027-12-31, IonQ publishes Tempo's per-pair gate times, fidelities and addressing method, or an addressed chain above 60 ions is benchmarked; demote if IonQ's next systems ship on electronic or integrated delivery. Open questions. (1) What sets the neighbour floor below 10⁻³ — aberration, scatter or rf intermodulation? (2) Can multi-tone AODs run parallel gates without stray beams? (3) How does pointing drift scale with rf duty cycle? (4) Does double-sided steering hold at 100 ions? (5) When does a photonic link beat a longer chain?
References
- [18] IonQ, “IonQ Completes Acquisition of Oxford Ionics, Rapidly Accelerating Its Quantum Computing Roadmap,” Sep. 17, 2025. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-oxford-ionics-rapidly-accelerating-its-quantum - [100] J.-S. Chen et al., “Benchmarking a trapped-ion quantum computer with 30 qubits,” Quantum, vol. 8, Art. no. 1516, Nov. 2024, doi: 10.22331/q-2024-11-07-1516. arXiv:2308.05071. D
- [101] IonQ, “IonQ Tempo: 100-Qubit Quantum Computer (#AQ 64).” [Online]. Available: https://ionq.com/
quantum-systems/ Ctempo - [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [109] E. Tham et al., “Breakeven demonstration of quantum low-density parity-check codes,” arXiv:2606.06455, Jun. 2026. D
- [121] S.-A. Guo et al., “A site-resolved two-dimensional quantum simulator with hundreds of trapped ions,” Nature, vol. 630, no. 8017, pp. 613–618, May 2024, doi: 10.1038/s41586-024-07459-0. D
- [128] Alpine Quantum Technologies GmbH, “AQT Sets New European Industry Standard: Introducing the ‘LYNX’ Series with Record-Breaking Quantum Volume,” AQT, May 5, 2026. [Online]. Available: https://www.aqt.eu/
lynx-quantum-volume-record/ C - [132] IonQ, “IonQ's Accelerated Roadmap: Turning Quantum Ambition into Reality,” Jun. 13, 2025. [Online]. Available: https://www.ionq.com/
blog/ Rionqs-accelerated-roadmap-turning-quantum-ambition-into-reality - [253] I. Pogorelov et al., “Compact Ion-Trap Quantum Computing Demonstrator,” PRX Quantum, vol. 2, no. 2, Art. no. 020343, Jun. 2021, doi: 10.1103/PRXQuantum.2.020343. arXiv:2101.11390. D
- [254] L. Egan et al., “Fault-tolerant control of an error-corrected qubit,” Nature, vol. 598, no. 7880, pp. 281–286, Oct. 2021, doi: 10.1038/s41586-021-03928-y. arXiv:2009.11482. D
- [255] L. Postler et al., “Demonstration of fault-tolerant universal quantum gate operations,” Nature, vol. 605, pp. 675–680, 2022, doi: 10.1038/s41586-022-04721-1. arXiv:2111.12654. D
- [302] M. U. Rehman, “Top Chinese Quantum Computing Companies in 2026,” The Quantum Insider, May 15, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P05/ 15/ 10-plus-companies-leading-the-quantum-technologies-race-in-china/ - [322] M. Ivezic, “The Optical Table's Hidden Supply Chain: Who Really Wins If Trapped-Ion Quantum Computing Wins,” PostQuantum.com, Oct. 1, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Ptrapped-ion-quantum-ecosystem/ - [323] AQT, “AQT lands million euro contract,” Dec. 5, 2023. [Online]. Available: https://www.aqt.eu/
aqt-lands-million-euro-contract/ C - [375] PatSnap, “Trapped Ion Quantum Computing: Technology Landscape 2026,” Apr. 23, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ trapped-ion-quantum-computing-2026-patsnap-eureka/ - [382] Alpine Quantum Technologies, “19-inch rack-mounted quantum computer,” AQT. [Online]. Available: https://www.aqt.eu/
products/ Cibex-q1/ - [504] Gooch & Housego (G&H), “G&H Acousto-Optic Deflectors Referenced in Nature Papers Demonstrating 3,000 & 6,100 Qubit Quantum Systems,” G&H, Mar. 2026. [Online]. Available: https://gandh.com/
news-and-resources/ Cg-and-h-acousto-optic-deflectors-in-nature-papers - [585] S. Debnath, N. M. Linke, C. Figgatt, K. A. Landsman, K. Wright, and C. Monroe, “Demonstration of a small programmable quantum computer with atomic qubits,” Nature, vol. 536, no. 7614, pp. 63–66, Aug. 2016, doi: 10.1038/nature18648. arXiv:1603.04512. D
- [586] K. Wright et al., “Benchmarking an 11-qubit quantum computer,” Nat. Commun., vol. 10, Art. no. 5464, Nov. 2019, doi: 10.1038/s41467-019-13534-2. arXiv:1903.08181. D
- [587] J. Yu et al., “Design and Characterization of Compact Acousto-Optic-Deflector Individual Addressing System for Trapped-Ion Quantum Computing,” arXiv:2601.01647, Jan. 2026. D
- [588] R. Paschotta, “Acousto-optic Deflectors,” RP Photonics Encyclopedia. [Online]. Available: https://www.rp-photonics.com/
acousto_optic_deflectors.html G - [589] IonQ, “IonQ Achieves Key Photonic Interconnect Milestone, Demonstrating Networked Quantum Systems Using Entanglement,” Apr. 14, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-achieves-key-photonic-interconnect-milestone-demonstrating-networked-quantum-systems-using-entanglement
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הטקסט בעברית נטען…
Electro-optic drive + feed-forward electronics (room temperature)
Room-temperature modulators driven from detector outcomes inside one optical clock cycle — the feed-forward layer every photonic architecture needs.
Verdict. Loop latency reached 150–196 ns in 2026 against an 80 ns switch: electronics sit ~2× above the component floor, not orders of magnitude. Demote if no system-scale sub-µs loop by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The 300 K layer that drives photonic qubits and closes the measurement loop: pump lasers, thin-film lithium-niobate (TFLN) or barium-titanate (BTO) modulators, and electronics turning a detector click or homodyne quadrature into a drive voltage before the next photon arrives. Alone among control nodes it has no cryogenic variant: electronics at 300 K read detectors near 2 K, so every loop crosses that boundary twice. Attributes: no carrier of its own, immobile, loss-dominated error; electro-optic modality at room temperature, photonic-IC fabrication.
Physics & limits
Modulator bandwidth is not the constraint. What binds is detector rise, discrimination, decision and driver settling, which must fit inside optical delay you can afford. Holding a photon 100 ns in silicon nitride costs ~15 m of waveguide; at PsiQuantum's measured 1.8 ± 0.2 dB/m single-mode SiN loss that is ~27 dB against a per-photon budget near 0.5 dB. The same delay in fibre costs ~4 mdB plus two fibre-to-chip transitions at 52 ± 12 mdB D[169]. Feed-forward delay must live off-chip; its loss price is packaging, not waveguide S. Past ~1 GHz the wall becomes SNSPD dead time.
Engineering state of the art
table
June 2026 reset the arithmetic: 80 ns against a 1 µs cycle is ~12×, and rack electronics at 150–196 ns cut it to ~2×. That array's zero static power costs 1.48 dB per cell, ~15× PsiQuantum's 100 mdB in-line switch D[169], [516] — routing plane, not fusion plane.
The three 2026 latency figures sit at different reference planes, and no source reconciles them. The 27 dB on-chip against 4 mdB in-fibre delay comparison is derived from published loss figures, not measured. Not published: a cost per modulator or per feed-forward channel.
Manufacturing, materials & supply chain
TFLN comes from two merchant vendors, HyperLight and Lightium P[518]; volume BTO only from PsiQuantum's 300 mm GlobalFoundries flow D[169] and Lumiphase's pilot D[516]; Xanadu's 0.085 dB/facet coupling used Corning and DISCO C[172]. No cost per channel is public. I/O burden is this node: a driver and DAC per modulator, a coax and discriminator per detector. QuiX's unit is 32×32 C[825], so 10³ modes is ~30 racks; at 10⁴ the wall is inter-rack clock skew, at 10⁶ nothing scales. The machine falls under BIS ECCN 4A906 fact.
Role in the stack
Shared, not an architecture choice: it drives the fusion architecture (PsiQuantum, Quandela, QuiX) and the continuous-variable/GKP architecture (Xanadu) identically, also serves the boson sampler, and sets the derived clock wherever fusions or homodyne measurements iterate — 1.0 MHz at system scale, 5–7 MHz at unit scale. Verification: the figures sit at three reference planes. QuiX's ~150 ns is detector-to-drive C[825]; 196 ns a full CV loop P[822]; Aurora's 1 MHz a cycle time, not a latency D[173].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Xanadu | developer | CA | Only system-scale single-cycle feed-forward | D[173] |
| PsiQuantum | developer | US | 300 mm BTO switches, DARPA V&V | D[169] |
| QuiX Quantum | developer | NL | Rack feed-forward unit, ~150 ns | C[825] |
| Lumiphase | supplier | CH | Non-volatile BTO array | D[516] |
Money.
2024-09 · HyperLight · Series B · USD 37 M · Summit Partners · closed P[518]
2025-07-10 · QuiX · Series A · EUR 15 M · Invest-NL, EIC · closed Cfact
2026-05-21 · GlobalFoundries · CHIPS LOI · USD 375 M · US Commerce fact
2026-07-22 · PsiQuantum · QBI Stage C, BTO-switch V&V · USD 125 M · DARPA P[181]
Market & supply chain. Two TFLN vendors, one volume BTO line, and no merchant vendor of low-latency feed-forward at all — each firm builds its own. The scarce input is the deterministic sub-200 ns detector-to-driver path, not the modulator. Pays for G3/G4, G6.
IP & standards. No feed-forward patent family surfaced from a dated database as of 2026-09-04; the BTO gate array is the dated advance D[516].
Roadmaps & track record. Xanadu 1 MHz (delivered 2025-01, unimproved) D[173]; QuiX named fast feed-forward a 2026 blocker in 2025-07 and installed the unit 2026-06-02 C[825]; PsiQuantum published no 2026 hardware result P[181]. QuiX alone shipped what it named.
Strategic reading. If sub-200 ns loops generalise, the bottleneck migrates to detector dead time and the fibre delay lines holding photons during the decision — favouring owners of packaging and detector supply over FPGA vendors. A merchant feed-forward box would commoditise a layer three firms treat as differentiation.
Outlook & open questions
Confirm by 2027: a loop under 200 ns above 32 channels, or a system cycle faster than 1 MHz; demote if Aurora's 1 MHz still stands in 2028. Best case 2029: ~10 MHz rack-scale. Worst case: unit latency never couples to scale. Open: does 150 ns hold under 32-channel load; does non-volatile BTO reach usable in-line loss.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [172] Xanadu, “Xanadu sets new industry benchmark in photonic chip packaging,” PR Newswire, Jun. 10, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cxanadu-sets-new-industry-benchmark-in-photonic-chip-packaging-302796562.html - [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [181] M. Abdel-Kareem, “PsiQuantum Secures $125 Million Expanded Agreement with DARPA under QBI Program,” Quantum Computing Report, Jul. 22, 2026. [Online]. Available: https://quantumcomputingreport.com/
psiquantum-secures-125-million-expanded-agreement-with-darpa-under-qbi-program/ P - [516] C. Català-Lahoz et al., “High-speed non-volatile barium titanate field-programmable photonic gate array,” Nat. Photon., vol. 20, no. 8, pp. 932–940, Aug. 2026, doi: 10.1038/s41566-026-01934-y. D
- [518] optics.org, “Lithium niobate in vogue as thin-film developers raise cash,” Sep. 24, 2024. [Online]. Available: https://optics.org/
news/ Plithium-niobate-in-vogue-as-thin-film-developers-raise-cash - [822] D. Duggan et al., “FPGA Based Feedforward System for Photonic Quantum Computing Applications,” arXiv:2606.03500, Jun. 2026. P
- [825] QuiX Quantum, “QuiX Quantum Installs Real-Time Control Component for Universal Photonic Quantum Computer,” Jun. 2, 2026. [Online]. Available: https://www.quixquantum.com/
news/ Cquix-quantum-installs-real-time-control-component-for-universal-photonic-quantum-computer
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הטקסט בעברית נטען…
Mid-circuit erasure check
Ancilla- or fluorescence-based test of whether a qubit is still in its code space, flagging decay/leakage as a located erasure without reading the logical state.
Verdict. The check is solved on transmons (384 ns, residual 6×10⁻⁴); unsolved are erasure fraction under two-qubit gates, false negatives and the cycle-time tax. Demote if no erasure system shows logical Λ > 2 by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A mid-circuit erasure check asks "is this qubit still inside its code space?" and returns a one-bit herald with the qubit's location without disturbing the logical state. It needs an encoding whose dominant decay leaves the code space: dual-rail (one excitation in two transmons or two cavities; loss leaves the detectable vacuum) or a metastable atomic qubit (³P₀ in ¹⁷¹Yb, D₅/₂ in ⁴⁰Ca⁺) whose ground-state decay fluoresces under a beam the qubit does not see. Proposals: Princeton/Yale, 2022-01 — 98% of ¹⁷¹Yb errors convertible, surface-code threshold 0.937%→4.15% S[8]; AWS dual-rail transmons, 2022-08 S[334]; Yale cavities, 2022-12 S[399]. Demonstrations: Princeton ¹⁷¹Yb D[141] and Caltech ⁸⁸Sr D[143] in 2023-05; AWS transmons D[400] and Yale cavities D[401] in 2023-07.
Attributes from the technology graph (legend: a affinity natural↔fabricated; b time, deterministic/heralded; c readout mechanism, time, destructive?, mid-circuit?; d mobility; e control @ placement; f error structure; g manufacturing):
- a = 0.5, carrier-agnostic.
- b = n/a.
- c = ancilla erasure check, ≈400 ns (10^−6.4 s), non-destructive, mid-circuit — the transmon record D[85], not the atomic 20 µs D[141].
- d = none.
- e = microwave @ room temperature (atoms: optical).
- f = erasure-convertible (located, heralded loss).
- g = none (a protocol, not an object).
Rank 1 of 111; shared by the superconducting and neutral-atom families.
Physics & limits
In a transmon dual-rail pair the logical states are |10⟩ and |01⟩, so a T1 decay of either transmon lands in |00⟩. The check is a joint dispersive readout tuned so that both logical states pull the shared resonator equally while the vacuum pulls it differently; AWS reaches a residual logical splitting of −0.7(5) kHz against a −4.25 MHz dispersive shift D[85]. In a cavity pair an ancilla sensitive to the total photon number does the same job in 1.82 µs D[404]. For atoms a decay from ³P₀ to ¹S₀ is caught by 20 µs of fluorescence on ¹S₀–¹P₁, invisible to the metastable qubit, so survivors pick up less than 10⁻⁵ error per check D[141].
Each check costs one exposure to T1: AWS measures 2.54(1)×10⁻² erasure per 384 ns check against a residual undetected error of 6.0(2)×10⁻⁴; their ratio, the erasure bias of 42(1), is what a code cares about D[85].
Three floors are intrinsic. False negatives re-enter the code as leakage: Yale's 3.7% false-negative rate times its erasure rate gives a missed-erasure fraction of 9.0(5)×10⁻⁴ D[404]; AWS's are the readout's ≈0.8% separation error D[85]. Back-action: residual χ mismatch dephases the qubit by 8(3)×10⁻⁵ per check and the readout tone halves the erasure lifetime while on D[85]. Time: in atoms the 20 µs check stretches to 420 µs when Rydberg population must decay before imaging — hence 56(4)% of single-qubit but only ≈33% of two-qubit errors are converted D[141]. The code sees a located erasure p_e, a Pauli residual ≈p_e/40 and an unheralded leakage tail ≈FN×p_e; under that channel the surface-code threshold is 4.15% S[8] and biased-erasure codes reach 8.2–10.3% S[643]. The floor moves with longer T1, stronger readout and, for atoms, faster Rydberg-leakage detection.
Engineering state of the art
Best demonstrated: one dual-rail transmon qubit checked in 384 ns with a 6×10⁻⁴ residual (2026-04) D[85]; a cavity CZ with 0.5% erasure and 0.03% Pauli error (2026-08) D[84]. Typical at scale (3 Sep 2026): nothing above ten erasure qubits except OQC GENESIS, 16 dual-rail sites with error-detected readout — SUSTech's four dual-rail transmons at 98.8% logical Bell fidelity (2025-04) D[406], Quantum Circuits' 8-qubit Seeker (2024-11) C[86]. On atoms, Princeton's [[4,2,2]] blocks D[142] and JILA's 20-atom GHZ state D[644] (2025-06) are the largest erasure-checked circuits; Microsoft/Atom Computing's 24 logical qubits use end-of-round loss imaging, not mid-circuit checks D[149].
table
| Year | Figure | Who | Tag | Src |
|---|---|---|---|---|
| 2023-05 | 20 µs check at 0.986 detection fidelity; 56(4)% of 1Q errors converted | Princeton ¹⁷¹Yb | D | [141] |
| 2023-07 | Erasure 2.19(2)×10⁻³ per gate, residual ≈40× lower, <0.1% dephasing per check | AWS transmons | D | [400] |
| 2024-06 | 1.82 µs mid-circuit check, FP 0.51%, FN 3.7% | Yale cavities | D | [404] |
| 2024-11 | ⁴⁰Ca⁺ Bell 98.56→99.14% with erasure excision; 1 ms check | Oregon | D | [393] |
| 2025-06 | ¹⁷¹Yb error-detected CZ 99.78(4)%, >90% Rydberg-decay detection | JILA | D | [644] |
| 2025-06 | [[4,2,2]] teleportation 0.771→0.802 with erasure-selected ancillas | Princeton | D | [142] |
| 2026-04 | 384 ns check, residual 6.0(2)×10⁻⁴, bias 42(1) | AWS | D | [85] |
| 2026-08 | Dual-rail CZ 500 ns, erasure ≈0.5% per gate, Pauli 0.029(6)%, bit-flip 2.8(4)×10⁻⁶ | Quantum Circuits | D | [84] |
Dominant term today: on transmons the idling erasure during the check (T1 ≈25 µs); on cavities the ancilla's decoherence; on atoms undetectable two-qubit errors and the Rydberg dead time.
Manufacturing, materials & supply chain
Transmon dual-rail uses standard superconducting lithography, but the pair must be flux-tunable to find a χ-matched point and dodge two-level systems, and both must be good — a yield-squared problem; AWS's five-day samples fluctuate with near-resonant TLSs D[85]. Cavity dual-rail needs two machined high-Q cavities plus an ancilla per qubit, hand-assembled — hence Quantum Circuits' plan of 8 → 17 → 49 → 181 qubits over 2024–2028 R[94]. The atomic check needs only an imaging beam and a camera. Cost and energy per checked qubit are unpublished. The transmon check inherits the dispersive-readout chain, whose amplifiers and refrigerators are the concentrated items. Export exposure: the BIS rule of 2024-09-06 G[301] fact lists parametric amplifiers and cryo-CMOS (3A901), refrigerators of ≥600 µW at ≤0.1 K (3A904) and quantum computers (4A906), these only when their qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact; the rule does not say whether a dual-rail qubit counts as one or two.
Control, readout & I/O burden
Superconducting: one readout resonator per dual-rail qubit on a multiplexed feedline, two flux lines per qubit, one TWPA per line — twice a transmon's I/O. Replacing an erased qubit within the cycle needs feed-forward of a few hundred ns. At 10³ qubits the wiring is the transmon wall doubled; at 10⁴ only cold multiplexing or cryo-CMOS works, helped by the one-bit flag; at 10⁶ the 384 ns per cycle and 2×10⁶ transmons are the price of the 40× bias. Atoms: one global 20 µs pulse and one camera frame per check — lines do not grow with N, but camera readout and processing (0.1–1 ms) set the loop latency, and fast frames cost survival (98.80(44)% for Kyoto's 17.6 µs ¹⁷⁴Yb imaging D[261]); the wall beyond 10⁴ atoms is frame budget.
Role in the stack
Two architectures: superconducting dual-rail erasure and alkaline-earth(-like) neutral atoms. It requires an erasure-detectable encoding — dual-rail, or the metastable "omg" (optical–metastable–ground) encoding — and provides the flags that dual-rail encodings and erasure-adapted codes consume. It displaces leakage removal and post-selection on bare transmons. The price of switching is 2× transmons plus a check every cycle; on atoms the metastable manifold costs single-qubit fidelity (99.12(4)% in ³P₀ against 99.968(3)% in the ground state of JILA's omg device D[645]). The pairing "fabricated carrier with an erasure error structure" is genuine; "natural carrier with ≤10 µs readout" is inherited from the transmon time, not earned by the 20 µs atomic check. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: dual-rail architecture 2.8 µs, set by the gate layers, with the 0.40 µs check a seventh of it; atom architecture 1.3 ms, set by transport, the check ≈1.5% of it. Neighbouring empty slots: the cold-stage decoder (a natural consumer of one-bit heralds) and the microwave–optical transducer.
Evidence — how the numbers were measured
FP/FN (false-positive/false-negative rates) come from preparing |0_L⟩, |1_L⟩ and the erased state and repeating the check; AWS quotes FP ≈ FN ≈0.8% and derives residual and bias from repeated-check and interleaved sequences under continuous detection D[85]. Gate-level erasure fractions are flag statistics and the residual Pauli error a low-depth linear fit D[84]. Atomic conversion fractions rest on the 0.986 detection fidelity D[141]; Caltech's ≥0.9971 Bell fidelity is a post-excision, SPAM-corrected bound D[143].
Not captured: survival (every headline fidelity is conditioned on "no erasure"; at 2.5% per check, forty checks halve the sample); false negatives, visible only as leakage in a multi-round code; spectator dephasing on shared feedlines, unbenchmarked beyond four qubits; drift (TLS-driven swings over 5–18 days D[85]); the time tax. Independent replications: AWS (2023, 2026) D[85], [400], Yale (2023, 2024) D[401], [404], Quantum Circuits (2026) D[84], SUSTech (2025) D[406], UMass (2026) D[405]; Princeton (2023, 2025) D[141], [142], Caltech (2023) D[143], JILA (2025) D[644]; Oregon (2024) D[393].
Conflicts. D-Wave says its qubits detect "approximately 90% of errors" C[94]; at gate level the fraction is 83–94% depending on whether the Pauli residual is the <0.1% bound or the 0.029% fit D[84]. Atomic two-qubit conversion is 33–38% D[141], [142] against the proposal's 98% S[8]. The [[4,2,2]] gain from erasure information is 1.9(4)× in the 2025-06 arXiv text D[142] but 3.6× as carried in the graph from the 2026-06 Nature Physics version D[142]; the arXiv value is used pending the published text.
Quantum Circuits' cumulative funding of ≈ $84 M to May 2024 is a trade-press figure P[646]; the company's release states no total. Oregon's metastable-ion Bell fidelities read 98.61 → 99.16 % in abstract summaries and 98.56 → 99.14 % in the arXiv v1 full text, the values used here D[393]. Not published: whether Quantum Circuits is the unnamed 18th DARPA QBI Stage A company — DARPA names 17 of 18 fact; the cost or energy per checked qubit, from any actor; a patent count for the Yale/Quantum Circuits dual-rail cavity families beyond two individual patents; AWS's spending on its dual-rail programme, and the grants attributable to this primitive behind the Princeton, Caltech, Yale, Oregon and SUSTech groups; and the atomic species of Google's neutral-atom track.
Actors & economics
Who.
| Organisation | Role | Country | What it does with the check | Evidence |
|---|---|---|---|---|
| Quantum Circuits Inc. | developer | US | Cavity dual-rail qubits; 8-qubit Seeker; 17-qubit system due 2026; D-Wave unit since 2026-01 | D[84] C[86] fact |
| AWS Center for Quantum Computing | developer | US | 384 ns χ-matched transmon check | D[85], [400] |
| Yale University | research | US | Cavity dual-rail origin; ancilla check | D[401], [403], [404] |
| SUSTech (Shenzhen) | research | China | Four dual-rail transmon qubits | D[406] |
| Princeton University | research | US | ¹⁷¹Yb metastable conversion; [[4,2,2]] | D[141], [142] |
| Google Quantum AI | developer | US | Atom track under Kaufman (ex-JILA ¹⁷¹Yb omg), 2026-03 | fact P[158] D[644], [645] |
| Atom Computing | developer | US | ¹⁷¹Yb 1,225-atom systems; loss by imaging; Magne with Microsoft | D[149] fact |
Money.
- 2024-05 · Quantum Circuits · Series B extension · $26.5 M · Sequoia · cumulative ≈$84 M · closed P[646] fact
- 2024-08-15 · Quantum Circuits · Series B close · >$60 M · ARCH, F-Prime, Sequoia, Hither Creek · overlaps the extension · closed C[647] fact
- 2025-07-17 · QuNorth · Magne order, 50 logical qubits · €80 M · Atom Computing/Microsoft · ordered fact
- 2025-11-06 · DARPA QBI Stage B · up to $15 M each · eleven teams, no dual-rail vendor · official G[65] fact
- 2026-01-07 · D-Wave · acquires Quantum Circuits · $550 M ($300 M stock + $250 M cash) · closed 2026-01-19/20 C[14], [648] fact
- 2026-05-21 · D-Wave; Atom Computing · US DoC CHIPS letters of intent · $100 M each · LOI fact
- 2026-06-16 · Atom Computing · Series C · $100 M · Third Point Ventures · >$300 M cumulative · closed C[154] fact
- 2026-08-06 · D-Wave · H1-2026 results · revenue $5.9 M (−67% YoY), cash $546.2 M · reported fact
Market & supply chain. Nobody sells an erasure check; it rides on the amplifiers and refrigerators of dispersive readout (concentrated, BIS-listed G[301]). Unit economics are unpublished; the structural cost is 2× transmons or two cavities plus an ancilla per qubit, against Quantum Circuits' claim of 10–20 physical per logical instead of ~200 C[86]. Only G3 and G4 pay, once codes run 10⁵–10⁶ rounds.
IP & standards. Amazon Technologies: US 11,748,652 B1, "Heralding of amplitude damping decay noise for quantum error correction" (Kubica, Retzker; filed 2021-12-10, granted 2023-09-05): heralded decay via a level outside the code space, dual-rail included G[336]. Yale: US 12,288,135, ancilla with an asymmetric error channel (filed 2019-06-28, granted 2025-04-29) G[408]. The Yale/Quantum Circuits cavity families now sit with D-Wave. No standard; Stim's HERALDED_ERASE instruction P[397] commoditises the decoding side.
Roadmaps & track record.
- D-Wave: promised 2026-01-07 · initial dual-rail system available in 2026 · not delivered as of 2026-09-03 C[14].
- D-Wave: promised 2026-06-01 · 17 qubits with logical error 2× below physical (2026), 49 / 20× (2027), 181 / 2,000× (2028), 10 logical (2030), 100 logical (2032), Λ = 10 · pending, no logical data R[94] fact.
Credibility: Quantum Circuits/D-Wave high on physics, unproven on dates; AWS publishes results and promises no product; Princeton delivered the single-qubit half of its 2022 proposal S[8] D[141]; Atom Computing on schedule, uncommitted to mid-circuit checks.
Strategic reading. If erasure checks scale, the winners own high-T1 fabrication and the readout chain — D-Wave, AWS and the alkaline-earth(-like) camp (Atom Computing, Google); the losers are bare-transmon roadmaps buying threshold with Λ alone. Substitution threats: qutrit erasure qubits D[405] remove the 2× overhead; fast Yb imaging D[261] and loss-aware decoding erode the case for metastable encodings. Bargaining power stays with platform vendors, not suppliers.
Outlook & open questions
Confirm within 12–24 months if: D-Wave ships the 17-qubit system with published logical error 2× below physical by mid-2027 R[94]; any group runs ≥10 rounds of a distance-3 code on dual-rail qubits with survival reported; atomic two-qubit conversion reaches ≥70% with a check ≤50 µs; a χ-matched check reaches ≤250 ns with residual ≤3×10⁻⁴. Demote if by end-2027 no erasure system reports Λ >2 on unconditioned data. Best case by 2029: 100–200 dual-rail qubits at Λ ≈4–10 with 2 µs cycles, and Yb machines running erasure-aware codes. Worst case: erasure stays a two-qubit showpiece while bare transmons reach 10⁻³ and Λ ≈3 without it.
Open questions: (1) does the 40× bias survive parallel checks on qubits sharing feedlines? (2) can Rydberg leakage be made bright within microseconds? (3) what does a decoder do with false negatives at 10⁻³ as leakage accumulates? Watch: D-Wave's 2026 delivery, AWS's next multi-qubit paper, Google/Kaufman Yb results.
References
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news/ Chome/ 20260119513563/ en/ D-Wave-Completes-Acquisition-of-Quantum-Circuits-Inc.-Creating-Worlds-Leading-Quantum-Computing-Company
Русский текст загружается…
הטקסט בעברית נטען…
Single-photon detection (SNSPD / TES)
Cryogenic superconducting detectors that destroy a photon to register it; the shared readout organ of every photonic and photon-linked platform.
Verdict. Efficiency is solved in the lab (99.73% on-chip) but not at wafer scale (93.4% median on Omega); channel count and cryogenics, not physics, decide whether photonic fault tolerance is buildable.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A current-biased superconducting nanowire absorbs one photon, forms a resistive hotspot and emits a voltage pulse; a transition-edge sensor (TES) instead measures the absorbed energy calorimetrically and so resolves photon number. Gol'tsman's group at Moscow State Pedagogical University demonstrated the first NbN device in 2001 D[626]; the voltage-biased TES dates to Irwin (1995) D[627]. Scontel, still in Moscow, descends directly from that first group.
Attributes. Carrier affinity: fabricated — a lithographic thin film, not a natural quantum system. Characteristic time and entanglement: not applicable; the node hosts no qubit and performs no entangling operation. Readout: single-photon detection, ~1.0×10⁻⁸ s per event including reset, destructive, not mid-circuit — the photon is consumed. Mobility: none; a fixed terminal. Control modality and placement: electro-optical bias and amplification at the 1–4 K stage. Dominant error structure as the code sees it: loss — a missed detection is an erasure at a known location, a dark count a false positive the decoder cannot distinguish from a real click. Manufacturing: photonic-integrated-circuit process, increasingly the one that carries the waveguides.
Physics & limits
A 1550 nm photon carries 0.80 eV against an NbN gap of a few meV, so absorption breaks of order 10³ Cooper pairs; the signal is enormous relative to the gap, which is why internal detection efficiency saturates near unity (99.99% at 5.5 µA bias D[628]). Efficiency is therefore an optics problem, not a superconductivity problem: it factorises into fibre coupling × absorption × internal efficiency, and the art is removing the first term (waveguide integration) or engineering the second (dielectric mirrors D[618]). The real floors are timing and rate: reset is kinetic inductance over load, about 10 ns, capping per-pixel rates in the tens of Mcps, while jitter has a Fano floor from hotspot statistics plus a geometric term along the wire — which is why 2.7 ± 0.2 ps FWHM at 400 nm degrades to 4.6 ± 0.2 ps at 1550 nm D[629]. TES trades both away: number resolution for ~µs recovery at ~100 mK, a dilution refrigerator rather than a 2–4 K cold head.
In the currency photonic fault tolerance uses, 1% inefficiency costs 0.044 dB. PsiQuantum's 93.4% median on-chip efficiency D[169] costs 0.30 dB against a fusion per-photon budget near 0.5 dB, and its 6.6% inefficiency alone is 2.4× the 2.7% loss threshold of 6-ring fusion schemes S[179]. Nothing else here matters as much as that arithmetic.
Engineering state of the art
Best demonstrated is a cascaded waveguide pair at 99.73% on-chip efficiency, 1.5 K, NbN, 100 nm wide and 5 nm thick D[628]. Typical at scale is different: 93.4% median on-chip across PsiQuantum's 300 mm Omega wafers at ~2 K D[169], and catalogue systems quoting only ">90% near 1550 nm" with sub-100 ps jitter C[630], [631]. The gap between a hero device and a wafer median is the engineering problem. The dominant term today is inefficiency convolved with waveguide and switch loss; in a networking machine it is dark counts and jitter against the coincidence window.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2001 | First NbN nanowire single-photon detector | Moscow State Pedagogical University | D[626] |
| 2008 | TES 95% efficiency at 1556 nm, photon-number resolving | NIST Boulder | D[632] |
| 2020-11 | System detection efficiency 98.0 ± 0.5% at 1550 nm, fibre-coupled | NIST | D[618] |
| 2020 | Timing jitter 2.7 ± 0.2 ps FWHM at 400 nm; 4.6 ± 0.2 ps at 1550 nm | JPL | D[629] |
| 2023-10 | 400,000-pixel camera, 4 × 2.5 mm, thermal row–column readout | NIST Boulder | D[339] |
| 2025-02 | Median on-chip efficiency 93.4% at ~2 K, 300 mm foundry line | PsiQuantum | D[169] |
| 2025-10 | On-chip efficiency 99.73% cascaded (97.33% single), 1.5 K | Nanjing University | D[628] |
Manufacturing, materials & supply chain
Four material systems compete: NbN and NbTiN (fast, 2–4 K, the commercial default), amorphous WSi (highest efficiency, ~1 K, NIST's choice for records) and MoSi. Amorphous films are more uniform across a wafer, which is what a 300 mm line needs; polycrystalline NbN is faster. PsiQuantum's integration of detectors into a GlobalFoundries 300 mm flow alongside SiN waveguides and barium-titanate switches is the only wafer-scale datapoint, and its published median — not its best die — is the honest yield statement D[169].
The supply chain is short and concentrated. Merchant vendors are Single Quantum (Delft), ID Quantique (Geneva, IonQ-owned since 2025), Photon Spot (Monrovia, CA), Quantum Opus (Michigan) and Scontel (Moscow); NIST and JPL set the records but sell nothing. Every one ships inside a closed-cycle cryostat, so the single point of failure is upstream: Gifford-McMahon and pulse-tube cold heads from a handful of makers (Sumitomo Heavy Industries, Cryomech, and integrators such as Bluefors), plus helium-4, cryogenic coax and fibre feedthroughs. Photon Spot mitigates this by selling its own Cryospot cryostats C[630].
Export-control exposure sits on the cryogenics, not the detector. The BIS interim final rule of 2024-09-06 created ECCN 3A904 for cryogenic refrigeration below 4.5 K, with 3A901.b for quantum-limited amplifiers fact[301]; single-photon detectors are not named, but the box they live in is controlled. Scontel's Moscow location makes it effectively unavailable to Western programmes post-2022 — a judgment, not a sourced fact.
Control, readout & I/O burden
Per channel: a bias current, an amplifier, a coaxial line from 1–4 K to room temperature, and a time-tagger input. Tolerable at 10¹–10² channels — the entire commercial market — and binding above it. At 10³ the coax heat load and 2–4 K cooling budget dominate; Bluefors' KIDE, with nine pulse-tube cryocoolers and "more than 4,000 RF lines" Cfact[303], is roughly the shippable ceiling. At 10⁴ wiring must give way to multiplexing: the 400,000-pixel camera's thermal row–column scheme D[339] shows this works when timing can be sacrificed, but fusion networks need MHz–GHz feed-forward from click to switch and cannot sacrifice it. At 10⁶ detector, amplifier and demultiplexer must be monolithic in the photonic process and the cryoplant becomes kilowatt-class at 2–4 K; PsiQuantum's DARPA Stage C work explicitly covers packaging and cryogenics validation Pfact[181], and the Linde cryoplant for its Moreton Bay site is not due for delivery until 2H 2027 Cfact.
Role in the stack
The node sits on the fusion-based discrete-variable architecture (PsiQuantum, Quandela, QuiX), the continuous-variable/GKP architecture (Xanadu) and the boson sampler. It requires single photons and provides heralding for linear-optical fusion plus photon detection for the ion–photon and spin–photon interconnects: one part is the readout organ for three otherwise unrelated modalities. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset — no such round on a photonic architecture; the detector contributes ~1.0×10⁻⁸ s, so it is never the slow term for ion or defect links (rates 10–250 s⁻¹ D[115], [116]) and only marginally so for fusion, where feed-forward latency dominates.
It conflicts with the surface code specifically: destructive detection precludes repeated syndrome extraction on the same photon, so photonic QEC must regenerate carriers between rounds. Switching away is asymmetric — Xanadu's CV architecture uses room-temperature homodyne for most measurements and needs number resolution only for GKP preparation D[173], [174]. Neighbouring empty slots: a room-temperature >99% number-resolving detector, and any non-destructive telecom photon counter, which would dissolve the conflict above.
Evidence — how the numbers were measured
System detection efficiency is measured against a heavily attenuated laser and a calibrated power meter whose uncertainty the Nanjing authors put at 2–5% D[628] — comparable to the gap between the 98.0 ± 0.5% D[618] and 99.73% D[628] headlines. The two are also different quantities: on-chip efficiency excludes fibre-to-chip coupling, so waveguide-integrated records must never be tabulated beside fibre-coupled ones without that caveat. Uncaptured: afterpulsing, latching, blinding attacks, and the joint distribution of efficiency and jitter across a wafer, which is what an integrator needs.
Conflict. A "98.9% median (PsiQuantum)" figure is quoted elsewhere; the Omega paper and the shared fact record both give 93.4% median on-chip D[169]fact. The primary-source figure, 93.4%, stands; the difference is 0.30 dB versus 0.05 dB per detection.
Silicon avalanche photodiodes, still used instead of superconducting nanowire or transition-edge detectors to characterise sources, emit breakdown flashes that leak between the two detectors of a Hanbury Brown–Twiss set-up (a beam splitter feeding two detectors whose coincidences measure the multiphoton fraction) and raise the zero-delay coincidence peak in the near-infrared; a second-order correlation g⁽²⁾(0) measured this way is an upper bound on the multiphoton fraction P[887].
Cold-head supplier concentration (Sumitomo Heavy Industries, Cryomech) and Scontel's unavailability to Western programmes after 2022 are analyst judgments, not sourced facts. The abstract of Korzh et al. gives the jitter figures but not that device's operating temperature or detection efficiency. Not published: the ID Quantique acquisition consideration, and SNSPD system prices or vendor revenues from Single Quantum, Photon Spot, Quantum Opus or Scontel, so unit economics cannot be checked.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | In-house SNSPDs monolithic in Omega on 300 mm GlobalFoundries, 93.4% median | D[169] |
| Single Quantum | supplier | NL | Turnkey SNSPD systems; 400th shipped to Q*Bird 2026-07 | P[621] |
| ID Quantique | supplier | CH | SNSPD and InGaAs detectors plus QKD; IonQ-acquired 2025-05-06 | P[633] |
| Photon Spot | supplier | US | SNSPDs plus its own Cryospot cryostats; >90% QE, sub-100 ps jitter | C[630] |
| Quantum Opus | supplier | US | Opus One, ≥90% at 1310/1550 nm, >2 K, number-resolving under licence | C[631] |
| Scontel | supplier | RU | Large-area, ultra-low-noise and number-resolving SSPD lines | C[634] |
| NIST Boulder | research | US | 98.0% efficiency record, WSi films, 400 kpixel camera, calibration | D[339], [618] |
| JPL | research | US | 2.7 ps jitter record; deep-space optical-comms arrays | D[629] |
| Nanjing University | research | CN | 99.73% cascaded on-chip efficiency | D[628] |
| Xanadu | user | CA | CV architecture leans on homodyne; number resolution only for GKP | D[173] |
| Bluefors | supplier | FI | Cryogenic platforms; KIDE, nine pulse-tube coolers, >4,000 RF lines | C[303] |
Money.
- 2025-05-06 · IonQ / ID Quantique · M&A · consideration not disclosed in the cited releases · — · closed P[633]
- 2025-09-10 · PsiQuantum · Series E · $1 B at $7 B · BlackRock, Temasek, Baillie Gifford · closed fact
- 2025-11-06 · DARPA QBI Stage B · programme · up to $15 M each, 11 performers incl. Xanadu, Photonic Inc. · DARPA · awarded fact[65]
- 2026-03-26 · Xanadu · SPAC close · ~$302 M gross, ~40% below plan · Crane Harbor · closed fact
- 2026-05-21 · PsiQuantum · CHIPS letter of intent · $100 M · US Dept of Commerce · LOI (non-binding) fact[300]
- 2026-06-16 · Quandela · DARPA QBIT Stage A · amount not disclosed · DARPA · announced fact
- 2026-07-04 · Single Quantum · 400th SNSPD system delivered · revenue not disclosed · Q*Bird · reported P[621]
- 2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion (switches, packaging, cryogenics V&V) · $125 M, after $31.8 M in 2025-09 · DARPA · announced Pfact[181]
- 2026-08-28 · Xanadu · Canadian factory funding · CAD 195 M · federal programme · announced C[178]
No detector vendor appears in that ledger with a disclosed round: the merchant supply base is private, opaque, and an order of magnitude smaller than the platform vendors depending on it.
Market & supply chain. No vendor publishes prices C[630], [631], [634], so unit economics are unverifiable. Paying demand today is G6 networking — QKD, where Single Quantum's 400 systems and ID Quantique's line live — plus a non-quantum anchor in G7 deployable systems (deep-space and lunar optical communications; NASA, NIST, Fermilab, Sandia and Argonne are named customers C[630], [631]). G3/G4 pays only through PsiQuantum, Xanadu, Quandela, QuiX and Photonic Inc. Concentration risk is upstream: cold heads, helium, cryogenic coax.
IP & standards. Quantum Opus holds an exclusive licence to US 11,274,962 B2 for photon-number resolution C[631]. No dated patent-count figure from a named database was found for this node as of 2026-09-03. There is no SNSPD-specific standard; calibration traceability is de facto NIST's D[339], [618].
Roadmaps & track record. PsiQuantum (promised since 2021 · useful system by end-2027 · at risk: Moreton Bay groundbreaking only 2026-06, cryoplant delivery due 2H 2027 Cfact, no 2026 hardware demonstration published) P[181]. Xanadu (promised 2026-08-31 · loss 24.1× above threshold in 2026 → 1.0× in 2030, 1,000+ logical qubits by 2031 · paper roadmap only) C[178]. Single Quantum (no public roadmap; 400 delivered systems is the only dated metric) P[621]. Credibility: the detector vendors under-promise and ship; PsiQuantum's detector physics is credible and its schedule is not; Xanadu's roadmap is three weeks old and untested.
Strategic reading. If fusion-based photonic computing scales, detectors per machine go from 10² to 10⁶ and merchant vendors must become foundry-integrated IP licensors or be displaced by in-house monolithic detectors — PsiQuantum has already chosen the second outcome for itself. Supplier bargaining power is weak against platform vendors and strong only in QKD and space communications, where volumes are real and integration is not. The substitution threat is homodyne detection on the CV architecture: cheap and room-temperature. The quiet winner in every scenario is the cryocooler industry.
Outlook & open questions
Confirm in 12–24 months if a published wafer map shows >99% median on-chip efficiency across a 300 mm line; if a >10³-channel cryogenic readout is demonstrated with per-channel jitter and feed-forward latency; if PsiQuantum's Moreton Bay cryoplant is delivered in 2H 2027 as promised Cfact. Demote if PsiQuantum publishes no detector data through 2027, or wafer medians stay below 95% while switch and coupling losses fall. Best case by 2029: waveguide-integrated detectors above 99% median with thousands of channels multiplexed on chip. Worst case: records keep being set on two-detector laboratory devices while wafer medians stall near 93–95% and the 2.7% loss threshold stays unreachable.
Open questions. (1) What is the efficiency–jitter joint distribution across a 300 mm wafer, and what is the yield criterion? (2) Can number resolution be had at 2 K, or does GKP permanently require a TES near 100 mK? (3) What cooling power per channel at 2 K does a 10⁵-channel machine need, and who builds that plant? (4) Does any non-destructive scheme reach telecom wavelengths with usable efficiency? (5) Do merchant vendors have a foundry-compatible path? Watch PsiQuantum's next hardware paper and Stage C milestones, and any disclosed round at Single Quantum, Photon Spot or Quantum Opus — the first signal that demand has moved beyond QKD.
References
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- [116] J. O'Reilly et al., “Fast photon-mediated entanglement of continuously-cooled trapped ions for quantum networking,” Phys. Rev. Lett., vol. 133, Art. no. 090802, Aug. 2024, doi: 10.1103/PhysRevLett.133.090802. arXiv:2404.16167. D
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [174] M. V. Larsen et al., “Integrated photonic source of Gottesman–Kitaev–Preskill qubits,” Nature, vol. 642, no. 8068, pp. 587–591, Jun. 2025, doi: 10.1038/s41586-025-09044-5. D
- [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. S
- [181] M. Abdel-Kareem, “PsiQuantum Secures $125 Million Expanded Agreement with DARPA under QBI Program,” Quantum Computing Report, Jul. 22, 2026. [Online]. Available: https://quantumcomputingreport.com/
psiquantum-secures-125-million-expanded-agreement-with-darpa-under-qbi-program/ P - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [303] Bluefors, “KIDE Cryogenic Platform — For Large-Scale Quantum Computing,” Jun. 16, 2026. [Online]. Available: https://bluefors.com/
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- [628] Z.-G. Li et al., “Surpassing 99% detection efficiency by cascading two superconducting nanowires on one waveguide with self-calibration,” Light: Science & Applications, vol. 14, no. 1, Art. no. 369, Oct. 2025, doi: 10.1038/s41377-025-02031-5. D
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- [633] IonQ, “IonQ Completes Acquisition of ID Quantique, Cementing Leadership in Quantum Networking and Secure Communications,” May 6, 2025. [Online]. Available: https://investors.ionq.com/
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Русский текст загружается…
הטקסט בעברית נטען…
Dispersive microwave readout (+TWPA, Purcell)
The qubit state is read as a dispersive shift of a coupled resonator, Purcell-filtered on chip and amplified near the quantum limit before the HEMT.
Verdict. Falsifiable — assignment fidelity is already 99.94%, so if fleet readout error stays near 1% through 2027 the binding term is measurement-induced leakage and QND violation, not amplifier noise.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A resonator coupled off-resonantly (coupling g, detuning Δ ≫ g) acquires a state-dependent shift χ ≈ g²/Δ, so a probe tone carries the state in its phase without exchanging quanta with the qubit — non-demolition by construction. Wallraff and colleagues at Yale established it as circuit QED's readout channel D[591]. Two additions make it usable: an on-chip Purcell filter, which passes the probe while blocking qubit emission into the same line, and a near-quantum-limited parametric amplifier before the HEMT (high-electron-mobility transistor).
Attributes: carrier affinity a = 1.0, fully fabricated. Readout ≈280 ns (10^−6.55 s), non-destructive, mid-circuit capable.
Physics & limits
Separation needs a fixed number of signal photons at the amplifier input, so readout time falls with probe power and rises with chain noise. A Josephson travelling-wave amplifier giving 12 dB across 4 GHz near the quantum limit D[592] removes the HEMT's noise penalty, so the amplifier is not the floor. The floor is what hard probing does to the qubit: above a critical photon number the dressed system undergoes measurement-induced transitions out of the computational subspace, and the code inherits leakage — unheralded, sticky, correlated in time, not a Pauli flip. The IQM device shows the split: 99.94% simultaneous assignment fidelity with a 240 ns pulse and shelving into the second excited state, but 99.3% QNDness D[38]. Assignment error is 6×10⁻⁴; the chance the qubit does not survive as measured is an order of magnitude larger — and that is what syndrome extraction consumes. The Purcell filter's linewidth buys speed but, widened, reopens the emission channel it exists to close. What moves the floor: shelving-free discrimination, on-chip isolation, and encodings that turn a failed measurement into a heralded erasure.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-12 | Willow, 105 q: readout 99.5%, 1.1 µs error-correction cycle | D[1] | |
| 2025-08 | 99.94% simultaneous readout, 240 ns pulse, QNDness 99.3% | IQM | D[38] |
| 2026-08 | Dual-rail cavity readout: SPAM ≈0.02%, erasure ≈0.5% per gate | Quantum Circuits | D[84] |
| 2026-07 | Fleet readout error ~1×10⁻² | IBM | C[33] |
The spread is the story: 6×10⁻⁴ on a characterised pair, 5×10⁻³ over 105 qubits, ~10⁻² across a fleet D[38]D[1]C[33]; Zuchongzhi 3.0 reads out at 99.13% D[35]. Readout is the largest single-channel error term at scale, larger than two-qubit gates, and the one whose fleet value has barely moved in two years.
Manufacturing, materials & supply chain
On chip there is no extra process: resonator and Purcell filter are patterned in the qubit's own lithography, the cost being area and frequency planning: each qubit on a feedline needs a distinct resonator frequency in the amplifier's band. Off chip the chain — isolators, circulators, parametric amplifier, HEMT — is the fridge's bulkiest hardware and where a merchant market has appeared: Silent Waves (Grenoble) sells Argo, Carthago and Zephyr, the last launched 2026-03-13, to Rigetti, Alice & Bob, Qilimanjaro, QphoX and CEA C[593]; QuantWare sells a Crescendo TWPA C[594]; QuantumCore is developing one with the Institute for Quantum Computing P[595]. Export exposure is direct: ECCN 3A901, effective 2024-09-06, covers sub-4.5 K electronics and names parametric amplifiers, so a TWPA is controlled in its own right G[301].
Control, readout & I/O burden
Each qubit consumes a resonator, a share of a feedline (eight to ten qubits multiplexed per line), a share of one amplifier's dynamic range, and a digitiser channel with real-time discrimination. The amplifier is the scaling constraint nobody has published a number for: TWPA saturation caps simultaneous tones per device, and each feedline needs its own isolator stack — volume, not silicon. Instrumentation has followed (over 1,000 channels per rack C[526]), but the budget is set downstream: Google's real-time decoder ran at 63 µs latency for d=5 against a 1.1 µs cycle D[1], so readout plus decode defines the loop. At 10⁶ the chain must move into the cold, and no cryogenic digitiser has been shown beyond a handful of qubits.
Role in the stack
It serves every superconducting-family architecture: transmons, bosonic cat and GKP encodings, dual-rail erasure qubits, and the same chain in annealers. It requires the transmon's dispersive shift and, for bosonic codes, an ancilla mediating the cavity measurement, and provides the mid-circuit non-destructive measurement every error-correction scheme here assumes — no substitute exists inside the family. Its clock contribution is direct: derived clock = sum of the syndrome round: gate layers + transport + readout + reset is 0.65 µs, of which readout is 0.28 µs — the largest term, against ~0.048 µs per gate layer D[1]D[38] — inside a measured 1.1 µs cycle. No neighbouring empty slot in the technology graph.
Evidence — how the numbers were measured
Three quantities circulate as "readout fidelity" and are not interchangeable: assignment fidelity, QNDness (the qubit is left in the state reported), and SPAM. The 99.94% headline is simultaneous assignment fidelity with shelving; QNDness on the same device is 99.3% D[38]. IBM's fleet ~10⁻² is undecomposed into amplifier noise, Purcell-limited decay and measurement-induced transitions C[33]. Value conflict: the graph record quotes 280 ns readout, the preprint a 240 ns pulse, so ~280 ns should be read as the full window. No independent laboratory has replicated the 99.94% result.
Not published: a named TWPA or Purcell-filter patent family with assignee and grant year; TWPA yield, unit cost, or the number of multiplexed tones one amplifier sustains before compression, from any supplier; and a fleet-average QNDness from any vendor.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IQM | developer | Finland | Readout record: 99.94% with shelving, QNDness 99.3% | D[38] |
| Google | developer | US | 99.5% readout across 105 qubits in a 1.1 µs cycle | D[1] |
| IBM | developer | US | Publishes the only at-scale fleet readout error, ~10⁻² | C[33] |
| Silent Waves | supplier | France | Merchant TWPA maker, three shipping products | C[593] |
| QuantumCore | supplier | Canada | TWPA development with IQC Waterloo | P[595] |
Money.
- 2026-05-05 · QuantWare · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners · closed C[547]fact
- 2026-04-25 · QuantumCore · listing (CSE: QNCR, 2026-04-14) plus NSERC Alliance grant · $10.7 M raised, $1.7 M grant · NSERC/IQC · closed P[595]
- 2026-01 · D-Wave · M&A (Quantum Circuits) · $550 M · — · announced C[84]
Market & supply chain. The chain, not the chip, is what this node buys: isolators and circulators, HEMTs, the parametric amplifier. The TWPA market is thin — three small merchant suppliers against in-house builds at Google and IBM — so one exit matters more here than anywhere else, and the parts are export-controlled G[301]. G2 and G3 pay for this node; G7 buys the instrumentation.
IP & standards. No TWPA or Purcell-filter patent family with a named assignee and grant year was found; Silent Waves' 2025 Nature Electronics amplifier-isolator is a published design, not a grant C[593]. No litigation identified, and no standards body defines how readout fidelity is reported — hence three numbers quoted interchangeably.
Roadmaps & track record. Silent Waves: three products with named customers (Zephyr promised and launched 2026-03-13) C[593], the most credible record here. QuantumCore: announced 2026-04-25, too recent to judge P[595]. No platform vendor publishes a fleet-average readout target as distinct from best-device fidelity — a notable omission when readout is the largest fleet error term.
Strategic reading. This is a shared chokepoint: four architectures depend on the same amplification and isolation hardware, so concentration risk is systemic in a way qubit-chip choices are not. If fleet readout stays near 10⁻², Λ stalls whatever gates do, since syndrome extraction inherits the measurement error — the case for erasure-style encodings that make a failed measurement heralded. Winners: merchant amplifier suppliers and whichever vendor solves QND rather than assignment. Bargaining power sits with the platform vendors, though export licensing gives regulators a lever.
Outlook & open questions
Confirm or demote within 12–24 months: does any vendor publish a fleet-average QNDness; does fleet readout error fall below 5×10⁻³. Best case by 2029: shelving-free discrimination and on-chip isolation take fleet readout error toward 10⁻³ without slowing the cycle. Worst case: measurement-induced leakage holds QNDness near 99.3% whatever the amplifier does, and readout stays the term that caps Λ. Open questions: how the fleet 1% decomposes; how many tones one TWPA carries before compression.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [33] IBM, “IBM Quantum Computing — Hardware and roadmap.” [Online]. Available: https://www.ibm.com/
quantum/ Chardware - [35] D. Gao et al., “Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor,” Phys. Rev. Lett., vol. 134, Art. no. 090601, Mar. 2025, doi: 10.1103/PhysRevLett.134.090601. arXiv:2412.11924. D
- [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
- [84] N. Mehta et al., “An entangling gate for dual-rail erasure qubits,” Nature, vol. 656, no. 8126, pp. 47–53, Aug. 2026, doi: 10.1038/s41586-026-10822-y. arXiv:2503.10935. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [526] Zurich Instruments, “Zurich Instruments Launches the ZQCS Quantum Control System to Master the Long-Lived Logical Qubit Challenge,” Mar. 9, 2026. [Online]. Available: https://www.zhinst.com/
americas/ Cen/ news/ zurich-instruments-launches-zqcs-quantum-control-system-master-long-lived-logical-qubit/ - [547] QuantWare, “QuantWare Raises $178 Million to Build World’s Most Powerful Quantum Processors at an Industrial Scale,” May 5, 2026. [Online]. Available: https://quantware.com/
news/ Cquantware-raises-178-million - [591] A. Wallraff et al., “Strong coupling of a single photon to a superconducting qubit using circuit quantum electrodynamics,” Nature, vol. 431, no. 7005, pp. 162–167, Sep. 2004, doi: 10.1038/nature02851. arXiv:cond-mat/0407325. D
- [592] T. C. White et al., “Traveling wave parametric amplifier with Josephson junctions using minimal resonator phase matching,” arXiv:1503.04364, Mar. 2015. D
- [593] Silent Waves, “Silent Waves - Traveling-Wave Parametric Amplifiers (TWPAs),” Mar. 13, 2026. [Online]. Available: https://www.silent-waves.com/ C
- [594] QuantWare, “Peripherals — Crescendo TWPA,” 2026. [Online]. Available: https://quantware.com/
product/ Cperipherals - [595] D. Finke, “QuantumCore Secures $1.7M NSERC Grant to Advance Superconducting Amplifiers,” Quantum Computing Report, Apr. 25, 2026. [Online]. Available: https://quantumcomputingreport.com/
quantumcore-partners-with-iqc-and-nserc-in-1-7m-traveling-wave-parametric-amplifier-twpa-development-initiative/ P
Русский текст загружается…
הטקסט בעברית נטען…
Fluorescence state detection (ions, defects)
State-dependent resonance fluorescence, counted on a PMT, EMCCD, SNSPD or trap-integrated photodiode, is the default non-destructive mid-circuit readout for trapped ions.
Verdict. Readout is no longer the weakest link on the best ion system; falsifiable if any published SPAM figure on a production ion system exceeds that system's two-qubit gate error.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A closed cycling transition scatters photons only when the qubit sits in one logical state; counting them collapses the measurement onto a classical bit. Detectors are photomultipliers, EMCCD (electron-multiplying CCD) cameras, superconducting nanowire single-photon detectors (SNSPDs) or, recently, avalanche photodiodes built into the trap. In use since the earliest trapped-ion demonstrations (1995), unchanged in principle. Attributes: c = fluorescence readout, non-destructive, mid-circuit capable, ~10⁻⁴ s — 11 µs at 99.931(6)% on ¹⁷¹Yb⁺ with SNSPDs D[617]; e = optical control, detection hardware at room temperature unlike the ion.
Physics & limits
The mechanism is photon counting against a dark-count and stray-light background, so the signal is set entirely by how many scattered photons reach a detector: collection numerical aperture (a few percent of 4π), UV transmission, detector quantum efficiency. That last term is where the platform hurts — the cycling transitions are ultraviolet (369.5 nm for Yb⁺), where PMT efficiency is tens of percent and where the 98% system detection efficiencies quoted for SNSPDs do not apply, those being telecom-band figures D[618]. The 2019 record worked because a molybdenum-silicide SNSPD was built specifically for 369.5 nm, letting the experiment stop on a single detection event D[617]. The floor is geometry and efficiency, not atomic physics. Errors are Pauli-like misclassification, except when the dark state leaks out of the cycling transition — a loss channel standard SPAM folds into one number. What moves the floor: higher-NA collection, UV-optimised detectors, and moving the detector onto the trap die.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2019-08-21 | 11 µs mean detection at 99.931(6)%, crosstalk ~2×10⁻⁵ at 370 µm, MoSi SNSPD on ¹⁷¹Yb⁺ | Duke University | D[617] |
| 2022-09-02 | 99.92(1)% in 450 µs with room-temperature trap-integrated avalanche photodiodes, Sr⁺ | MIT Lincoln Laboratory | D[619] |
| 2025-11 | Helios (98 Ba⁺): SPAM 3.3–4.8×10⁻⁴, leakage 1.1×10⁻⁵/Clifford | Quantinuum | D[97] |
| 2026 | Forte (36-ion chain): SPAM 0.5% | IonQ | C[99] |
The reversal matters: on Helios, SPAM sits below the two-qubit gate error (7.9×10⁻⁴) D[97], and logical SPAM in the [[80,48,4]] code is below 8×10⁻⁶ D[105]. Readout dominated ion error budgets a decade ago; not now.
Manufacturing, materials & supply chain
Optical assembly, not a fab layer — high-NA objectives, UV viewports, a detector — aligned per system, so detector variation is a calibration cost, not a yield loss. PMTs and EMCCD/qCMOS cameras come from Hamamatsu and Andor (Oxford Instruments), Hamamatsu the only named vendor for single-photon-sensitivity cameras in this class C[620]. SNSPDs come from a five-vendor merchant base — Single Quantum, ID Quantique, Photon Spot, Quantum Opus, Scontel — none of which has disclosed funding or revenue P[621], each carrying a closed-cycle cryostat that PMT and camera channels do not. Upstream, the single points of failure are shared with the rest of the ion stack: UV lasers (TOPTICA) and Infineon's merchant trap fab P[322]. No ion-readout ECCN exists; the 2024 BIS rule reaches computers and refrigerators, not detectors.
Control, readout & I/O burden
One collection channel per readout zone, not per qubit — Quantinuum's QCCD shuttles ions into dedicated zones, so channel count scales with zones D[97]. That is why this layer has not yet hit a wall: at 10³ qubits, zone readout is demonstrated at 98 ions across 8 zones. At 10⁴ a free-space objective per zone stops being buildable and the answer must be integration — trap-integrated photodiodes D[619] or multiplexed SNSPD arrays, for which a 400,000-pixel row-column camera is the existence proof, at a cost in timing resolution D[339]. At 10⁶ nothing is published. Mid-circuit readout must also keep up with real-time decoding; at 11–100 µs it does.
Role in the stack
Serves all three trapped-ion architectures — QCCD, the linear Paul trap with individual laser addressing, and electronic qubit control — and is reused by defect-spin network nodes for optical spin readout. It requires a cycling transition; no competing readout mechanism exists for ions at product scale, dispersive readout being superconducting-specific. The only real choice is detector type, whose switching price is a redesign of the collection optics, not of the processor. In the derived clock — sum of the syndrome round: gate layers + transport + readout + reset — readout has large slack: 100 µs of a 9.7 ms round against 9.0 ms of transport, and a full-width layer is ~55 ms because sorting, transport and cooling dominate D[97], so faster readout buys nothing today. Multiplexed many-zone readout without a linear cost in channels and cryostats remains an empty slot.
Evidence — how the numbers were measured
SPAM is measured by preparing known bright and dark states and counting misclassification; Helios's 3.3–4.8×10⁻⁴ is a per-zone range, not one number D[97]. Standard SPAM conflates preparation with measurement and rarely separates leakage or loss from misclassification — quoting discrimination and survival separately, as a 2026 neutral-ytterbium imaging study does (99.89% and 98.80%, not an ion result), is uncommon here P[261]. The headline numbers are also not commensurable: three species, three detectors, three machines. IonQ's Forte SPAM of 0.5% C[99] is an order of magnitude worse than Helios's — plausibly a real architecture difference, long chains on a camera versus zoned detection, but it is a specification page against a preprint.
Not published: the ID Quantique purchase price, so the detector-supply position carries no valuation; a per-channel detector cost from any vendor, and ion-readout revenue separable in Hamamatsu's or Oxford Instruments' reporting; and a UV (369–400 nm) SNSPD system detection efficiency to set against the 98% telecom-band figure.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | USA/UK | Zoned fluorescence readout on Helios, SPAM 3.3–4.8×10⁻⁴ | D[97] |
| IonQ | developer | USA | Camera readout on Forte chains; owns SNSPD maker ID Quantique | C[99] |
| ID Quantique | supplier | Switzerland | SNSPD detection systems; IonQ-owned since 2025-05-06 | P[622] |
| Hamamatsu Photonics | supplier | Japan | PMTs and the only named single-photon-sensitivity cameras here | C[620] |
| Single Quantum | supplier | Netherlands | Merchant SNSPDs, the main non-IonQ alternative | P[621] |
| MIT Lincoln Laboratory | research | USA | Trap-integrated avalanche photodiodes, 99.92% | D[619] |
Money.
2025-03-03 · IonQ · M&A, ID Quantique (SNSPD detectors) · undisclosed · closed 2025-05-06 P[622]
2025-09-04 · Quantinuum · private round · USD 600 M at USD 10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed G[122]
2026-06-03 · Quantinuum · IPO, Nasdaq QNT · USD 1.68 B gross · cash USD 2.1 B · closed G[123]
2026-07 · IonQ · M&A, SkyWater Technology foundry · USD 1.8 B · closed G[19]
Market & supply chain. Small money attached to large money. IonQ's purchase of ID Quantique gave one of the two QBI Stage-B ion vendors in-house SNSPD supply that Quantinuum, eleQtron and Quantum Art must buy on the merchant market P[622]P[621] — the sharpest concentration event here, though its weight is limited while PMTs and cameras remain adequate. No per-channel price is public. Pays for G2 and G3: every ion error-correction result, Helios's 48 logical qubits included, rests on it. It also gates G6, since photonic interconnects need the same detectors at far higher rates.
IP & standards. No dated patent-family count specific to ion fluorescence readout was found in a named database — no dated fact found. Photon-number-resolving SNSPD operation is covered by US 11,274,962 B2, licensed exclusively to Quantum Opus C[621]. No consortium standard governs ion readout.
Roadmaps & track record. No vendor publishes a standalone readout roadmap; it rides inside system roadmaps — Quantinuum Sol 2027 and Apollo 2029 R[97], IonQ 256 qubits at 99.99% slipped from 2026 to H1 2027 R[132]. Quantinuum delivered Helios on schedule with the SPAM figure it promised; IonQ has published nothing peer-reviewed behind its 0.5% specification, and its detector acquisition has produced no published readout result.
Strategic reading. If UV SNSPDs or trap-integrated photodiodes become standard at 10⁴ zones, IonQ's detector ownership plus its SkyWater fab is a real integration advantage and Hamamatsu loses a niche. If PMTs and cameras stay adequate — which Helios suggests — detector choice stays a commodity decision.
Outlook & open questions
Confirm by end-2027 if IonQ publishes a peer-reviewed SPAM figure; demote the 0.5% claim if it stays a specification page. Best case by 2029: trap-integrated detectors or multiplexed SNSPD arrays make per-zone readout free at 10⁴ zones. Worst case: readout stays one free-space objective per zone and becomes the mechanical limit on zone count. Open questions: does IonQ's owned detector supply produce a measurable SPAM advantage; can UV SNSPD efficiency approach telecom-band figures; do trap-integrated photodiodes reach the tens of µs free-space detection already achieves.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Gionq-completes-acquisition-of-skywater-technology - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [99] IonQ, “IonQ Forte: High-Performance Commercial Quantum Computer.” [Online]. Available: https://www.ionq.com/
quantum-systems/ Cforte - [105] S. Dasu et al., “Computing with many encoded logical qubits beyond break-even,” arXiv:2602.22211, Feb. 2026. D
- [122] Honeywell, “Honeywell Announces $600 Million Capital Raise for Quantinuum at $10B Pre-Money Equity Valuation to Advance Quantum Computing at Scale,” Sep. 4, 2025. [Online]. Available: https://www.honeywell.com/
us/ Gen/ news/ press-releases/ 2025/ 09/ honeywell-announces-600-million-capital-raise-for-quantinuum-at-10b-pre-money-equity-valuation-to-advance-quantum-computing-at-scale - [123] Quantinuum, “Quantinuum Announces Pricing of Upsized Initial Public Offering,” Jun. 3, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Gquantinuum-announces-pricing-of-upsized-initial-public-offering - [132] IonQ, “IonQ's Accelerated Roadmap: Turning Quantum Ambition into Reality,” Jun. 13, 2025. [Online]. Available: https://www.ionq.com/
blog/ Rionqs-accelerated-roadmap-turning-quantum-ambition-into-reality - [261] R. Yokoyama et al., “Minimally Destructive Fast Imaging of Single Atoms in an Optical Tweezer Array with Coherent Excitation,” arXiv:2605.24175, Jun. 2026. Also https://arxiv.org/
abs/ . P2605.24175 - [322] M. Ivezic, “The Optical Table's Hidden Supply Chain: Who Really Wins If Trapped-Ion Quantum Computing Wins,” PostQuantum.com, Oct. 1, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Ptrapped-ion-quantum-ecosystem/ - [339] B. G. Oripov et al., “A superconducting nanowire single-photon camera with 400,000 pixels,” Nature, vol. 622, no. 7984, pp. 730–734, Oct. 2023, doi: 10.1038/s41586-023-06550-2. D
- [617] S. Crain et al., “High-speed low-crosstalk detection of a ¹⁷¹Yb⁺ qubit using superconducting nanowire single photon detectors,” Commun. Phys., vol. 2, no. 1, Art. no. 97, Aug. 2019, doi: 10.1038/s42005-019-0195-8. D
- [618] D. V. Reddy, R. R. Nerem, S. W. Nam, R. P. Mirin, and V. B. Verma, “Superconducting nanowire single-photon detectors with 98% system detection efficiency at 1550 nm,” Optica, vol. 7, no. 12, p. 1649, Dec. 2020, doi: 10.1364/OPTICA.400751. D
- [619] D. Reens et al., “High-Fidelity Ion State Detection Using Trap-Integrated Avalanche Photodiodes,” Phys. Rev. Lett., vol. 129, no. 10, Art. no. 100502, Sep. 2022, doi: 10.1103/PhysRevLett.129.100502. D
- [620] Hamamatsu Photonics, “APS DAMOP 2026,” Aug. 25, 2026. [Online]. Available: https://www.hamamatsu.com/
us/ Cen/ news/ events/ 2026/ APS-DAMOP-2026.html - [621] TipRanks, “Single Quantum Hits 400-System Milestone as It Deepens European Quantum Partnerships,” Jul. 4, 2026. [Online]. Available: https://www.tipranks.com/
news/ Pprivate-companies/ single-quantum-hits-400-system-milestone-as-it-deepens-european-quantum-partnerships - [622] startupticker.ch, “US-based company acquires ID Quantique,” Mar. 3, 2025. [Online]. Available: https://www.startupticker.ch/
en/ Pnews/ US-based-company-acquires-id-quantique
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הטקסט בעברית נטען…
Fluorescence imaging of atom arrays
Camera-based fluorescence detection of neutral atoms — non-destructive, mid-circuit, millisecond by default, microsecond in single-group demos.
Verdict. Sets the neutral-atom QEC round at ~1 ms; unless sub-100 µs low-loss imaging reaches shipped hardware by 2028 it stays the largest fixed cost in the cycle.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An atom on a closed cycling transition scatters photons into a high-NA objective and onto a camera; a photon-count threshold per site decides occupancy or state. Standard on tweezer arrays since about 2016, and the readout every neutral-atom architecture builds on.
Camera fluorescence imaging, ~0.5–1 ms, non-destructive, mid-circuit capable.
Optical control at room temperature; free-space bench optics; error structure is loss.
Resonant fluorescence imaging resolving each site's state in tens of microseconds instead of the 0.5–1 ms exposure atom arrays have always needed D[4]. Two August-2026 preprints a week apart define the state of the art: Kyoto's coherent excitation on ¹⁷⁴Yb, 17.6 µs at 99.89(5)% discrimination and 98.80(44)% survival D[261], and USTC's site-resolved adaptive protection with continuous photon counting, 15 µs average probe D[623].
Physics & limits
Signal is collection solid angle times quantum efficiency times scattering rate times integration time, and threshold error falls exponentially in collected photons: discrimination is cheap. The cost is recoil: every scattered photon heats the atom, and past a few thousand it leaves the trap, so the failure mode is loss — 0.46% bit-flip against 0.24% loss at 448 atoms D[4]. Shorter probes improve survival: both 2026 microsecond results report loss an order below the millisecond baseline. NA and quantum efficiency sit near their practical ceiling, leaving recooling during the probe, brighter transitions and parallel zones. Architecturally the round matters: CZ gates take 270 ns while a QEC round takes 1–4.5 ms, imaging 0.5–1 ms of it and transport the rest D[4].
The floor is a photon budget. Discrimination needs enough detected photons to separate bright from dark above camera read noise, and detected photons are the scattered count times collection efficiency — an NA-0.6 objective collects about a tenth of 4π D[261]. Every scattered photon carries two recoils, so the heating that ejects the atom scales with the same count that buys the discrimination: survival and fidelity trade through one variable. Both 2026 results therefore attack the count, not the exposure — Kyoto by exciting coherently, halving the heating rate of incoherent schemes D[261], USTC by stopping the scattering at each site the moment continuous photon counting has decided its state, reaching 4.1×10⁻⁵ discrimination infidelity at 2.1×10⁻⁴ loss D[623]. What moves the floor is collection: higher NA, cavity collection, photon-counting arrays in place of EMCCD (electron-multiplying CCD) cameras, cooling during the probe.
Engineering state of the art
table
Dominant error: imaging-induced loss, not misassignment.
The dominant term is no longer the exposure: at 17.6 µs the optical step is a twenty-sixth of the classical chain C[826] and an order of magnitude below transport D[4]. What enters the code is loss during the probe, not discrimination.
Manufacturing, materials & supply chain
No fab: an objective, dichroics and a camera on a bench. Hamamatsu's ORCA-Quest qCMOS is the named sensor across the Harvard/QuEra line, with no second source at this sensitivity P[329]; objectives are commodity microscope optics. Imaging sits inside the QEC cycle, so its cost is per round, not per shot. At 10³ atoms one frame covers the array; at 10⁴–10⁶ pixel count, frame rate and illumination power force parallel zones with a camera each — the regime where beam steering also stops scaling in one device: a deflector resolves as many spots as its rf bandwidth times the acoustic transit across the beam, a transit that also bounds how fast it re-points a trap, and liquid-crystal modulators reframe only at tens of hertz. Export exposure is indirect: 4A906 binds the machine only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact; nothing names tweezer optics or cameras G[301].
No chip: sensors, objectives and lasers. Three camera vendors appear across every sourced result — Hamamatsu qCMOS in the Harvard/QuEra line Cfact, Andor (Oxford Instruments) EMCCD at Kyoto D[261], Teledyne Kinetix in Quantum Machines' stack C[826] — and no atom-array company makes one, so the sensor is the clearest single point of failure. Export exposure is asymmetric: the machine is caught by ECCN 4A906 (BIS, 2024-09-06) G[301], the cameras are dual-use instruments outside the 2024 quantum ECCNs.
Control, readout & I/O burden
Fast imaging removes one term, not the cycle. An atom QEC round is imaging (0.5–1 ms) plus transport (hundreds of µs) plus gates, 1–4.5 ms in total D[4]; taking imaging to 17.6 µs leaves transport and the classical chain, so the round improves by about a factor of two, not the 30–50× the imaging figures alone suggest. The classical chain is the larger term: 442 µs camera-to-server transfer plus 21–85 µs processing, 460 µs on a 10×10 array C[826] — twenty-six times the exposure. At 10³ sites the camera link binds; at 10⁴–10⁶ only per-site counting with an on-sensor decision scales.
Role in the stack
It is the readout of all three neutral-atom architectures: the alkali (Rb/Cs) and alkaline-earth(-like) (Yb/Sr) Rydberg tweezer arrays and the neutral-atom analogue simulator. Requires an alkali or alkaline-earth(-like) atom with a cycling transition; provides the non-destructive mid-circuit measurement real-time decoding needs, and turns atom loss into detectable erasure, not silent Pauli error. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 1.3×10⁻³ s, transport first and this readout second at 501 µs, not the 270 ns gate — ~10³× a superconducting round. Verification: both microsecond results are single-group and single-species; Kyoto's uses spinless ¹⁷⁴Yb, so it establishes occupancy discrimination, not hyperfine state readout, and USTC's 15 µs averages over a 25-site subarray. Neither has run inside a logical memory.
Fast imaging is, so far, an alkaline-earth(-like) result: Kyoto's 17.6 µs is on ¹⁷⁴Yb D[261] and USTC does not state its species D[623], so the microsecond end of this readout is tied to the Yb/Sr architecture until an alkali array shows it. At ~18 µs it would cut ~0.5 ms from the 1.3 ms round and leave transport (~800 µs) the largest term.
Evidence — how the numbers were measured
Both are single-lab preprints a week apart, neither replicated. Kyoto's 17.6 µs is imaging alone, with no array size in the abstract D[261]. USTC's 15 µs is an average probe time, and the 1.7 kHz, 120-round run applied adaptive protection to a 25-site subarray of a 100-qubit array D[623] — untested where it matters. The precedent is Atom Computing's toric code: suppression survived 90 rounds but vanished once reloading was included, 0.63% against 0.64% per cycle D[148]. Continuous operation is proven separately — >3,000 qubits over two hours D[144] — never with microsecond readout.
The Kyoto/Yaqumo 17.6 µs result is on spinless ¹⁷⁴Yb, which has no hyperfine qubit: it is occupancy discrimination, not state readout. QuNorth's €80 M Magne order is sourced from trade press, with no vendor release. That scientific cameras fall outside the 2024 quantum ECCNs is read from those ECCNs' own scope [301], not from a camera-specific ruling. Quantum Machines' 460 µs chain figure is self-reported and not independently audited [826]. Not published: the camera used in the Kyoto demonstration, and a unit cost per readout channel for camera plus objective. Not stated in the abstract of arXiv:2608.17189: USTC's atom species and transition, detector type and collection NA.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Harvard/MIT | research | US | 448-atom fault-tolerant baseline | D[4] |
| QuEra Computing | developer | US | Ships this readout in its roadmap | C[153] |
| Atom Computing | developer | US | Yb arrays; Magne with Microsoft | C[154] |
| Kyoto Univ./Yaqumo | research | Japan | 17.6 µs Yb imaging demo | P[261] |
| Hamamatsu Photonics | supplier | Japan | qCMOS sensor, no second source | P[329] |
| USTC | research | China | 15 µs adaptive probe with sub-µs feed-forward decoding | D[623] |
| Quantum Machines | supplier | Israel | Sells the classical readout chain | C[826] |
Money. 2025-09-09 · QuEra · Series B · $230 M+ USD · Google, SoftBank VF2, NVentures C[153]. 2025-11-06 · DARPA · QBI Stage B · ≤$15 M each · Atom and QuEra among eleven G[65]. 2026-02 · Infleqtion · NYSE listing · >$550 M USD, plus $100 M DoC LOI C[155]. 2026-06 · Atom Computing · raise · $300 M+ USD incl. $100 M Commerce LOI C[154]. 2026 · QuNorth · Magne order, 50 logical · €80 M · Atom/Microsoft P[12]. 2025-02-25 · Quantum Machines · Series C · $170 M · closed C[528]fact. Nothing is funded as fast readout: it is instrument spend inside platform budgets, and both defining results came from universities, not the companies that need them.
Market & supply chain. One vendor's sensor sits in the critical path of every leading array, the rest being commodity optics — sharp concentration risk. It pays into G3 and G4: no mid-circuit imaging, no real-time decoding. The enabling suppliers are camera vendors (Hamamatsu, Andor, Teledyne) and control vendors (Quantum Machines); no fast-atom-readout product exists. Sensor concentration is severe: three vendors, none replaceable in-house. Capturable value sits in the classical chain, which is why the control vendor publishes the benchmarks C[826]. Pays into G3 and G4, and into G1 where shot rate is throughput.
IP & standards. No dated patent family or standard specific to atom-array imaging. No dated patent family for fast atom-array readout surfaced as of 4 Sep 2026; both results are preprints and the only company on either author list is Yaqumo Inc. D[261]. No standards body governs sensor choice. The absence of IP is itself a finding: the technique is published, not fenced.
Roadmaps & track record. (2026-08 · fast imaging shown standalone · not folded into a logical run); (2028–29 · QuEra Libra and Magne targets · assume the cycle keeps shrinking) R[153]. Vendor roadmaps price in a speed-up shown only on subarrays. Atom Computing with Microsoft (2025-07 · Magne, 50 logical, €80 M, turn of 2026/27 · being installed) R[11]. QuEra (2026-06 · Libra 2028, >256 logical · its 2024 roadmap promised 100 logical in 2026 — a two-year slip) R[162]. Nobody has dated a commitment to ship sub-20 µs readout; the sector's record is a ~2-year slip.
Strategic reading. Whoever ships sub-100 µs low-loss imaging first collapses the largest fixed cost in the neutral-atom cycle taking a factor of several in effective clock, the platform's one structural weakness. Camera suppliers hold more leverage than their revenue implies; atom vendors none over them. The winner is whichever atom company gets the camera out of the loop, not whichever gets the exposure shortest: the bottleneck measured is a 442 µs frame transfer, not a 17.6 µs probe C[826]. Camera vendors hold supplier power today and lose it the moment integrated detection arrives. The platform reading is soberer — closing the imaging term moves the atom cycle disadvantage from ~10³× to perhaps ~10²×, which does not settle the architecture argument D[4].
Outlook & open questions
Confirm if a microsecond result is folded into a logical memory run by 2028; demote if it stays readout-only. Best case 2029: sub-50 µs imaging is standard and QEC rounds fall below 0.5 ms. Worst case: millisecond imaging stays the default and caps the cycle near 1 ms. Open: does fast imaging hold across a full array, and does it shift the loss-versus-Pauli mix decoders assume?
Confirm/demote in 12–24 months: either result reproduced by a second group; sub-20 µs readout inside a live logical-qubit run; readout held under reloading at full array size. Best case 2029: microsecond imaging is standard, the round is transport-limited at a few hundred µs, and loss detection is cheap enough to make erasure conversion routine. Worst case: the numbers hold only on small static subarrays. Open questions: what species USTC used; does adaptive stopping survive on a full array where counting runs everywhere at once; who builds the first sensor with the decision on the die.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [11] Novo Nordisk Foundation, “New quantum computer with great potential to boost Nordic research and innovation,” Novo Nordisk Fonden, Jul. 17, 2025. [Online]. Available: https://novonordiskfonden.dk/
en/ Rnews/ new-quantum-computer-with-great-potential-to-boost-nordic-research-and-innovation/ - [12] M. Abdel-Kareem, “Denmark's QuNorth to Acquire 50-Logical-Qubit Magne Quantum Computer from Atom Computing and Microsoft,” Quantum Computing Report, Jul. 17, 2025. [Online]. Available: https://quantumcomputingreport.com/
denmarks-qunorth-to-acquire-50-logical-qubit-magne-quantum-computer-from-atom-computing-and-microsoft/ P - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [155] L. Roady, “Infleqtion Becomes First Neutral-Atom Quantum Company to Go Public,” Infleqtion, Feb. 17, 2026. [Online]. Available: https://infleqtion.com/
infleqtion-becomes-first-neutral-atom-quantum-company-to-go-public/ C - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [261] R. Yokoyama et al., “Minimally Destructive Fast Imaging of Single Atoms in an Optical Tweezer Array with Coherent Excitation,” arXiv:2605.24175, Jun. 2026. Also https://arxiv.org/
abs/ . P2605.24175 - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [329] M. Ivezic, “The Tweezer Array's Hidden Supply Chain: Who Really Wins If Neutral-Atom Quantum Computing Wins,” PostQuantum.com, Nov. 17, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Pneutral-atom-quantum-ecosystem/ - [528] Quantum Machines, “Quantum Machines Raises $170M as Its Customer Base Exceeds 50% of Companies Developing Quantum Computers,” Feb. 25, 2025. [Online]. Available: https://www.quantum-machines.co/
press-release/ Cquantum-machines-raises-170-million-in-series-c-funding/ - [623] Xu-Zhao-Qiu Zeng et al., “Fast Nondestructive Readout for High-Clock-Rate Atom Array Quantum Processor,” arXiv:2608.17189, Aug. 2026. P
- [826] U. Akhouri, “Classically Accelerated Readout for Neutral Atoms with CPU/GPU Integration,” Quantum Machines Blog, Jun. 2026. [Online]. Available: https://www.quantum-machines.co/
resources/ Cblog/ classically-accelerated-readout-neutral-atoms-cpu-gpu-readout/
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הטקסט בעברית נטען…
Spin-to-charge conversion + rf reflectometry
Spin converted into a charge-motion event by Pauli spin blockade or energy-selective tunnelling, then read by an rf-matched charge sensor in microseconds without destroying the qubit.
Verdict. The readout every silicon architecture uses and the term that sets the silicon clock — 6 µs at 99.2% or 100 µs at 99.9%, with no published device delivering both.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Spin carries no charge, so a tunnelling event is made spin-conditional — Pauli spin blockade (PSB; two-spin parity, scale = singlet–triplet splitting) or energy-selective Elzerman tunnelling (single spin, needing Zeeman ≫ kT) — and a charge sensor reports it. The sensor is a single-electron transistor or a gate-based single-electron box read via quantum capacitance, in an LC (inductor–capacitor) tank near 0.1–2 GHz. Elzerman single-shot readout dates to 2004. Attributes: readout — spin-to-charge, ~6 µs, non-destructive, mid-circuit-capable; control — low-frequency drive from room temperature, sensor in CMOS, carrier immobile.
Physics & limits
Per-shot signal-to-noise is the phase shift integrated against amplifier noise over a window capped by T1 and floored by tank bandwidth — the whole trade: 99.2% under 6 µs D[624] against 99.9% SPAM at 100 µs D[189]. Elzerman readout dies as kT approaches the Zeeman energy, so hot (≈1 K) operation costs readout first; Pauli spin blockade survives there but answers parity. Relaxation inside the window returns a false ground state, and sensor charge noise walks the threshold, so measurement error is drifting and correlated, not independent as decoders assume. Quantum-limited amplification and in-fridge demodulation move the floor.
Engineering state of the art
table
| year | figure | who | tag+key |
|---|---|---|---|
| 2023-02-23 | 99.2% single-shot in <6 µs, rf single-electron box | Quantum Motion | D[624] |
| 2025-09-24 | 99.9% SPAM at 100 µs, 300 mm SiMOS | Diraq | D[189] |
Dominant term: SNR at short windows, T1 at long; no foundry device publishes sub-10 µs readout above 99.5%.
The ZQCS channel count is a trade-press restatement of a vendor launch, not a primary release. Not published: a readout-only fidelity, separated by randomised benchmarking, behind the Diraq/imec 99.9% quoted as SPAM.
Manufacturing, materials & supply chain
Built in the qubit's own 300 mm CMOS stack, the sensor adds no materials risk; the gate-based box, needing only an electrode and a tank, is the foundry-favoured form. Instrumentation is bought, not built: Zurich Instruments' SHFQC-LRT gives ≤32 µs weighted integration C[625], and Quantum Machines' OPX1000 lists nine spin customers including Diraq, HRL, imec and Equal1 C[449]. Frequency multiplexing keeps line count sub-linear: the wall at 10³ is tank spacing across the band; at 10⁴–10⁶ it is aggregate readout bandwidth and amplifier count, not the sensor. HRL's 4 K controller (366 DACs, ≤3.5 W) shows the chain can move inside the fridge D[190].
Role in the stack
Required by quantum-dot and donor spins, with no replace or conflict edges — the load-bearing readout node in both the silicon/germanium quantum-dot spin architecture and the donor-spin architecture. The register lists 10 machines using it, among them QM-One, RacQ (Bell-1), the 11-qubit donor processor and the HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots). With exchange gates in tens of nanoseconds, readout at 6–100 µs sets derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 8.5×10⁻⁶ s at the fast end, 6.3 µs of it readout. Verification: the two headline figures are different devices with different sensors — a speed–fidelity curve, not one system — and the 99.9% bundles initialisation. Neither is replicated independently.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Quantum Motion | developer | UK | Single-electron-box readout, 99.2% in <6 µs | D[624] |
| Diraq | developer | Australia | 99.9% SPAM on 300 mm imec SiMOS | D[189] |
| Silicon Quantum Computing | developer | Australia | Readout of donor nuclear registers | Dfact |
| HRL Laboratories | developer | USA | Readout sequenced by 4 K cryo-CMOS | Dfact |
| Zurich Instruments | supplier | Switzerland | Sells the reflectometry instruments | C[625] |
| Quantum Machines | supplier | Israel | Readout stack for nine spin teams | C[449] |
Money. 2025-02-25 · Quantum Machines · Series C · $170 M · PSG Equity, Intel Capital · closed Cfact. 2025-11-06 · Diraq, Quantum Motion, SQC · QBI Stage B · ≤$15 M each · DARPA · selected fact. 2026-05-07 · Quantum Motion · Series C · $160 M · DCVC, Kembara · closed Cfact. 2026-05-21 · Diraq · CHIPS LOI · ≤$38 M · US Commerce · non-binding fact.
Market & supply chain. Zurich Instruments and Quantum Machines supply the rf chain nearly every spin team buys rather than builds C[449], [625]; cryogenic amplification is the second pinch point. Pays into G2, G3, G7.
IP & standards. No dated patent family for spin-to-charge conversion or rf reflectometry in a named database as of 4 Sep 2026.
Roadmaps & track record. Diraq (2026-08-27 · 150 k physical, 1 k logical by 2029 · unmet; its 2026-07-09 release said "thousands by 2029") Rfact. Zurich Instruments (2026-03-09 · ZQCS for "several thousand qubits" · shipping) P[526]. No vendor promises a dated readout rate; instruments ship on schedule, qubit counts do not.
Strategic reading. Readout is the one silicon subsystem bought rather than built, so control-electronics vendors keep leverage whichever qubit wins; if the gate-based box displaces the sensor transistor, the foundry captures it and per-qubit-sensor designs lose twice.
Outlook & open questions
Confirm or demote in 12–24 months: ≥99.9% below 20 µs on a foundry device; ≥16 sensors multiplexed on one line with a crosstalk number. Best case 2029: >100 sensors read under 10 µs each, demodulated in-fridge. Worst case: readout stays the clock-setting term and the largest syndrome-cycle error. Open: (1) tanks per quantum-limited amplifier; (2) whether parity readout suffices without a per-qubit ancilla; (3) how correlated threshold drift looks to a decoder.
References
- [189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fidelity,” Nature, vol. 646, no. 8083, pp. 81–87, Sep. 2025, doi: 10.1038/s41586-025-09531-9. D
- [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
- [449] Quantum Machines, “Semiconductor Spin Qubits,” Aug. 11, 2026. [Online]. Available: https://www.quantum-machines.co/
qubit-types/ Csemiconductor-spin-qubits/ - [526] Zurich Instruments, “Zurich Instruments Launches the ZQCS Quantum Control System to Master the Long-Lived Logical Qubit Challenge,” Mar. 9, 2026. [Online]. Available: https://www.zhinst.com/
americas/ Pen/ news/ zurich-instruments-launches-zqcs-quantum-control-system-master-long-lived-logical-qubit/ - [624] G. A. Oakes et al., “Fast High-Fidelity Single-Shot Readout of Spins in Silicon Using a Single-Electron Box,” Phys. Rev. X, vol. 13, no. 1, Art. no. 011023, Feb. 2023, doi: 10.1103/PhysRevX.13.011023. D
- [625] Zurich Instruments, “SHFQC-LRT Long Readout Time,” Jan. 30, 2025. [Online]. Available: https://www.zhinst.com/
en/ Cproducts/ shfqc-lrt-long-readout-time
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הטקסט בעברית נטען…
rf quantum-capacitance parity readout
Dispersive gate sensing of a Majorana island's quantum capacitance by rf reflectometry, reading fermion parity without charge transfer; non-destructive and mid-circuit.
Verdict. The method is real and independently replicated; falsified as fault-tolerance-grade unless an assignment error below 10⁻³ at a stated integration time is published by 2028, on any stack.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A dot–nanowire interference loop's ground state disperses differently with gate charge in the two parity sectors; that curvature is a quantum capacitance, read as a dispersive shift of an off-chip resonator by rf reflectometry, with no charge transfer. Microsoft, Nature 2025-02-19: 1% assignment error, SNR 1 in 3.6 µs, dwell above 1 ms near 2 T D[13]. This is the single-wire (Z-type) measurement; the joint projection a gate needs is unbuilt.
a fabricated (1.0) · b not a gate · c quantum capacitance, ~4 µs, non-destructive, mid-circuit
d no transport · e rf reflectometry from room temperature · f assignment error plus poisoning · g MBE wire stack
Physics & limits
Signal accumulates as √t while parity survives only until a quasiparticle arrives, so assignment error is a race, modelled as err ≈ ½[1 − e^(−2t/τ)·erf(SNR/√2)²] at mean SNR near 1.2 per µs D[20]. The floor is the poisoning time τ, set by loop geometry, not the amplifier: the same device gives 12.4 ms on the Z loop against 14.5 µs on the X loop, attributed to the two-loop configuration's larger quasiparticle-capture cross-section D[20]. Lead replaced aluminium to raise τ D[21]. What it reads is contested: Nature's editor's note says the results do not by themselves establish Majorana zero modes P[214].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-02 | 1% assignment error, SNR 1 in 3.6 µs, dwell >1 ms, InAs–Al | Microsoft Azure Quantum | D[13] |
| 2026-02 | Independent single-shot parity readout, ~1.85 ms switching, InSb Kitaev chain | QuTech | D[216] |
| 2026-06 | ~20 s parity switching in one InAs–Pb wire, same readout family | Microsoft Quantum | D[21] |
Typical at scale is undefined: no multiplexed multi-tetron readout is published; the 2026 device came up one wire at a time D[21].
The arXiv full text of [20] also gives X ~4 µs and Z ~9.3 ms for other tunings, against the 14.5 µs / 12.4 ms used here. The quasiparticle-poisoning rate during a readout dwell has only been inferred, never measured directly. Not published: a readout-specific R&D spend.
Manufacturing, materials & supply chain
No dedicated process: dots, gates and loop share the wire device's lithography, resonator off-chip. Room-temperature rf drive and demodulation feed a millikelvin amplifier, from the merchant control-electronics base superconducting readout uses Cfact; no single point of failure beyond the wire stack, and no export-control category specific to it. I/O is a gate line and a resonator per measurable parity, multiplexed on a shared feedline: 10³ is solved packaging. The wall is time: 3.6 µs is fast against 12.4 ms, slow against 14.5 µs, so at 10⁴–10⁶ the limit is how many X projections fit in the shorter window.
Role in the stack
The one demonstrated block the topological architecture owns: it requires the Majorana-parity carrier and provides the projective measurement a measurement-based gate would consume, non-destructively and mid-circuit, the precondition for measurement-only architecture. It is the only defined term of the architecture's derived clock: in sum of the syndrome round: gate layers + transport + readout + reset only readout is published, ~3.6 µs to SNR 1 D[13], with no code and no reset figure. Verification: QuTech's Nature paper (2026-02-11) independently replicates the principle on InSb dot-based Kitaev chains rather than a tetron, at ~1.85 ms telegraph lifetimes D[216]; its follow-up shows coherent parity oscillations with only limited protection D[217]. Legg disputes whether the read regions are gapped at all D[22]. Nobody has replicated the 1% error.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Originated the method; used on every tetron device | D[13] |
| QuTech | research | NL | Independent parity readout and coherent parity qubit, on Eindhoven-grown InSb wires | D[216] |
| DARPA | investor | US | Funds the only industrial user; US2QC final stage since 2025-02-06 | fact |
Money. 2025-02-06 · Microsoft · US2QC final Validation & Co-Design stage · undisclosed · DARPA · announced fact. 2026-01-23 · Microsoft · Quantum Pioneers Program, readout an award topic · ≤ USD 200,000 per proposal · announced Pfact.
Market & supply chain. No standalone market; rf reflectometry and cryogenic amplification are generic and multi-sourced, so concentration risk sits in the wire stack. G3 and G4 only.
IP & standards. Dispersive gate sensing is common property across semiconductor-qubit groups; no dated patent count specific to parity readout as of 4 Sep 2026.
Roadmaps & track record. (used in every public Microsoft device from 2025-02, implicitly for fault tolerance by 2029; status 4 Sep 2026: no fidelity or speed target published for the readout) C[215]. QuTech publishes with no schedule to defend, the more credible record.
Strategic reading. The method is public and replicated, so Microsoft's exclusivity has moved into the wire stack; whoever first publishes assignment error near 10⁻³ at a stated integration time sets the downstream pace.
Outlook & open questions
Falsifiable in 12–24 months: a third group publishing parity readout; a sub-1% assignment error from anyone but Microsoft; a directly measured poisoning rate. Confirm if two land; demote if it stays a two-laboratory result to 2028. Best case, readout stops being the open variable; worst case, τ on a joint loop stays in tens of µs. Open: does multiplexed multi-tetron readout work; is 1% reproducible off Microsoft's devices.
References
- [13] Microsoft Azure Quantum, “Interferometric single-shot parity measurement in InAs–Al hybrid devices,” Nature, vol. 638, no. 8051, pp. 651–655, Feb. 2025, doi: 10.1038/s41586-024-08445-2. D
- [20] M. Aghaee et al., “Distinct Lifetimes for X and Z Loop Measurements in a Majorana Tetron Device,” arXiv:2507.08795, Jul. 2025. D
- [21] M. Aghaee et al., “20 Second Parity Lifetime in an InAs–Pb Tetron Device,” arXiv:2606.03884, Jun. 2026. D
- [22] H. F. Legg, “On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E22–E26, Jun. 2026, doi: 10.1038/s41586-026-10567-8. arXiv:2503.08944. D
- [214] P. Ball, “Experts Weigh in on Microsoft's Topological Qubit Claim,” Physics, vol. 18, p. 57, 2025. [Online]. Available: https://physics.aps.org/
articles/ Pv18/ 57 - [215] C. Nayak, “Majorana 2 – Microsoft's Scalable Quantum Processor With Reliable, Long-Lasting Qubits,” Microsoft Quantum. [Online]. Available: https://quantum.microsoft.com/
en-us/ Cinsights/ blogs/ majorana-2-scalable-quantum-processor - [216] N. van Loo et al., “Single-shot parity readout of a minimal Kitaev chain,” Nature, vol. 650, no. 8101, pp. 334–339, Feb. 2026, doi: 10.1038/s41586-025-09927-7. D
- [217] F. Zatelli et al., “Majorana parity qubit in coupled minimal Kitaev chains,” arXiv:2607.09511, Jul. 2026. D
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הטקסט בעברית נטען…
Fast unconditional / dissipative qubit reset
Returning a superconducting qubit to |0⟩ in ~100–500 ns by handing its excitation to a lossy mode, usually the readout resonator, instead of waiting for T1 or measuring and flipping.
Verdict. Demonstrated since 2018 and inside production error-correction rounds (Google's 160 ns step in a 921 ns round; USTC's all-microwave ancilla reset). IBM's dissipative gadget on Nighthawk r2 is company-reported only: no reset duration or absolute residual population published as of 2026-09-26.
T1 = energy-relaxation time; κ = energy-decay rate of the lossy mode; LRU = leakage reduction unit; DQLR = data-qubit leakage removal; MLR = multi-level reset; Λ = error-suppression factor per code-distance step; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Reset returns a qubit to |0⟩ before a shot and, in error correction, every measure qubit once per syndrome round. Unconditional reset — this technology — hands the excitation to a lossy mode with no classical decision, unlike waiting for T1 or measuring and flipping. It began with the all-microwave "f0g1" scheme: a drive couples |f,0⟩ to |g,1⟩ of the transmon–resonator pair (g, f = ground and second excited states; 0, 1 = resonator photons) and the photon leaks out, leaving 0.2% residual excitation in under 500 ns without feedback D[596]. It sits in the readout layer because the lossy mode is usually the readout resonator and feedline D[597]D[598]. Attributes: on-chip, superconducting lithography, driven from room temperature, no transport; error class leakage.
Physics & limits
Passive relaxation is too slow: even with no thermal floor, 10⁻³ at T1 = 200 µs takes ln(10³)·T1 ≈ 1.4 ms S. The floor matters too: a 5 GHz transmon at 50 mK effective temperature holds ~0.8% excitation S, so reset must cool — with engineered rate Γ_r ≫ Γ_q the residual tends to (Γ_q·n_q + Γ_r·n_r)/(Γ_q + Γ_r), the colder bath's occupation S. Speed is set by the lossy mode: an excitation swapped into a mode of decay rate κ leaves no faster than the critically damped κ/2, so 10⁻³ takes ≈ 21/κ, 170–340 ns for κ/2π = 20–10 MHz S — the 100–500 ns band. A 34 ns flux swap thus becomes 284 ns once the resonator must be emptied D[599]; a broadband metamaterial bath escapes the single-mode bound D[600]. A switchable dissipator decouples reset rate from idle T1: IBM's moves effective T1 from ~200 µs to ~25 ns C[601], an on/off ratio of ~8×10³ S. Leakage is the companion problem: a conditional X acts only on |0⟩↔|1⟩, so |2⟩ stays leaked S; MLR empties |1⟩–|3⟩ at one setting D[597].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2018-08-07 | f0g1: 0.2% residual in <500 ns | Magnard et al. | D[596] |
| 2021-03-19 | MLR of |1⟩–|3⟩ in ~250 ns, >99% (readout-limited) | D[597] | |
| 2021-10-11 | Flux swap: 0.08% ± 0.08% in 34 ns; 284 ns with depletion | Zhou et al. | D[599] |
| 2023-02-22 | 160 ns reset + 500 ns measurement in a 921 ns round | Google, Sycamore | D[602] |
| 2024-09-25 | Reset + leakage reduction in 83 ns, fixed-frequency, >99% | Chen et al. | D[598] |
| 2024-11-05 | Reset error <0.13% (|1⟩), 0.16% (|2⟩) in 88 ns; |2⟩-only LRU 44 ns | Kim et al. | D[600] |
| 2025-12-22 | Microwave LRUs + ancilla reset: leakage ÷72 to 6.4×10⁻⁴; d=7, Λ = 1.40 ± 0.06 | USTC, Zuchongzhi 3.2 | P[603] |
| 2026-08-31 | 120 reset elements; initialisation error ÷25 | IBM, Nighthawk r2 | C[601] |
Sycamore spent 660 of 921 ns (72%) measuring and resetting, and its authors name data-qubit idling during them a dominant error D[602]. Willow runs MLR on measure qubits and DQLR on data qubits every 1.1 µs cycle D[1], after DQLR cut data-qubit leakage tenfold, below 10⁻³ device-wide D[604]. USTC's row is the press reading of its PRL D[3]. IBM's gain is shot rate: 100,000 circuits per second, 25× Heron C[601]. Dominant term: residual population, which production vendors do not publish.
Manufacturing, materials & supply chain
Resonator-based reset adds no fabrication step D[596]. The cost follows qubit type: flux-tunable transmons reuse their flux lines D[597]; fixed-frequency ones use the microwave route, a tunable coupler D[598] or a dedicated element per qubit C[601]. A tunable element is in general one more control signal per qubit S; press coverage credits USTC's microwave-only route with avoiding Google's DC-pulse wiring P[605].
Control, readout & I/O burden
Unconditional reset is an open-loop pulse: no discrimination, decision or feed-forward. Conditional reset stacks readout, ring-down, a decision and a π pulse, floored by assignment error; IBM's earlier scheme flipped on |1⟩, then idled hundreds of microseconds between executions C[601], an idle exposed as rep_delay that trades execution time against state-preparation error C[606]. In a surface code the measurement happens anyway; what follows is a 160 ns step D[602] or a feed-forward loop paid every round S.
Role in the stack
Slot 6 of the Transmon lattice with tunable couplers architecture, beside dispersive readout. It requires the transmon (the qubit to be reset) and ro_disp (the readout resonator as loss channel); no provides, replaces or conflicts edge exists as of 2026-09-26. The ro_disp edge is the common case, not a necessity: Nighthawk r2 couples each qubit to a cold environment through its own tunable coupler C[601]. It answers gap G-reset with reset time and residual population as attributes; the Atlas's derived clock counts readout + reset as ≈ two-thirds of the superconducting round. The ledger's cat and dual-rail placements were not taken; atom re-initialisation or reloading has no lossy-mode step and is not this technology G. The sibling gap G-lru, data-qubit leakage removal, stays open. Register machines, primary: Sycamore-class 72-qubit processor, IBM Quantum Loon, IBM Quantum Nighthawk r2; alternate: Zuchongzhi 3.2, IBM Quantum System Two at CSCS (Swiss Quantum Innovation Hub).
Evidence — how the numbers were measured
Reset is checked by reading the qubit afterwards, so readout error bounds it: McEwen et al.'s ~10⁻³ was readout-limited D[597]. Reported quantities do not compare — residual excitation, reset error, effective T1, an error ratio. All four register cells are verified ✅, but only Sycamore's has a figure locator (Fig. 1b); IBM's rest on blogs, Loon's naming "reset gadgets" without figures C[486]; Zuchongzhi 3.2's has neither locator nor reset figure.
The Zuchongzhi 3.2 figures (72×, 6.4×10⁻⁴, d = 7, Λ) come from press analysis. The 1.4 ms, 0.8%, ≈21/κ and 8×10³ figures are derived from arXiv:2409.16748 and arXiv:2411.02950, not quoted by them. Not published, as of 2026-09-26: USTC's reset duration and residual; Nighthawk r2's reset duration, absolute residual and any paper — its blog gives an effective T1, a 25× ratio and ~1 µs idle; Loon's reset-gadget figures; Heron's conditional-reset duration and feed-forward latency; and Willow's measurement and reset durations, with the DQLR duration of Miao et al.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | 160 ns reset in Sycamore's round; MLR + DQLR every Willow cycle | D[602]D[1] |
| IBM | developer | US | Conditional reset on Heron; 120 dissipative elements on Nighthawk r2; gadgets on Loon | C[601]C[486] |
| USTC / Hefei National Laboratory | developer | CN | Microwave LRUs and in-cycle ancilla reset, Zuchongzhi 3.2 | P[603] |
Money. No dated financial item is specific to qubit reset as of 2026-09-26.
Market & supply chain. No separate market: reset is bought as chip design and calibration and pays out as round time and shot rate, into G2–G4.
IP & standards. No standard defines a reset figure of merit; no dated patent count from a named database as of 2026-09-26.
Roadmaps & track record. IBM named reset gadgets on 2025-11-12 C[486] and shipped them on Nighthawk r2 on 2026-08-31 C[601]: delivered, with ratios rather than absolute figures.
Strategic reading. Reset is where fixed-frequency and tunable architectures part. If switchable dissipators keep their off-state T1 at scale, readout resonators can be optimised for readout alone.
Outlook & open questions
Confirm if IBM or an independent group publishes Nighthawk r2's reset duration, absolute residual and mid-circuit use by 2027-06-30, and if a d ≥ 9 surface code brings readout + reset below half its round by 2027-12-31; demote the gadget to a throughput feature if figures cover only between-shot initialisation.
Open questions. (1) What absolute residual does Nighthawk r2 reach? (2) What does a dissipator's off-state cost in T1 across 10³ qubits? (3) Can reset overlap ring-down to shrink the 660 ns term? (4) Do microwave-only resets match flux-based speed without crosstalk? (5) Which data-qubit leakage scheme closes G-lru without adding a round step?
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [3] T. He et al., “Experimental Quantum Error Correction below the Surface Code Threshold via All-Microwave Leakage Suppression,” Phys. Rev. Lett., vol. 135, no. 26, Art. no. 260601, Dec. 2025, doi: 10.1103/rqkg-dw31. D
- [486] R. Mandelbaum, “Scaling for quantum advantage and beyond,” IBM Quantum Computing Blog, Nov. 12, 2025. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ qdc-2025 - [596] P. Magnard et al., “Fast and Unconditional All-Microwave Reset of a Superconducting Qubit,” Phys. Rev. Lett., vol. 121, no. 6, Art. no. 060502, Aug. 2018, doi: 10.1103/physrevlett.121.060502. arXiv:1801.07689. D
- [597] M. McEwen et al., “Removing leakage-induced correlated errors in superconducting quantum error correction,” Nat. Commun., vol. 12, Art. no. 1761, Mar. 2021, doi: 10.1038/s41467-021-21982-y. arXiv:2102.06131. D
- [598] L. Chen et al., “Fast unconditional reset and leakage reduction in fixed-frequency transmon qubits,” arXiv:2409.16748, Sep. 2024. D
- [599] Y. Zhou et al., “Rapid and unconditional parametric reset protocol for tunable superconducting qubits,” Nat. Commun., vol. 12, Art. no. 5924, Oct. 2021, doi: 10.1038/s41467-021-26205-y. D
- [600] G. Kim et al., “Fast Unconditional Reset and Leakage Reduction of a Tunable Superconducting Qubit via an Engineered Dissipative Bath,” arXiv:2411.02950, Nov. 2024. D
- [601] H. Haas, D. McKay, and R. Davis, “IBM Quantum Nighthawk r2—more circuits, faster,” IBM Quantum Computing Blog, Aug. 31, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ nighthawk-r2 - [602] R. Acharya et al., “Suppressing quantum errors by scaling a surface code logical qubit,” Nature, vol. 614, pp. 676–681, Feb. 2023, doi: 10.1038/s41586-022-05434-1. D
- [603] M. Ivezic, “China's Zuchongzhi 3.2 Crosses the Error Correction Threshold - and Takes a Different Path Than Google to Get There,” PostQuantum.com, Dec. 30, 2025. [Online]. Available: https://postquantum.com/
quantum-research/ Pzuchongzhi-3-2-belowthreshold/ - [604] K. C. Miao et al., “Overcoming leakage in quantum error correction,” Nat. Phys., vol. 19, pp. 1780–1786, Oct. 2023, doi: 10.1038/s41567-023-02226-w. D
- [605] M. Swayne, “China Demonstrates Quantum Error Correction Using Microwaves, Narrowing Gap With Google,” The Quantum Insider, Dec. 26, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P12/ 26/ china-demonstrates-quantum-error-correction-using-microwaves-narrowing-gap-with-google/ - [606] IBM, “Qubit initialization.” [Online]. Available: https://quantum.cloud.ibm.com/
docs/ Cen/ guides/ repetition-rate-execution
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הטקסט בעברית נטען…
Homodyne quadrature detection (CV)
A signal mode interfered with a strong local oscillator on a balanced photodiode pair, whose difference current samples one chosen field quadrature — the computational measurement of continuous-variable and GKP machines.
Verdict. The receiver physics is mature — integrated detectors stay shot-noise-limited to 9–20 GHz against a 1 MHz machine clock — but as of 2026-09-26 no CV machine has published the efficiency or electronic-noise clearance of its computational homodyne channels, and upstream loss, not the detector, sets the error floor.
LO = local oscillator; GKP = Gottesman–Kitaev–Preskill grid state; MBQC = measurement-based quantum computation; PNR = photon-number-resolving; TES = transition-edge sensor; TIA = transimpedance amplifier; OPA = optical parametric amplifier; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A weak signal mode and a strong LO meet on a 50:50 beamsplitter; subtracting the two photocurrents cancels the LO's classical noise and leaves a signal proportional to the quadrature x̂_θ = x̂ cos θ + p̂ sin θ, θ set by the LO phase. Heterodyne detection measures two conjugate quadratures at once for one extra unit of vacuum noise. It became a computational readout when time-multiplexed CV cluster states were read mode by mode — Tokyo D[635] and DTU D[636], both 2019 — and moved onto chips in Xanadu's Aurora D[173].
Attributes: destructive but mid-circuit (in MBQC the measurement angle is the gate); ~10⁻⁶ s per measurement at the 1 MHz clock; room-temperature electro-optic control; Gaussian-noise errors; photonic-IC fabrication.
Physics & limits
Efficiency η acts as loss before an ideal detector: variance V is recorded as ηV + (1−η) in vacuum units, so observing 10 dB of squeezing needs η > 0.90 even for infinite input squeezing S. For GKP states, rescaling by 1/√η turns inefficiency into a Gaussian displacement of variance (1−η)/η: η = 0.99 adds 0.010, a tenth of the 0.106 the Atlas's ~9.75 dB target allows (~0.4 dB); η = 0.95 alone drags 9.75 dB to 8.0 dB S. Electronic-noise clearance C dB is an equivalent efficiency 1 − 10^(−C/10): 20 dB costs 1 %, 28 dB 0.16 % S. LO phase jitter δθ admits the anti-squeezed quadrature, V ≈ Vsq + V_anti·δθ²; at 15 dB anti-squeezing, 1° rms costs as much as 1 % inefficiency S. Bandwidth must exceed the inverse mode duration — Tokyo's 40 ns bins sat under ~100 MHz detectors D[635]. A GKP outcome is binned to the nearest multiple of √π and its parity read as the logical value; q̂, p̂ and q̂+p̂ implement Z, X and Y, and the distance to the bin edge can weight the outer decoder S[637].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2019 | 2D cluster state; ~100 MHz homodyne, efficiency 0.75–0.80; nullifiers −4.8 to −5.3 dB | Univ. of Tokyo | D[635] |
| 2019 | >30,000-mode 2D cluster state; two fibre homodyne detectors; nullifiers −4.7 / −4.3 dB | DTU | D[636] |
| 2021 | Ge-on-Si + SiGe receiver: 1.7 GHz 3-dB bandwidth, shot-noise-limited beyond 9 GHz | Univ. of Bristol | D[638] |
| 2021 | Silicon photonics + GaAs TIA: shot-noise-limited beyond 20 GHz, 28 dB clearance | Ghent Univ. | D[639] |
| 2023 | OPA pre-amplification: 5.2 ± 0.5 dB squeezing, DC–43 GHz, uncorrected | Univ. of Tokyo, NTT | D[640] |
| 2025 | Aurora: on-chip homodyne, 12 modes per 1 MHz cycle, single-cycle feed-forward | Xanadu | D[173] |
| 2026 | Squeezer and homodyne on one chip: 34 modes, ~3 dB, 72 % efficiency | Univ. of Virginia | D[641] |
Speed is solved three orders of magnitude beyond need; efficiency is not. The one generation-plus-detection chip reaches 72 % D[641], and Aurora states no efficiency, bandwidth or clearance for its channels D[173]. OPA pre-amplification sidesteps the detector: equivalent post-amplifier loss falls from 92.4 % to 0.4 % D[640]. Dominant term: loss upstream — ~56 % in Aurora's heralding paths, over 95 % in its heralded paths, against ~1 % budgets D[173].
Manufacturing, materials & supply chain
Aurora's QPU array is five modules on AIM Photonics' 300 mm silicon-photonic platform — SiN and Si waveguides, germanium photodiodes, carrier-depletion modulators — with the LO envelope shaped by an Exail MXIQER-LN-30 modulator D[173]. Squeezing wants low-loss waveguides, detection strong absorption; Virginia joined both on one chip by heterogeneously integrating photodiodes D[641]. Bandwidth is photodiode capacitance against the amplifier — SiGe electronics at Bristol D[638], a GaAs pHEMT TIA at Ghent D[639]. The parts are coherent-telecom stock; Tokyo's receiver is a 5G photodiode D[640].
Control, readout & I/O burden
Each channel is a photodiode pair, TIA, ADC, phase-controlled LO path and a feed-forward link acting within one clock. In Aurora a reference laser carries the phase that stabilises measurement angles, and a controller informed by algorithm and decoder selects bases every cycle, with single-clock-cycle feed-forward D[173]; DTU locked its LOs by AC demodulation D[636]. Receivers run at room temperature; heralding by Aurora's 36 PNR detectors is a separate chain D[173]. Channels scale linearly with modes per clock — 12 in Aurora; at 10³–10⁴ the ADC and feed-forward budget, not the optics, dominates S.
Role in the stack
The Readout slot of the Continuous-variable photonic — GKP architecture, beside single-photon detection. It requires a squeezed-light source (a quadrature to measure) and electro-optic control (LO phase); it provides no downstream edge; single-photon detection replaces it wherever photons are counted. The gap ledger (G-homodyne) created it because SNSPD/TES counting heralds a CV machine but does not compute; Aurora confirms the fix D[173], while GKP preparation still heralds with PNR detectors quoted above 99 % efficiency P[642]. Register: Aurora primary, cell ✅. Borealis does not carry it: its 216 squeezed modes pass a 1-to-16 demultiplexer onto 95 %-efficient TES PNR detectors, no homodyne stated D[270].
Evidence — how the numbers were measured
Receivers are qualified by shot-noise linearity, clearance and squeezed-light efficiency calibration; systems by nullifier variances below the −3 dB entanglement bound — all 1,500 of DTU's were D[636]. Such figures include detection, like the uncorrected 5.2 dB at 43 GHz D[640]; loss-corrected squeezing and GKP effective squeezing — 0.62 dB for Xanadu's integrated source in the Atlas's record D[174] — are other quantities. Thresholds depend on architecture: static linear optics needs 10.1 dB with all modes GKP, 13.6 dB with one per macronode, lossless S[637]. As of 2026-09-26 Aurora reports path losses but no per-channel efficiency, clearance or phase noise D[173].
The ~9.75 dB target has no primary source; Tzitrin et al. give 10.1 dB, 13.6 dB or ~10 dB depending on architecture. DTU's 2019 arXiv text gives its homodyne efficiency only by reference to earlier work. Not published: Aurora's homodyne bandwidth and feed-forward latency.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Xanadu | developer | Canada | On-chip homodyne with single-cycle feed-forward (Aurora) | D[173] |
| University of Tokyo, NTT | research | Japan | Cluster-state readout; OPA-amplified 43 GHz measurement | D[635], [640] |
| DTU | research | Denmark | Cluster state read by fibre homodyne detectors | D[636] |
| University of Bristol | research | UK | Ge-on-Si + SiGe receiver, 9 GHz | D[638] |
| Ghent University | research | Belgium | Silicon photonics + GaAs TIA, >20 GHz | D[639] |
| AIM Photonics | foundry | US | 300 mm platform with Ge photodiodes for Aurora | D[173] |
Money. No dated financial item specific to homodyne readout was found as of 2026-09-26.
Market & supply chain. No merchant market in computational receivers; the parts are shared with CV key distribution and random-number generation D[639]. It pays into G4 and G6; the G1 sampler does without it.
IP & standards. As of 2026-09-26 no standard for reporting homodyne efficiency or clearance, and no dated patent count specific to it.
Roadmaps & track record. No developer has published a dated homodyne target as of 2026-09-26. Aurora's 35 chips and 86.4 billion modes over 2 h are a scale result, not a readout-quality one D[173].
Strategic reading. If effective squeezing nears threshold, receivers become a CV machine's most numerous active component — one per mode per clock — and value moves to whoever co-integrates them with feed-forward on the photonic die; OPA pre-amplification is the hedge. If not, homodyne stays in key distribution and metrology.
Outlook & open questions
Confirm if, by 2027-12-31, a CV machine publishes per-channel homodyne efficiency ≥ 99 % with ≥ 20 dB clearance, or on-chip GKP effective squeezing exceeds 3 dB; demote if by 2028-06-30 no CV system paper discloses receiver figures while effective squeezing stays below 1 dB.
Open questions. (1) Aurora's per-channel efficiency and clearance? (2) Can photodiodes on a low-loss squeezing platform reach 99 %? (3) Does OPA pre-amplification scale to one locked pump per mode? (4) What LO phase noise does GKP binning tolerate near 10 dB? (5) How much of the gap from 0.62 dB is detection loss?
References
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [174] M. V. Larsen et al., “Integrated photonic source of Gottesman–Kitaev–Preskill qubits,” Nature, vol. 642, no. 8068, pp. 587–591, Jun. 2025, doi: 10.1038/s41586-025-09044-5. D
- [270] L. S. Madsen et al., “Quantum computational advantage with a programmable photonic processor,” Nature, vol. 606, no. 7912, pp. 75–81, Jun. 2022, doi: 10.1038/s41586-022-04725-x. D
- [635] W. Asavanant et al., “Time-Domain Multiplexed 2-Dimensional Cluster State: Universal Quantum Computing Platform,” Science, vol. 366, p. 373, 2019, doi: 10.1126/science.aay2645. arXiv:1903.03918. D
- [636] M. V. Larsen, X. Guo, C. R. Breum, J. S. Neergaard-Nielsen, and U. L. Andersen, “Deterministic generation of a two-dimensional cluster state,” Science, vol. 366, p. 369, 2019, doi: 10.1126/science.aay4354. arXiv:1906.08709. D
- [637] I. Tzitrin et al., “Fault-tolerant quantum computation with static linear optics,” PRX Quantum, vol. 2, Art. no. 040353, 2021, doi: 10.1103/PRXQuantum.2.040353. arXiv:2104.03241. S
- [638] J. F. Tasker et al., “Silicon photonics interfaced with integrated electronics for 9 GHz measurement of squeezed light,” Nat. Photon., vol. 15, pp. 11–15, Jan. 2021, doi: 10.1038/s41566-020-00715-5. arXiv:2009.14318. D
- [639] C. Bruynsteen et al., “Integrated balanced homodyne photonic–electronic detector for beyond 20 GHz shot-noise-limited measurements,” Optica, vol. 8, no. 9, pp. 1146–1152, Sep. 2021, doi: 10.1364/OPTICA.420973. D
- [640] A. Inoue et al., “Toward a multi-core ultra-fast optical quantum processor: 43-GHz bandwidth real-time amplitude measurement of 5-dB squeezed light using modularized optical parametric amplifier with 5G technology,” Appl. Phys. Lett., vol. 122, Art. no. 104001, 2023, doi: 10.1063/5.0137641. arXiv:2205.14061. D
- [641] H. Chen et al., “Heterogeneously Integrated Squeezed-Light Generation and Detection on a Single Photonic Chip,” arXiv:2608.13218, Aug. 2026. D
- [642] Xanadu, “Xanadu Unveils 1st On-Chip Error-Resistant Photonic Qubit,” HPCwire, Jun. 5, 2025. [Online]. Available: https://www.hpcwire.com/
off-the-wire/ Pxanadu-unveils-1st-on-chip-error-resistant-photonic-qubit/
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Flux readout via QFP / SQUID shift registers (annealers)
At the end of an anneal each flux qubit's persistent-current state is latched by a quantum flux parametron and carried as a classical bit to a detector — a dc SQUID, or on Advantage a frequency-multiplexed microresonator at the chip perimeter; no qubit is coupled to a readout resonator.
Verdict. Mature for its one job — 17–101 µs per read and ≤10⁻³ error per qubit on Advantage2, by D-Wave's own figures — but terminal by construction: as of 2026-09-26 no annealer reads mid-schedule, and no published Advantage2 readout architecture or readout-error method was found.
QFP = quantum flux parametron, an rf-SQUID flux latch; dc SQUID = two-junction interferometer used as a switching detector; Φ-DAC = on-chip flux digital-to-analogue converter; FASTR = flux-sensitive superconducting microresonator; CSFQ = capacitively shunted flux qubit; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An annealer needs one measurement, in one basis, once. At the end of the schedule the tunnelling term A(s) is negligible and every rf-SQUID flux qubit has localised into one of two persistent-current states C[607]; the technology reads that classical flux. A QFP coupled to each qubit latches its sign, with flux sensitivity well beyond what a practical mutual inductance to a dc SQUID gives D[608]. The lineage is D-Wave's: a "robust and scalable" rf-SQUID qubit D[609], a 128-qubit latch-plus-dc-SQUID readout D[608], and on Advantage QFP shift registers feeding perimeter microresonators C[607]. Attributes: flux mechanism, fabricated, terminal with no mid-circuit read, low-frequency control at the mK stage, bit-flip (Pauli) error.
Physics & limits
The readout tells apart two macroscopically distinct flux states, not two microwave frequencies. A QFP's barrier is raised while the qubit's flux tilts its potential, so it settles into the favoured well and a small signal becomes a full-scale latch state G[608]. The latch is robust against the current pulses of switching dc SQUIDs, so it can be read repeatedly to beat stochastic switching: single-qubit read error <10⁻⁶, and 8×10⁻⁵ on a 128-qubit system at optimal latch bias D[608]. The floor sits before the latch: flips during freeze-out are read faithfully as wrong answers, and no readout metric separates them S.
"Destructive" here means terminal rather than state-destroying: with reinitialize_state = False each reverse anneal "is initialized from the final state of the qubits after the previous cycle" C[610]. Dispersive readout (ro_disp) would need a resonator per qubit and coherent state-dependent frequency shifts, for thousands of quasi-statically biased qubits read once S. The coherent-annealer variant puts a QFP, as isolator and amplifier, before a low-Q resonator (Qₑ = 760): 98.6% fidelity in 80 ns, 99.6% in 1 µs on a CSFQ D[611].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2009-05 | 128-qubit XY readout: N latches, N dc SQUIDs, 2√N + 2 bias lines; system error 8×10⁻⁵ | D-Wave | D[608] |
| 2010-04-07 | "Robust and scalable" rf-SQUID flux qubit | D-Wave | D[609] |
| 2014-01 | 512-qubit processor; readout left to "a subsequent publication" | D-Wave | D[430] |
| 2015-09 | Tunable microresonator detectors, >1,000 per line possible | D-Wave | D[612] |
| 2020 | QFP-isolated resonator readout of a CSFQ, 98.6% in 80 ns | Northrop Grumman | D[611] |
| 2021-08 | Advantage: QFP shift registers, ~10 Mbit/s per track, frequency-multiplexed FASTRs | D-Wave | C[607] |
| 2026-09 | Advantage2_system1, 4,575 qubits: 17–101 µs per read, readout error ≤0.001 | D-Wave | C[613] |
The upper per-read time fell from 235 µs on Advantage_system4 (5,627 qubits) to 101 µs on Advantage2_system1 C[613]; it "can vary depending on the size of the problem" C[614]. Dominant term: time per sample, not error.
Manufacturing, materials & supply chain
The chain is built in the processor's own superconducting multilayer process: QFP shift registers run along horizontal and vertical tracks from the qubits to the perimeter, where the microresonators sit C[607]. Readout adds no die, bond or foundry of its own; its yield risk is the processor's S. The only microwave element is the perimeter array, read in parallel by frequency multiplexing C[607], a detector class that scales past 1,000 per line D[612].
Control, readout & I/O burden
The technology keeps annealer I/O sublinear. Berkley's XY scheme needed 2√N + 2 bias lines — ~25 for 128 qubits, ~137 if applied to 4,575 S[608]; Advantage drops per-qubit detectors, shifting bits out at ~10 Mbit/s per track C[607]. Time is the cost: per sample Ts/R ≈ Ta + Tr + Td; D-Wave's worked example has anneal 20.0 µs, readout 39.76 µs, delay 21.02 µs, and 15.9 ms programming per job C[614]. For a full problem, readout is ~56% of each sample on Advantage2_system1 (Tr ≤ 101 µs, Td = 60.6 µs) and ~85% on Advantage_system4 (235 µs, 20.5 µs) S[613]. The Atlas's whole-chip read time of milliseconds (t = −3) overstates it 4–60-fold; milliseconds accrue per job S[613].
Role in the stack
On the architecture Quantum annealer — flux qubits (anneal) the technology fills slot 6 beside ro_disp; slots 7–9 are empty. It requires flux qubits latched by QFPs (fluxq) and on-chip shift registers and DACs (ct_fluxdac); it provides no edge, its product being the classical sample; ro_disp is its declared replacement (dispersive vs flux-latch readout). Register machines: Advantage (primary, ✅), Advantage2 (primary, 🔎); Qilimanjaro's AQPU (10 analogue fluxonium qubits, inaugurated at BSC in May 2026) is not among them, its readout undisclosed. Gap ledger G-fluxro is answered — D-Wave does not read qubits dispersively — but "no dispersive resonator anywhere" overstates it: Advantage's perimeter microresonators read shift-register bits C[607]. ro_disp belongs on this architecture only for the QFP-plus-resonator hybrid D[611].
Evidence — how the numbers were measured
D-Wave publishes readout error as a bound, ≤0.001 on every listed Advantage and Advantage2 system, with no method stated C[613]; at that bound a 4,575-qubit sample carries an expected ≤4.6 flipped bits S[613]. The only published method found is Berkley's, error measured against latch bias D[608]. Without a mid-anneal read there is no syndrome round: any code is decoded once, from the final sample, and mitigation is post hoc — repeated reads and software spin-reversal transforms C[610]. Register grades: both D-Wave cells cite arXiv:0905.0891 Fig. 1 (🔎), whose abstract confirms the latch–dc-SQUID chain but for a 128-qubit XY design; Boothby et al. fits Advantage, the solver-properties page Advantage2. The Qilimanjaro cell cites a D-Wave page.
The 20 µs anneal is the documentation's worked example, not a confirmed solver default, and the 60.6 µs against 20.6 µs delay difference is unexplained. Not published: a per-qubit readout-error distribution for D-Wave systems, and the Advantage2 readout architecture (resonator count, shift rate).
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| D-Wave Quantum | developer | Canada/USA | QFP latches, shift registers and perimeter microresonators on Advantage and Advantage2 | C[607] |
| Northrop Grumman | research | US | QFP-isolated resonator readout for high-coherence annealers | D[611] |
| Qilimanjaro Quantum Tech | developer | Spain | Coherent annealer platform (the AQPU at BSC, May 2026); readout chain not confirmed as of 2026-09-26 | C[615] |
Money. No dated financial item is specific to this readout technology as of 2026-09-26.
Market & supply chain. One shipping vendor; readout is not sold separately and rides on the processor's niobium process. It pays into G1 and G5 through throughput: ~182 µs per full-chip sample on Advantage2_system1 is ~5,500 samples per second S[613].
IP & standards. No readout-specific patent count from a named database and no standards activity found as of 2026-09-26.
Roadmaps & track record. Advantage2 is generally available with 4,400+ qubits and 40,000+ couplers, 20 per qubit C[616]; its full-chip read is ~2.3× faster than Advantage_system4's S[613]. The register records no next-generation annealer as of 2026-09-26.
Strategic reading. Readout is where annealing loses throughput, not quality; faster reads help sample-hungry G5 work, and D-Wave's gate-model line cannot reuse the chain, since nothing in it acts mid-circuit S.
Outlook & open questions
Confirm if by 2027-06-30 D-Wave publishes an Advantage2 readout description with a measured per-qubit error distribution; demote ≤10⁻³ to an unqualified company bound if not. Confirm Qilimanjaro here if by 2027-12-31 it publishes a flux-latch chain; move it to ro_disp if a resonator reads its QFP or qubit. Open questions. (1) What sets the 17 µs floor — shift clock, resonator ring-down or thermalisation? (2) Does readout error vary along a track? (3) Does latch back-action bias the next reverse anneal? (4) Can a mid-anneal read be made non-terminal? (5) Why does Advantage2_system1 need a 60.6 µs per-sample delay against 20.6 µs on system2?
References
- [430] P. I. Bunyk et al., “Architectural considerations in the design of a superconducting quantum annealing processor,” arXiv:1401.5504, Jan. 2014. D
- [607] K. Boothby et al., “Architectural considerations in the design of a third-generation superconducting quantum annealing processor,” arXiv:2108.02322, Aug. 2021. C
- [608] A. J. Berkley et al., “A scalable readout system for a superconducting adiabatic quantum optimization system,” Supercond. Sci. Technol., vol. 23, Art. no. 105014, 2010. arXiv:0905.0891. D
- [609] R. Harris et al., “Experimental demonstration of a robust and scalable flux qubit,” Phys. Rev. B, vol. 81, no. 13, Art. no. 134510, Apr. 2010, doi: 10.1103/PhysRevB.81.134510. D
- [610] D-Wave Quantum Inc., “QPU Solver Parameters — D-Wave Quantum Computing Products documentation.” [Online]. Available: https://docs.dwavequantum.com/
en/ Clatest/ quantum_research/ solver_parameters.html - [611] J. A. Grover et al., “Fast, Lifetime-Preserving Readout for High-Coherence Quantum Annealers,” PRX Quantum, vol. 1, no. 2, Art. no. 020314, 2020, doi: 10.1103/PRXQuantum.1.020314. arXiv:2006.10817. D
- [612] J. D. Whittaker et al., “A frequency and sensitivity tunable microresonator array for high-speed quantum processor readout,” arXiv:1509.05811, Sep. 2015. D
- [613] D-Wave Quantum Inc., “Per-QPU Solver Properties and Schedules — D-Wave Quantum Computing Products documentation.” [Online]. Available: https://docs.dwavequantum.com/
en/ Clatest/ quantum_research/ solver_properties_specific.html - [614] D-Wave Quantum Inc., “Operation and Timing — D-Wave Quantum Computing Products documentation.” [Online]. Available: https://docs.dwavequantum.com/
en/ Clatest/ quantum_research/ operation_timing.html - [615] Qilimanjaro Quantum Tech, “Towards a European full-stack coherent quantum annealer platform,” Mar. 2, 2021. [Online]. Available: https://qilimanjaro.tech/
towards-a-european-full-stack-coherent-quantum-annealer-platform/ C - [616] D-Wave Quantum Inc., “D‑Wave's Advantage2 Quantum Computer Now Generally Available,” D-Wave Support, May 14, 2025. [Online]. Available: https://support.dwavesys.com/
hc/ Cen-us/ articles/ 32105885880087-D-Wave-s-Advantage2-Quantum-Computer-Now-Generally-Available
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Erasure-adapted codes
Surface and block codes decoded with located-error flags; thresholds 4–10% and Λ ≈ 27 in simulation, 1.7–1.9× gains in hardware.
Verdict. Theory promises Λ ≈ 27 and 4–10% thresholds; hardware shows only 1.7–1.9× from erasure information and no erasure-decoded superconducting code. Confirm if a d=3→5 erasure-decoded memory reports Λ ≥ 3 by end-2027; demote otherwise.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An erasure-adapted code is a stabiliser code whose decoder takes, besides the syndrome, a per-qubit flag saying "this qubit was lost or left the code space here", with layout and schedule chosen for a channel in which located errors dominate. A located error removes the which question and leaves only the what, so the surface code fails only when erasures percolate — a 50% code-capacity threshold set by square-lattice bond percolation S[679], against 18.9(3)% for depolarising noise S[334] — and its distance against erasures is d rather than ⌈d/2⌉. Maximum-likelihood erasure decoding is linear-time peeling on a spanning forest S[680]; Union-Find extends it to Pauli errors in O(n α(n)) S[681]. The hardware turn came in 2022: 98% of ¹⁷¹Yb errors convertible, lifting the circuit-level surface-code threshold from 0.937% to 4.15% S[8], and dual-rail transmons, where at 1% erasure the code tolerates 0.51% Pauli error, 5.2× the standard figure S[334]; the first full loss-correction cycle had run on five trapped ions in 2020 D[682]. The flags belong to the Mid-circuit erasure check brief (layer 6); this brief covers what the code does with them.
Attributes (graph record; legend: a affinity natural↔fabricated; b time, deterministic/heralded entangling; c readout; d mobility; e control @ placement; f error structure; g manufacturing):
- a = 0.5 — carrier-agnostic; one decoder serves atoms and transmons.
- b = no time or entangling of its own.
- c = none — it consumes the check's flag.
- d = static.
- e = no control modality, no placement.
- f = erasure — located loss dominant, small Pauli residual.
- g = none — layout and software.
Rank 3 of 111; shared by the neutral-atom and superconducting families; it pairs a fabricated carrier with an erasure error structure.
Physics & limits
The gain has three parts, each taxed. Threshold: the converted fraction sets it. Wu's 4.15% assumes 98% conversion S[8]; measured fractions are 56(4)% of single-qubit and ≈33% of two-qubit errors on ¹⁷¹Yb D[141] and 38(6)% of Princeton's CZ error D[142], so the realised threshold sits between the Pauli and erasure limits; biased-erasure XZZX codes lift the ceiling to 8.2%, hybrid-fusion to 10.3% S[643]. Checks are not free: each exposes the qubit to T1, and erasure qubits win only when the check is short against the cycle S[683]; with false positives and negatives the threshold stays at least twice the Pauli value and the effective distance roughly doubled S[395]. Erasures spread through gates, and a missed erasure re-enters as leakage, the error the surface code handles worst S[684]. The idealised ceiling is Quantum Circuits' simulation: ancilla erasure 0.4%, data erasure 0.1%, dephasing 0.04/0.01/0.01% and perfect checks delayed to the end of each round give Λ ≈ 27 per distance step against Λ ≈ 14 for 0.1% depolarising noise S[84]; Google's hardware surface code sits at Λ = 2.14(2) D[1]. The bias behind such numbers is ≈40:1 — 6×10⁻³ erasure against 1.6×10⁻⁴ Pauli per operation S[334] — matching AWS's measured 42(1) D[85] fact. What moves the floor: conversion under two-qubit gates, the false-negative rate, check time, and decoders that use delayed loss information so no mid-circuit check is needed S[508].
Engineering state of the art
Best demonstrated, atoms: Harvard/MIT/QuEra's surface code on up to 448 atoms, 2.14(13)× below threshold in a four-round characterisation circuit, loss information plus machine-learning decoding giving 1.73(13)× over conventional decoding D[4]; Princeton's [[4,2,2]] block, whose logical decay slows 1.9(4)× with erasure flags in the decoder D[142]; Microsoft/Atom Computing's 24 logical qubits in 48 atoms with 1.8 lost atoms corrected per run D[149]. Superconductors: no erasure-decoded code has run on dual-rail hardware as of 3 Sep 2026; the largest erasure-encoded circuits are SUSTech's four dual-rail transmons, with a 93.9% three-logical-qubit GHZ state (Nature Physics version) D[406] fact and Quantum Circuits' 8-qubit Seeker, error-detecting only C[86] fact. Typical at scale: only the Harvard and Microsoft machines decode with loss flags above 100 atoms.
table
| Year | Figure | Who | Tag | Src |
|---|---|---|---|---|
| 2009 | 50% loss threshold (bond percolation) | Stace/Barrett/Doherty | S | [679] |
| 2022-01 | Threshold 0.937% → 4.15% at 98% conversion | Princeton/Yale | S | [8] |
| 2022-08 | Dual-rail: 0.51% Pauli tolerated at 1% erasure, 5.2× | AWS | S | [334] |
| 2023-02 | XZZX biased erasure 8.2%; hybrid-fusion 10.3% | Yale/Princeton | S | [643] |
| 2024-11 | 24 logical in 48 atoms; 1.8 lost atoms corrected per run | Microsoft/Atom | D | [149] |
| 2025-06 | [[4,2,2]] decay 1.9(4)× slower with erasure flags | Princeton | D | [142] |
| 2025-06 | 2.14(13)× below threshold; loss info + ML 1.73(13)× | Harvard/QuEra | D | [4] |
| 2026-08 | Λ ≈ 27 vs 14, structured dual-rail noise, perfect checks | QCI/D-Wave | S | [84] |
Dominant error term today: on atoms the unconverted two-qubit error, ≈62–67% of CZ error D[141], [142]; on dual-rail the ancilla's erasure per CZ, 0.400(4)%, and check dead time D[84] fact; on both, a false-negative tail nobody has counted over many rounds.
Manufacturing, materials & supply chain
Nothing is fabricated for the code; its burden lands on the hardware it selects. Dual-rail asks for two good transmons or two cavities per site — a yield-squared problem — plus an ancilla per cavity pair S[399], hence Quantum Circuits' hand-assembled 8 → 17 → 49 → 181 plan R[94] fact. Alkaline-earth(-like) atoms add no hardware but cost single-qubit fidelity in the metastable manifold, 99.12(4)% against 99.968(3)% in the ground state of JILA's device D[645]. The decoder is the code's only artefact: Union-Find on a Xilinx VCU129 decodes d=21 at 11.5 ns per round under 0.1% phenomenological noise D[685]; erasure input is native to Union-Find S[681] but no FPGA benchmark with erasure flags is published; Stim exposes HERALDED_ERASE P[397]. Unit cost: 2× physical qubits per site on dual-rail, against Quantum Circuits' claim of 10–20 physical per logical instead of ≈200 C[86]. Export control: the BIS rule of 2024-09-06 G[301] fact controls quantum computers (4A906: only when qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact), software "specially designed" for developing or producing controlled qubit and control devices (4D906) and the related technology (4E906); a decoder shipped as firmware for a controlled control system falls inside 4D906.
Control, readout & I/O burden
The code adds one bit per qubit per cycle to the syndrome stream and a decision: reset and re-entangle the erased qubit before the next round, or defer. On dual-rail that is feed-forward within ≈1 µs (0.50 µs gate, 0.38 µs check) D[84], [85]; on atoms a camera frame and a reload, ≈1 ms D[4]. Delayed-erasure decoding S[508] and superchecks D[4] remove the mid-circuit branch at the price of correlated decoding. Walls: at 10³ the wall is the hardware's; at 10⁴ the decoder must absorb ≈10⁴ flags plus syndromes per microsecond — 10 Gbit/s, within FPGA reach D[685] but untested with erasures; at 10⁶ dual-rail means 2×10⁶ transmons, and on atoms the frame budget of the Mid-circuit erasure check brief applies unchanged.
Role in the stack
Two architectures: superconducting dual-rail erasure (D-Wave/Quantum Circuits, AWS, SUSTech) and alkaline-earth(-like) neutral atoms (Atom Computing/Microsoft, Princeton, Caltech). The code requires the mid-circuit erasure check's flags, provides logical qubits to nothing yet registered downstream, and replaces the Pauli-decoded surface code. The price of switching is hardware, not software: 2× physical qubits and a check per cycle on dual-rail, the metastable fidelity tax on atoms, plus a decoder that weights erased edges to zero. It conflicts with nothing formally but competes with IBM's qLDPC memory for the same G4 budget Rfact. The atom and superconducting camps share one artefact, the decoder. A fabricated carrier with an erasure error structure is genuine on dual-rail; atoms bring erasure as a natural carrier. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: 2.8 µs on dual-rail (gate-limited, four 0.5 µs layers over the 0.40 µs check), 1.3 ms on atoms (transport); the code rides on the host code's d₂ and adds no term. Neighbouring slots: erasure-adapted qLDPC codes (no demonstration found), the cold-stage decoder, and, one column over, photonic fusion-based computation at 10.4% tolerated loss per fusion S[179], where Xanadu reports loss 24.1× above threshold in 2026 Rfact.
Evidence — how the numbers were measured
Headline numbers are logical decay rates versus hold time decoded with and without flags (Princeton) D[142], or detected-error ratios between distances in a four-round circuit (Harvard's 2.14(13)×) D[4]; simulated Λ comes from Stim-style circuit noise with an assumed bias S[84]. Not captured: post-selection — Princeton's teleportation fidelities, 0.771(9) → 0.802(8), are conditioned on trivial syndromes and a flag D[142]; four rounds are not a memory over 10⁵ rounds; the Λ ≈ 27 simulation assumes perfect checks, no false negatives, no check-induced dephasing S[84]; nobody reports survival beside Λ. Independent replications: Harvard/QuEra D[4], Microsoft/Atom D[149], Princeton D[142]; theory from AWS S[334], [683], [684], Yale S[395], [643], Duke S[392]. Conflicts: (i) the [[4,2,2]] gain is 1.9(4)× in arXiv v1 and v2 (2026-06-23) D[142] but 3.6× in the technology graph from the Nature Physics text D[142] fact; the published text is paywalled and 1.9(4)× is used. (ii) 98% conversion S[8] against 38–56% measured D[141], [142]. (iii) Λ ≈ 27 S[84] against Λ = 2.14(2) on the best Pauli-decoded hardware D[1] — a simulation-to-hardware gap.
Gu, Retzker and Kubica publish thresholds as surfaces, not single values S[684]. The 11.5 ns per decoding round is for phenomenological noise D[685]. Not published: an FPGA decoding benchmark with erasure flags; a Princeton or Harvard patent family on erasure conversion; the neutral-atom species of planqc and of Google; the cost or energy per logical qubit, from any actor; and the NSF award behind D-Wave's "$1.57 million in NSF funding for gate-model development" C[15].
Actors & economics
Who.
| Organisation | Role | Country | What it does with erasure-adapted codes | Evidence |
|---|---|---|---|---|
| Quantum Circuits (D-Wave unit) | developer | US | Dual-rail cavity qubits; Λ ≈ 27 simulation; 17-qubit system due 2026 | D[84] C[15] |
| AWS Center for Quantum Computing | developer | US | Dual-rail transmon theory and hardware; check-schedule optimisation | S[334], [683] D[85] |
| Yale University | research | US | Biased-erasure XZZX codes; imperfect-check theory; C2QA partner | S[395], [643] G[686] |
| Princeton University | research | US | ¹⁷¹Yb erasure conversion; first erasure-decoded logical qubit | S[8] D[142] |
| Harvard University | research | US | Loss-aware surface-code decoding on 448 atoms; delayed-erasure decoder | D[4] S[508] |
| QuEra Computing | developer | US | Libra 2028, >256 logical at 10⁻⁶; QBI Stage B | R[162] fact |
| Atom Computing | developer | US | ¹⁷¹Yb machines; loss correction with Microsoft's decoder; Magne | D[149] fact |
| Google Quantum AI | developer | US | Stim HERALDED_ERASE; Pauli-decoded baseline Λ = 2.14; atom track since 2026-03 | P[397] D[1] fact |
| Caltech | research | US | ⁸⁸Sr erasure conversion; erasure-code theory | D[143] S[684] |
Money.
- 2024-08-15 · Quantum Circuits · Series B close · >$60 M · ARCH, F-Prime, Sequoia, Hither Creek · ≈$84 M cumulative per trade press · closed fact
- 2025-11-04 · US DOE · NQISRC renewal, C2QA (Brookhaven/Yale) · $125 M of $625 M over up to five years · programme · awarded G[474], [686]
- 2025-11-06 · DARPA QBI Stage B · up to $15 M each · Atom Computing, QuEra among eleven; no dual-rail vendor · official G[65] fact
- 2026-01-07 · D-Wave · acquires Quantum Circuits · $550 M ($300 M stock + $250 M cash) · closed 2026-01-19/20 C[14] fact
- 2026-05-21 · D-Wave; Atom Computing · US DoC CHIPS letters of intent · $100 M each · LOI fact
- 2026-06-16 · Atom Computing · Series C · $100 M · Third Point · >$300 M cumulative · closed fact
- 2026-08-06 · D-Wave · Q2-2026 results · revenue $3.1 M, cash $546.2 M; $1.57 M NSF grant for gate-model work · reported C[15] fact
Market & supply chain. Nobody sells an erasure-adapted code; the decoders are open-source (Stim, PyMatching, Union-Find) P[397] and the FPGA implementations academic D[685], so the money is in the hardware overhead: two transmons or two cavities plus an ancilla per site, or a metastable manifold and a camera. Concentration risk is the dual-rail readout chain and refrigerators, BIS-listed G[301]; on atoms, the ¹⁷¹Yb/⁸⁸Sr laser set. G3 and G4 buy the full code; G2 and G1 pay today for erasure detection as post-selection (Seeker C[86], Caltech's excised Rydberg simulator D[143]); G5–G7 do not pay.
IP & standards. Amazon Technologies US 11,748,652 B1, heralded amplitude-damping decay for QEC (Kubica, Retzker; granted 2023-09-05) G[336] fact; Yale US 12,288,135, asymmetric-error-channel ancilla (granted 2025-04-29) G[408]; Quantum Circuits' cavity families sit with D-Wave. No Princeton or Harvard erasure patent surfaced in the searches run; no database count found. No standard; Stim's HERALDED_ERASE P[397] is the de-facto interface; D-Wave announced a forthcoming gate-model simulator for "error-aware programming" C[15].
Roadmaps & track record.
- D-Wave: promised 2026-01-07 · first dual-rail system in 2026 · not delivered as of 2026-09-03; restated 2026-08-06 as a 17-qubit system with logical error 2× below physical in 2026 C[14], [15].
- D-Wave: promised 2026-06-01 · 49 qubits / 20× (2027), 181 / 2,000× (2028), 10 logical (2030), 100 logical (2032), Λ = 10 · pending R[94] fact.
- QuEra: promised 2024-01 · 100 logical qubits in 2026 · missed; restated 2026-06-15 as Libra, >256 logical at 10⁻⁶ in 2028 R[162] fact.
- Atom Computing/Microsoft: promised 2025-07-17 · Magne, 50 logical qubits, delivery around the turn of 2026/27 · pending fact.
Credibility: Quantum Circuits/D-Wave publish the physics and miss the dates; Harvard/QuEra deliver papers on schedule, roadmaps late; Microsoft/Atom on schedule, silent on the code; AWS publishes and promises nothing; Princeton delivers each step of its 2022 proposal S[8], smaller than promised.
Strategic reading. If erasure-adapted codes reach Λ ≥ 5 on hardware, the winners own erasure-native qubits at scale — D-Wave's cavity line, AWS's transmon pairs, the ¹⁷¹Yb camp (Atom Computing, Google's atom track) — and the decoder becomes a commodity; the losers are Pauli-only roadmaps buying Λ with fidelity alone (Google's superconducting line, IBM's qLDPC) and rubidium vendors without a metastable manifold. Substitution runs both ways: delayed-erasure decoding S[508] and superchecks D[4] give atoms most of the gain without erasure-native qubits; qutrit erasure encodings would strip the 2× overhead from transmons. Bargaining power sits with platform vendors; decoder authors have none.
Outlook & open questions
Confirm within 12–24 months if: any group decodes a d=3 → 5 memory with erasure flags over ≥ 10 rounds and reports Λ ≥ 3 with survival; D-Wave's 17-qubit system shows logical error 2× below physical by mid-2027 C[15]; a dual-rail simulation with measured false negatives and check dephasing still returns Λ ≥ 10; atom conversion under two-qubit gates passes 70%. Demote if end-2027 arrives with erasure decoding worth < 2× on every platform. Best case by 2029: dual-rail memories at Λ ≈ 5–10 with 100–200 qubits and Yb machines running loss-aware codes by default. Worst case: a decoder option worth 1.7–1.9× while Pauli-decoded transmons reach Λ ≈ 3–4 without it.
Open questions: (1) what is Λ once false negatives accumulate as leakage over 10³ rounds? (2) does the 40:1 bias survive parallel gates on shared readout lines? (3) can the metastable fidelity tax on Yb be removed? (4) is an erasure-adapted qLDPC code with a fast decoder possible? Watch: D-Wave's 2026 delivery, AWS's next multi-qubit paper, Google/Kaufman's Yb results.
Erasure-aware decoding also works at a photonic interface between surface-code processors: with ideal local operations, the threshold for erased fusion outcomes reaches the 50% bond-percolation ceiling of the square lattice (fitted 49.40–50.60% at d = 11–19), equivalent to 18.35% photon loss without fusion boosting, and it falls roughly linearly with resource-state error and ever faster as local circuit noise nears its own threshold P[893]. The result is from simulation only.
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Rotated surface code (+ yoked variants)
Weight-4 CSS stabiliser code on a square lattice; the only code with below-threshold hardware data on three platforms, and the most expensive.
Verdict. The default code because it needs nothing but a static degree-4 lattice; at Λ ≈ 2 it costs 600–1,500 physical per logical. Demote if a qLDPC memory beats it on hardware before end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A CSS stabiliser code: weight-4 X and Z plaquettes on a square lattice, weight-2 on the boundary. The rotated layout — the one everybody builds — puts one logical qubit in d² data and d²−1 measure qubits: a distance-7 patch is 97 physical qubits. Errors show up as pairs of syndrome defects, which a decoder pairs across a three-dimensional matching graph (two space dimensions, d rounds) into a Pauli frame. Lineage: Kitaev's toric code (1997) S[649]; the planar memory and its threshold in Dennis, Kitaev, Landahl and Preskill (2002) S[650]; the rotated d²-qubit layout in Bombín and Martín-Delgado (2007) S[651]; lattice surgery in Horsman et al. (2011) S[652]; the engineering canon in Fowler et al. (2012) S[653]; yoking in Gidney et al. (2023) S[654].
Attributes from the technology graph (a affinity; b time; c readout; d mobility; e control @ placement; f error structure as the code sees it; g manufacturing): a = 0.5, carrier-agnostic — a layout, not a device, with b and c inherited from the host and e, g none of its own; d = static, patches moving only by lattice surgery; f = Pauli, the defining assumption and the defining weakness, since whatever is not an X/Z flip — leakage, loss, bias, erasure — is discarded information or unmodelled damage. Rank 7 of 111; shared by the superconducting, neutral-atom and spin families.
Physics & limits
The code turns a physical error rate p into a logical rate falling exponentially in d, while p sits below a threshold. Λ, the factor by which logical error drops per two distance steps, is the whole economics: at Λ = 2.14 a tenfold drop in logical error costs three factors of Λ (log 10 / log 2.14 ≈ 3.0), so d grows by about 6 — from d=7 that is ~3.5× the qubits, since a patch needs 2d²−1. The threshold is decoder- and noise-dependent: 0.937% under uniform circuit-level depolarising noise S[8], but 0.55% for Riverlane's unweighted hardware decoder against 0.7% for weighted matching under leakage D[238]. Every quoted Λ describes a decoder as much as a chip.
Three floors are intrinsic. Area and time: a logical qubit is 2d²−1 physical qubits and a logical operation costs d rounds, so from 7.72×10⁻⁴ at d=7 with Λ ≈ 2 D[2], reaching 10⁻⁶ needs d ≈ 25 and over 1,200 physical per logical unless p falls below 10⁻³; at p = 10⁻³ the teraquop footprint (for 10¹² reliable operations) is about 1,500 physical per logical plain, 800 with one-dimensional and 600 with two-dimensional yokes S[654], or about 650 plain with correlated matching S[655]. Non-Pauli errors: leakage produces syndromes matching cannot explain, and atom loss is tractable only if the decoder is told where it happened. Correlated bursts: Google sees events roughly hourly pinning a floor near 10⁻¹⁰ irrespective of d D[1]. What moves the floor is error-structure engineering — bias, erasure, leakage removal — exactly what this code discards; yokes move only the constant.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: distance-7 memory at 7.72×10⁻⁴ logical error per cycle on Google's 105-qubit Willow, with reinforcement-learning calibration inside the QEC loop D[2]. Typical at scale: nothing. No vendor sells a surface-code logical qubit; logical two-qubit gates exist only at d=3 D[43]; on atoms the code ran on 448 atoms for four rounds D[4].
table
| Year | Figure | Who | Tag | Src |
|---|---|---|---|---|
| 2023-02 | d=5 at 2.914(16)%/cycle vs d=3 average 3.028(23)% | D | [602] | |
| 2024-12 | Λ = 2.14 ± 0.02 (d=3→5→7); d=7 at 0.143(3)%/cycle; 2.4(3)× the best physical qubit; 10⁶ cycles at d=5 | Google (Willow) | D | [1] |
| 2025-11 | 448 atoms: 2.14(13)× over d=3→5 in four rounds; loss-aware ML decoding worth 1.73(13)× | Harvard/MIT/QuEra | D | [4] |
| 2025-12 | Local Clustering Decoder under 1 µs/round on FPGA to d=17; 4× qubit saving (d=33→17) under leakage | Riverlane | D | [238] |
| 2025-12 | 107-qubit device below threshold at d=7, Λ = 1.40(6) | USTC | D | [3] |
| 2026-07 | Logical CNOT between two d=3 patches, fidelity 0.643, no post-selection | USTC | D | [43] |
Dominant term: two-qubit gate error, about 40% of the comparable colour-code budget on the same chip D[41], then leakage and readout, then bursts no larger d removes D[1].
Manufacturing, materials & supply chain
The code has no fabrication of its own; it imposes one — a static degree-4 lattice, a measure qubit between every data pair, non-destructive mid-circuit readout on every ancilla, and uniformity, because all 2d²−1 qubits must work. That is a yield problem in d², and why Google patented variants tolerating dead qubits G[656]. Its real supply chain is the decoding chain: Riverlane's decoder takes about 6% of a Xilinx VU19P's logic at d=17 D[238], and that FPGA family is single-source (AMD), as is the GPU alternative (NVIDIA, 3.84 µs round trip over NVQLink fact). Cost per logical qubit is unpublished. Export exposure: the US BIS rule of 2024-09-06 fact controls refrigerators (3A904), and quantum computers (4A906) only when their qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact; a distance-5 patch, 49 qubits, is caught only at a C-NOT error of 10⁻⁴ or better.
Control, readout & I/O burden
Every cycle measures and resets every ancilla: on Willow, 48 measurement bits per 1.1 µs for a distance-7 patch, roughly 44 Mbit/s of syndrome per logical qubit D[1]. The decoder must consume that stream faster than it arrives or the backlog diverges — sub-microsecond per round in FPGA fabric D[238] against Google's 63 µs mean latency at d=5 in 2024 D[1]. At 10³ qubits the wall is per-qubit wiring; at 10⁴ it is syndrome bandwidth off the fridge, the case for cold-stage predecoding (a cryo-CMOS study claims 3,780× reduction under 0.56 mW at 4 K Sfact); at 10⁶ decoding is a datacentre-scale streaming problem sized by syndrome rate, not qubit count.
Role in the stack
Five architectures carry it: superconducting transmons, alkali neutral atoms, alkaline-earth(-like) erasure-native atoms, silicon/germanium quantum-dot spins and donor spins in silicon. It requires only a static nearest-neighbour lattice — the reason it is the default — hosts magic-state factories (cultivation reaches 0.9999(1) at 8% acceptance D[42]) and feeds FPGA and neural decoders D[238], [657]. It is replaced by, not composed with, the colour code (better gates, worse slope: Λ₃/₅ = 1.56 on the same chip D[41]), bivariate bicycle qLDPC codes (288 physical for 12 logical against roughly 3,000 surface-code qubits D[248]) and high-rate transversal codes on movable atoms. It conflicts with cat qubits (an unbiased code wastes the bias), dual-rail encodings (matching discards erasure flags) and destructive detection. Switching costs run both ways: leaving buys a 3–10× overhead cut and demands connectivity the hardware lacks; staying costs 600–1,500 physical per logical S[654]. It is the one genuinely platform-agnostic code-layer node, which is why a decoder company can exist. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 0.65 µs derived on the transmon lattice against the measured 1.1 µs cycle, readout and reset two-thirds of it rather than the 25–40 ns gates D[1]; 1.31 ms on atoms, set by transport. Neighbouring empty slots: a decoder inside the fridge, and cross-module patches — no code has run across two modules.
Evidence — how the numbers were measured
Λ is a fit of logical error per cycle against d, and three things make it soft. Decoder-conditioned: the same Sycamore data gives 3.028% under tensor-network decoding and 2.901% under AlphaQubit at d=3 D[602], [657]. Subset-conditioned: a d=7 patch adds worse qubits to the d=5 set. Duration-conditioned: four-round circuits D[4] never see the drift and burst physics a 10⁶-cycle run does D[1]. Not captured: leakage populations, bursts, reload survival bias, decoder failure in real time. Replicated independently — Google D[1], [2], USTC D[3], Harvard/MIT/QuEra D[4].
Conflicts. Λ per two distance steps: 2.14 ± 0.02 (Google, d=3→7) D[1] versus 1.40(6) (USTC) D[3] versus 2.14(13)× (atoms, four rounds, lost on reloading) D[4] — different noise, not different codes, and only Google's survives a million cycles. Threshold: 0.937% S[8] versus 0.55–0.7% under leakage D[238]; budget against the second.
Riverlane's Series C is $75 M in the 2024-08-06 release C[661] but "$85 million in 2024", with "$120 million+" cumulative, in the 2026-03-12 roadmap release C[658]. The yoked-code footprints (≈1,500 / ≈800 / ≈600 physical per logical at p = 10⁻³) come from a secondary rendering of arXiv:2312.04522 S[654]. Not published: the cost or energy per logical qubit, and Riverlane's revenue and contract values.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | Willow memory to d=7, the d=7 record, AlphaQubit, yoked-code theory | D[1], [2], [657] S[654] |
| IBM | developer | US | Ran heavy-hex surface-code variants on Falcon; roadmap leaves them for bivariate bicycle qLDPC on overhead grounds | D[248] fact |
| Riverlane | supplier | UK | Only pure-play QEC vendor; Local Clustering Decoder, sub-µs per round on FPGA | D[238] C[658] |
| Harvard/MIT + QuEra | research + developer | US | Surface code on 448 atoms with loss-aware ML decoding | D[4] fact |
| USTC, Zhejiang University | research | China | d=7 below threshold; logical CNOT at d=3; 125-qubit lattice surgery | D[3], [43], [44] |
| NVIDIA, Qblox | suppliers | US, NL | NVQLink and control stacks that close the decode loop in real time | fact C[659] |
Money. Nobody funds a code; these are deliverables denominated in surface-code units.
- 2024-05-01 · Riverlane · Horizon Europe EIC Transition grant (SkyTALE, with Qblox) · £2.1 M · awarded C[660]
- 2024-08-06 · Riverlane · Series C · $75 M · Planet First Partners lead, with ETF Partners, EDBI, Cambridge Innovation Capital, Amadeus · closed C[661]
- 2025-11-06 · DARPA · QBI Stage B · up to $15 M each, eleven teams; IBM the only transmon vendor, its plan qLDPC fact
- 2026-03-12 · Riverlane · roadmap release claims $120 M+ raised and an "$85 M" Series C · conflicts with the 2024 release C[658]
- 2026-06-02 · IBM · quantum commitment · >$10 B over five years · announced fact
Market & supply chain. The only sellable artefact here is the decoder and its integration; Riverlane is the sole pure-play, claiming over 20 partnerships with makers and national labs C[658]; NVIDIA commoditises the GPU path. Concentration risk is upstream (AMD/Xilinx, NVIDIA, a two-vendor refrigerator market); unit economics are unpublished beyond the 600–1,500 physical per logical every buyer pays S[654]. Only G3 and G4 pay for it.
IP & standards. Google LLC, US 12,518,194, "Surface codes with densely packed gauge operators" (granted 2026-01-06) G[656]; Riverlane Ltd, GB 2641501 A, "Quantum decoder" (published 2025-12-10) G[662]. The code is unpatentable prior art from 1997–2007 S[649], [651], so the fight is over decoders and layouts. No standard; the interfaces are open source — Stim, PyMatching, Deltakit P[397].
Roadmaps & track record.
- Google: promised 2023-02 · milestone 3, a "long-lived logical qubit" at 10⁻⁶ · not reached; best 7.72×10⁻⁴ at d=7 D[2] C[32].
- IBM: promised 2025-06-10 · Kookaburra, first qLDPC memory-plus-logic module, in 2026 · not delivered as of 2026-09-03 fact.
- Riverlane: promised 2026-03-12 · megaquop before end of decade, gigaquop early 2030s, teraquop from 2033 · pending C[658].
Credibility: Google delivered every milestone it announced, late but real, and alone has numbers surviving a million cycles; IBM executes but has left this code; Riverlane ships peer-reviewed hardware; the atom camp has the best overhead story and the weakest duration data fact.
Strategic reading. If the surface code stays the workhorse the winners are whoever makes physical qubits cheap and cycles fast — the superconducting camp — plus a decoder supply chain selling to every platform. The losers are anyone whose case assumed 10² physical per logical: at 600–1,500, a 200-logical-qubit machine is a 10⁵-qubit machine — IBM's stated reason for leaving D[248]. Substitution threats are dated: qLDPC at break-even on trapped ions, transversal codes on movable atoms, erasure-adapted codes. Bargaining power sits with platform vendors, except in real-time decoding, which most would rather buy than build.
Outlook & open questions
Confirm within 12–24 months if: any group reports Λ ≥ 3 over ≥10⁵ cycles; a logical two-qubit gate at d ≥ 5 reaches 99% without post-selection; a patch runs across two modules; yoked patches appear on hardware. Demote if a qLDPC memory beats a surface-code patch at equal qubit count before end-2027. Best case by 2029: a few hundred logical qubits at 10⁻⁶ on 10⁵–10⁶ physical qubits, decoding a commodity — what Starling and Libra assume. Worst case: Λ stays near 2, d ≈ 25 stays the price of 10⁻⁶, and the code survives only as a benchmark. Open questions: (1) does Λ hold above 10³ physical qubits, where crosstalk and drift scale differently? (2) can yoking run on hardware, or does outer-code decoding defeat the real-time budget? (3) how much of the 2026 record is calibration rather than physics, given that RL steering alone moved d=7 from 1.43×10⁻³ to 7.72×10⁻⁴? Watch: Google's next distance step and IBM's Kookaburra.
Lattice surgery split across two processors joined by a photonic link does not automatically keep distance d at the seam: a straight Bell-pair interface gives d + 1 on the merge outcome but only ⌊(d + 1)/2⌋ on the perpendicular observable, a zig-zag partition restores d, and a linear-cluster fusion seam gives 2d + 1 and d — distances that count interface faults only P[893].
References
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- [8] Y. Wu, S. Kolkowitz, S. Puri, and J. D. Thompson, “Erasure conversion for fault-tolerant quantum computing in alkaline earth Rydberg atom arrays,” Nat. Commun., vol. 13, Art. no. 4657, 2022, doi: 10.1038/s41467-022-32094-6. arXiv:2201.03540. S
- [32] Y. Chen and M. Devoret, “Our quantum hardware: the engine for verifiable quantum advantage,” Google Blog, Oct. 22, 2025. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ quantum-hardware-verifiable-advantage/ - [41] N. Lacroix et al., “Scaling and logic in the color code on a superconducting quantum processor,” Nature, vol. 645, no. 8081, pp. 614–619, May 2025, doi: 10.1038/s41586-025-09061-4. arXiv:2412.14256. D
- [42] E. Rosenfeld et al., “Magic state cultivation on a superconducting quantum processor,” arXiv:2512.13908, Dec. 2025. D
- [43] W. Lin et al., “Surface code logical operations on a superconducting quantum processor,” arXiv:2607.01473, Jul. 2026. D
- [44] Y. Wang et al., “A superconducting surface-code processor with lattice-surgery logical operations,” arXiv:2606.06598, Jun. 2026. D
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- [248] S. Bravyi et al., “High-threshold and low-overhead fault-tolerant quantum memory,” Nature, vol. 627, no. 8005, pp. 778–782, Mar. 2024, doi: 10.1038/s41586-024-07107-7. arXiv:2308.07915. D
- [397] quantumlib, “Gates supported by Stim,” GitHub. [Online]. Available: https://github.com/
quantumlib/ PStim/ blob/ main/ doc/ gates.md - [602] R. Acharya et al., “Suppressing quantum errors by scaling a surface code logical qubit,” Nature, vol. 614, pp. 676–681, Feb. 2023, doi: 10.1038/s41586-022-05434-1. D
- [649] A. Y. Kitaev, “Fault-tolerant quantum computation by anyons,” Annals of Physics, vol. 303, no. 1, pp. 2–30, 2003, doi: 10.1016/S0003-4916(02)00018-0. arXiv:quant-ph/9707021. S
- [650] E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, “Topological quantum memory,” Journal of Mathematical Physics, vol. 43, no. 9, pp. 4452–4505, 2002, doi: 10.1063/1.1499754. arXiv:quant-ph/0110143. S
- [651] H. Bombin and M. A. Martin-Delgado, “Optimal resources for topological two-dimensional stabilizer codes: Comparative study,” Phys. Rev. A, vol. 76, no. 1, Art. no. 012305, 2007, doi: 10.1103/PhysRevA.76.012305. arXiv:quant-ph/0703272. S
- [652] D. Horsman, A. G. Fowler, S. Devitt, and R. Van Meter, “Surface code quantum computing by lattice surgery,” New Journal of Physics, vol. 14, Art. no. 123011, Nov. 2011, doi: 10.1088/1367-2630/14/12/123011. arXiv:1111.4022. S
- [653] A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, “Surface codes: Towards practical large-scale quantum computation,” Phys. Rev. A, vol. 86, no. 3, Art. no. 032324, Sep. 2012, doi: 10.1103/PhysRevA.86.032324. arXiv:1208.0928. S
- [654] C. Gidney, M. Newman, P. Brooks, and C. Jones, “Yoked surface codes,” arXiv:2312.04522, Dec. 2023. S
- [655] C. Gidney and C. Jones, “New circuits and an open source decoder for the color code,” arXiv:2312.08813, Dec. 2023. S
- [656] Google LLC, “Surface codes with densely packed gauge operators,” U.S. Patent 12,518,194 B2, Jan. 6, 2026. [Online]. Available: https://patents.google.com/
patent/ Also https://patents.justia.com/US12518194B2/ en search?q=%22surface+code%22+quantum+error+correction&company=google . G - [657] J. Bausch et al., “Learning high-accuracy error decoding for quantum processors,” Nature, vol. 635, no. 8040, pp. 834–840, Nov. 2024, doi: 10.1038/s41586-024-08148-8. D
- [658] Riverlane, “Riverlane publishes QEC Technology Roadmap that can accelerate quantum computing's path to utility scale by 3–5 years,” Mar. 12, 2026. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-publishes-qec-technology-roadmap - [659] Qblox; Riverlane, “Qblox and Riverlane Demonstrate Integration Enabling Real-Time Quantum Error Correction,” PR Newswire, Mar. 17, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cqblox-and-riverlane-demonstrate-integration-enabling-real-time-quantum-error-correction-302716254.html - [660] Riverlane, “Riverlane awarded £2.1m by Horizon Europe to develop the next generation of its quantum error correction decoder,” May 1, 2024. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-awarded-2-1m-by-horizon-europe-to-develop-the-next-generation-of-its-quantum-error-correction-decoder - [661] Riverlane, “Riverlane raises $75 million to meet surging global demand for quantum error correction technology,” Aug. 6, 2024. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-raises-75-million-to-meet-surging-global-demand-for-quantum-error-correction-technology - [662] A. B. Ziad, A. Zalawadiya, B. Barber, and L. Skoric, “Quantum decoder,” Google Patents, Dec. 10, 2025. [Online]. Available: https://patents.google.com/
patent/ GGB2641501A/ en - [893] F. Burt et al., “Loss-tolerant distributed lattice surgery using fusion networks,” arXiv:2610.01923, Oct. 2026. P
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הטקסט בעברית נטען…
Non-local qLDPC codes (bivariate bicycle, 'gross')
Sparse high-rate stabiliser codes on a degree-6 torus that cut physical-per-logical overhead roughly tenfold against the surface code.
Verdict. Real overhead win, proven only at distance 3–5 on 32–40 physical qubits; without a delivered long-range-coupled module by end-2027 it stays a paper advantage.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes.
Identity & lineage
A bivariate bicycle (BB) code is a CSS stabiliser code whose two parity-check matrices are polynomials in a pair of commuting cyclic shifts, so the checks tile a torus: every check touches six qubits, every qubit sits in six checks. Four neighbours are near, two are long-range wraps — sparsity and high rate bought with non-planar connectivity. The lineage runs from MacKay's bicycle codes and Tillich–Zémor hypergraph products through Panteleev–Kalachev lifted products to Bravyi, Cross, Gambetta, Maslov, Rall and Yoder, Nature 627, 778 (2024-03-27), whose [[144,12,12]] "gross code" holds 12 logical in 288 physical qubits at a circuit-level threshold of 0.8%, against ≈3,000 physical for the same 12 logical in the surface code at p = 0.1% D[248].
Attributes (technology graph): carrier affinity 0.5 — a code layer, indifferent between natural and fabricated carriers but inheriting their errors. Characteristic time: none of its own; entangling neither deterministic nor heralded here. Readout: none of its own — it consumes fast non-destructive mid-circuit syndrome measurement from the carrier. Mobility: long-range, the defining requirement. Control modality: none, at no placement. Error structure as the code sees it: Pauli. Manufacturing: none.
Physics & limits
The code sets no energy scale, only an accounting rate: k/n and syndrome depth. The gross code encodes one twelfth of its data qubits, and its depth-7 syndrome circuit costs seven two-qubit layers plus a measurement per round — the surface code's depth, on a graph the hardware does not have D[248]. The floor is the threshold, 0.8% under circuit-level depolarising noise D[248]; below it, suppression per distance step beats the surface code because the block carries more logical qubits per unit of syndrome information, not because any qubit is better.
Two structural penalties are real. Distance is not free: distance 12 in 288 qubits needs the long-range wraps, and deleting them collapses the family to something a heavy-hex lattice can host, rate advantage gone. Decoding is harder: the Tanner graph has short cycles, so minimum-weight matching does not apply and plain belief propagation does not converge; the practical choices are BP with ordered-statistics post-processing (accurate, too slow) or Relay-BP S[48]. The worst failure mode is anything the code does not see as Pauli — leakage, ion or atom loss — a sparse code having fewer redundant checks to localise a hyper-edge. Erasure conversion and leakage removal move this floor further than better gates.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: IonQ's eight codes on one 40-ion chain (June 2026, revised 14 Sep 2026) — break-even within error bars in one code the paper does not identify, 3.95 ± 0.68 s against 3.84 ± 0.48 s physical; the best bivariate bicycle lifetime in its Table II is [[24,4,4]]'s 3.39 ± 0.47 s, and [[18,4,3]], 4 logical qubits in 18 data ions, reaches 2.48 ± 0.40 s D[109]. Typical at scale: nothing — no BB code has run on more than 40 physical qubits (IonQ's [[30,4,5]], ancillas included), and none has hosted a logical two-qubit gate.
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-03 | [[144,12,12]]: 288 physical for 12 logical, threshold 0.8%, ≈10× fewer qubits than surface code | IBM | D[248] |
| 2025-05 | First BB code on hardware: [[18,4,4]] on 32 transmons, 8.91 ± 0.17% per logical qubit per cycle — above physical error | Zhejiang University | D[74] |
| 2025-06 | Modular architecture: 288-qubit module + 90-qubit logical processing unit, 5,000 physical → 121 logical at p = 10⁻³ | IBM | S[496] |
| 2025-10 | Gross-code decoding on FPGA: 24 ns belief-propagation iteration, under 1 µs mean per cycle at p < 3×10⁻³ | IBM | S[48] |
| 2026-06 / 2026-09 | First qLDPC break-even, within error bars: 3.95 ± 0.68 s in one code vs 3.84 ± 0.48 s physical (3.3 ± 0.9 s in the June version, revised in the arXiv version of 14 Sep 2026; leakage post-selected), 9× better logical error than the transmon run | IonQ | D[109] |
Dominant error term: on the ion run, post-selected leakage and loss; on the transmon run, two-qubit error over a depth-7 round on couplers up to 6.5 mm D[74], [109].
Manufacturing, materials & supply chain
The code has no fab of its own, which is why it is a supply-chain question. On superconducting hardware it is unbuildable without multi-layer routing and long on-chip couplers: IBM's Loon, announced 2025-11-12 with six-way connections, longer c-couplers and low-loss routing layers, is the process vehicle, on 300 mm at Albany — no qubit count, coupler length or coupler fidelity published as of 3 Sep 2026 C[49]. Zhejiang's Kunlun processor shows the alternative: 84 air-bridged overlapping couplers, links to 6.5 mm, on a conventional process — good enough at 32 qubits, not at break-even D[74]. The single point of failure is a packaging and lithography capability held by two or three organisations: IBM/Albany, IQM's resonator hubs C[487], the Chinese academic fabs. The ion route has no fab constraint — connectivity comes from the motional bus, which is why IonQ got there first D[109]. Export-control exposure is indirect: the exposure sits in the hardware (US Export Administration Regulations ECCN 3A901; 3B904/3D901 for equipment and software), not the published mathematics.
Control, readout & I/O burden
Each round needs one mid-circuit measurement with reset per check qubit — 144 for the gross code — giving 144 syndrome bits per cycle per module, ~144 Mbit/s at a 1 µs cycle, an order of magnitude above a distance-7 surface patch for twelve times the logical qubits. The binding constraint is decode latency, not bandwidth: the decoder must return inside the cycle or the backlog grows without bound, and BP+OSD (belief propagation plus ordered-statistics decoding) cannot. IBM's FPGA Relay-BP shows it can be met in principle — 24 ns per iteration, under 1 µs mean per cycle — but it is a simulation-driven study, not a decode of live syndromes S[48]. At 10³ qubits the burden is unremarkable; at 10⁴ (≈35 modules, ~500 logical) the aggregate rate is ~5 Gbit/s and the decoder must be co-located, making NVQLink-class fabric (3.84 µs round trip) or a cold-stage ASIC a prerequisite P[324]. At 10⁶ nothing has been designed.
Role in the stack
Architectures: primary code on three — trapped ions in a linear Paul trap with individual laser addressing (IonQ), trapped ions with electronic (laser-free, microwave-driven) gates and chip control (IonQ/Oxford Ionics) and colour-centre spin network nodes (Photonic Inc.); alternate on three — the transmon lattice with tunable couplers (IBM, IQM, Zhejiang), continuous-variable photonic GKP and silicon/germanium quantum-dot spins (Diraq). It requires millimetre-scale long-range on-chip couplers, ion shuttling, the ion-chain motional bus, or tweezer transport of atoms; it provides the syndrome stream Relay-BP-class decoders consume; it replaces the surface code; it conflicts with nearest-neighbour-only connectivity — heavy-hex is insufficient without c-couplers. Price of switching: ≈10× in qubits gained; planarity, matching decoders and the body of lattice-surgery technique lost, the BB replacement (adapters, logical processing units) existing only on paper S[496]. It is one of the few code-layer nodes reaching superconducting, ion and photonic carriers at once, its value set by whichever delivers degree-6 connectivity first. Derived clock: it sets d₂ — seven gate layers — so the round on trapped ions with electronic gates is 1.52 ms, gate-set, against a measured ≈1–5 ms; the transmon lattice's round is 0.65 µs derived against the 1.1 µs QEC cycle D[1]. Neighbouring empty slot: a hardware logical CNOT between two BB blocks.
Evidence — how the numbers were measured
Break-even here is a memory comparison: logical lifetime against the best physical qubit on the same device, over repeated syndrome rounds and a destructive final readout. IonQ's 3.95 ± 0.68 s versus 3.84 ± 0.48 s (the physical baseline, 3·T2: 3.3 ± 0.9 s in the June version, revised in the arXiv version of 14 Sep 2026) overlaps within one standard deviation, and is stated with leakage post-selection D[109] — defensible for a memory claim, but it removes exactly the error class a sparse code handles worst, and the acceptance rate is not in the abstract. The protocol also misses what a code is for: no BB demonstration anywhere reports a logical two-qubit gate, so the overhead advantage is verified only for storage. Value conflict: the main report lists a Harvard/QuEra [[16,6,4]] run beside IonQ's; that is a high-rate block code, not a bivariate bicycle code, and no primary source was found — treat IonQ and Zhejiang as the only BB hardware results. IBM's July-2026 "70 logical qubits, 468 T gates" is an error-detecting* spacetime code and does not belong here D[46].
IonQ's 3.95 ± 0.68 s break-even lifetime follows the introduction of its arXiv version of 14 Sep 2026; that version's Table II lists no code at 3.95 s, and its best lifetime there is BB[[24,4,4]] at 3.39 ± 0.47 s. Not published: the code, round count and per-round logical error behind the 3.95 s figure, and a dated qLDPC patent-family count. Photonic Inc.'s "up to 20× fewer physical qubits" is a company claim with no stated logical error rate. IBM's blog "10× fewer qubits" rounds the Nature comparison of 288 against ≈3,000 physical qubits, a ratio that depends on the assumed physical error rate.
Actors & economics
Who.
| Organisation | Role | Country | What they do with it | Evidence |
|---|---|---|---|---|
| IBM | developer | US | Invented the gross code; Loon connectivity chip, Kookaburra module, Relay-BP decoder | D[248]S[48], [496] |
| IonQ | developer | US | Only qLDPC break-even claim on hardware — within error bars, in one code the paper does not identify; its [[18,4,3]] (4 logical in 18 ions) stays below the physical lifetime | D[109] |
| Zhejiang University | research | CN | First BB code on hardware, 32-qubit Kunlun processor | D[74] |
| Photonic Inc. | developer | CA | SHYPS qLDPC family, "up to 20x fewer physical qubits" | C[670]P[671] |
| IQM | developer | FI | Resonator hubs; qLDPC demonstrators promised 2027-28 | C[487] |
| DARPA | funder | US | QBI Stage B funds IBM, IonQ, Photonic Inc. and eight others | G[65]fact |
Money.
- 2025-11-06 · DARPA · QBI Stage B, eleven teams · up to $15 M each (USD) · announced G[65]fact
- 2026-05-12 · Photonic Inc. · final close · $200 M at $2 B (USD) · Microsoft among returning investors · $350 M total · closed P[186]fact
- 2026-05-21 · IBM/Anderon · CHIPS letter of intent · $1 B + $1 B IBM cash (USD) · Dept of Commerce · LOI G[300]fact
- 2026-06-02 · IBM · five-year quantum commitment · >$10 B (USD) · announced C[57]fact
- 2026-07-31 · IonQ · SkyWater, captive ion-trap fab · ~$1.8 B (USD) · closed C[19]fact
Market & supply chain. Nobody sells qLDPC. What sells is the connectivity that makes it usable — multi-layer superconducting interconnect (IBM at Albany, IQM's resonator hubs), ion-trap chips (IonQ owns SkyWater C[19]) — and the decoding that makes it affordable (IBM in-house, NVIDIA's fabric P[324]). Concentration risk is extreme: one organisation holds both the code and the only connectivity vehicle built for it. Unit economics are the case, ~24 physical per logical against ~1,000 for a distance-25 surface patch D[1], [248]. Only G3 and G4 pay for it.
IP & standards. No bivariate bicycle patent family appears in the Justia index under that phrase as of 2026-09-03 — IBM published rather than fenced P[672]. Enforceable IP sits one layer down: IBM US 12,517,856 (granted 2026-01-06) and US 12,587,192 on resonator chains with tunable inductive couplers (granted 2026-03-24) G[498]fact. Decoder IP is filed by others: KAIST US 12,346,774 (2025-07-01), Princeton US 11,941,489 (2024-03-26), US 2026/0172053 on qLDPC decoders (2026-06-18) G[672]. Stim, PyMatching and BP+OSD carry the field; no standard exists.
Roadmaps & track record. IBM: Kookaburra, qLDPC memory plus logical processing unit (promised 2025-06-10 · for 2026 · not delivered as of 2026-09-03); Cockatoo modules (2025-06-10 · 2027 · pending); Starling, 200 logical and 10^8 gates (2025-06-10 · 2029 · pending) R[72], [481]. The 2022-05-10 roadmap had promised Kookaburra as a 1,386-qubit processor for 2025 C[313]fact; IBM has shipped every published component of the stack except the code itself, so 2026 is optimistic and 2027 plausible. IQM: qLDPC demonstrators (2026-01-05 · 2027-28 · pending) C[487]. Photonic Inc.: SHYPS announced 2025-02-11, peer-reviewed 2026-08, still no hardware C[670]P[671].
Strategic reading. If BB codes work at scale, IBM wins the architecture argument it has made since 2024 and every surface-code roadmap absorbs a 10× overhead disadvantage or switches. Ions and photonic-linked platforms win incidentally; the loser is any platform whose only lever is planar lithography. Bargaining power sits with whoever controls high-degree interconnect, not the code's authors.
Outlook & open questions
Confirm within 12–24 months if IBM demonstrates a gross-code memory below break-even with real-time decoding (Kookaburra, promised 2026), if any group performs a logical two-qubit gate between BB blocks, or if a BB result appears without leakage post-selection. Demote if Kookaburra slips past end-2027, or if Loon's c-coupler fidelity when published is poor enough to eat the 10× rate advantage. Best case by 2029: Starling-class machines, 200 logical qubits at ≈24–40 physical each, factoring estimates falling to the 10⁵-qubit range S[7], [29]. Worst case: a 20-qubit laboratory curiosity, connectivity costing more fidelity than the rate saves.
Open questions: (1) what two-qubit fidelity does a millimetre-scale coupler cost, and does it exceed the rate advantage? (2) can Relay-BP hold its latency on live syndromes? (3) do BB logical gates via adapters beat lattice surgery once the logical processing unit is counted? (4) how does the threshold move under leakage and loss rather than depolarising noise? (5) does anyone outside IBM adopt this family? Watch the Loon fidelity disclosure and IQM's 2027 demonstrator.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [7] C. Gidney, “How to factor 2048 bit RSA integers with less than a million noisy qubits,” arXiv:2505.15917, May 2025. S
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [29] P. Webster et al., “The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes,” arXiv:2602.11457, Feb. 2026. S
- [46] S. Martiel et al., “Sampling hard circuits with verifiably high fidelity,” arXiv:2607.25941, Jul. 2026. D
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. S
- [49] IBM, “IBM Delivers New Quantum Processors, Software, and Algorithm Breakthroughs on Path to Advantage and Fault Tolerance,” Nov. 12, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance C - [57] IBM Quantum, “Why IBM is investing $10 billion into quantum computing,” Jun. 2, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ 10-billion-investment-faq - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [72] IBM, “Quantum Roadmap.” [Online]. Available: https://www.ibm.com/
roadmaps/ Rquantum/ - [74] K. Wang et al., “Demonstration of low-overhead quantum error correction codes,” Nat. Phys., 2026, doi: 10.1038/s41567-025-03157-4. arXiv:2505.09684. D
- [109] E. Tham et al., “Breakeven demonstration of quantum low-density parity-check codes,” arXiv:2606.06455, Jun. 2026. D
- [186] M. Abdel-Kareem, “Photonic Inc. Reaches $2B Valuation with $200M Final Close,” Quantum Computing Report, May 12, 2026. [Online]. Available: https://quantumcomputingreport.com/
photonic-inc-reaches-2b-valuation-with-200m-final-close/ P - [248] S. Bravyi et al., “High-threshold and low-overhead fault-tolerant quantum memory,” Nature, vol. 627, no. 8005, pp. 778–782, Mar. 2024, doi: 10.1038/s41586-024-07107-7. arXiv:2308.07915. D
- [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [313] J. Gambetta, “Expanding the IBM Quantum roadmap to anticipate the future of quantum-centric supercomputing,” IBM Quantum Blog, May 10, 2022. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ ibm-quantum-roadmap-2025 - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Pnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [481] R. Mandelbaum et al., “How IBM will build the world's first large-scale, fault-tolerant quantum computer,” IBM Quantum Computing Blog, Jun. 10, 2025. [Online]. Available: https://www.ibm.com/
quantum/ Rblog/ large-scale-ftqc - [487] F. Vigneau, “IQM Constellation: A New Quantum Processor Architecture for Scalable Error Correction,” IQM Quantum Computers, Sep. 30, 2025. [Online]. Available: https://iqm.tech/
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- [498] Justia Patents, “Patent search: ‘long-range coupler’ qubit (results as of Sep. 3, 2026).” [Online]. Available: https://patents.justia.com/
search?q=%22long-range+coupler%22+qubit Also https://patents.google.com/patent/ . Also https://patents.google.com/US12517856B2/ en patent/ . GUS12587192B2/ en - [670] Photonic Inc., “Photonic accelerates the timeline to useful quantum computing with breakthrough results in error correction,” Feb. 11, 2025. [Online]. Available: https://photonic.com/
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search?q=%22parity+check%22+quantum+error+correction+code Also https://patents.google.com/patent/ . PUS12346774B2/ en
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High-rate concatenated codes with transversal gates
Many logical qubits per block (iceberg, tesseract, concatenated [[4,2,2]]), Clifford gates transversal, paid for with all-to-all connectivity and post-selection.
Verdict. The reason ions and atoms quote 48–96 logical qubits while superconducting quotes 1–2; holds only at distance 2–4 and only where acceptance stays above ~50%.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Block codes whose rate k/n is a large fraction of unity and whose logical Cliffords run transversally — depth-one layers of two-local physical gates — instead of d rounds of lattice surgery. Four members define the node. The iceberg code [[k+2,k,2]] detects any single-qubit error (Quantinuum: Self, Benedetti, Amaro; Nature Physics 20, 219, 2024-01-05) D[673]. Two-level concatenation gives [[(k₁+2)(k₂+2), k₁k₂, 4]]; [[80,48,4]] (k₁=6, k₂=8) is the largest cycle executed anywhere D[105]. The tesseract colour code [[16,6,4]] is a doubly-even self-dual 4D CSS code from the [16,5,8] Reed–Muller code (subsystem variant [[16,4,2,4]]), its logical Clifford group depth-one D[674]. Goto's many-hypercube codes concatenate [[4,2,2]] blocks to ~30% rate S[675].
Attributes: no carrier of its own (affinity 0.0), it inherits the platform's; no characteristic time and no entangling determinism here; no readout of its own; mobility by physical transport of the carriers, which supplies the required all-to-all; no control modality, placed nowhere; error structure as the code sees it, depolarising Pauli noise; no manufacturing.
Physics & limits
[[80,48,4]] costs 1.67 physical qubits per logical at distance 4 D[105], the tesseract 2.67 D[674]; a teraquop surface code (sized for 10¹² reliable operations) costs 650 under 0.1% noise S[655], IBM's [[144,12,12]] 24 at distance 12 D[248]. The comparison is not like-for-like, and that is the limitation: distance 4 corrects one error, suppression goes roughly as p², and there is no Λ-style exponential handle. Distance 2 corrects nothing — it detects, and detection means discarding.
Hence acceptance: the [[80,48,4]] cycle accepted 0.62(2) of shots after post-selecting uncorrectable errors D[105], and the 64-logical XY-model simulation accepted 3.2% at algorithmic depth D[97]. Acceptance falls exponentially in circuit volume, so a claim here that omits it is unreadable.
Transversality is not universality (Eastin–Knill): magic states come from outside the block — [[6,2,2]] at 7×10⁻⁵ on ions D[107], 5-to-1 colour-code distillation on atoms D[147]. Transversal CNOT correlates errors across blocks, so decoding must be block-wide; algorithmic fault tolerance is the compensating theory, a constant number of syndrome rounds per logical gate rather than d S[152]. Ion leakage at 1.1×10⁻⁵ per Clifford D[97] and atom loss are not Pauli errors, so loss-aware decoding is a precondition.
Engineering state of the art
Best demonstrated as of 3 Sep 2026: 48 error-corrected logical qubits in one [[80,48,4]] block on a 98-qubit machine, logical gate infidelity (1.0–1.2)×10⁻⁴ against ~8×10⁻⁴ bare physical two-qubit error D[97], [105]. Typical at scale is thinner — that platform's 94 "logical" qubits are distance-2 iceberg, detection only D[105].
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-01 | Iceberg [[k+2,k,2]]: 8 logical qubits, 256 layers, logical quantum volume 2⁸ | Quantinuum | D[673] |
| 2024-09 | Tesseract [[16,6,4]]: graph states on 12 logical qubits, 5 correction rounds | Microsoft + Quantinuum | D[667] |
| 2025-11 | [[16,6,4]] on 448 atoms: 96 logical qubits active, hundreds of teleportations | Harvard/MIT/QuEra | D[4] |
| 2026-02 | [[80,48,4]]: 48 corrected logical qubits, cycle infidelity ≤4×10⁻⁵, acceptance 0.62(2) | Quantinuum Helios | D[105] |
| 2026-06 | Carbon [[12,2,4]] + tesseract: 11×–800× logical-error improvement | Microsoft + Quantinuum | D[667] |
The dominant budget term is the residual weight-2 error at distance 4 plus the discarded fraction: at 62% acceptance per cycle, a hundred-cycle circuit is out of reach.
Manufacturing, materials & supply chain
No fabrication of its own; the dependency is the connectivity hardware. On ions that is the QCCD trap — Helios runs 1,228 electrodes and at least seven laser wavelengths, and Sol (2027) moves to a Honeywell-fabricated 2D grid trap D[97]R[118]. On atoms it is AOD/SLM tweezer optics and the laser chain D[4]. Single points of failure: ion-trap chip fabrication (Honeywell in-house; IonQ bought SkyWater's foundry, ~$1.8 B, closed 2026-07-31 fact), acousto-optic deflectors, high-power lasers. Export control attaches to the machines, not the mathematics: US EAR quantum-computer controls and EU dual-use equivalents cover traps and lasers; the codes are published and ship as software.
Control, readout & I/O burden
The burden is decoding, not wiring. Syndrome extraction is shallow, but each transversal gate correlates errors across the block, so the decoder handles block-wide syndromes and, on atoms, loss flags, inside the reaction time. Not yet binding: ion cycles run 1–5 ms and atom cycles ~1–4.5 ms D[97]D[4] against decoders at tens of microseconds. Pinnacle instead assumes a 1 µs cycle and 10 µs reaction time S[29] — superconducting or photonic numbers, where real-time correlated decoding becomes the wall. At 10³ physical qubits one [[80,48,4]] block plus routing fits; at 10⁴ the constraint is all-to-all between blocks; at 10⁶ the family does not close without long-range couplers or bounded-degree qLDPC.
Role in the stack
Four architectures: primary on trapped-ion QCCD (Quantinuum) and alkali neutral atoms (Harvard/MIT, QuEra, Pasqal, Infleqtion, Google); alternate on ions in a linear Paul trap with laser gates (AQT, Quantum Art, Innsbruck) and ions with electronic (laser-free, microwave-driven) gates and chip control (IonQ/Oxford Ionics, eleQtron). It requires transport-supplied connectivity — AOD tweezer transport in a zoned architecture, ion shuttling through QCCD junctions and grid traps, or a single chain's motional bus — and provides for correlated, loss-aware decoding. It replaces the surface code at an explicit price: the surface code needs only nearest-neighbour coupling and has a mature ~1% threshold with exponential distance scaling, while this family needs all-to-all and buys width instead of depth, and it conflicts with nearest-neighbour connectivity outright.
Across families: this node explains the largest divergence in the 2026 fault-tolerance table — 48 and 96 logical qubits on ions and atoms against 1–2 on superconducting — a connectivity fact, not a qubit-quality fact. It adds no clock of its own; it sets the QEC cycles per logical layer, ≈1 with transversal gates plus correlated decoding versus ≈d for lattice surgery S[152]. Derived clock (= sum of the syndrome round: gate layers + transport + readout + reset): 9.66 ms on the ion QCCD architecture, transport-set, against the ~55 ms Helios full-width layer, and 1.31 ms on the alkali atom architecture against a measured ~1–4.5 ms round. Empty slots nearby: no high-rate transversal code on a nearest-neighbour platform, no member above distance 4, no magic-state factory inside a high-rate block.
Evidence — how the numbers were measured
Headline numbers come from repeated logical preparation and measurement in both bases, post-selected on detected-but-uncorrectable events. Two cautions: the Helios ≤4×10⁻⁵ cycle figure is a confidence upper bound from zero logical errors in 5,000 shots per basis, not a measured rate D[105]; and no number is interpretable without its acceptance D[105]D[97]. Leakage and loss sit outside the Pauli model — IonQ's break-even, within error bars in one code the paper does not identify (3.95 ± 0.68 s against 3.84 ± 0.48 s physical, while its [[18,4,3]] memory reaches 2.48 ± 0.40 s), needed leakage post-selection D[109]. Nothing here reports Λ-style distance scaling. Replication is good: the tesseract has run on two unrelated platforms D[667]D[4].
Conflicts. The tesseract is [[16,6,4]], not [[16,4,4]] — the Error Correction Zoo entry and the arXiv abstract agree D[674]D[667]. "48 corrected" and "94 detected" on Helios are different codes at different distances, routinely conflated D[105]. Iceberg's sub-100,000-qubit RSA-2048 claim assumes p=10⁻³ with 1 µs cycles S[29], not comparable to Gidney's <1 M S[7].
Not published: Iceberg Quantum's headquarters — trade press gives a Berlin base with a US presence, the founding institution is the University of Sydney, and the company site names no location P[677]C[676]; whether the Oxford Ionics–Iceberg Quantum partnership continues under IonQ — as of 2026-09-30 Iceberg Quantum lists PsiQuantum and Diraq as partners and names neither Oxford Ionics nor IonQ C[676]; the acceptance of the Harvard [[16,6,4]] 96-logical-qubit runs; and a dated patent-family count for this code family. Quantinuum's Q2-2026 claim of "near five-nines logical fidelity with a novel code family" has no public paper as of 2026-09-03. Goto's many-hypercube codes have no hardware demonstration; their 30% rate (64 logical in 216 physical qubits) is simulation only S[675].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Quantinuum | developer | US/UK | Introduced the iceberg code; ran [[80,48,4]] on Helios | D[105]D[673] |
| Microsoft Quantum | developer / user | US | Co-authored the tesseract demonstrations on Quantinuum hardware | D[667] |
| Harvard/MIT (Lukin) | research | US | [[16,6,4]] with 96 logical qubits on 448 atoms | D[4] |
| QuEra | developer | US | Commercialises that architecture; Libra 2028 targets >256 logical | Rfact |
| IonQ (incl. Oxford Ionics) | developer | US/UK | Eight codes on 40 ions (nine in the June version), break-even within error bars in one unidentified code ([[18,4,3]] stays below the physical lifetime); Oxford Ionics and Iceberg Quantum partnered on a fault-tolerant architecture with Iceberg's qLDPC codes (2025-07, within QBI Stage A) | D[109]Cfact |
| Iceberg Quantum | supplier (architecture) | AU/DE/US | Only pure-play: licenses high-rate/qLDPC architectures (Pinnacle) | S[29]P[677] |
| DARPA | funder | US | QBI Stage B funds Quantinuum, IonQ, QuEra, Atom Computing | fact |
| IBM | competitor | US | Bivariate bicycle qLDPC is the substitution threat | D[248] |
Money.
- 2025-03-24 · Iceberg Quantum · pre-seed · $2 M · Blackbird lead, LocalGlobe · closed P[678]
- 2025-09-04 · Quantinuum · equity · $600 M at $10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed fact
- 2025-09-17 · IonQ · M&A, Oxford Ionics · $1.075 B · closed fact
- 2025-11-06 · DARPA · QBI Stage B, up to $15 M each, eleven performers · announced fact
- 2026-02-13 · Iceberg Quantum · seed · $6 M · LocalGlobe lead, Blackbird, DCVC · cumulative ~$8 M · closed P[677]
- 2026-06-03 · Quantinuum · IPO · $1.68 B gross, Nasdaq QNT; Q2-2026 revenue $8.0 M · closed fact
- 2026-06-16 · Atom Computing · $100 M Series C + $100 M DoC CHIPS LOI · >$300 M · closed + LOI fact
- 2026-07-31 · IonQ · M&A, SkyWater Technology · ~$1.8 B · closed fact
Market & supply chain. Nobody sells a code. Value accrues to machine vendors that can quote logical-qubit counts (Quantinuum, QuEra, Atom/Microsoft), to one architecture licensor (Iceberg Quantum C[676]), and to the decoder layer (Riverlane, NVIDIA's NVQLink transport fact). Concentration risk is extreme: the experimental record rests on four groups — Quantinuum with Microsoft, Harvard/MIT with QuEra, Infleqtion, Innsbruck — and two hardware families, and one group authored both the code and the machine. Unit economics are the rate — 1.67 physical per logical at d=4 D[105] against 650 for a teraquop surface code S[655]. Goals paid for: G3 primarily, G2 (bare iceberg as a cheap detection layer D[673]), G7 where a machine is sold in logical qubits, G4 only if concatenation beyond d=4 survives leakage.
IP & standards. The iceberg code is published (Nature Physics 2024) D[673] and the tesseract catalogued in the open Error Correction Zoo P[674]; Microsoft and Quantinuum publish jointly rather than cross-licensing visibly D[667]. Pinnacle is a preprint with no disclosed patent position S[29]. No dated patent count exists for this code family — the PatSnap figures cited are device-class Pfact. Tooling is open; no standards body governs code choice.
Roadmaps & track record. Quantinuum (promised 2024-09 · Sol 2027 ~100 logical, Apollo 2029 · Helios on schedule 2025-11, [[80,48,4]] delivered 2026-02) Rfact — credible; code results ran ahead of the hardware. QuEra/Harvard (promised 2024-01 · 100 logical in 2026 · slipped to Libra 2028) Rfact — the 96 logical qubits were physics, not product. IonQ (promised 2025-06 · 25–50 physical per logical by 2030) Rfact — needs high-rate codes; its 2020 roadmap missed 2026 by ~40×. Iceberg Quantum (promised 2026-02 · partners at utility scale in 3–5 years) P[677] — seed-stage, no hardware.
Strategic reading. Winners: all-to-all platforms and anyone selling logical-qubit counts. Losers: 2D-local platforms, which must buy long-range couplers to compete on rate. The substitution threat is near — bounded-degree qLDPC gets most of the rate and real distance scaling without all-to-all D[248]; if IBM's gross-code module works in 2026–27, this family retreats to cheap distance-2/4 detection. Bargaining power sits with hardware vendors; a code-architecture supplier has none unless its IP proves essential.
Outlook & open questions
Confirm within 12–24 months if: a distance-6 or -8 member of the concatenated iceberg family runs with acceptance above 0.5 (Sol, 2027); a high-rate block is sustained over ≥50 QEC cycles without post-selection; or a partner names Pinnacle in a published roadmap by end-2027. Demote if 2027 machines still quote logical counts only at single-digit-percent acceptance at depth, or if IBM's gross-code module matches the rate at distance 12 on degree-≤7 connectivity. Best case by 2029: Apollo- and Libra-class machines run hundreds of logical qubits at constant syndrome rounds per logical gate S[29]S[7]. Worst case: the family stays a detection layer and bounded-degree qLDPC takes the fault-tolerant road.
Open questions: (1) does concatenation to d≥6 keep the rate advantage once leakage and loss are modelled honestly? (2) can a magic-state factory live inside a high-rate block? (3) what is the true acceptance scaling with circuit volume? (4) can block-wide loss-aware decoders keep up at 1 µs cycles? (5) is any nearest-neighbour route cheaper than long-range couplers? Watch Sol's first logical results, Quantinuum's unpublished "near five-nines" code-family claim, IBM Kookaburra, and the first partner adoption of Pinnacle.
References
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- [7] C. Gidney, “How to factor 2048 bit RSA integers with less than a million noisy qubits,” arXiv:2505.15917, May 2025. S
- [29] P. Webster et al., “The Pinnacle Architecture: Reducing the cost of breaking RSA-2048 to 100 000 physical qubits using quantum LDPC codes,” arXiv:2602.11457, Feb. 2026. S
- [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [105] S. Dasu et al., “Computing with many encoded logical qubits beyond break-even,” arXiv:2602.22211, Feb. 2026. D
- [107] S. Dasu et al., “Breaking even with magic: demonstration of a high-fidelity logical non-Clifford gate,” arXiv:2506.14688, Jun. 2025. D
- [109] E. Tham et al., “Breakeven demonstration of quantum low-density parity-check codes,” arXiv:2606.06455, Jun. 2026. D
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off-the-wire/ Piceberg-quantum-launches-with-2m-and-psiquantum-partnership/
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Magic-state factory (cultivation / distillation / code switching)
The subsystem that manufactures non-Clifford resource states so a code with transversal Cliffords can run universal circuits.
Verdict. Three routes are demonstrated on three carriers, but every headline number is a post-selected stand-alone state; no factory has yet fed a real algorithm.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A magic-state factory manufactures the non-Clifford resource states — |T⟩, |H⟩, |CCZ⟩ (controlled-controlled-Z) — that gate teleportation injects to supply the rotation a host code cannot perform transversally. Eastin–Knill forbids a transversal universal gate set on any code with distance, so universality must be bought with spacetime volume, and the factory is where that purchase is made. Bravyi and Kitaev showed in 2004–05 that Cliffords plus noisy ancillas give universality, and that ancillas polarised beyond roughly 65% along a magic direction purify asymptotically S[689]. Three families exist: distillation, code switching, and cultivation — grow and verify one state in place (Gidney, Shutty, Jones, 2024-09) S[690].
Attributes. a — carrier affinity 0.5: a code-layer construct inheriting whatever carrier hosts it. b: no characteristic time of its own, entangling not applicable; it runs at the host's cycle. c — readout: none of its own, it consumes the host's mid-circuit measurement. d — mobility: static, a fixed tile region. e — control: no modality, no placement — compiled, not wired. f — error structure as the code sees it: Pauli. g — manufacturing: none.
Physics & limits
The factory converts fidelity into volume at a rate set by the protocol's suppression exponent. Fifteen-to-one distillation on the quantum Reed–Muller code suppresses input error cubically, so 10⁻⁹ from a 10⁻³ injected state needs two concatenated levels and the footprint that dominated the field's resource estimates. Cultivation changes the price rather than the exponent: a |T⟩ is grown in a small patch, checked fault-tolerantly, then escaped to a large one, reaching 2×10⁻⁹ under 10⁻³ uniform depolarising circuit noise and 4×10⁻¹¹ at 5×10⁻⁴, with about the gate count of a lattice-surgery CNOT of equal reliability and an order of magnitude fewer qubit-rounds than distillation S[690].
Two quantities set the floor. The host's physical error rate fixes achievable output error; the acceptance rate fixes throughput and has no analogue in code memory. All three routes are heralded, so a factory is a yield problem: Google retained 8% of attempts D[42], the [[6,2,2]] route discarded 14.8% D[107], code switching succeeded 82.58% of the time D[666]. The dangerous failure is the undetected one — a coherent logical fault entering the algorithm where no later correction helps — so required output error is roughly the inverse T-count: IBM's 10⁸-gate Starling target implies ~10⁻⁹ per state, exactly cultivation's theoretical figure. Erasure conversion, noise bias or faster cycles move the floor; a code with a transversal non-Clifford gate would delete the node.
Engineering state of the art
Best demonstrated is Google's cultivation run: 0.9999(1) fidelity at 8% retention, 40× error reduction, including code-switching into a surface code and a purpose-built fault-tolerant protocol to bound the fidelity D[42]. Typical at scale is nothing — as of 3 September 2026 no factory has run inside an algorithm anywhere, and every result is stand-alone and post-selected. Demonstrated (10⁻⁴) sits five orders above required (10⁻⁹), and acceptance looks harder to close than fidelity.
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2005 | Purification threshold ≈65% polarisation along a magic direction | Bravyi, Kitaev | S[689] |
| 2025-06-17 | Magic-state infidelity 7×10⁻⁵ at 14.8% discard; logical controlled-Hadamard ≤2.3×10⁻⁴, [[6,2,2]] on 8 qubits | Quantinuum | D[107] |
| 2025-07-14 | First logical-level 5-to-1 distillation, d=3 and d=5 colour codes, neutral atoms | QuEra, Harvard, MIT | D[147] |
| 2025-10-15 | Code switching [[15,1,3]]→[[7,1,3]]: ≤5.1(2.7)×10⁻⁴ at 82.58% success | Quantinuum | D[666] |
| 2025-12-15 | Cultivation on a superconducting processor: 0.9999(1), 8% acceptance, 40× | Google Quantum AI | D[42] |
The dominant budget term is the escape step, where the state enters a large patch and loses post-selection; below it sit host two-qubit errors, mean 1.2×10⁻³ on the leading transmon system C[32].
Manufacturing, materials & supply chain
Nothing is fabricated: the bill of materials is host-code patches, mid-circuit measurement and classical compute, and the unit of cost is qubit-rounds. An attempt escaping to distance 15 implies a working region of order 10³ physical qubits per concurrent attempt, against a teraquop (10¹² reliable operations) memory footprint of 650 physical per logical at 0.1% noise S[655] — a handful of logical qubits per factory, not the hundreds implied by two-level distillation. The supply chain is classical: real-time decoders (Riverlane, NVIDIA, Zurich Instruments), the accept/reject interconnect, and the tooling that certifies output; the verification stack is the single point of failure. Export-control exposure is inherited — controls attach to the host machine under the 2024 US quantum-computer rules, not to a code.
Control, readout & I/O burden
The factory adds no wires and one hard latency requirement: each attempt ends in an accept/reject verdict that must reach the scheduler before the state decays, so it rides the memory's real-time decode path and competes for its bandwidth. On a 1.1 µs superconducting cycle D[1] a distance-15 escape is about 17 µs per attempt, and at 8% acceptance the attempt rate must be ~12× consumption. On QCCD ion and neutral-atom hosts the cycle is 1–5 ms, the same attempt costs 15–75 ms, and throughput binds rather than fidelity. Measured decode latency is 63 µs at d=5 D[1], above the per-attempt budget; Riverlane's sub-microsecond-per-round FPGA decoder D[238] and NVQLink's 3.84 µs mean round trip P[324] are what make pipelining possible. The wall: at 10³ qubits factory and algorithm do not coexist; at 10⁴ one or two fit; at 10⁶ the problem is scheduling tens of factories, each with its own decoder stream.
Role in the stack
It sits, as an alternate, on four architectures: the transmon lattice with tunable couplers (Google, IBM, Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu), trapped-ion QCCD (Quantinuum), the linear Paul trap with individual laser addressing (AQT, Innsbruck) and the alkali neutral-atom architecture (Harvard/MIT, QuEra, Pasqal, Infleqtion, Google's 2026 atom track). It requires a host — the rotated surface code with its yoked variants, or the colour code — and provides the non-Clifford axis without which a stabiliser machine is classically simulable. Cultivation replaces multi-level distillation; the switching price is architectural, since cultivation is surface-code-native and post-selection-heavy while code switching needs a colour code. It is one primitive reaching all three leading carriers with no substitute, so its value lies entirely in what it unlocks. It does not set the derived clock but multiplies it — derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture, so 0.65 µs superconducting (1.1 µs measured) and 9.66 ms for QCCD ions, times escape depth and inverse acceptance. Empty neighbouring slots: no factory on bosonic, photonic or spin platforms, none on a qLDPC code.
Evidence — how the numbers were measured
Every headline number is a post-selected stand-alone fidelity, measured on a state then discarded rather than used. Google reports a bound from a purpose-built fault-tolerant measurement protocol, not a tomographic estimate D[42]; the 7×10⁻⁵ figure is quoted at a stated discard rate D[107]; code switching's 5.1(2.7)×10⁻⁴ carries an uncertainty of the same order as the value D[666]; the neutral-atom paper reports improvement over input rather than an absolute output infidelity D[147]. Unmeasured everywhere: throughput under scheduling load, the cost of discards, factory-to-consumer correlations, and the loss channels post-selection removes. Independent checking is unusually strong — Wan, Zhong and Zapirain decompose d=5 cultivation circuits into about 8 Clifford terms on average via the ZX-calculus, over 10⁶× fewer than prior stabiliser decompositions D[691]. No value conflicts were found among the sources used.
A factory's output can be certified with the operations the code already has: Bell-coherence fidelity estimation measures the infidelity ε of any pure resource state, including continuous-angle rotation states, to a fixed relative accuracy from Θ(1/ε) copies using only Clifford gates and Pauli measurements — optimal even against collective measurements — and in distance-3 surface-code simulations it needed up to about 27× fewer states than direct fidelity estimation P[896]. The measured copies are consumed.
Not published in the abstracts of [42] and [147]: the escape-stage code distance, physical-qubit count and cycle count of Google's cultivation run, and the absolute output infidelity, atom count and acceptance rate of the QuEra/Harvard/MIT distillation, whose stated figure is the improvement over the input. Not published: a dated patent-family count for magic-state preparation. The distance-15 escape region of order 10³ qubits and ~17 µs per attempt are derived from [690] and [1], not quoted by a source.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | Invented cultivation; first superconducting demonstration | S[690] D[42] |
| Quantinuum | developer | US/UK | Code switching and the [[6,2,2]] logical non-Clifford gate | D[107], [666] |
| QuEra Computing | developer | US | First logical-level 5-to-1 distillation on colour codes | D[147] |
| Harvard University | research | US | 448-atom universal fault-tolerance architecture | D[4] |
| IBM | developer | US | Starling budgets 10⁸ logical gates; on Heron, post-selected magic-state injection only, no factory | R[67] |
| NVIDIA | supplier | US | NVQLink, the accept/reject path a pipelined factory needs | P[324] |
| Riverlane | supplier | UK | Sub-microsecond decoding, the throughput gate on cultivation | D[238] |
| DARPA | funder | US | QBI Stage B funds IBM, Quantinuum, QuEra and eight others | fact |
Money.
- 2025-09-04 · Quantinuum · capital raise · $600 M at $10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed fact
- 2025-09-09 · QuEra · financing round · $230 M+ · Google, SoftBank Vision Fund 2, NVentures · closed fact
- 2025-11-06 · DARPA · QBI Stage B · up to $15 M each · eleven teams · announced fact
- 2026-06-03 · Quantinuum · IPO · $1.68 B gross, Nasdaq QNT; FY guidance $28–32 M · closed fact
- 2026-06 · IBM · corporate commitment · $10 B, US quantum manufacturing and R&D · announced C[67]
Market & supply chain. Nobody sells a magic-state factory; it is bundled into a machine and given away in a compiler. The sellable adjacencies are real-time decoding and interconnect, resource estimation, and the host hardware. Concentration is extreme: Google, Quantinuum, and QuEra with Harvard and MIT hold every demonstrated result except Innsbruck's code switching and the magic-state injections on IBM's Heron and Zhejiang University's 125-qubit processor, and two of the three routes trace to one theory group. G3 and G4 pay for this directly, G6 indirectly; G1, G2 and G5 pay nothing, which is why a primitive on every fault-tolerance critical path carries almost no dedicated revenue.
IP & standards. No dated patent-family count specific to magic-state factories was found from a named database as of 3 September 2026; PatSnap's landscape published on 2026-06-30 counts IBM 4,388, Google 2,385 and Microsoft 1,175 quantum patent families but does not break them down to this node Pfact. There is no interface standard; the de-facto portability layer is the Quantum Intermediate Representation used in the 2023 real-time demonstration C[692], the verification layer open-source stabiliser and ZX simulation D[691]. No litigation on record.
Roadmaps & track record. Google (2024-09-26, "as cheap as a CNOT"): demonstrated 2025-12-15 at 0.9999, fifteen months theory to silicon, still five orders above target. Quantinuum (2024-09-10, universal fault tolerance by 2029): two demonstrations, both on the 20-qubit H1-1, none yet on Helios. QuEra (2024-01, 100 logical qubits in 2026): distillation shown 2025-07, count not met, restated as Libra in 2028. IBM (2025-06-10, Starling 2029): no factory result, Kookaburra slipped a year. Credibility: Google highest, with theory, hardware and verification tooling in one place; Quantinuum high on primitives, unproven at scale; QuEra high on primitives, slipped roadmap; IBM unevidenced here.
Strategic reading. If cultivation holds at scale, the winner is whoever has the fastest cycle and the best sub-microsecond decoder — favouring superconducting over ions and atoms by two to three orders of magnitude in throughput; the loser is the distillation-dominated resource estimate that made fault tolerance look ten times dearer than it now appears, and any security timeline resting on it. Substitution threats are real but undemonstrated: transversal non-Clifford codes, algorithmic fault tolerance, Clifford-heavy redesign. Bargaining power sits with the platform vendor, since the factory is a compiler asset; the only supplier leverage is the accept/reject path.
Outlook & open questions
Confirm, within 12–24 months, if a cultivated state is consumed by a logical algorithm rather than measured in isolation, with end-to-end error below 10⁻⁶ by end-2027; if cultivation reaches a discard rate below 50%, against 92% today; if any magic-state result appears on IBM hardware before Starling, or any factory runs on a qLDPC code. Demote if Google's next processor cannot push cultivation below 10⁻⁵ while raising acceptance, or if the fidelity bound fails to survive consumption. Best case by 2029: in-line cultivation near 10⁻⁹ and factories a minority of the footprint, so T-count-limited algorithms become clock-limited. Worst case: acceptance stays near 10%, throughput binds, distillation returns as a second stage and the 10³-physical-per-logical estimates with it. Open questions: does the bound survive use rather than measurement; what does post-selection cost under real scheduling; can code switching be made deterministic; is a qLDPC-native factory possible; does erasure conversion raise this threshold as it raises the memory's. Watch Google's next cultivation paper, the first Helios magic-state numbers, IBM Kookaburra and QuEra Libra.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [32] Y. Chen and M. Devoret, “Our quantum hardware: the engine for verifiable quantum advantage,” Google Blog, Oct. 22, 2025. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ quantum-hardware-verifiable-advantage/ - [42] E. Rosenfeld et al., “Magic state cultivation on a superconducting quantum processor,” arXiv:2512.13908, Dec. 2025. D
- [67] IBM, “IBM Sets the Course to Build World's First Large-Scale, Fault-Tolerant Quantum Computer at New IBM Quantum Data Center,” Jun. 10, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-06-10-IBM-Sets-the-Course-to-Build-Worlds-First-Large-Scale,-Fault-Tolerant-Quantum-Computer-at-New-IBM-Quantum-Data-Center R - [107] S. Dasu et al., “Breaking even with magic: demonstration of a high-fidelity logical non-Clifford gate,” arXiv:2506.14688, Jun. 2025. D
- [147] P. S. Rodriguez et al., “Experimental demonstration of logical magic state distillation,” Nature, vol. 645, no. 8081, pp. 620–625, Jul. 2025, doi: 10.1038/s41586-025-09367-3. D
- [238] A. B. Ziad et al., “Local clustering decoder as a fast and adaptive hardware decoder for the surface code,” Nat. Commun., vol. 16, no. 1, Art. no. 11048, Dec. 2025, doi: 10.1038/s41467-025-66773-x. D
- [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Pnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [655] C. Gidney and C. Jones, “New circuits and an open source decoder for the color code,” arXiv:2312.08813, Dec. 2023. S
- [666] L. Daguerre, R. Blume-Kohout, N. C. Brown, D. Hayes, and I. H. Kim, “Experimental Demonstration of High-Fidelity Logical Magic States from Code Switching,” Phys. Rev. X, vol. 15, no. 4, Art. no. 041008, Oct. 2025, doi: 10.1103/dck4-x9c2. arXiv:2506.14169. D
- [689] S. Bravyi and A. Kitaev, “Universal Quantum Computation with ideal Clifford gates and noisy ancillas,” Phys. Rev. A, vol. 71, Art. no. 022316, 2005, doi: 10.1103/PhysRevA.71.022316. arXiv:quant-ph/0403025. S
- [690] C. Gidney, N. Shutty, and C. Jones, “Magic state cultivation: growing T states as cheap as CNOT gates,” arXiv:2409.17595, Sep. 2024. S
- [691] K. H. Wan, Z. Zhong, and A. Zapirain, “Simulating magic state cultivation with few Clifford terms,” Quantum, vol. 10, Art. no. 2134, Jun. 2026, doi: 10.22331/q-2026-06-12-2134. D
- [692] Quantinuum, “A Quantinuum-led team has built the quantum programming tools for real-time magic state distillation on a quantum computer,” Oct. 24, 2023. [Online]. Available: https://www.quantinuum.com/
blog/ Ca-quantinuum-led-team-has-built-the-quantum-programming-tools-for-real-time-magic-state-distillation-on-a-quantum-computer - [896] S. Takahashi and K. Fujii, “Efficient fidelity estimation of general quantum resource states via Clifford circuits,” arXiv:2610.05222, Oct. 2026. P
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הטקסט בעברית נטען…
Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC)
A discrete outer code — repetition or qLDPC — wrapped around a bosonic inner qubit whose noise is already shaped, so the outer code corrects only one residual channel.
Verdict. The whole family rests on one number, the phase-flip rate under a gate. Measured hardware is two orders of magnitude away from every published resource estimate.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The construction shapes the inner qubit's noise so the outer code has less to do. A cat qubit stabilised by two-photon dissipation suppresses bit-flips exponentially in photon number while phase-flips grow only linearly, so a 1D repetition code suffices: distance d costs d cats, not d². A GKP inner qubit instead hands up an analogue shift syndrome that a qLDPC outer code decodes with soft information. Theory came first and is precise. Gouzien et al. (PRL 131, 040602, 2023) size a repetition-cat machine at 126,133 cats, 19 photons each, for a 256-bit elliptic-curve logarithm in 9 hours at an assumed loss ratio of 10⁻⁵ S[95]; Ruiz et al. then gave 2D-local LDPC-cat codes, 758 cats for 100 logical qubits at ≤10⁻⁸ per cycle, assuming ~0.1% phase-flip S[96].
Attributes: partly fabricated (0.75); static, no control channel or readout of its own; biased plus Gaussian error — "Outer code exploits inner bias/shift correction; Ocelot d=3→5 nearly flat; LDPC-cat assumes 0.1% phase-flip (measured ~10%)" (graph record).
Physics & limits
The family trades one error channel against another, and the exchange rate is the noise bias. Photon number buys exponential bit-flip suppression and pays linearly in phase-flips, so an architecture picks the point where bit-flips fall below the outer code's reach and lives with the rate left — assumed near 10⁻³. Hardware is not there: in Ocelot's CX at |α|² = 2 the phase-flip is 9.6(4)×10⁻² and the bit-flip 3.5(4)×10⁻³, a bias above 25 under the gate and above 30 idle D[80] — a per-CX figure, not per cycle. The deeper limit: bias belongs to the idle manifold and a dissipative CX degrades the asymmetry the code is built on, so the open problem is a bias-preserving gate, not a better memory. What moves the floor: a larger ratio of two-photon dissipation to single-photon loss, and unitary rather than dissipative gates.
Engineering state of the art
One hardware result with a measured logical error carries the family: Ocelot (Putterman et al., AWS and Caltech, Nature 638, 927, 2025-02-26), a repetition code over five cat qubits with four ancilla transmons and five buffer modes — logical error 1.75(2)% at distance 3 and 1.65(3)% at distance 5, per 2.8 µs cycle D[80]. These are not the same operating point (d=3 at |α|² = 1, d=5 at |α|² = 1.5), so the repeated "flat below threshold" mixes a distance step with a photon-number step and scaling is not isolated. No bias-preserving cat–cat CNOT exists — the AWS-affiliated proposal is unitary and simulated S[81] — and no GKP-plus-qLDPC hardware exists. The register lists two more code runs on hardware, neither with a published logical error rate: Alice & Bob Helium (on-premise system), 18 cats as one logical qubit, and Aurora, a distance-2 repetition code on a GKP cluster state, detection only.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-01 | LDPC-cat, 2D-local: 758 cats → 100 logical at ≤10⁻⁸/cycle, assumes 0.1% phase-flip | Ruiz et al. | S[96] |
| 2025-02 | Ocelot: 1.75(2)% at d=3 (|α|²=1) → 1.65(3)% at d=5 (|α|²=1.5), 2.8 µs cycle | AWS/Caltech | D[80] |
| 2026-07 | Unitary bias-preserving cat–cat CNOT; d=7 repetition of 13 cats below 10⁻⁶, simulated | AWS-affiliated | S[81] |
Manufacturing, materials & supply chain
No process step of its own: this is an architecture and a decoder, and the graph record leaves fabrication unset. It inherits the cat or GKP host, and the superconducting hosts differ by builder. Yale's GKP oscillator is a seamless coaxial-stub cavity of high-purity aluminium with a tantalum transmon ancilla on a sapphire chip Dfact; Nord Quantique's is a double-post cavity of high-purity aluminium with an auxiliary transmon D[82]. AWS's Ocelot holds its cats in tantalum resonators on one die, bump-bonded to a second die that carries the aluminium junctions, and adds an ancilla transmon per repetition check — four for five cats D[80]. Alice & Bob's cats are tantalum-on-sapphire circuits with no transmon at all: two-photon dissipation through a buffer mode stabilises them, and the buffer also carries the readout factCfact. All four run in a dilution refrigerator. The accounting worth keeping is Ocelot's fourteen engineered elements for five data cats — the real denominator behind any "fewer qubits" comparison D[80]. Helium draws about 40 kW for a logical qubit using as few as 18 cats C[87]. No code-specific export control exists; ECCN 3A904 applies to the host G[301].
Control, readout & I/O burden
The decoder is the cheap part: a 1D repetition syndrome stream is simpler than 2D matching and, at 2.8 µs, inside existing FPGA decoders. The cost moved into analogue stabilisation — each cat needs a two-photon dissipation drive and a buffer pump, plus readout (through the buffer at Alice & Bob, through an ancilla transmon per check on Ocelot), so lines per data qubit exceed a bare transmon's. The saving is in code distance, not wiring: at 10³ cats the cryostat resembles a 10³-transmon machine with extra pumps. The cycle is also 2.5× slower than a 1.1 µs surface-code cycle D[1].
Role in the stack
The code requires a biased cat or a GKP inner qubit; as the terminal outer layer it has no dependents, and it replaces fusion-based discrete-variable fault tolerance. It sits on two architectures, as the primary code on both: bosonic cavity qubits with cat and GKP encodings (Alice & Bob, AWS, Nord Quantique) and continuous-variable photonic GKP, where Xanadu concatenates GKP under qLDPC Cfact. Switching inner qubits is no re-parameterisation: the cat branch buys a 1D outer code and owes a bias-preserving gate; the GKP branch buys an analogue syndrome and owes ~10 dB of squeezing. Its derived-clock contribution (= sum of the syndrome round: gate layers + transport + readout + reset) is d₂ = 2 gate layers, a 1.44 µs round against the measured 2.8 µs cycle D[80]. The neighbouring empty slot is an LDPC-cat memory on hardware — unbuilt as of 4 Sep 2026.
Evidence — how the numbers were measured
The "100–1000× fewer qubits" claim is a resource estimate, not a measurement, and both papers state the assumption plainly: ~0.1% phase-flip S[95], [96]; hardware is at 9.6×10⁻² per CX D[80]. No protocol captures gate-level bias preservation under load, because the gate does not exist; Ocelot has no independent replication and mixes operating points across its distance comparison. Helium is sold but publishes no logical-performance data, and the roadmap quotes a September 2025 peak bit-flip time of 252 minutes against a 44-minute mean for the same run C[412].
No LDPC-cat or GKP-plus-qLDPC code has run on hardware. Not published: a dated patent-family count specific to bosonic codes, and AWS's funding for the Ocelot programme.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| AWS | Developer | US | Ocelot repetition-cat hardware; cat–cat CNOT proposal | D[80] |
| Alice & Bob | Developer | FR | Cat hardware; Graphene repetition-cat roadmap | C[412] |
| Nord Quantique | Developer | CA | GKP inner qubits for an outer code | D[82] |
| Xanadu | Developer | CA | Optical GKP under qLDPC, roadmap stage | Rfact |
| D-Wave | Developer | US | Bosonic gate-model roadmap after buying Quantum Circuits | Cfact |
Money.
- 2025-01-28 · Alice & Bob · Series B · €100 M · NVentures extension 2026-05-22, undisclosed · closed Cfact
- 2025-11-06 · DARPA · QBI Stage B: Nord Quantique and Xanadu in, Alice & Bob not · ≤$15 M each · closed fact
- 2026-01-20 · D-Wave · acquisition of Quantum Circuits · $550 M ($300 M stock, $250 M cash) · closed Cfact
- 2026-05-18 · Nord Quantique · growth equity · $30 M at a $1.4 B valuation · closed Cfact
Market & supply chain. Nobody sells this layer; it is bundled into machines with a superconducting bill of materials, so concentration risk sits with amplifier and refrigerator vendors, not foundries. G3 and G4 pay for it indirectly: what customers buy is the qubit-count claim, which is why GENCI's June 2026 Helium purchase precedes any published logical-performance number Cfact.
IP & standards. No dated, code-specific patent-family count was found in any named database. The constructions are academic and openly published, so defensible IP sits in the stabilisation circuits — buffer design, two-photon dissipation, bias-preserving gates — not the codes. No standards activity found.
Roadmaps & track record. Alice & Bob (as of 2026-09-04): Helium, 12–18 cats and one logical qubit at 10⁻², current; then 48, 250 and finally 2,000 cats for 100 logical at 10⁻⁶ in 2030, with a stated 13-minute bit-flip requirement R[412]. D-Wave (2026-06-01): 10 logical in 2030, 100 in 2032, Λ = 10 Rfact. Xanadu: fault tolerance 2028–29 Rfact. Every roadmap is in logical qubits while the demonstrated quantity is one at 10⁻²; AWS publishes no dated roadmap and holds the only scaling data.
Strategic reading. This family is the bosonic companies' only argument against better-funded transmon incumbents: close the phase-flip gap and they leapfrog on qubit count per dollar. Fail, and qLDPC-on-transmon or dual-rail erasure takes the slot without needing an unproven bias-preserving gate.
Outlook & open questions
Confirm or demote within 12–24 months: a demonstrated bias-preserving cat–cat CNOT; a distance scan at fixed photon number; any LDPC-cat or GKP-plus-qLDPC hardware result. Best case by 2029: a repetition-cat logical qubit with isolated below-threshold scaling and a measured bias-preserving gate, making the 758-cat estimate arguable. Worst case: phase-flip stays near 10⁻¹ and the family survives as a research line. Open: whether bias survives any two-qubit gate.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [81] Y. Ye et al., “Bias-preserving cat-cat CNOT gate via vacuum-conditional beam-splitter,” arXiv:2607.22852, Jul. 2026. S
- [82] S. Turcotte et al., “Quantum error correction of a grid-state qubit with state preparation and measurement errors below 10⁻³,” arXiv:2607.06718, Jul. 2026. D
- [87] N. Coppola, “Alice & Bob Unveils First Quantum System, Helium,” Alice & Bob, Jun. 10, 2026. [Online]. Available: https://alice-bob.com/
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roadmap/ C
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Colour code (transversal Cliffords)
Triangular 2D stabiliser code whose whole Clifford group acts transversally, skipping lattice surgery, at roughly 1.9× the surface code's teraquop footprint (physical qubits per logical qubit for 10¹² reliable operations).
Verdict. The colour code's future is as the magic-state factory feeding surface-code memory, not as the memory. Demote the memory case if no platform reports a colour-code logical memory beating the surface code on total qubits for a fixed logical target by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A 2D topological stabiliser code on a three-colourable trivalent lattice, each plaquette carrying an X and a Z stabiliser of weight 6. Because the two types share support, the entire Clifford group — H, S, CNOT — is transversal, where the surface code gets only CNOT natively and pays lattice surgery for the rest. Bombín and Martín-Delgado introduced it in 2006 D[663]; the first full hardware demonstration is Google's, submitted December 2024 D[41]. The price is density: ~1.9× the surface code's teraquop footprint, 1,250 against 650 physical per logical at 0.1% noise S[655]fact.
d = static triangular lattice, no transport; e = inherits the host's control modality and placement [graph].
f = Pauli stabilisers only; a = 0.5 — identical on fabricated and natural carriers, needing only a static nearest-neighbour lattice [graph].
Physics & limits
The transversal gate needs no merge/split: Google puts a logical Hadamard at ~20 ns against ~1,000× longer through lattice surgery C[664]. Weight-6 checks mean deeper extraction and hook errors that cut the effective distance unless the schedule avoids them — a 2026 construction avoids all malign bulk hook errors with one auxiliary per plaquette S[665]. Errors also fire three detectors, so the syndrome is a hypergraph: matching does not apply and decoders must project or search. Hence the gap: Λ₃/₅ = 1.56(4) D[41] against 2.14 for the surface code on the same processor family D[1], and Google's 2026 d=5 colour-code memory reached 8.19(14)×10⁻³ per cycle only with the search-based Tesseract decoder D[2]. What moves the floor is circuit scheduling and decoders, not the code.
Engineering state of the art
table
| Year | Figure | Who | Tag+Key |
|---|---|---|---|
| 2024-12 | Λ₃/₅ = 1.56(4); transversal Clifford adds 0.0027(3) | Google Quantum AI | D[41] |
| 2025-07 | first logical 5-to-1 distillation, d=3 and d=5 patches | QuEra | D[147] |
| 2026-07 | distance-5 colour-code memory, 8.19(14)×10⁻³ per cycle | Google Quantum AI | D[2] |
Dominant term: the syndrome round, not the transversal gate — weight-6 extraction and hypergraph decoding leave Λ at 1.56 against 2.14 D[1], [41].
Manufacturing, materials & supply chain
No fabrication of its own: it inherits the host's chip, trap or tweezer array, tiled hexagonally rather than square, and brings no new supplier D[41]. Export exposure is the host's: ECCN 4A906 (BIS, 2024-09-06) controls a quantum computer only when its qubit count and C-NOT error fall in the same band — from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits on fact — while the code is published mathematics from 2006 D[663].
Control, readout & I/O burden
Control and readout per qubit match the host's surface-code burden. The difference is per round: each data qubit sits in six weight-6 checks against the surface code's four weight-4 checks, so a round costs about 1.5× the two-qubit gates on a deeper schedule, and that is where the threshold goes. Against it, a logical Clifford needs no merge/split rounds at all. Decoding is the harder item: hypergraph syndromes rule out a stock matching engine, and the only published d=5 hardware decode is Google's Tesseract search decoder D[2].
Role in the stack
Sits, as an alternate code, in four architectures — the transmon lattice with tunable couplers, trapped-ion QCCD, the linear Paul trap with individual laser addressing and the alkali Rydberg tweezer array [graph]; requires the same static nearest-neighbour lattice as the surface code and hosts magic-state factories. All three 2025–26 magic-state milestones ran in colour codes: cultivation to 0.9999(1) at 8% acceptance before code-switching out D[42], Quantinuum's [[15,1,3]]→[[7,1,3]] switching at ≤5.1(2.7)×10⁻⁴ D[666], QuEra's 5-to-1 distillation D[147]. It replaces the surface code where transversal Cliffords beat the ~1.9× footprint; switching costs a decoder and a layout, not hardware. Clock contribution ~20 ns per logical Hadamard C[664]; the code does set d₂, the gate-layer count summed into the round (derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture), 0.65 µs derived against the measured 1.1 µs host cycle. Neighbouring empty slot: no hardware colour-code decoder.
Evidence — how the numbers were measured
Λ₃/₅ = 1.56(4) and the 0.0027(3) transversal-Clifford error are Google's own, one processor, unreplicated by a second vendor D[41]. Two framings of that paper conflict: it reports 86.5(1)–90.7(1)% teleported-state fidelities for lattice surgery, while Google's blog presents 86–91% as "two-qubit gate fidelity" C[664] — trust the paper. Magic injection exceeds 99% only with post-selection keeping ~75% of runs D[41]. The footprint claims are not comparable either: "fewer physical qubits per code distance" C[664] against total qubits for a fixed logical target S[655]. Nothing published separates code error from decoder error in the transversal figure.
Not published: a quantified Monte Carlo improvement for the hook-error-free colour-code circuit [665].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Google Quantum AI | Developer/user | US | Only superconducting colour-code memory; cultivation host | D[41], [42] |
| Quantinuum | Developer/user | US | Colour-code code switching; tesseract [[16,6,4]] on Helios | D[666], [667] |
| Microsoft Quantum | Developer | US | Co-authored the tesseract colour-code result | D[667] |
| QuEra | Developer/user | US | First logical 5-to-1 distillation on colour-code patches | D[147] |
Money. 2025-07-14 · QuEra · publication (first logical 5-to-1 distillation) · no figure · funded from its $230 M+ 2025 round C[153] · published D[147]. 2025-11-06 · DARPA QBI Stage B · up to $15 M per team · eleven teams, Quantinuum and QuEra among them G[65]. 2026-06-03 · Quantinuum · IPO · $1.68 B gross at $60/share, Nasdaq QNT; Q2-2026 revenue $8.0 M, cash $2.1 B · closed G[123]. No round, grant or acquisition is specific to the colour code: it is a line item inside platform programmes.
Market & supply chain. No dedicated supply chain; it rides the host's fab and the general classical stack. The market it moves is decoding: hypergraph syndromes need search or projection decoders (FPGA/GPU work from AMD and NVIDIA), and no vendor ships a colour-code hardware decoder as of 4 Sep 2026. Pays into G3 and G4 through magic-state factories: every logical magic-state milestone since 2025 ran in a colour code D[42], [147], [666].
IP & standards. The code is published mathematics from 2006 D[663]. PatSnap's April 2026 landscape counts 12 QEC patents — Google 6, IBM 4, Tencent 2 — with no colour-code cluster P[668]. Google's granted surface-code patent covers gauge operators, not this code fact. No standards body; the de facto interface is a Stim detector-error model.
Roadmaps & track record. Google (2025-06-23 · colour code a "workhorse configuration", no dated milestone · a d=5 memory followed in July 2026) C[664]D[2]. Quantinuum (2024-09 · Helios 2025 → Sol 2027 → Apollo 2029 · Helios shipped 2025-11-05 and carried the tesseract result) Rfact. QuEra (2026-06 · Libra, >256 logical, 2028 · its January-2024 roadmap promised 100 logical in 2026, undelivered) Rfact. Google's claims have been measurements, not promises; Quantinuum's schedule has held; QuEra's research runs ahead of its product roadmap.
Strategic reading. The colour code favours platforms where qubits are cheap and logical time expensive — superconducting and neutral atoms — over trapped ions, where a 1.9× premium falls on the scarce resource. Its likeliest 2029 position is not memory but the T-state factory feeding surface-code memory: cultivation cut magic-state cost ~40× inside a colour code and then switched out D[42], making it a component of a surface-code machine rather than a competitor. Substitution threats: high-rate qLDPC blocks with transversal gates, and algorithmic fault tolerance replacing O(d) rounds per logical gate. Losers: toolchains built only around lattice surgery.
Outlook & open questions
Confirm/demote in 12–24 months: a colour-code memory beyond d=5 with Λ approaching 2.14; a second vendor reproducing transversal Cliffords. Best case 2029: cultivation makes it the standard magic-state substrate, the footprint premium confined to factory patches. Worst case: hook-error and decoder overheads keep Λ near 1.5 and it survives only as a distillation substrate. Open questions: does the one-auxiliary-per-plaquette circuit S[665] recover a competitive threshold on hardware; do planar non-Clifford circuits S[669] beat distillation; will anyone publish a total-footprint comparison.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [41] N. Lacroix et al., “Scaling and logic in the color code on a superconducting quantum processor,” Nature, vol. 645, no. 8081, pp. 614–619, May 2025, doi: 10.1038/s41586-025-09061-4. arXiv:2412.14256. D
- [42] E. Rosenfeld et al., “Magic state cultivation on a superconducting quantum processor,” arXiv:2512.13908, Dec. 2025. D
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [123] Quantinuum, “Quantinuum Announces Pricing of Upsized Initial Public Offering,” Jun. 3, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Gquantinuum-announces-pricing-of-upsized-initial-public-offering - [147] P. S. Rodriguez et al., “Experimental demonstration of logical magic state distillation,” Nature, vol. 645, no. 8081, pp. 620–625, Jul. 2025, doi: 10.1038/s41586-025-09367-3. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [655] C. Gidney and C. Jones, “New circuits and an open source decoder for the color code,” arXiv:2312.08813, Dec. 2023. S
- [663] H. Bombín and M. A. Martin-Delgado, “Topological Quantum Distillation,” Phys. Rev. Lett., vol. 97, Art. no. 180501, 2006, doi: 10.1103/PhysRevLett.97.180501. arXiv:quant-ph/0605138. D
- [664] A. Bourassa and K. Satzinger, “A colorful quantum future,” Google Research Blog, Jun. 23, 2025. [Online]. Available: https://research.google/
blog/ Ca-colorful-quantum-future/ - [665] G. Kishony and A. Fowler, “Color code off-the-hook: avoiding hook errors with a single auxiliary per plaquette,” arXiv:2603.28852, Mar. 2026. S
- [666] L. Daguerre, R. Blume-Kohout, N. C. Brown, D. Hayes, and I. H. Kim, “Experimental Demonstration of High-Fidelity Logical Magic States from Code Switching,” Phys. Rev. X, vol. 15, no. 4, Art. no. 041008, Oct. 2025, doi: 10.1103/dck4-x9c2. arXiv:2506.14169. D
- [667] A. Paetznick et al., “Improved quantum processor logical error rates via correction and detection,” Nature, vol. 654, no. 8118, pp. 349–355, Jun. 2026, doi: 10.1038/s41586-026-10628-y. D
- [668] PatSnap, “Quantum Error Correction Technology Landscape 2026,” Apr. 22, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ articles/ quantum-error-correction-patent-landscape-2026/ - [669] A. Bauer and J. C. M. de la Fuente, “Planar Fault-Tolerant Circuits for Non-Clifford Gates on the 2D Color Code,” PRX Quantum, vol. 7, no. 2, Art. no. 020367, Jun. 2026, doi: 10.1103/p7c9-x1m9. arXiv:2505.05175. S
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Algorithmic FT / transversal architectures
Replacing O(d) syndrome-extraction rounds per logical gate with a constant number, via transversal block-to-block gates plus correlated decoding.
Verdict. The transversal half is measured on atoms and ions; the correlated-decoding half is a proof plus simulation. No run has closed transversal gate, correlated decode and feed-forward in real time.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Algorithmic fault tolerance, introduced by Zhou, Bluvstein, Kubica, Lukin and co-workers as a preprint in June 2024 and published in Nature in 2025 D[152], runs logical gates transversally between code blocks and decodes the algorithm's whole syndrome history jointly, so a logical gate costs a constant number of extraction rounds rather than the O(d) lattice surgery needs.
Mobility: it presumes a machine that can bring any two blocks into register — tweezer transport or ion shuttling — not a fixed lattice. Error structure: no new channel — the code's own Pauli and erasure noise, atom loss dominant, with physical-cycle overhead traded for classical decoding overhead.
Physics & limits
The d-round rule exists because one round cannot distinguish a measurement error from a data error; repeating the syndrome circuit d times makes the detector graph's spacetime distance equal the code distance. That redundancy is only needed when each block is decoded alone: a transversal CNOT maps a fault in one block to its partner in the other, so the joint graph across blocks and time still has distance d after O(1) rounds — if the decoder uses it. The proof bounds deviation from the ideal logical measurement distribution as exponentially small D[152].
The cost moves to the classical side, structurally. The joint graph does not factorise, so the sliding window that keeps per-block decoding local in time is no longer exact: the decoder spans several logical gates, cannot close its window until the next feed-forward point, and its work grows with the blocks entangled since the last measurement, not with d.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-06 | O(d) → O(1) rounds per logical gate, >10× spacetime reduction (proof, simulation) | Harvard/QuEra | D[152] |
| 2025-05 | RSA-2048 in 5.6 days on 19 M atoms at a 1 ms cycle, ~50× faster than comparable | Harvard/QuEra | S[31] |
| 2025-11 | 448 atoms: transversal CNOTs, hundreds of teleportations, 96 logical qubits | Harvard/QuEra | D[4] |
| 2026-03 | Shor with 10,000 atoms (26,000 for speed): P-256 in days, RSA-2048 far longer | Harvard/Caltech | S[30] |
| 2026-06 | [[16,6,4]] tesseract code, transversal logical Cliffords, on trapped ions | Quantinuum | D[667] |
Every reported gain is simulation or an offline decode of stored syndromes: no published run closes the loop — transversal gate, correlated decode, feed-forward — in real time.
Manufacturing, materials & supply chain
An architecture and decoding layer with no process, yield or unit cost. Its supply-chain exposure is second-hand but specific: crossed acousto-optic deflectors, where AA Opto-Electronic and Gooch & Housego are the only vendors named in the 448-atom work D[4], and the classical hardware running the decode. NVIDIA's NVQLink sets the yardstick at 3.84 µs round trip and 67 µs median decode with BP+OSD (belief propagation plus ordered-statistics decoding) — on the far easier per-block problem C[324].
Control, readout & I/O burden
No new laser, control line or detector; the burden is classical and real-time. A correlated decoder must ingest syndromes from every block touched by a transversal gate and return a correction before the next feed-forward point — within milliseconds on atoms, on a graph 10²–10³× larger than the single-block problem GPUs handle now. At 10³ logical qubits the evidence is simulation; at 10⁴–10⁶ no latency model has been published, and both resource estimates assume decoding keeps up S[31]S[30]. That assumption, not atom count, is where this fails if it fails.
Role in the stack
It applies on any architecture that can move qubits: the alkali Rydberg tweezer array (QuEra, Pasqal, Infleqtion) and — though the graph record models it on that array alone — Atom Computing's alkaline-earth(-like) arrays and the trapped-ion QCCD architecture, where Quantinuum runs the same [[16,6,4]] code transversally D[667]. It requires transport plus correlated, loss-aware decoding, and conflicts with fixed nearest-neighbour lattices, which cannot pair arbitrary blocks without a routing layer. It adds no term to the derived clock but multiplies it, cutting rounds per logical gate from ~d (at d=7 on atoms, ~9 ms per gate) to O(1). Neighbouring empty slot: a real-time correlated decoder.
Evidence — how the numbers were measured
Transversal gates and 96 active logical qubits are hardware measurements D[4]; the >10× reduction is a theorem plus simulation D[152], unreproduced outside the author group. The two resource estimates differ by three orders in space — a trade curve, not a contradiction: 19 M atoms buys RSA-2048 in 5.6 days S[31], while 10,000–26,000 atoms buys P-256 in days and RSA-2048 one to two orders slower S[30]; "RSA-2048 with 10,000 atoms" is what neither paper says. The sharpest counter-evidence is Atom Computing and Microsoft's toric code: Λ_Z ≈ 1.9 but Λ_X ≈ 1.2, average 1.30 over four cycles, and with reloading over 90 rounds suppression vanished (0.63% versus 0.64% per cycle) D[148]. Atoms have not shown sustained below-threshold memory, and constant-round fault tolerance is a claim about long algorithms.
Not published: a common assumption set (physical error rate, code distance, decoder model) for the 19 M-atom / 5.6-day and 10,000-atom estimates, and a real-time correlated-decoder latency above roughly 10² logical qubits. The >10× spacetime reduction has no replication outside the overlapping Harvard/QuEra/Caltech author group.
Actors & economics
Who.
| Organisation | Role | Country | What they do here | Evidence |
|---|---|---|---|---|
| Harvard | research | US | Originated the scheme; 448-atom transversal demo | D[4], [152] |
| QuEra | developer | US | Co-author and hardware; Libra 2028 needs the gain | Cfact |
| Quantinuum | developer | US/UK | Transversal logical Cliffords on ions, same code | D[667] |
| Atom Computing | developer | US | Zoned transport; published the counter-result | D[148] |
| Google Quantum AI | developer | US | Neutral-atom track since 2026-03, QEC-focused | C[9] |
| Pasqal | developer | FR | Transport architecture, 100 logical by 2029 | Cfact |
Money. 2025-09-09 · QuEra · round · $230 M+ · Google, SoftBank Vision Fund 2, NVentures · closed G[153]fact. 2025-11-06 · Atom Computing and QuEra · QBI Stage B · ≤$15 M each · active G[65]fact. 2026-02-17 · Infleqtion · IPO · >$550 M · NYSE INFQ G[155]. 2026-05-21 · Atom Computing and Infleqtion · CHIPS LOI · $100 M each · US Commerce · non-binding G[300]fact. 2026-06-16 · Atom Computing · Series C · $100 M, Third Point G[154]fact. 2026-08-28 · Pasqal · SPAC · ~$360 M cash · Nasdaq PSQL G[156]fact.
Market & supply chain. Nothing is sold under this name; it multiplies someone else's machine, so rent accrues to the transport optics and the decoder stack. It pays for G3, cutting physical-per-logical from ~10³ toward ~10², and for G4 if it holds; nothing for G1 or G5.
IP & standards. The founding work is peer-reviewed in Nature and open on arXiv, as is the ISCA resource analysis; no patent family specific to algorithmic fault tolerance or correlated decoding was found as of 2026-09-04.
Roadmaps & track record. QuEra: Libra promised 2026-06-15 for 2028 (>256 logical, 10⁻⁶) after a January 2024 promise of 100 logical qubits in 2026 — a two-year slip, so the schedule now leaning on constant-round fault tolerance has been reset once R[162]fact. Pasqal: 10,000 physical slipped 2026 to 2028 Rfact. Every atom roadmap past 2027 prices in this gain; none names it as a dependency.
Strategic reading. If it holds at scale, every transport-capable vendor's fault-tolerance date moves left at once and the millisecond atom cycle stops being disqualifying — the bet behind zoned architectures. Ions gain equally and are further along on transversal Cliffords, so the winner need not be an atom company. The losers are fixed nearest-neighbour superconducting lattices, which cannot claim the discount.
Outlook & open questions
Confirm/demote in 12–24 months: a group closes transversal gate, correlated decode and feed-forward on hardware; an atom system shows sustained below-threshold memory with reloading; QuEra restates Libra without the gain. Best case 2029: constant-round fault tolerance at 10³ logical qubits, compressing every transport-capable roadmap. Worst case: correlated decoding stalls at a few dozen blocks and stays a resource-estimation tool. Open: does decoder latency scale past 10⁴ blocks; does >10× survive loss-heavy noise. Watch: Libra milestones and any real-time correlated-decoder demonstration.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [9] H. Neven, “Building superconducting and neutral atom quantum computers,” Google, Mar. 24, 2026. [Online]. Available: https://blog.google/
innovation-and-ai/ Ctechnology/ research/ neutral-atom-quantum-computers/ - [30] M. Cain et al., “Shor's algorithm is possible with as few as 10,000 reconfigurable atomic qubits,” arXiv:2603.28627, Mar. 2026. S
- [31] H. Zhou et al., “Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays,” Proc. 52nd Annu. Int. Symp. Comput. Archit. (ISCA), 2025, doi: 10.1145/3695053.3731039. arXiv:2505.15907. S
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [152] H. Zhou et al., “Low-Overhead Transversal Fault Tolerance for Universal Quantum Computation,” Nature, vol. 646, no. 8084, pp. 303–308, 2025, doi: 10.1038/s41586-025-09543-5. arXiv:2406.17653. D
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Gquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Gatom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [155] L. Roady, “Infleqtion Becomes First Neutral-Atom Quantum Company to Go Public,” Infleqtion, Feb. 17, 2026. [Online]. Available: https://infleqtion.com/
infleqtion-becomes-first-neutral-atom-quantum-company-to-go-public/ G - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ G08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [667] A. Paetznick et al., “Improved quantum processor logical error rates via correction and detection,” Nature, vol. 654, no. 8118, pp. 349–355, Jun. 2026, doi: 10.1038/s41586-026-10628-y. D
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Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime)
Codes that flag any single fault and discard the run instead of correcting it: [[4,2,2]], the distance-2 surface code, the [[k+2,k,2]] iceberg code and spacetime checks on Clifford circuits.
Verdict. Detection lifts post-selected circuit fidelity up to 236× above the bare circuit, at an acceptance that decays exponentially with circuit volume and with no distance to scale. The register's twelve carriers are all filed for detection runs; the ion machines, where the largest runs live, carry it only as an alternate to their high-rate codes.
[[n,k,d]] = n physical qubits carrying k logical qubits at distance d; acceptance = fraction of runs kept after post-selection; Λ = error-suppression factor per code-distance step; RB = randomised benchmarking; CZ = controlled-Z gate; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A distance-2 stabiliser code turns any single-qubit error into a non-trivial syndrome but cannot locate it, so the run is discarded (post-selected), not repaired. Members: [[4,2,2]], checks XXXX and ZZZZ; the distance-2 rotated surface code [[4,1,2]]; Quantinuum's iceberg code [[k+2,k,2]] D[673]; and spacetime codes, which treat a Clifford circuit's outcome bits as a code and add checks that catch faults anywhere in it S[710]. Fault-tolerant detection dates from 2017: [[4,2,2]] on trapped ions D[711] and on IBM's five-qubit cloud chips D[712]. The d=2 surface code followed on transmons at ETH Zürich D[713] and QuTech D[714], and Google ran a small surface-code detection experiment beside its repetition codes D[715].
Carrier-agnostic; static wiring; no control or readout of its own; stochastic Pauli errors only — leakage and loss need their own flags.
Physics & limits
One fault flips a check, so an undetected logical error needs two: post-selected infidelity scales as O(ε²), not O(ε) — how IBM's encoded magic state beat every physical qubit pair on its chip D[716]. The price is acceptance. With N fault locations each faulting detectably with probability p, acceptance ≈ e^(−pN) and the sampling overhead, its inverse D[717], is e^(pN) — ~2×10⁴ runs per kept sample at p = 10⁻³, N = 10⁴ — while residual error grows as ~Np² S. A fixed distance-2 code has no threshold and no Λ; circuit volume, not code size, sets the exponent. Iceberg rotations are compiled non-fault-tolerantly, letting some single faults through D[673]. A threshold returns only when detection codes are concatenated and upper levels correct: Knill's C4/C6 scheme gave evidence for computing above 3% error per gate S[718], and concatenated iceberg codes suppress post-selection by raising the distance D[105].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2017-10 | [[4,2,2]] fault-tolerant encoding and syndrome measurement | Maryland, trapped ions | D[711] |
| 2019-02 | [[4,2,2]] logical RB: two-qubit infidelity 5.8(2)% → 0.60(3)% | Harper & Flammia, IBM cloud | D[719] |
| 2020-06 | d=2 surface code, 7 transmons, logical initialisation 96.1% | ETH Zürich | D[713] |
| 2024-01 | Iceberg: 8 logical qubits, up to 256 layers, logical quantum volume 2⁸ | Quantinuum H1-2 | D[673] |
| 2025-04 | Spacetime checks: 50 logical qubits, 2,450 CZ, fidelity gain up to 236× | IBM Heron (ibm_kingston) | D[717] |
| 2025-11 | d=2 surface: transversal CNOT 88.9(5)%, logical Bell 79.4–79.5% | Origin Wukong | D[720] |
| 2026-02 | Iceberg and concatenated iceberg: 48–94 logical qubits beyond break-even | Quantinuum Helios | D[105] |
| 2026-09 | Spacetime-coded sampling: 76 physical qubits, 10× gate-error suppression, fidelity ≥ 0.349 (95%) | IBM/UChicago | D[46] |
Best demonstrated as of 2026-09-26: Helios' 94 iceberg-detected logical qubits D[105]. Dominant term: acceptance, rarely printed beside the headline.
Manufacturing, materials & supply chain
Nothing is fabricated for detection; its supply chain is the host machine's. Connectivity decides the code: on heavy-hex, [[4,2,2]] uses flag qubits — extra ancillas that catch faults spreading out of a syndrome circuit D[716]; iceberg's global parity checks suit all-to-all ion traps D[673]; spacetime checks are searched for under whatever connectivity the chip has D[717].
Control, readout & I/O burden
Detection needs syndrome bits, not a decoder in the loop: discarding can follow the run, so there is no latency budget unless preparation is adaptive D[716]. Wukong read its stabilisers from the final data measurement alone, with no mid-circuit readout D[720]. The burden is shots: injection on ibm_fez kept 36.28(9)% of runs, ~2.8 runs per state D[721]; QPU time grows as e^(pN) S.
Role in the stack
Slot 7 of three architectures: Transmon lattice with tunable couplers; Trapped ions — QCCD (transport between zones); Trapped ions — linear Paul trap with individual laser addressing. It requires syndrome measurement (dispersive readout on transmons). It provides post-selected logical states and gates, a first rehearsal of transversal logic D[720], and the discard stage of magic-state preparation: ibm_fez injection gave |HL⟩ 0.8806(2) and |TL⟩ 0.8665(3), above the 0.854 and 0.827 distillation thresholds D[721]. It is replaced by the rotated surface code — correction instead of detection. Algorithmic fault tolerance takes nothing further: its guarantee is exponential in distance S[152].
The register lists twelve carriers, seven primary and five alternate. The superconducting ones are all primary. IBM Quantum Heron r2 D[721], IBM Quantum Heron r3 (ibm_pittsburgh) D[46], Origin Wukong (3rd gen) D[720] and the IQM six-qubit star QPU (Deneb-class), 0.25(2)–0.91(3)% logical error per [[4,2,2]] cycle D[488], match their evidence; Origin Wukong 102 is listed by inference from the Wukong paper. IBM Quantum Falcon r5.11 is carried by the [[4,2,2]] magic state on ibm_peekskill D[716], not by its distance-3 subsystem code, decoded by matching with only leakage post-selected (4.37–4.91% of shots per round) — correction D[722]. Rigetti Ankaa-2 is not a carrier: its 8-qubit stability experiment was decoded in real time, with no post-selection reported D[723]. The alternates are ion machines: System Model H1 (H1-1), for the iceberg run on H1-2 D[673], and Helios D[105]; the iceberg run on H2-1 (up to 20 logical qubits) D[724] is not listed. A quantum-dot spin device is primary too: HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots). This answers gap G-detect7: transmon slot 7 listed only correcting codes, while what shipped was detection.
Evidence — how the numbers were measured
Every headline here is conditional on acceptance: Harper & Flammia's 0.60(3)% is logical RB inside the code space D[719]; Wukong's gates and the ibm_fez states are post-selected D[720]D[721]. Acceptance belongs beside every fidelity, and the physical baseline deserves the same discard. Microsoft and Quantinuum report correction and detection on the same codes, 11× to 800× below physical baselines D[667]. Detection can also certify: IBM's spacetime-coded sampling bounds fidelity from syndrome statistics, device-dependent but under weaker assumptions than proxy benchmarks D[46] — fidelity, not hardness: version 1's 70-qubit circuit (bound 0.284) was simulated classically in 37.3 min on 256 H100 GPUs, log-XEB 0.350 D[47]; version 3 (2026-09-02) reports 76 physical qubits and a bound of 0.349 D[46].
Not published: the acceptance rate of Helios' 94-logical-qubit iceberg runs.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IBM | developer | US | [[4,2,2]] magic state on Falcon; spacetime checks on Heron | D[716]D[717] |
| Quantinuum | developer | US/UK | Iceberg code on H1-2, H2-1 and Helios | D[673]D[105] |
| Origin Quantum | developer | CN | d=2 surface-code logical gate set on Wukong | D[720] |
| IQM | developer | FI | [[4,2,2]] on a star-topology processor | D[488] |
Money. No dated financial item is specific to error-detection codes as of 2026-09-26; they are paid for inside machine and research budgets.
Market & supply chain. Nobody sells detection; vendors sell QPU time, which detection multiplies by 1/acceptance. It pays into G2 — IBM reports lower sampling overhead than error mitigation D[717] — and into G3 only as rehearsal and state-preparation discard.
IP & standards. No detection-specific patent family or reporting standard found as of 2026-09-26; the codes are published D[673]S[710].
Roadmaps & track record. No vendor roadmap sets a detection milestone. Quantinuum moved from distance-2 iceberg (2024) to distance-4 concatenated iceberg (2026) within one code family D[673]D[105].
Strategic reading. Detection is the honest NISQ-to-QEC step: encoding, fault-tolerant preparation and logical gates at a stated discard cost, no scaling claimed. It favours platforms whose fidelity keeps pN small — the largest runs are on ions D[105] — and gives transmon vendors a compiler-level route to better G2 circuits. It undercuts only reporting that calls a distance-2 block a fault-tolerant logical qubit.
Outlook & open questions
Confirm if by 2027-12-31 a detection-certified sampling run holds a fidelity bound above 0.3 on a circuit no published classical method reproduces within a week; demote to history if by 2028-12-31 magic-state preparation and utility circuits on transmons and ions run with correction, not discard. Open questions. (1) Where do detection and probabilistic error cancellation cross in sampling cost at 100–150 qubits? (2) How much gain survives a baseline given the same leakage discard? (3) Can spacetime checks leave the Clifford regime, where valid checks thin out exponentially D[717]? (4) What acceptance do Helios' 94-qubit iceberg runs keep at depth? (5) Is concatenated detection a cheaper route to early fault tolerance on 2D chips than surface-code memories?
References
- [46] S. Martiel et al., “Sampling hard circuits with verifiably high fidelity,” arXiv:2607.25941, Jul. 2026. D
- [47] H. Manabe, H. Gu, and F. Pan, “Classical Simulation and Design Frontiers for IBM's Doped Clifford Sampling Experiment,” arXiv:2608.13110, Aug. 2026. D
- [105] S. Dasu et al., “Computing with many encoded logical qubits beyond break-even,” arXiv:2602.22211, Feb. 2026. D
- [152] H. Zhou et al., “Low-Overhead Transversal Fault Tolerance for Universal Quantum Computation,” Nature, vol. 646, no. 8084, pp. 303–308, 2025, doi: 10.1038/s41586-025-09543-5. arXiv:2406.17653. S
- [488] F. Vigneau et al., “Quantum error detection in qubit-resonator star architecture,” arXiv:2503.12869, Mar. 2025. D
- [667] A. Paetznick et al., “Improved quantum processor logical error rates via correction and detection,” Nature, vol. 654, no. 8118, pp. 349–355, Jun. 2026, doi: 10.1038/s41586-026-10628-y. D
- [673] C. N. Self, M. Benedetti, and D. Amaro, “Protecting expressive circuits with a quantum error detection code,” Nat. Phys., vol. 20, no. 2, pp. 219–224, Jan. 2024, doi: 10.1038/s41567-023-02282-2. arXiv:2211.06703. D
- [710] N. Delfosse and A. Paetznick, “Spacetime codes of Clifford circuits,” arXiv:2304.05943, Apr. 2023. S
- [711] N. M. Linke et al., “Fault-tolerant quantum error detection,” Sci. Adv., vol. 3, no. 10, Art. no. e1701074, Oct. 2017, doi: 10.1126/sciadv.1701074. arXiv:1611.06946. D
- [712] C. Vuillot, “Is error detection helpful on IBM 5Q chips?,” Quantum Inf. Comput., vol. 18, no. 11&12, pp. 949–964, 2018. arXiv:1705.08957. D
- [713] C. K. Andersen et al., “Repeated quantum error detection in a surface code,” Nat. Phys., vol. 16, no. 8, pp. 875–880, Jun. 2020, doi: 10.1038/s41567-020-0920-y. arXiv:1912.09410. D
- [714] J. F. Marques et al., “Logical-qubit operations in an error-detecting surface code,” Nat. Phys., vol. 18, p. 80, 2022, doi: 10.1038/s41567-021-01423-9. arXiv:2102.13071. D
- [715] Z. Chen et al., “Exponential suppression of bit or phase errors with cyclic error correction,” Nature, vol. 595, pp. 383–387, Jul. 2021, doi: 10.1038/s41586-021-03588-y. D
- [716] R. S. Gupta et al., “Encoding a magic state with beyond break-even fidelity,” Nature, vol. 625, pp. 259–263, Jan. 2024, doi: 10.1038/s41586-023-06846-3. arXiv:2305.13581. D
- [717] S. Martiel and A. Javadi-Abhari, “Low-overhead error detection with spacetime codes,” arXiv:2504.15725, Apr. 2025. D
- [718] E. Knill, “Quantum computing with realistically noisy devices,” Nature, vol. 434, pp. 39–44, Mar. 2005, doi: 10.1038/nature03350. arXiv:quant-ph/0410199. S
- [719] R. Harper and S. T. Flammia, “Fault-Tolerant Logical Gates in the IBM Quantum Experience,” Phys. Rev. Lett., vol. 122, no. 8, Art. no. 080504, Feb. 2019, doi: 10.1103/PhysRevLett.122.080504. arXiv:1806.02359. D
- [720] J. Zhang et al., “Demonstrating a universal logical gate set in error-detecting surface codes on a superconducting quantum processor,” npj Quantum Inf., vol. 11, Art. no. 177, Nov. 2025, doi: 10.1038/s41534-025-01118-6. D
- [721] Y. Kim, M. Sevior, and M. Usman, “Magic state injection on IBM quantum processors above the distillation threshold,” Sci. Rep., vol. 16, Art. no. 11189, Feb. 2026, doi: 10.1038/s41598-026-40381-1. arXiv:2412.01446. D
- [722] N. Sundaresan et al., “Demonstrating multi-round subsystem quantum error correction using matching and maximum likelihood decoders,” Nat. Commun., vol. 14, Art. no. 2852, May 2023, doi: 10.1038/s41467-023-38247-5. D
- [723] L. Caune et al., “Demonstrating real-time and low-latency quantum error correction with superconducting qubits,” Nat. Commun., vol. 17, Art. no. 7383, Jun. 2026, doi: 10.1038/s41467-026-73331-6. arXiv:2410.05202. D
- [724] Z. He, D. Amaro, R. Shaydulin, and M. Pistoia, “Performance of quantum approximate optimization with quantum error detection,” Commun. Phys., vol. 8, Art. no. 217, May 2025, doi: 10.1038/s42005-025-02136-8. arXiv:2409.12104. D
Русский текст загружается…
הטקסט בעברית נטען…
Fusion-based fault tolerance
A fault-tolerant code assembled from destructive linear-optical fusions on pre-made photonic resource states, tolerating 2.7–17.4% photon loss in theory and never run end-to-end.
Verdict. Real: loss thresholds derived in simulation, 2.7% (boosted 6-ring) to 17.4% ({7,4} encoded). Unproven: any hardware run of the scheme; only components exist. Demote if no fusion-lattice demonstration by 2029.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A fault-tolerant architecture with no deterministic two-qubit gate: pre-made photonic resource states are consumed by destructive linear-optical fusions, and the code lives in the pattern of which fusions succeeded, failed or reported loss. Bartolucci, Birchall, Bombín and colleagues at PsiQuantum formalised it with thresholds in 2023 S[179]. It replaces GKP-bosonic concatenation as photonics' route to fault tolerance. Attributes: flying photons, no native control modality and no clock of its own; pure-loss errors, no manufacturing precursor beyond fusion and resource-state generation.
Physics & limits
Loss is the design variable: a lost photon turns a fusion into a heralded erasure at a known location; an intrinsic failure erases one of its two outcomes, and the decoder routes around both. Hence unusually high tolerances — 2.7% loss per photon with a boosted 6-ring, 17.4% with a {7,4}-encoded state of ~168 photons nobody can make S[179]. The catch sits below threshold. A 2026 re-analysis shows fusion failure alone, at zero physical loss, leaves a logical-error floor shrinking only with code distance, so being under threshold says nothing about the overhead for 10⁻¹⁰; emitter-mediated fusion raises the threshold to 7.0–7.3% against an unencoded 6-ring's 0.38–0.82% S[264]fact. Moving the floor takes lower-loss photonics, boosted fusion, or emitters.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2023-02 | FBQC framework and thresholds derived | Bartolucci et al., PsiQuantum | S[179] |
| 2025-02 | Component fusion Bell fidelity 99.22% | PsiQuantum | D[169] |
| 2025-06 | Loss threshold 2.7% (boosted 6-ring) to 17.4% ({7,4}) | theory | S[179] |
| 2026-06 | Fusion-failure floor at zero loss; 7.0–7.3% emitter threshold | Sparrow | S[264] |
On the report's cross-platform table photonics scores zero on every fault-tolerance primitive: no below-threshold scaling, no logical qubit past break-even, no logical two-qubit gate, detection-only decoding D[687].
The 6-ring loss thresholds are not comparable: 2.7% per photon for a boosted 6-ring [179] against 0.38–0.82% (static bias) for an unencoded 6-ring [264], under different boosting, bias models and decoders. Every fusion threshold is a simulation, none is measured, and no independent group has reproduced them. As of 4 Sep 2026 PsiQuantum has published no response to the 2026-06 subthreshold critique and no 2026 hardware result; its progress is visible only through DARPA V&V contracting.
Manufacturing, materials & supply chain
Nothing is manufactured for this code; it inherits the photonic-IC stack of its inputs (300 mm silicon at GlobalFoundries) Cfact. No yield, cost or energy figure exists because nothing runs it. The burden it imposes is synchronisation: a {7,4}-encoded state means ~168 photons per round, each with a source, switch path and detector channel, against a record of 8 fused photons at 0.4–2.3 per minute D[688]. At 10³ fusions/s the constraint is switch loss; at the 10⁶ a useful machine needs, cryogenic detector channels and GHz feed-forward, neither built. ECCN 4A906 covers the assembled machine fact.
Role in the stack
Requires linear-optical fusion and a resource-state generator (RSG), neither at code-relevant scale, and provides nothing downstream — it tops the photonic fusion architecture (PsiQuantum, Quandela, QuiX). It replaces GKP-bosonic concatenation, and the switch is total: different carrier, detectors, error model. Its MHz cycle is a design claim, not a measurement: the real cycle is resource-state supply, ~0.4–2.3 per minute D[688]. Verification: the thresholds are decoder simulations under stated noise models, never measured or independently reproduced; the 2026 re-analysis is the first published challenge to the framework's relevance, unanswered as of 4 Sep 2026.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | Originated FBQC; sole roadmap bet on it | S[179] |
| Quandela | developer | FR | Fields compatible linear-optical hardware | Cfact |
| Sparrow Quantum | research | DK | Published the 2026 subthreshold critique | Sfact |
| DARPA | investor | US | QBI Stage C V&V of PsiQuantum's stack | fact |
Money.
2024-04 · PsiQuantum · Australian federal and Queensland commitment · A$940 M · announced Pfact
2025-09-10 · PsiQuantum · Series E · USD 1 B at USD 7 B · closed fact
2026-05-21 · PsiQuantum · US CHIPS letter of intent · USD 100 M · non-binding fact
2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · USD 125 M · definitive fact
Market & supply chain. No product, no market: the asset is a roadmap plus government commitments; the suppliers that matter sit upstream. Pays for G3/G4 alone.
IP & standards. No dated patent family specific to the fusion-lattice code as of 4 Sep 2026; nearest is ORCA's US 12,437,225 fact.
Roadmaps & track record. (2024-04 · Brisbane machine useful by end-2027 · at risk: site moved to Moreton Bay, groundbreaking slipped to 2026-06, Linde cryoplant not due for delivery until 2H 2027 Cfact) Pfact. Strong paper record, weak schedule.
Strategic reading. If the subthreshold critique holds, the largest privately funded photonics bet needs a far lower-loss network or a pivot to emitter hybrids — a redesign for a company already late. Winners if it works: PsiQuantum, its foundry, detector vendors; losers: bosonic GKP and anyone selling a fast gate rather than cheap erasure.
Outlook & open questions
Confirm by 2028: an end-to-end fusion-lattice demonstration at any code distance with measured loss and logical error; demote if only component numbers persist. Best case 2029: a small working lattice. Worst case: it stays a paper and emitter hybrids inherit it. Open: does anyone rebut the 2026 critique; which threshold survives hardware; does Stage C publish a code-level number.
Fusion networks need not carry a whole computation: a 2026 construction confines them to the seam of distributed surface-code lattice surgery between matter-qubit processors, where 'hybrid checks' combine local ancilla readouts with the fusion outcomes of photonic resource states P[893]. In simulation with no local noise, the seam tolerates erasure of 50% of fusion outcomes (38% and 32% with resource chains truncated to eight and five qubits) and the merge observable's interface distance rises from d + 1 to 2d + 1; at circuit and resource-state error rates of 10⁻³, local errors largely mask that advantage, and resource-state generation is not modelled P[893].
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [179] S. Bartolucci et al., “Fusion-based quantum computation,” Nat. Commun., vol. 14, Art. no. 912, Feb. 2023, doi: 10.1038/s41467-023-36493-1. arXiv:2101.09310. S
- [264] M. C. Löbl, L. A. M. Pettersson, J. Dragašević, S. X. Chen, and O. A. D. Sandberg, “The subthreshold issue of fusion-based quantum computing,” arXiv:2606.28490, Jun. 2026. S
- [687] R. Neeman, “Quantum Technology Atlas,” ed. 2026.09, Qodeh, Sep. 2026, §3.2. D
- [688] P. Thomas, L. Ruscio, O. Morin, and G. Rempe, “Fusion of deterministically generated photonic graph states,” Nature, vol. 629, no. 8012, pp. 567–572, May 2024, doi: 10.1038/s41586-024-07357-5. D
- [893] F. Burt et al., “Loss-tolerant distributed lattice surgery using fusion networks,” arXiv:2610.01923, Oct. 2026. P
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הטקסט בעברית נטען…
Error mitigation in the code slot (ZNE, PEC) — not a code
Classical post-processing of many noisy runs — zero-noise extrapolation, probabilistic error cancellation or amplification, readout twirling, tensor-network noise inversion — that removes bias from expectation values without encoding, detecting or correcting a single error.
Verdict. The only error handling in most utility-scale superconducting experiments, including two of IBM's three July-2026 advantage claims; it buys bias reduction at a shot cost exponential in the circuit's error mass and yields no logical qubit, so as of 2026-09-26 it is a placeholder for a code, not a step towards one.
ZNE = zero-noise extrapolation; PEC = probabilistic error cancellation; PEA = probabilistic error amplification; TREX = twirled readout error extinction; TEM = tensor-network error mitigation; γ = norm of the signed mixture that inverts the noise; P = summed Pauli error probability in an observable's backward light cone (the gates that can affect it); CZ = controlled-Z; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Error mitigation estimates an observable's noiseless expectation value from many noisy runs and classical post-processing; nothing is encoded, no syndrome is measured, no error corrected G[693]. Temme, Bravyi and Gambetta proposed extrapolation to zero noise by Richardson's method and cancellation by quasi-probability resampling in 2016 D[694]; Li and Benjamin independently extrapolated boosted errors to zero D[695]. Hardware ZNE followed in 2019 D[696]; then PEA, amplifying a learned noise model with injected Pauli errors D[308], TREX for readout C[693] and TEM, a tensor-network inverse of the global noise S[697]. Attributes: platform-agnostic, static, no transport or control modality; Pauli error class after twirling.
Physics & limits
PEC writes each layer's inverse noise as a signed mixture of implementable operations of norm γ ≥ 1; the estimate is unbiased, but shots grow as γ² and γ exponentially with depth C[693]. For Pauli noise γ ≈ e^(2P), so shots multiply by ≈ e^(4P) S. At Heron r3's median CZ error of 0.15% D[698], 1,000 CZs in the light cone give P ≈ 1.5 and ≈ 400× the shots, 7,500 give ~10¹⁹× S; today's 10²–10³× budgets cap P near 1.2–1.7 S. ZNE samples at amplified noise — by default three factors, nominally ~3× C[693] — and extrapolates; it is biased by its fit and must resolve a signal attenuated by up to e^(−2P), so its cost grows comparably S. TEM claims the square root of PEC's overhead S[697], still exponential S. The limit is general: overhead grows exponentially with depth for any protocol under local depolarising noise D[699], nonlinear post-processing included D[700], and worst-case estimation needs superpolynomially many samples at shallow depth D[701]. Only lower physical error moves the exponent.
Under local depolarising noise, a circuit's noisy expectation value is the Laplace transform of its reactivity function — the contribution of Pauli paths sorted by weight (the number of qubits a Pauli operator acts on non-trivially); inverting it exactly is ill-conditioned, with coefficients growing exponentially in weight, and only smoothed features in weight are recoverable, at a sampling cost exponential in the ratio of weight to resolution P[891]. The Atlas's reading, not derived in the paper: noise-scaling mitigation attempts the same inversion, so its cost is set by the circuit's high-weight Pauli content, not by the error rate alone.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2019-03-27 | ZNE by stretched pulses; variational chemistry and magnetism | IBM, Kandala et al. | D[696] |
| 2023-05-08 | PEC with a learned sparse Pauli–Lindblad model, crosstalk included, 20 qubits | IBM, van den Berg et al. | D[702] |
| 2023-06-14 | 127 qubits, up to 60 layers, 2,880 CNOTs; ZNE with PEA | IBM Eagle, Kim et al. | D[308] |
| 2023-06/08 | Classical reproductions: tensor network more accurate than the hardware; Pauli dynamics on one laptop core; converged to <0.01 | Tindall et al.; Begušić, Chan; Begušić, Gray, Chan | D[309]D[703]D[704] |
| 2025-11-12 | "samplomatic" cuts PEC sampling overhead 100× | IBM | C[486] |
| 2026-07-27 | QESEM (PEC- and ZNE-based) on Heron r3, 51–74 qubits, up to 30 Floquet cycles; tensor networks fail to converge | Qedma, RIKEN, BlueQubit | D[233] |
| 2026-07-28 | PEC on 56 qubits, circuits up to ~1,000 CZs: ~1.5 h and ~4 h of QPU time at two depths | Algorithmiq et al., ibm_boston | D[698] |
| 2026-08-31 | PEA observable estimation on 7,500-gate circuits | IBM Nighthawk r2 | C[601] |
The 2023 claim of accuracy "beyond brute-force classical computation" D[308] was matched classically within weeks, and converged values exposed bias in its extrapolation D[704]; the 2026 claims rest on classical heuristics disagreeing, not on proven hardness D[698]. Dominant term: P. Faster shots — Nighthawk r2's 100,000 circuits per second, 25× Heron — shorten wall-clock time, not the exponent C[601].
Manufacturing, materials & supply chain
Nothing is fabricated; the bill is QPU time and classical compute — 3.2 million shots, ~45 min of QPU time per point for Algorithmiq's rescaled estimate D[698]. Supply is the vendor runtime C[693] plus Qedma's QESEM, which learns device noise, adapts circuits and post-processes C[705], and Algorithmiq's TEM in IBM's Qiskit Functions Catalog C[706].
Control, readout & I/O burden
The requirement is a calibrated, stable noise model: PEA and PEC learn a sparse Pauli–Lindblad model per layer of entangling gates under random Pauli twirling D[308]D[702]; every circuit is compiled in many randomised instances S. TREX randomises measurements with X gates and classical bit flips, diagonalising the readout matrix for inversion C[693]. Drift is the failure mode: a model learned before a four-hour PEC run is wrong by whatever drifts during it S. There is no feed-forward, and the output is expectation values, not samples G[693].
Role in the stack
Slot 7 of the Transmon lattice with tunable couplers architecture, beside code_surface, code_color, code_qldpc, code_magic and code_detect. It requires ct_rt, for calibrated noise models; it provides nothing downstream — no logical qubit, no syndrome for slot 8's decoders; it is replaced by code_surface, and the open conflict edge (2023-06) lists no remedy for its exponential overhead. code_detect discards flagged runs at a cost of 1/acceptance, also exponential in circuit size; mitigation keeps every run and reweights, removing bias only on average S. The gap ledger's "all three IBM July-2026 advantage claims" is two of three — QESEM on Heron r3 D[233] and PEC on ibm_boston D[698]; IBM–UChicago's post-selects on spacetime codes, a code_detect result C[45]. The ledger's ion placement was not taken, though Qedma repeated cycles on Quantinuum H2 and Helios D[233]. Register: IBM Eagle r1–r3 (primary, retired); Heron r3 and Nighthawk r2 (alternate).
Evidence — how the numbers were measured
PEC is unbiased, with error bars, if its noise model is right, so verification becomes validating the model C[45]. Of the register's three cells, Heron r3's and Nighthawk r2's are verified ✅ — the first by the July-2026 ibm_boston preprints D[233], [698], the second by a section of the r2 blog C[601] — and Eagle's is 🔎, though its source supports it D[308]. Heron r1 and Nighthawk r1 hold no code: no primary source shows a named mitigation method run on r1 itself, and the press article on r3 that its cell cites names none P[707]. Zuchongzhi 3.0 and Tianyan-287 run random-circuit sampling scored on raw fidelity; their abstracts mention neither mitigation nor correction D[35]D[708], so as of 2026-09-26 their code slot is empty, not mitigated.
IBM's 100× PEC-overhead reduction by samplomatic (2025-11-12) is a blog claim. Not published: its baseline and circuit class, and the shot count, QPU time and observable of Nighthawk r2's 7,500-gate PEA run. The e^(4P) shot scaling and the P values are derived from the PEC construction and published error rates, not quoted from a source.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IBM | developer | US | TREX, ZNE, PEA, PEC in Qiskit Runtime; 2023 utility experiment; PEA at 7,500 gates | C[693]D[308]C[601] |
| Qedma | software vendor | IL | QESEM: noise learning, PEC- and ZNE-based estimators | D[233] |
| Algorithmiq | software vendor | IT (formerly FI) | TEM in IBM's catalogue; PEC in the Loschmidt-echo claim | C[706]D[698] |
| Flatiron Institute | research | US | Contributor to the open advantage tracker | C[486] |
Money.
- 2025-07-03 · Qedma · Series A led by Glilot Capital Partners, IBM participating · USD 26 M · announced C[705]
- 2026-05-11 · Algorithmiq · round led by United Ventures, with CDP and Inventure · EUR 18 M (EUR 36 M in total) · announced C[709]
Market & supply chain. Sold as runtime options and third-party functions on the hardware vendor's cloud, with IBM holding equity in Qedma: a vertically tied market. It pays into G2 only; G3–G4 need a code.
IP & standards. No standard defines a figure of merit for mitigated estimates or a noise-model disclosure format; no dated patent count from a named database, as of 2026-09-26.
Roadmaps & track record. IBM promised Nighthawk revisions at 5,000, 7,500, 10,000 and 15,000 gates R[486]; the 7,500-gate step, its 2026 milestone, shipped on 2026-08-31 with PEA C[601].
Strategic reading. Mitigation makes the noise model the product and keeps value inside the hardware vendor's stack. Only noise learning carries over to fault tolerance; when a code runs, the technology empties.
Outlook & open questions
Confirm if an unbiased PEC estimate on ≥5,000 gates appears with error bars by 2027-12-31, or a July-2026 claim survives to 2027-07-31 without converged classical reproduction; demote those claims to utility if converged tensor-network or Pauli-propagation values match them, as in 2023.
Open questions. (1) How stable is a learned Pauli–Lindblad model over a multi-hour run at 10³–10⁴ gates? (2) Does TEM's quadratic saving survive model error on hardware? (3) At what size does a detection code plus mitigation beat mitigation alone in shots? (4) Can a mitigated expectation-value task be proven classically hard? (5) What shot multiplier did Nighthawk r2's 7,500-gate PEA run spend?
References
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- [309] J. Tindall, M. Fishman, M. Stoudenmire, and D. Sels, “Efficient Tensor Network Simulation of IBM's Eagle Kicked Ising Experiment,” PRX Quantum, vol. 5, no. 1, Art. no. 010308, Jan. 2024, doi: 10.1103/PRXQuantum.5.010308. arXiv:2306.14887. D
- [486] R. Mandelbaum, “Scaling for quantum advantage and beyond,” IBM Quantum Computing Blog, Nov. 12, 2025. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ qdc-2025 - [601] H. Haas, D. McKay, and R. Davis, “IBM Quantum Nighthawk r2—more circuits, faster,” IBM Quantum Computing Blog, Aug. 31, 2026. [Online]. Available: https://www.ibm.com/
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docs/ Cen/ guides/ error-mitigation-and-suppression-techniques - [694] K. Temme, S. Bravyi, and J. M. Gambetta, “Error mitigation for short-depth quantum circuits,” Phys. Rev. Lett., vol. 119, Art. no. 180509, 2017, doi: 10.1103/PhysRevLett.119.180509. arXiv:1612.02058. D
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- [696] A. Kandala et al., “Error mitigation extends the computational reach of a noisy quantum processor,” Nature, vol. 567, pp. 491–495, Mar. 2019, doi: 10.1038/s41586-019-1040-7. arXiv:1805.04492. D
- [697] S. Filippov, M. Leahy, M. A. C. Rossi, and G. García-Pérez, “Scalable tensor-network error mitigation for near-term quantum computing,” arXiv:2307.11740, Jul. 2023. S
- [698] S. V. Barron et al., “Observable Estimation in the Absence of Classical Verification,” arXiv:2607.25998, Jul. 2026. D
- [699] R. Takagi, S. Endo, S. Minagawa, and M. Gu, “Fundamental limits of quantum error mitigation,” npj Quantum Inf., vol. 8, Art. no. 114, 2022, doi: 10.1038/s41534-022-00618-z. arXiv:2109.04457. D
- [700] R. Takagi, H. Tajima, and M. Gu, “Universal Sampling Lower Bounds for Quantum Error Mitigation,” Phys. Rev. Lett., vol. 131, Art. no. 210602, 2023, doi: 10.1103/PhysRevLett.131.210602. arXiv:2208.09178. D
- [701] Y. Quek, D. S. França, S. Khatri, J. J. Meyer, and J. Eisert, “Exponentially tighter bounds on limitations of quantum error mitigation,” Nat. Phys., vol. 20, p. 1648, 2024, doi: 10.1038/s41567-024-02536-7. arXiv:2210.11505. D
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Neural decoders (AlphaQubit 2, CNN, transformers)
Learned syndrome decoders — recurrent transformers, CNNs, LSTMs, state-space models — that beat matching by absorbing non-Pauli device noise from data.
Verdict. The accuracy lead is real, but real-time speed is shown only on recorded or simulated data, to distance 11, and live only at distance 3; the open question is whether the lead survives live throughput and drift beyond distance 11.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A neural decoder replaces the combinatorial inference step of error correction with a trained function approximator: syndrome history in, logical correction out. Decoding is Bayesian inference over a detector-error hypergraph, and minimum-weight perfect matching is exact only when that hypergraph is graphlike — every error flips at most two detectors, with independent, known, static probabilities. Real devices break all three: leakage parks a qubit outside the computational subspace for many rounds, correlated bursts couple distant detectors, readout is analogue before thresholding, and noise drifts. A learned decoder fits the joint distribution from labelled data instead, consuming soft readout and leakage flags matching cannot represent. The lineage runs from convolutional decoders (2017) to the recurrent-transformer AlphaQubit, published by Google DeepMind with Google Quantum AI on 2024-11-20 D[657]fact, and to AlphaQubit 2, named in the July 2026 Willow paper as "a scalable and real-time neural decoder for topological quantum codes" D[2].
Attributes: carrier affinity 0.5 and no carrier of its own; no characteristic time or entangling operation, inheriting the host's syndrome period (1.1 µs on Willow D[1]fact); no readout, though it consumes the soft values matching discards; no mobility beyond the detector-error graph it was trained on; no control modality — placement is the variable, room-temperature logic today, cold silicon proposed; Pauli error structure, with its value in the non-Pauli residue; no manufacturing of its own.
Physics & limits
The floor is information-theoretic and computational, not physical: the ceiling is maximum-likelihood decoding, and matching sits measurably below it. On Sycamore data AlphaQubit reached 2.748(15)×10⁻² logical error per round at distance 5 against 2.915(16)×10⁻² for the tensor-network decoder, an approximate maximum-likelihood decoder, and 2.901(23)×10⁻² versus 3.028(23)×10⁻² at distance 3 — about 6% and 4% fewer errors D[657]; against correlated matching at distance 5 it made ~30% fewer C[731]. On simulated data with crosstalk and leakage, correlated matching tuned to that noise and fed the analogue readouts made 1.25× AlphaQubit's errors at distance 3, 1.4× at 9 and 1.25× at 11 D[657]. The lead holds out to distance 11 without growing steadily, and it comes from noise outside matching's model — crosstalk and leakage.
The computational limit is the backlog condition: a decoder slower than the syndrome rate accumulates an unbounded queue and the logical clock stalls, which on a transmon means roughly 10⁶ decode-rounds per second per logical qubit. Google's 2024 framing: AlphaQubit "is still too slow to correct errors in a superconducting processor in real time" C[731]. Cost scaling is architectural: attention over a distance-d patch is O(d⁴) per round against O(d²) for a state-space recurrence, and the cheaper model measured a higher real-time threshold, 1.04% versus 0.97%, because latency-induced degradation belongs in that figure of merit S[732].
Failure modes are statistical: distribution shift degrades a fine-tuned model with no error signal, retraining needs data from the same processor, and there is no proved threshold, only a measured one. Soft information, joint training with the calibration loop and O(d²) architectures would move the floor.
Engineering state of the art
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-11 | Distance-5 Sycamore memory 2.748(15)×10⁻²/round vs 2.915(16)×10⁻² for the tensor-network decoder (~6% fewer errors); at simulated distance 11 matching makes 1.25× as many errors | Google DeepMind (AlphaQubit) | D[657]fact |
| 2025-10 | State-space decoder: real-time threshold 1.04% vs 0.97% transformer, O(d²) vs O(d⁴) per round | Yonsei University | S[732] |
| 2025-12 | Non-neural bar: clustering decoder under 1 µs/round to distance 17 on one Xilinx VU19P, ~6% of logic cells | Riverlane | D[238]fact |
| 2026-05 | First closed-loop neural decoding on hardware: 124 ns decode, 184 ns throughput period, 550 ns loop, distance 3, 6.9(2)%/round vs offline matching 7.2(2)% | International Quantum Academy | D[729] |
| 2026-07 | AlphaQubit 2 decodes the distance-7 Willow record, 7.72(9)×10⁻⁴ logical error per cycle, with no live decode stated; its own preprint times under 1 µs per cycle to distance 11 on TPUs, on recorded or simulated data | Google Quantum AI | D[2]fact |
Best demonstrated splits in two: for accuracy, the July 2026 Willow record, decoded with no live loop stated D[2]; for live operation, the Shenzhen distance-3 loop D[729]. Google's only live surface-code decode remains the 2024 distance-5 Willow run, on a Sparse Blossom matcher fact. Typical at scale is still matching or clustering; beyond Google, too, neural decoders run offline or without a stated real-time loop — on Zuchongzhi 3.2, the 448-atom fault-tolerant processor and Sqale. The decoder's own budget is dominated by model mismatch and latency, not arithmetic precision — the Shenzhen implementation quantised weights to 6-bit integers and lost nothing against offline matching D[729]. At system level the distance-7 record is limited by two-qubit gate and readout errors, and no Λ is reported for it D[2].
Manufacturing, materials & supply chain
The node is fabricated only through its host; three placements exist as of 3 Sep 2026. In room-temperature logic, the Shenzhen LSTM (32 hidden units, separate X and Z decoders, four pipelined stages on DSP blocks) fits a mid-range AMD Kintex-7 XC7K410T at distance 3, with current parts ceilinged near distance 13 D[729]; Riverlane's clustering decoder takes ~6% of the lookup tables of a Xilinx VU19P to distance 17 D[238]fact — a learned decoder buys accuracy with silicon. On graphics processors, NVQLink puts a GH200-class host in the loop at 3.84 µs mean round trip C[324]fact. In cold silicon, the "Pinball" cryo-CMOS predecoder claims 3,780× syndrome-bandwidth reduction under 0.56 mW at 4 K, but is an unfabricated design study S[733]fact.
AMD (Xilinx) and NVIDIA supply essentially all decode silicon, with no second source at the part sizes required. Yield is not a decoder problem; portability is — a fine-tune is per-processor, and nobody has published how many devices one trained model covers. Export exposure is indirect: the decoder ships as firmware in a control rack and inherits the accelerator's controls and the classification of the system it serves.
Control, readout & I/O burden
The burden is bandwidth and latency, not lines or lasers. A distance-7 patch produces 48 ancilla bits per 1.1 µs cycle — about 44 Mbit/s per logical qubit, so ~4.4 Gbit/s at 100 logical qubits and ~44 Gbit/s at 1,000, every bit needing a decision inside the feedback window. At 10³ physical qubits one mid-range part suffices. At 10⁴ the wall is aggregate: dozens of patches wanting sub-microsecond turnaround, and NVQLink's 3.84 µs round trip is three and a half Willow cycles — fine for millisecond-cycle ion and atom machines, marginal for transmons unless decode is local to the fridge C[324]fact. At 10⁶ neither room-temperature fabric nor a shared accelerator closes, and the syndrome must be reduced in the cold stage S[733]. The Shenzhen result proves the loop closes at all: 222 ns acquisition, 148 ns decoder logic and 180 ns electronic delay inside a 1.25 µs cycle D[729].
Role in the stack
It sits on the superconducting transmon architecture (Google, IBM, Rigetti, IQM, Oxford Quantum Circuits, USTC/Zhejiang, Fujitsu) and the alkali neutral-atom architecture (Harvard/MIT, QuEra, Pasqal, Infleqtion, Google), reaching both. It requires the rotated surface code and its yoked variants — every deployed model is trained on surface-code syndromes, and none has run on a sparse quantum parity-check code. It is not part of the in-loop reinforcement-learning calibration: that agent learns from the detection-event rate and reweights a matching graph, and AlphaQubit 2 decoded the calibrated record run separately D[2]. It replaces minimum-weight perfect matching at an asymmetric switching price — going learned costs a training pipeline, per-device fine-tuning and worst-case guarantees; going back costs only accuracy.
Nothing in the architecture is superconducting-specific, so the same family serves millisecond-cycle atom machines offline and microsecond-cycle transmons only with dedicated silicon; only the training data and latency budget differ. Contribution to the derived clock (derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture): zero while decode latency stays under the syndrome period — 0.65 µs derived on the transmon architecture — which it does live only at distance 3, where feedback-conditioned operations consume 0.55 µs of a 1.25 µs cycle D[729], and to distance 11 only on recorded or simulated data fact. Neighbouring empty slots: a fabricated cryogenic neural-decoder ASIC, and a learned decoder for bivariate bicycle codes on hardware.
Evidence — how the numbers were measured
Headline numbers come from memory experiments — run N syndrome rounds, fit logical fidelity against N — decoded offline or, since 2026, in the loop. The protocol misses three things. The baseline is a choice: on the same distance-5 Sycamore data AlphaQubit makes ~6% fewer errors than the tensor-network decoder D[657] but ~30% fewer than correlated matching C[731], and 20–29% fewer than matching in simulation to distance 11 D[657] — so a single band over matching mixes two baselines. Generalisation is untested: a model fine-tuned on one processor and evaluated on it is not evidence of transfer. And latency distributions are rarely reported, though only the tail causes backlog.
Conflicts: none over AlphaQubit — the blog's "6% fewer errors than tensor network methods" and "30% fewer errors than correlated matching" both describe the largest Sycamore experiments C[731] and agree with the Nature figures, 5.7% below the tensor-network decoder at distance 5 D[657]; the two percentages differ by baseline, not by regime. Riverlane's Series C is announced as $75 M (2024-08-06) but its 2026 roadmap states "$85 million in 2024" and "$120 million+" total C[661]fact; trust the 2024 release. No group has replicated AlphaQubit 2 on non-Google hardware as of 3 Sep 2026.
AlphaQubit 2's own paper is a preprint (arXiv:2512.07737, v2 2026-03-11) whose timings of under 1 µs per cycle to distance 11 on Trillium TPUs come from recorded or simulated data; neither it nor the July 2026 Nature paper [2] states that the distance-7 decode ran live fact. The real-time thresholds of [732] are simulated, under a standard superconducting circuit-noise model (SI1000) with injected noise standing for decoder latency. On neutral atoms, machine-learning decoding has one primary source: atom-loss information plus machine-learning decoding improved QEC performance 1.73(13)× over conventional decoding on Harvard/MIT/QuEra data from up to 448 atoms, decoded in post-processing, and the gain is unreplicated outside that dataset [4]. Not published: a Λ for the distance-7 AlphaQubit 2 run, so the decoder's share of the gain cannot be separated from that of the reinforcement-learning calibration, and a dated patent-family count for neural decoders.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Google DeepMind | developer | UK | AlphaQubit and AlphaQubit 2 architecture and training | D[2], [657] |
| Google Quantum AI | developer | US | Decoded the distance-7 Willow record with AlphaQubit 2, no live decode stated | D[2] |
| Riverlane | supplier | UK | Sells the deterministic rival (clustering decoder, Deltaflow) | D[238]C[658] |
| NVIDIA | supplier | US | NVQLink and CUDA-Q QEC; 3.84 µs host-in-the-loop round trip | C[324] |
| International Quantum Academy | research | CN | First closed-loop neural decoder on a superconducting chip | D[729] |
| Qblox | supplier | NL | Control hardware for the sub-microsecond closed loop | C[659] |
| IBM | developer | US | Relay-BP decoder, under 1 µs/cycle in simulation | S[48] |
| AMD | supplier | US | Kintex-7 and Virtex parts hosting both decoder families | D[238], [729] |
Money.
- 2024-05-01 · Riverlane · Horizon Europe EIC Transition grant (SkyTALE, with Qblox) · £2.1 M · European Innovation Council · closed fact
- 2024-08-06 · Riverlane · Series C · $75 M · Planet First Partners (lead), ETF Partners, EDBI, Cambridge Innovation Capital, Amadeus, NSSIF, Altair · company later states $85 M, $120 M+ cumulative · closed, disputed C[661]fact
- 2025-11-17 · NVIDIA · NVQLink launch, price undisclosed; Quantinuum Helios first deployment · — · announced C[324]fact
- 2025-11 · DARPA · QBI Stage B: eleven teams, no pure decoder vendor · — · programme record G[65]
- 2026-03-12 · Riverlane · roadmap: 10⁶ reliable operations before 2030, 10¹² from 2033 · — · roadmap CR[658]fact
- 2026-03-17 · Qblox and Riverlane · closed-loop demo, 250 physical / 1 logical qubit, 10,000 operations · — · announced C[659]fact
Market & supply chain. There is no decoder market in the ordinary sense: Google's decoder is captive, and the one merchant vendor of consequence, Riverlane, sells a deterministic decoder rather than a trained model. Enabling equipment is AMD programmable logic, NVIDIA accelerators and control racks from Qblox, Zurich Instruments and Quantum Machines; concentration risk sits with two American vendors. Unit economics are unquotable; the resource data give a proxy of one to two orders of magnitude more silicon per logical qubit than clustering. G3 and G4 pay for this node and G7 pays for it embedded; G1, G2 and G5 do not, since analogue and error-mitigated machines emit no syndromes.
IP & standards. Riverlane holds GB 2641501 A "Quantum decoder" (Ziad, Zalawadiya, Barber, Skoric; filed 2024-05-31, published 2025-12-10) on grouped processing elements running clustering in hardware — adjacent to, not on, learned models G[662]fact. Google LLC holds US 12,518,194 (granted 2026-01-06) on surface codes with densely packed gauge operators, which shapes the syndrome a decoder reads G[656]. No dated patent-database count for neural-decoder families was found. Standards are absent; the de facto interfaces are NVQLink and CUDA-Q QEC, against open-source Stim, PyMatching and Tesseract.
Roadmaps & track record. Google DeepMind: "too slow for real time" (2024-11) · real-time decoding · under 1 µs per cycle to distance 11 on recorded or simulated data (preprint, 2025-12-08), with no live decode stated for the distance-7 record of 2026-07-08 — not yet delivered on hardware factD[2]. Riverlane: sub-microsecond hardware decoding to distance 17 (2024–25) · delivered 2025-12 D[238]; 10⁶ operations before 2030 (2026-03) · not yet testable R[658]. NVIDIA: single-digit-microsecond quantum-classical link (2025-11) · demonstrated with IQM by 2026-03 P[239]. IBM: Relay-BP under 1 µs/cycle (2025-10) · simulation only, target module slipped a year S[48]. Google delivers and publishes; Riverlane delivers on engineering but is loose about its funding history; NVIDIA delivers plumbing; IBM's decoder promises run ahead of its hardware.
Strategic reading. If learned decoding becomes necessary rather than merely better, value migrates from the processor vendor to whoever owns the trained model and the silicon under it — and only Google owns chip, control loop and model together. IBM, Rigetti, IQM and Oxford Quantum Circuits would buy decoding — Riverlane's thesis. The two may split by regime: learned where accuracy binds, clustering where throughput binds. The substitution threat is physics — erasure conversion and lower physical error rates shrink the non-graphlike residue the network is paid to model. Bargaining power sits with AMD and NVIDIA, who sell into every branch.
Outlook & open questions
Confirm if by 2027-09 a learned decoder runs live in real time at distance ≥ 9 with published latency tails, decodes a sparse quantum code on hardware, or is taped out as an ASIC. Demote if by 2028-09 none has run live beyond distance 7, or a matching-class decoder comes within 5% of learned accuracy at distance ≥ 11 — that would make the silicon premium indefensible. Best case by 2029: learned decoding is default on superconducting machines at distance 15–25 on cold silicon, buying a distance step of physical-qubit savings. Worst case: erasure conversion and better physical error rates make graphlike decoders sufficient and the wall near distance 13 is never crossed.
Open questions. (1) Does the accuracy advantage grow, plateau or invert with distance once latency is charged honestly? (2) How fast does a fine-tuned model degrade between calibrations, and can training fold into the in-loop calibration agent? (3) Is there an architecture keeping O(d²) cost with full correlated-noise capacity outside simulation? (4) Can a learned decoder be certified when its worst case is unbounded? (5) Who pays when processor and decoder vendors differ?
Watch for: an AlphaQubit 2 result on non-Google hardware; the first neural decoder on a bivariate bicycle code; a cryogenic decoder tape-out; and NVQLink latency good enough for shared-accelerator decoding on transmons.
References
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- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. S
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [238] A. B. Ziad et al., “Local clustering decoder as a fast and adaptive hardware decoder for the surface code,” Nat. Commun., vol. 16, no. 1, Art. no. 11048, Dec. 2025, doi: 10.1038/s41467-025-66773-x. D
- [239] M. Abdel-Kareem, “IQM and Zurich Instruments Develop Real-Time QEC via NVIDIA NVQLink,” Quantum Computing Report, Mar. 17, 2026. [Online]. Available: https://quantumcomputingreport.com/
iqm-and-zurich-instruments-develop-real-time-qec-via-nvidia-nvqlink/ P - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [656] Google LLC, “Surface codes with densely packed gauge operators,” U.S. Patent 12,518,194 B2, Jan. 6, 2026. [Online]. Available: https://patents.google.com/
patent/ Also https://patents.justia.com/US12518194B2/ en search?q=%22surface+code%22+quantum+error+correction&company=google . G - [657] J. Bausch et al., “Learning high-accuracy error decoding for quantum processors,” Nature, vol. 635, no. 8040, pp. 834–840, Nov. 2024, doi: 10.1038/s41586-024-08148-8. D
- [658] Riverlane, “Riverlane publishes QEC Technology Roadmap that can accelerate quantum computing's path to utility scale by 3–5 years,” Mar. 12, 2026. [Online]. Available: https://www.riverlane.com/
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patent/ GGB2641501A/ en - [729] X. Yang et al., “Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder,” arXiv:2605.04892, May 2026. Also https://arxiv.org/
html/ . D2605.04892 - [731] Google DeepMind and Google Quantum AI, “AlphaQubit tackles one of quantum computing's biggest challenges,” Google The Keyword, Nov. 20, 2024. [Online]. Available: https://blog.google/
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Русский текст загружается…
הטקסט בעברית נטען…
MWPM / Sparse Blossom (+ correlated matching)
Graph-matching decoder turning the syndrome history — detection events across rounds — into the likeliest error chain; the accuracy reference and the shipped real-time decoder for surface codes.
Verdict. Matching stays the surface-code default through 2026 — Google's own below-threshold run decodes with Sparse Blossom. Demote if a live-hardware, same-syndrome test shows a non-matching decoder beating it on accuracy and latency together by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
MWPM makes each detection event (a check whose outcome changed between rounds) a vertex on a weighted graph whose edges are the errors flipping two detectors; the lowest-weight pairing explaining the set is the most probable single error chain under independent errors — not the maximum-likelihood decoding, which sums over all chains in a class and is what the tensor-network and BP-based decoders approximate. Dennis, Kitaev, Landahl and Preskill introduced it (2002) D[650]; Fowler showed in 2015 that below threshold it can be solved exactly in average O(1) parallel time per round — on a 2D array of classical processors, each serving a fixed number of qubits, independent of lattice size D[725]. Correlated matching reweights edges so a Y error is not charged twice. The engine is Higgott and Gidney's Sparse Blossom (Quantum 9, 1600, 2025-01-20) D[726], a sparse reformulation of Edmonds' 1965 blossom algorithm, shipped as PyMatching v2.
a = 0.5 — classical post-processing, no carrier; b, c, d, e do not apply [graph].
f = Pauli chain on a matching graph; g = none — software, no fabrication [graph].
Physics & limits
Throughput must exceed syndrome production or the backlog diverges and the machine stalls: Sparse Blossom clears ~10⁶ errors per core-second, under 1 µs per round at d=17 D[726], inside Willow's 1.1 µs cycle D[1]. Latency binds only where a logical measurement gates the next operation: 63 µs at d=5 is ~57 cycles of dead time D[1]. The accuracy floor is structural: matching finds the most probable single chain only when every error flips at most two detectors, and it never sums over the chains of one class as a maximum-likelihood decoder does, so hyperedges (Y errors, correlated measurement errors, leakage, loss) must be projected onto a matchable graph. That projection is the whole gap to a decoder modelling them — Λ = 2.04 ± 0.02 for matching against 2.14 ± 0.02 for the neural decoder on Willow's syndromes D[1], AlphaQubit ~25% better at simulated d=11 D[657]. What moves the floor is the graph: fitted edge weights, soft readout, leakage edges.
Engineering state of the art
table
| Year | Figure | Who | Tag+Key |
|---|---|---|---|
| 2023-03 | <1 µs/round at d=17, ~10⁶ errors/core-second, simulated | Google Quantum AI | D[726] |
| 2024-12 | 63 µs real-time latency at d=5 over 10⁶ cycles | Google Quantum AI | D[1]fact |
| 2025-03 | 0.8 µs FPGA latency at d=13, p=0.1%, 62 MHz | Yale University | D[727]fact |
Dominant term: the decoding graph — mis-calibrated weights, unrepresented leakage — not the matcher D[1].
Manufacturing, materials & supply chain
No fabrication: MIT-licensed software [728] on general compute, acceleration the paid, single-sourced layer. Every published real-time QEC decoder runs on AMD/Xilinx logic — Riverlane's on a VU19P at ≈6% of LUTs (lookup tables) for d≤17 D[238], Micro Blossom on a Versal VMK180 D[727], the Shenzhen neural decoder on a Kintex-7 D[729], IBM's Relay-BP on AMD parts P[48] — and GPU decoding is NVIDIA-only. No MWPM ASIC exists (4 Sep 2026). Export exposure is on that hardware: the BIS rule of 2024-09-06 controls quantum computers (4A906) and sub-4.5 K control ICs (3A901.a) G[301]; published decoder source is outside the EAR under 15 CFR §734.7.
Control, readout & I/O burden
At 10³ qubits one core suffices. At 10⁴ the binding term is syndrome bandwidth, not compute — d² detectors per logical qubit per 1.1 µs — hence cryogenic pre-compression, claimed at up to 3,780× below 0.56 mW at 4 K but not fabricated Sfact. At 10⁶ the interconnect decides: NVQLink's 3.84 µs round trip C[324] exceeds a transmon cycle, so GPU matching runs windowed there.
Role in the stack
Default real-time decoder for surface- and colour-code memories, shared across five families [graph]: all three superconducting architectures, all three trapped-ion architectures, both Rydberg tweezer arrays, the fusion-based and continuous-variable photonic architectures, and both spin architectures — primary on six of the twelve (cat and GKP, dual-rail, the linear Paul trap, fusion photonics, quantum-dot and donor spins), alternate on the rest; it needs the near-planar graph a static nearest-neighbour lattice supplies free. It replaces neural and belief-propagation decoders, which win once checks stop being matchable; switching is asymmetric — leaving costs a hardware implementation and a new verification story, returning costs nothing. Clock contribution ≈1.0 µs per round at d=17 D[726] against a derived clock of 0.65 µs for the transmon surface-code architecture (derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture). Empty slot nearby: no real-time matcher consumes soft readout or leakage flags.
Evidence — how the numbers were measured
Sparse Blossom's throughput comes from simulated Stim streams D[726]. The one hardware-integrated figure, Willow's 63 µs at d=5, used a specialised parallel Sparse Blossom built by Google, not stock PyMatching D[1]. Micro Blossom's 0.8 µs at d=13 is peer-reviewed (ASPLOS 2025) but replays syndromes D[727]; the repository's 367 ns appears in no paper Cfact. The much-quoted threshold spread is no conflict: 0.7% (PyMatching), 0.65% and 0.55% (Riverlane's software and hardware clustering decoders) come from one comparison under one noise model D[238]. Every challenger publishes MWPM as baseline; none replicates its speed.
Quantum X Labs' claim that its transformer decoder outperforms MWPM carries no quantitative figure and no peer review [730]. Not published: a separate description, hardware platform or resource figure for the specialised Sparse Blossom variant that decodes Willow in real time, so its 63 µs cannot be attributed to a named part.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Google Quantum AI | Developer/user | US | Co-authored Sparse Blossom; runs it in Willow | D[1], [726] |
| Riverlane | Supplier | UK | Sells Deltaflow QEC hardware; quotes MWPM as reference | Cfact |
| Yale University | Research | US | Micro Blossom exact-MWPM FPGA accelerator | D[727] |
| AMD | Supplier | US | Its parts carry every published real-time decoder | D[238], [727] |
| NVIDIA | Supplier | US | CUDA-Q QEC and the NVQLink GPU–QPU bus | C[324] |
Money. 2024-08-06 · Riverlane · Series C · $75 M (its roadmap says $85 M) · Planet First Partners lead · >$120 M cumulative · closed C[661]. 2025-11-17 · NVIDIA · NVQLink launch · undisclosed · Quantinuum first QPU partner Cfact. 2026-07-24 · Quantum X Labs · result · none disclosed · NVIDIA, Quantum Machines/IQCC · unquantified C[730]. No decoder-specific DARPA award exists; QBI funds eleven Stage B teams, each needing one fact. No later Riverlane round located as of 4 Sep 2026.
Market & supply chain. Nobody sells MWPM: the algorithm is free and the reference MIT-licensed [728], so value accrues to the box that runs it — Deltaflow, CUDA-Q QEC/NVQLink, in-house firmware. Concentration is one-deep twice: AMD for logic, NVIDIA for GPUs. The one public resource figure, ≈6% of a VU19P for d≤17 D[238], implies ~16 patches per part. Pays into G3 and G4.
IP & standards. No MWPM patent family — Edmonds (1965) via Dennis–Kitaev–Landahl–Preskill (2002) D[650]; PyMatching and Micro Blossom are MIT-licensed [727], [728]. The IP is on hardware decoders: Riverlane GB 2641501 A (published 2025-12-10), Google US 12,518,194 (granted 2026-01-06) fact. PatSnap counted 12 QEC patents in April 2026 (Google 6, IBM 4, Tencent 2), no decoder cluster P[668]. De facto interfaces: Stim detector-error models, NVQLink.
Roadmaps & track record. Higgott and Gidney (2023-03 · sub-µs decoding at scale · met, and inside Willow's loop) D[726]. Yale (2025-03 · d=13 at 0.8 µs on FPGA · met; the repository's 367 ns is not) D[727]. Riverlane (2026-03-12 · megaquop before 2030, teraquop from 2033 · no interim milestone due) R[658]. Google's claims track delivery and are the only ones measured live; Riverlane's roadmap is unfalsifiable before 2029.
Strategic reading. If matching holds, AMD and every surface-code builder win: the reference stays free and differentiation collapses to firmware. Riverlane's hardware decoder trades threshold (0.55% vs 0.7%) for latency and area D[238], so its moat is "under the cycle time" — which Micro Blossom now offers for exact MWPM, MIT-licensed D[727]. If matching loses it loses to belief propagation on qLDPC: decoder, code and connectivity change together.
Outlook & open questions
Confirm/demote in 12–24 months: a same-qubit, same-calibration comparison of matching against a challenger (all current ones are simulated, offline or self-refereed); an FPGA matcher closing a live loop at d≥7. Best case 2029: matching stays default past 10⁴ physical qubits, reaction time down from 63 µs to ~1 µs. Worst case: qLDPC memories carry the machines and belief propagation owns the socket. Open questions: does matching extend to loss-dominated atom syndromes; will anyone fund a decoder ASIC when 6% of an FPGA suffices; will QBI Stage C fix a decoder-agnostic benchmark.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. P
- [238] A. B. Ziad et al., “Local clustering decoder as a fast and adaptive hardware decoder for the surface code,” Nat. Commun., vol. 16, no. 1, Art. no. 11048, Dec. 2025, doi: 10.1038/s41467-025-66773-x. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [650] E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, “Topological quantum memory,” Journal of Mathematical Physics, vol. 43, no. 9, pp. 4452–4505, 2002, doi: 10.1063/1.1499754. arXiv:quant-ph/0110143. D
- [657] J. Bausch et al., “Learning high-accuracy error decoding for quantum processors,” Nature, vol. 635, no. 8040, pp. 834–840, Nov. 2024, doi: 10.1038/s41586-024-08148-8. D
- [658] Riverlane, “Riverlane publishes QEC Technology Roadmap that can accelerate quantum computing's path to utility scale by 3–5 years,” Mar. 12, 2026. [Online]. Available: https://www.riverlane.com/
press-release/ Rriverlane-publishes-qec-technology-roadmap - [661] Riverlane, “Riverlane raises $75 million to meet surging global demand for quantum error correction technology,” Aug. 6, 2024. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-raises-75-million-to-meet-surging-global-demand-for-quantum-error-correction-technology - [668] PatSnap, “Quantum Error Correction Technology Landscape 2026,” Apr. 22, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ articles/ quantum-error-correction-patent-landscape-2026/ - [725] A. G. Fowler, “Minimum weight perfect matching of fault-tolerant topological quantum error correction in average O(1) parallel time,” Quantum Inf. Comput., vol. 15, no. 1&2, pp. 145–158, Jan. 2015, doi: 10.26421/QIC15.1-2-9. arXiv:1307.1740. D
- [726] O. Higgott and C. Gidney, “Sparse Blossom: correcting a million errors per core second with minimum-weight matching,” Quantum, vol. 9, Art. no. 1600, Jan. 2025, doi: 10.22331/q-2025-01-20-1600. arXiv:2303.15933. Also https://arxiv.org/
abs/ . D2303.15933 - [727] Y. Wu, N. Liyanage, and L. Zhong, “Micro Blossom: Accelerated Minimum-Weight Perfect Matching Decoding for Quantum Error Correction,” Proc. 30th ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '25), vol. 2, Mar. 2025, doi: 10.1145/3676641.3716005. arXiv:2502.14787. Also https://github.com/
yuewuo/ . Dmicro-blossom - [728] O. Higgott, “PyMatching,” GitHub. [Online]. Available: https://github.com/
oscarhiggott/ GPyMatching - [729] X. Yang et al., “Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder,” arXiv:2605.04892, May 2026. Also https://arxiv.org/
html/ . D2605.04892 - [730] Quantum X Labs, “Quantum X Labs Reports Meaningful Error Correction Decoder Results with NVIDIA CUDA-Q QEC,” GlobeNewswire, Jul. 24, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 07/ 24/ 3332879/ 0/ en/ quantum-x-labs-reports-meaningful-error-correction-decoder-results-with-nvidia-cuda-q-qec.html
Русский текст загружается…
הטקסט בעברית נטען…
GPU decoding via NVQLink
RoCE link putting a GPU inside the QEC feedback loop at 3.84 µs mean round trip, so decoding runs as CUDA software on GH200-class hardware instead of a fixed FPGA bitstream.
Verdict. The round trip is bounded (3.96 µs max over 1,000 samples) and the decoder is software, but the only published decode is BP+OSD on Quantinuum's Helios at 67 µs median; no head-to-head against an FPGA decoder on identical syndromes exists as of 2026-09-04.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A low-latency RDMA-over-Converged-Ethernet (RoCE) path between a QPU's control electronics and a GPU, with an open-source FPGA core on the quantum side, so decoding and in-loop calibration run as CUDA software rather than a bitstream. NVIDIA announced it on 2025-10-28, naming 17 quantum-computer builders, five control-electronics vendors and nine US national laboratories C[531]; the numbers followed on 2025-11-17 C[324]. Attributes: d = platform-agnostic, reaching superconducting, trapped-ion QCCD and neutral-atom architectures; e/f/g = no control modality, corrects Pauli syndrome errors, no fabrication — commodity GPU and Ethernet hardware (graph record).
Physics & limits
Two budgets make up the round trip, and they must not be read the same way. Transport is bounded: 3.84 µs mean, 0.035 µs standard deviation, 3.96 µs maximum over 1,000 samples C[324] — the tightness matters more than the mean, because a feedback loop is sized by its tail. Decode is not: BP+OSD (belief propagation plus ordered-statistics decoding) on a GH200 against Quantinuum's Helios gives a 67 µs median for Bring's code, taking an 8-logical-qubit memory from 4.95 ± 0.67% to 0.925 ± 0.38% error, a 5.4× gain C[324]. Their sum, ~71 µs, is therefore a typical round trip, not a bound: only the transport term has a published maximum.
Whether 67 µs is slow depends on which clock it must meet. For memory the requirement is throughput, not per-cycle latency: Google sustained 10⁶ cycles at d=5 on a 1.1 µs cycle with a real-time decoder of 63 µs mean latency D[1] — the same order as the GPU figure — because a sliding window pipelines cycles instead of decoding each within one. Reaction time is the hard constraint, and it binds only where an operation is conditioned on a decode: magic-state injection, feed-forward, lattice surgery. That distinction, not the raw microseconds, decides where this layer is usable. GPU decoding is therefore comfortable on millisecond-cycle ion and atom platforms, adequate for superconducting memory, and unproven on the reaction-limited path. What moves the floor: kernels exploiting GPU parallelism rather than ports of serial algorithms.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-11 | RoCE round trip 3.84 µs mean, 0.035 µs SD, 3.96 µs max over 1,000 samples | NVIDIA | C[324]fact |
| 2025-11 | BP+OSD on GH200, Bring's code on Helios: 67 µs median, 4.95%→0.925% logical error | Quantinuum | C[324] |
| 2026-03 | Real-time QEC demonstrator over NVQLink, under 4 µs end-to-end | IQM | P[239]fact |
GPU decode time dominates at ~17× the network hop, so the interconnect is not what has to shrink. No published result runs GPU BP+OSD and an FPGA decoder on identical traces.
Manufacturing, materials & supply chain
No fabrication process. The GPU side is NVIDIA silicon — GH200 for Helios, RTX PRO 6000 Blackwell Max-Q for the networking demonstration C[324] — with no AMD or Intel equivalent as of 2026-09-04. The network side is deliberately unlocked: RoCE is a standard and NVIDIA published an open-source FPGA core for the QPU endpoint C[324], which let five control-electronics vendors integrate it C[531]. The asymmetry is the commercial design — give away the interface, sell the accelerator. Nothing is priced; it ships as a reference architecture with a sign-up page C[531]. Export exposure is inherited from US controls on advanced GPUs, not from a quantum ECCN.
Control, readout & I/O burden
The loop is control electronics → RoCE → GPU → back, at 3.84 µs plus decode. Helios is 98 physical qubits D[105], so nothing at 10³ has run end-to-end. At 10⁴–10⁶ the question is whether decode time grows with code size faster than throughput grows per GPU generation, and whether batching across logical blocks keeps the budget flat; no source states either. The offsetting argument, unquantified: one GPU cluster can serve several QPUs, which an FPGA bolted to one rack cannot.
Role in the stack
It requires nothing upstream and replaces FPGA-based real-time decoding, trading a fixed bitstream for software changeable between shots; the graph records it as the primary decoder on trapped-ion QCCD and as an alternate on the transmon lattice with tunable couplers and the alkali Rydberg tweezer array — one decoder across three families. Derived clock contribution: ~71 µs per decode round trip — transport plus median decode (2 s.f.) — 1–7% of a 1–5 ms ion or atom cycle but ~65 cycles of a 1.1 µs superconducting one D[1]. Switching cost is a rack and a software stack, not a code change — the opposite of the qLDPC decoders. Adjacent empty slot: an independent cross-vendor benchmark.
Evidence — how the numbers were measured
Both headline numbers come from NVIDIA's own blog, co-developed with Quantinuum, and are not peer-reviewed C[324]. The 5.4× carries uncertainties — better practice than most vendor claims — but it is one code on one machine, and the IQM demonstrator is trade press P[239]. No comparison exists against Relay-BP D[48] or Riverlane's decoder D[238] on the same syndromes, so "GPUs are slower than FPGAs" compares numbers from different codes and machines.
Not published: how GPU decoding time scales with code size or logical-block count at 10⁴–10⁶ qubits, and NVentures' separate investments in Quantinuum, QuEra and Alice & Bob, of which only the round totals are public. The launch release's headline counts of 17 builders and nine labs do not tally exactly with the names it lists.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| NVIDIA | Developer | USA | Built NVQLink and the nv-qldpc-decoder; supplies the GPUs | C[324], [531] |
| Quantinuum | User | USA/UK | Only published deployment: Helios plus GH200 running BP+OSD | C[324]fact |
| IQM | User | Finland | Real-time QEC demonstrator over NVQLink under 4 µs end-to-end | P[239]fact |
| Zurich Instruments | Supplier | Switzerland | Control electronics carrying the NVQLink endpoint | C[531] |
| DARPA | Funder | USA | QBI Stage B funds several of the named QPU builders | G[65]fact |
Money. 2025-10-28 · NVIDIA · launch, 17 builders / 5 control vendors / 9 labs · no financing disclosed · announced C[531]. 2025-09-04 · Quantinuum · $600 M at $10 B pre-money, NVentures participating · closed Cfact. 2026-05-22 · Alice & Bob · Series B extension with NVentures · closed Cfact. 2026-07-26 quarter · NVIDIA · revenue $96.2 B, Data Center $89.0 B, +106% y/y, quantum unmentioned · reported G[737] — the economics of this layer in one line.
Market & supply chain. No market yet — no price, SKU or licence terms disclosed C[531]. The chain splits: open interface, single-sourced accelerator, so concentration risk is the decoder host, not the link. Goal exposure is broader than any FPGA decoder — G3/G4 as a decoder, G2 because the same path serves mitigation and calibration, G7 because national-lab deployments are procurement-shaped.
IP & standards. No patent family specific to NVQLink was found in any named database. The standards posture is the interesting part: RoCE is an existing Ethernet standard and the QPU-side core is open source C[324], so NVIDIA standardises the boundary it does not sell. Third parties build against CUDA-Q QEC Pfact.
Roadmaps & track record. NVIDIA: (2025-10 · launch with 17 builders · delivered, one published deployment three weeks later) C[324], [531]; (2025-11 · partners to deploy on future processors · only Helios confirmed) C[324]. IQM: (2026-03 · demonstrator · delivered) P[239]. Launch-to-first-deployment was effectively zero; the gap between 17 announced builders and one published deployment is the number to watch.
Strategic reading. If GPU decoding wins, every fault-tolerant machine becomes a recurring GPU customer and decoding stops differentiating QPU vendors — good for builders without FPGA engineering, bad for Riverlane and IBM's in-house route. NVIDIA loses little if it fails: quantum does not appear in a $96.2 B quarter G[737], so this is a cheap option on the classical half of a future stack. The substitution threat is a decoder ASIC nobody sells. Bargaining power sits with NVIDIA on the accelerator and the control vendors on the endpoint.
Outlook & open questions
Falsifiable (12–24 months): confirm if a second QPU vendor publishes an NVQLink decode loop with numbers by end-2027; demote if published deployments still number one. Best case 2029: GPU decoding is the default on ion, atom and superconducting memory, reaction-limited operations handed to a small local FPGA. Worst case: 17 builders yield two deployments and dedicated hardware keeps the loop. Open questions: how decode time scales with code size and block count; whether anyone reports tail rather than median latency; whether AMD or Intel field a rival host. Watch: a second deployment and any independent benchmark.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. D
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iqm-and-zurich-instruments-develop-real-time-qec-via-nvidia-nvqlink/ P - [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [531] NVIDIA, “NVIDIA Introduces NVQLink — Connecting Quantum and GPU Computing for 17 Quantum Builders and Nine Scientific Labs,” Oct. 28, 2025. [Online]. Available: https://nvidianews.nvidia.com/
news/ Cnvidia-nvqlink-quantum-gpu-computing - [737] NVIDIA, “NVIDIA Announces Financial Results for Second Quarter Fiscal 2027,” Aug. 26, 2026. [Online]. Available: https://nvidianews.nvidia.com/
news/ Gnvidia-announces-financial-results-for-second-quarter-fiscal-2027
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Relay-BP for qLDPC (FPGA)
Belief propagation with disordered, partly negative memory strengths, chained in relay legs, decoding bivariate bicycle qLDPC syndromes at 24 ns per iteration on an FPGA.
Verdict. Removes the OSD post-processor that made qLDPC decoding non-real-time: 24 ns/iteration and under 1 µs average per cycle on FPGA. Never run on live syndromes — no gross-code memory exists on any QPU as of 2026-09-04.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Belief propagation in which each variable node carries its own memory strength — a damping coefficient drawn from a disordered distribution that must include negative values — with decoding run as a chain of relay legs, each restarted from the previous leg's messages. IBM (Müller, Alexander, Beverland, Bühler, Johnson, Maurer, Vandeth) introduced it on 2025-06-02 D[734]; a second IBM team put it on an FPGA on 2025-10-24 for the [[144,12,12]] gross code D[48]fact. Attributes: d = no physical connectivity, an off-chip classical block; e/f/g = no control modality, corrects Pauli errors, no fabrication — an FPGA bitstream (graph record).
Physics & limits
The limit is an accuracy-versus-latency budget, not a physical one. Plain BP stalls on degenerate stabiliser codes — distinct error patterns carry identical likelihood, so messages oscillate into trapping sets — and the standard repair, ordered-statistics post-processing, has a data-dependent cost no real-time loop absorbs. Relay-BP's claim is that disordered memory strengths break exactly the symmetry that stalls BP, making the post-processor unnecessary; the paper states a distribution containing negative values is indispensable D[734].
That buys latency: 24 ns per BP iteration and an average per-cycle decoding time under 1 µs for physical error probabilities below 3×10⁻³ D[48]. Average is where the risk sits — iteration count is data-dependent, so the latency distribution has a tail, and a decoder fed a fixed-rate stream at the 1.1 µs superconducting cycle must buffer, the backlog diverging rather than degrading if that tail exceeds the cycle time often enough. Neither paper reports anything but the mean. The second floor is the error rate itself: above 3×10⁻³ iteration counts climb, so the real-time property is conditional on the hardware already being good. What moves the floor: an ASIC, or windowing that commits early cycles while later ones converge.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-06 | Relay-BP beats BP+OSD+CS-10 on bivariate bicycle codes, matching-class on surface codes | IBM | D[734] |
| 2025-10 | FPGA: 24 ns/iteration, average < 1 µs per cycle at p < 3×10⁻³, simulated syndromes | IBM | D[48]fact |
| 2025-12 | Local Clustering Decoder: < 1 µs/round to d=17 using ≈6% of a Xilinx VU19P's LUTs | Riverlane | D[238]fact |
Both FPGA results are simulation-driven: no gross-code memory has run on any QPU, so Relay-BP has never consumed a hardware syndrome R[72]fact. The target code is IBM's [[144,12,12]], 288 physical qubits at a 0.8% threshold on a degree-6 Tanner graph D[248]fact; the only qLDPC break-even claim anywhere is IonQ's trapped-ion result — within error bars, in one code the paper does not identify, leakage post-selected D[109]fact.
Manufacturing, materials & supply chain
No fabrication process: the deliverable is a bitstream and the supply chain is merchant FPGA silicon, a duopoly restructured in 2025, when Intel's sale of 51% of Altera to Silver Lake at an $8.75 B valuation — ~$4.46 B to Intel, which keeps 49% — closed on 2025-09-15 G[735]fact. Every named real-time decoder here runs on AMD parts (Riverlane's LCD on a VU19P D[238]), and IBM's is reported as AMD by trade press whose page could not be retrieved P[736]fact. No decoder-specific export-control category exists as of 2026-09-04.
Control, readout & I/O burden
The decoder drives nothing; its burden is syndrome bandwidth and fan-in. One gross module is 144 data plus 144 check qubits, so a cycle yields 144 bits — ~0.14 Gbit/s per module at a 1 µs cycle S[248]. Scaled naively, 10⁴ physical qubits is ~5 Gbit/s and 10⁶ ~0.5 Tbit/s at fixed rate: the wall is not BP arithmetic but getting bits out of the cryostat into enough parallel instances.
Role in the stack
It requires the bivariate bicycle/gross qLDPC family and replaces minimum-weight perfect matching; the graph records it as the primary decoder on trapped ions with electronic gates and on continuous-variable photonic GKP, and as an alternate on the transmon lattice with tunable couplers and the linear Paul trap with individual laser addressing. Derived clock contribution: < 1.0 µs per cycle (2 s.f.), the first qLDPC decoder figure that fits inside a 1.1 µs superconducting cycle without an offline pass D[48]; surface-code decoders such as Riverlane's LCD already fitted D[238]. Switching costs a code change, not a board change: gross codes need degree-6 long-range couplers IBM has shown only as components, where LCD assumes the nearest-neighbour grid hardware already has D[238]fact. Adjacent empty slot: a merchant decoder ASIC.
Evidence — how the numbers were measured
Every headline is from simulated syndromes under a uniform circuit-noise model of strength p, with neither leakage nor correlated bursts — the dominant real-device terms D[48], [734]. No independent group has reproduced either number, and Riverlane's LCD uses a different code and FPGA, so the two are not commensurable D[238].
Not published: the FPGA part, its lookup-table (LUT) and memory use and the arithmetic precision — the AMD attribution rests on trade press [736] — and any latency distribution or tail percentile; only the average is given.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IBM | Developer | USA | Invented Relay-BP and built the FPGA implementation for its gross code | D[48], [734] |
| AMD | Supplier | USA | Xilinx FPGA silicon under IBM's demonstration and most rival decoders | P[736]fact |
| Altera | Supplier | USA | The only other merchant high-end FPGA source; 51% Silver Lake-owned since 2025 | G[735] |
| Riverlane | Developer | UK | Competing FPGA decoder for the surface code, sold as a product | D[238]fact |
| DARPA | Funder | USA | QBI Stage B funds IBM's fault-tolerance programme this serves | G[65]fact |
Money. 2024-08-06 · Riverlane · Series C · $75 M (its 2026 roadmap says $85 M — unreconciled) · Planet First Partners lead · closed C[661]fact. 2025-09-15 · Intel/Silver Lake · 51% of Altera at $8.75 B valuation, ~$4.46 B to Intel · closed (announced 2025-04-14) G[735]fact. 2025-11-06 · DARPA · QBI Stage B, up to $15 M each, IBM the only transmon vendor · awarded G[65]fact. Relay-BP itself has no round, grant or licence: in-house IBM work as of 2026-09-04.
Market & supply chain. Decoding is priced as bundled firmware, not silicon: Riverlane sells Deltaflow, integrated with Qblox control hardware C[659]fact, IBM ships Relay-BP inside its own stack. Concentration risk is FPGA supply — two vendors, one newly under private-equity control G[735]. Goal exposure is narrow, G3 and G4 only: a real-time decoder is worthless until a code needs it, so willingness to pay is vendors insuring their own 2027–2029 roadmaps.
IP & standards. Riverlane holds GB 2641501 A "Quantum decoder" (published 2025-12-10) on hardware clustering over the decoding hypergraph fact; IBM's bivariate bicycle estate covers the code, not the decoder, and no Relay-BP family appears in any named database. No standards body addresses decoder interfaces.
Roadmaps & track record. IBM: (2025-06 · Relay-BP algorithm · delivered); (2025-10 · FPGA implementation · delivered); (Kookaburra · promised for 2025 in the 2022 roadmap, re-promised for 2026 as the first qLDPC module · not delivered as of 2026-09-30) R[72]factfact. Riverlane: (2026-03 · teraquop decoding from 2033 · too early) Cfact. IBM's decoder software is on time twice over; the hardware it decodes is not.
Strategic reading. If Relay-BP holds up, IBM removes the strongest objection to qLDPC — that its decoder cannot run in real time — and the ~10× qubit saving over the surface code becomes bankable, hurting surface-code-shaped roadmaps and helping whoever can build degree-6 connectivity. If not, matching decoders keep the field. Decoding is becoming a component business with no dedicated supplier: two FPGA vendors, one GPU vendor pushing an alternative, no merchant ASIC. Bargaining power stays with the QPU vendor that picks the code.
Outlook & open questions
Falsifiable (12–24 months): confirm if Kookaburra ships and a gross-code memory is decoded in real time by end-2027; demote if Relay-BP has consumed no hardware syndrome by then. Best case 2029: Relay-BP-class decoding inside IBM's Starling stack at the demonstrated latency. Worst case: gross-code hardware keeps slipping and GPU or matching decoders take the installed base. Open questions: the 99.9th-percentile latency rather than the mean; whether accuracy survives leakage and correlated bursts; whether anyone builds a decoder ASIC. Watch: Kookaburra delivery, any live-syndrome decode, the first latency histogram.
References
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. D
- [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [72] IBM, “Quantum Roadmap.” [Online]. Available: https://www.ibm.com/
roadmaps/ Rquantum/ - [109] E. Tham et al., “Breakeven demonstration of quantum low-density parity-check codes,” arXiv:2606.06455, Jun. 2026. D
- [238] A. B. Ziad et al., “Local clustering decoder as a fast and adaptive hardware decoder for the surface code,” Nat. Commun., vol. 16, no. 1, Art. no. 11048, Dec. 2025, doi: 10.1038/s41467-025-66773-x. D
- [248] S. Bravyi et al., “High-threshold and low-overhead fault-tolerant quantum memory,” Nature, vol. 627, no. 8005, pp. 778–782, Mar. 2024, doi: 10.1038/s41586-024-07107-7. arXiv:2308.07915. D
- [659] Qblox; Riverlane, “Qblox and Riverlane Demonstrate Integration Enabling Real-Time Quantum Error Correction,” PR Newswire, Mar. 17, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cqblox-and-riverlane-demonstrate-integration-enabling-real-time-quantum-error-correction-302716254.html - [661] Riverlane, “Riverlane raises $75 million to meet surging global demand for quantum error correction technology,” Aug. 6, 2024. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-raises-75-million-to-meet-surging-global-demand-for-quantum-error-correction-technology - [734] T. Müller et al., “Improved belief propagation is sufficient for real-time decoding of quantum memory,” arXiv:2506.01779, Jun. 2025. D
- [735] Altera, “Altera Closes Silver Lake Investment to Become World's Largest Pure-play FPGA Solutions Provider,” Sep. 15, 2025. [Online]. Available: https://www.altera.com/
newsroom/ Gnews/ press-release/ altera-silver-lake - [736] A. Woodie, “IBM Touts Affordable Quantum Error Correction on AMD FPGAs,” HPCwire, Oct. 28, 2025. [Online]. Available: https://www.hpcwire.com/
2025/ P10/ 28/ ibm-touts-affordable-quantum-error-correction-on-amd-fpgas/
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Cryogenic / on-chip decoder (cryo-CMOS, SFQ)
Syndrome decoding or predecoding executed inside the cryostat — SFQ logic at millikelvin, CMOS at 4 K — instead of at room temperature.
Verdict. Four design studies, zero silicon as of 4 Sep 2026. Room-temperature FPGA decoders meet the 1.1 µs superconducting cycle, so only feedthrough count at 10⁴+ qubits can force this node into existence.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A cryogenic decoder evaluates the syndrome-to-correction map inside the refrigerator instead of shipping every syndrome bit up the harness. Two substrates compete: single-flux-quantum (SFQ) logic switching quantised flux pulses at tens of GHz at millikelvin, and CMOS characterised at 4 K. The lineage is architectural: a per-qubit SFQ decoder in 2020 S[744], an online SFQ surface-code decoder in 2021 S[745], then in 2025–26 an inversion — compressing syndromes at 4 K rather than decoding them S[733]S[746].
- Control and placement: cold digital logic at the millikelvin or 4 K stage.
- Manufacturing: Nb multilayer lithography or 4 K-characterised CMOS; no decoder-specific process exists.
Physics & limits
The limit is thermal bookkeeping. An SFQ junction transition dissipates of order I_cΦ₀ ≈ 10⁻¹⁹ J, so a 10⁵-junction decoder at 2 GHz sits in the tens of µW — 2.78 µW is the published point S[745] — against a dilution unit delivering hundreds of µW at 100 mK. Cryo-CMOS trades that for a ≈2 W plant at 4 K S[550], of which one design spends 1.5 W to serve 2,668 logical qubits at d=21 S[733]. Neither floor is fundamental: each is an allocation against a budget control already claims, and it moves with the logic family — lower-power cryo-CMOS, SFQ at ~1.6 µW per qubit, adiabatic quantum-flux-parametron (AQFP) logic lower still S[550]. The dominant failure mode is not a Pauli error — a decoder whose throughput falls below the syndrome rate accumulates unbounded backlog, so latency and bandwidth set the design. SFQ near the qubit die adds a second mechanism: pulse edges radiate, and photon-mediated quasiparticle poisoning measured 1.2(1)% error per Clifford on a separate-die SFQ driver that switches far less than a decoder would Dfact.
Engineering state of the art
All decoder figures are post-synthesis; the last row is the nearest fabricated analogue.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2021-03 | SFQ surface-code decoder: 2.78 µW at 2 GHz, 1.0% threshold, d=5–13 | Ueno et al. | S[745] |
| 2025-12 | 22 nm FD-SOI predecoder at 4 K: 3,780.72× bandwidth cut, peak < 0.56 mW | Univ. Michigan | Sfact |
| 2026-06 | 22 nm FD-SOI compressor at 4 K: 48× at d=17, 14,238× combined, 100 ns/round | Univ. Michigan | Sfact |
| 2026-07 | Fabricated 4 K CMOS controller self-sequencing a d=5 repetition code, ≤3.5 W | HRL Laboratories | Dfact |
The dominant budget term is classical: off-cryostat bandwidth and round-trip latency.
Manufacturing, materials & supply chain
Both cryo-CMOS designs run on 22 nm FD-SOI characterised at 4 K, and both took that PDK from Semiwise Ltd (UK) S[746] — one small supplier between every academic group and a tape-out. GlobalFoundries' 22FDX is the volume path behind it Cfact. The SFQ path depends on SEEQC's multilayer Nb foundry in Elmsford NY Dfact, the only merchant line of its class. No yield or unit cost exists: nothing has taped out. ECCN 3A901.a covers CMOS ICs "designed to operate at" ≤4.5 K — design intent, not performance — so the layout is controlled pre-fabrication fact.
Control, readout & I/O burden
The node exists to cut I/O. The superconducting QEC cycle is 1.1 µs D[1] and a distance-d logical qubit emits d²−1 syndrome bits per round — ≈0.4 Gb/s at d=21. At 10³ physical qubits nothing binds — a local clustering decoder holds under 1 µs per round to d=17 on a Xilinx VU19P using ≈6% of its LUTs (lookup tables) Dfact, and exact FPGA matching averages 0.8 µs at d=13 D[727]. The wall at 10⁴–10⁶ is mechanical before computational: feedthrough count, harness heat load, serialiser bandwidth crossing 4 K. Compression attacks that term.
Role in the stack
An alternate decoder on the transmon lattice with tunable couplers. It requires millikelvin SFQ or 4 K cryo-CMOS control first, provides for nothing downstream, and blocks no one. It replaces room-temperature FPGA decoding: an FPGA is reprogrammable as codes and noise models change, a cold ASIC is fixed-function, competes with control for cold watts, and is export-controlled from the design file. The argument for an ASIC is supply-side: merchant high-end FPGAs are an AMD/Altera duopoly, one side private-equity-controlled since 2025 fact. As a predecoder it adds ≈0.10 µs per round Sfact outside derived clock = sum of the syndrome round: gate layers + transport + readout + reset, which stays ≈0.65 µs against the measured 1.1 µs cycle; only the cabling cost changes.
Evidence — how the numbers were measured
Every decoder number is post-synthesis power/performance/area on a cryo-characterised PDK plus vector simulation, syndromes drawn from noise models rather than a device; the 2025 predecoder is at least evaluated under circuit-level rather than code-capacity noise, and neither study is replicated outside an overlapping author set. Power per qubit at 4 K has no shared definition — 23 mW measured by IBM driving a two-qubit gate, against an "optimistic" 5 mW and sub-2 mW claims Sfact; only 23 mW is tied to a running gate. The repeated 367 ns FPGA matching latency comes from a repository with no code distance and no paper; the peer-reviewed figure is 0.8 µs at d=13 D[727], used here.
Not published: SEEQC's offering size and price range, still blank in its S-1 amendment of 2026-09-11 fact, and a patent family specific to cryogenic decoding.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| University of Michigan | Research | USA | Authored both cold predecoder and compressor designs | Sfact |
| SEEQC Inc. | Developer, supplier | USA | Nb foundry and millikelvin SFQ control; only credible SFQ host | Dfact |
| HRL Laboratories | Developer | USA | Only fabricated cold logic inside a QEC loop | Dfact |
| IBM | Developer, acquirer | USA | Cryo-CMOS flux-bias ASICs on 156 qubits; acquired HRL | Cfactfact |
| Semiwise Ltd | Supplier | UK | Sole source of the 4 K 22 nm FD-SOI PDK used | S[746] |
| Riverlane | Developer, rival | UK | Room-temperature FPGA decoding incumbent | Dfact |
| US Bureau of Industry and Security | Regulator | USA | Controls ≤4.5 K CMOS ICs by design intent | fact |
Money. 2025-12/2026-06 · University of Michigan · DOE ARQC award DE-SC0025633, amount undisclosed · funds both studies · ongoing S[746]. 2026-05-21 · GlobalFoundries · CHIPS letter of intent · $375 M USD · US Commerce · non-binding fact. 2026-05-26 · SEEQC · Form S-4 for a Nasdaq listing through a 2026-01-16 Allegro merger agreement · $75 M offering plus $65 M PIPE at ~$1 B enterprise value · filed G[575]; the merger was terminated 2026-08-25, and SEEQC's separate S-1 IPO (filed 2026-06-29) had not priced by 30 Sep 2026 fact; SEEQC's amended S-1 of 2026-08-28 reports 2025 revenue of $4.2 M, a 2025 net loss of $12.2 M and $18.1 M in cash at 2026-06-30 fact. 2026-07-23 · IBM · acquisition of HRL Laboratories · terms undisclosed · closed 2026-08-26 Cfactfact. No programme funds cryogenic decoding directly.
Market & supply chain. Nobody sells this. The enabling goods sit one layer down: cryo-PDKs, 22FDX capacity, Nb multilayer runs, and the racks a cold decoder would displace. Concentration is severe at both ends; no unit economics are quotable. Only G4 pays for this.
IP & standards. No patent family specific to cryogenic decoding was found in a named dated database. The nearest is Riverlane's GB 2641501 A "Quantum decoder" (published 2025-12-10), claiming room-temperature hardware clustering fact. No standard exists for a syndrome interface across the 4 K boundary; NVIDIA's NVQLink standardises the warm side instead.
Roadmaps & track record. Michigan predecoder and compressor (2025-12-10, 2026-06-29 · no tape-out date · design-only as of 4 Sep 2026) — real PDK data, no fabrication commitment. SEEQC SFQ control (peer-reviewed 2026-03-10 · decode absent from its roadmap) — the only actor with its own process line and, should its pending IPO price, the proceeds to fund a tape-out. IBM cryo-CMOS control (abstracts 2026-03-16 · no preprint) — unproven at publication standard.
Strategic reading. If cold decoding works the winners already own cold silicon and cooling budget — SEEQC on SFQ, IBM/HRL and GlobalFoundries on CMOS — because decode folds into a chip they ship anyway. Losers are standalone decoder vendors whose value is reprogrammability, and accelerator vendors betting decode migrates to GPUs over a warm link. Bargaining power sits with the substrate owner.
Outlook & open questions
Confirm by 2028 if any cryogenic predecoder tapes out with measured silicon; demote if the 2027 literature is still post-synthesis. Best case 2029: a compressor at 4 K inside a QBI-adjacent system absorbs syndrome traffic before the harness. Worst case: room-temperature decoding scales with qLDPC codes and faster links. Open questions: which power baseline should size a cold decoder; can decode logic share a stage with control without reintroducing quasiparticle poisoning; does any platform hit the feedthrough wall before 10⁴ qubits. Watch the SEEQC listing and IBM's post-HRL roadmap.
The junction budget that sizes a single-flux-quantum (SFQ) decoder is falling on the design side: a clock-free xSFQ cell library with built-in fan-out amplifiers cuts the Josephson-junction count 2.7–3.4× (63–71%) on standard single-cycle logic benchmarks and 41–66% on pipelined ones, with one cell fabricated and verified at 4.2 K P[897]. No decoder was built; the figures are for generic logic.
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [550] S. Kawabata, “Integration and Resource Estimation of Cryoelectronics for Superconducting Fault-Tolerant Quantum Computers,” arXiv:2601.03922, Jan. 2026. S
- [575] SeeQC, Inc., “Form S-4 Registration Statement (SeeQC, Inc. / Allegro Merger Corp.),” U.S. Securities and Exchange Commission, May 2026. [Online]. Available: https://www.sec.gov/
Archives/ Gedgar/ data/ 1779977/ 000121390026061108/ ea0278139-04.htm - [727] Y. Wu, N. Liyanage, and L. Zhong, “Micro Blossom: Accelerated Minimum-Weight Perfect Matching Decoding for Quantum Error Correction,” Proc. 30th ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '25), vol. 2, Mar. 2025, doi: 10.1145/3676641.3716005. arXiv:2502.14787. Also https://github.com/
yuewuo/ . Dmicro-blossom - [733] A. Knapen et al., “Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise,” arXiv:2512.09807, Dec. 2025. S
- [744] A. Holmes et al., “NISQ+: Boosting quantum computing power by approximating quantum error correction,” arXiv:2004.04794, Apr. 2020. S
- [745] Y. Ueno, M. Kondo, M. Tanaka, Y. Suzuki, and Y. Tabuchi, “QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code,” arXiv, Nov. 8, 2021. [Online]. Available: https://arxiv.org/
abs/ S2103.14209 - [746] G. Tao et al., “CryoZip: An Efficient Cryogenic Compressor for Quantum Error Correction Syndromes,” arXiv:2606.30805, Jun. 2026. S
- [897] P. Papanikolaou, A. Vanasse, H. Jin, G. Tzimpragos, and J. Volk, “Duplication-aware retiming and cell interface redesign for superconductor circuit minimization,” arXiv:2610.02333, Oct. 2026. P
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Correlated / loss-aware decoding (transversal, atom loss)
Decoders that consume atom-loss heralds as located erasures and decode across transversal gate layers instead of round-by-round.
Verdict. Real on one dataset (1.73(13)× over a loss-blind decoder, 448 atoms, four rounds); unproven under reloading, at depth, or in a second lab.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Not hardware, a decoding discipline. Loss-aware decoding consumes the herald: a missing atom is an erasure at a known site, so stabilisers touching the vacancy multiply into higher-weight supercheck operators that still commute with the surviving code [4]. Correlated decoding solves the joint syndrome history across transversal (block-to-block) layers rather than block-by-block; Cain et al. (Harvard, 2024-03-05) showed the rounds between Clifford gates drop O(d)→O(1) [738], generalised as algorithmic fault tolerance (Nature 2025) [152].
f = loss + erasure; a/c/d/e/g = none — classical compute, no fab or placement [graph].
Physics & limits
The herald is the asset: >80% of Rydberg-array leakage is atom loss, and imaging finds it [4]. A located erasure costs the decoder only the Pauli frame, not the position — why erasure conversion lifts circuit-level thresholds 3–4× at fixed gate physics [8]. The price is distance: each supercheck is a product of two stabilisers, so every vacancy locally thins the code. Correlated decoding pays differently: transversal CNOTs propagate errors between blocks, so the graph grows with circuit depth, not d. Nothing moves the floor — the unheralded residual is untouched, m_F leakage 0.008(1)% per atom per gate against atom loss 0.087(5)% fact.
Engineering state of the art
table
| Date | Figure | Who | Tag+key |
|---|---|---|---|
| 2025-11-10 | 1.73(13)× gain from loss flags + ML over conventional decoding, same 448-atom data | Harvard/MIT/QuEra | D[4]fact |
| 2026-03 | Correlated-loss decoder: 4% threshold vs 3.2% assuming independent loss; 144 µs/round; simulation | QPerfect | S[739]fact |
| 2026-06-12 | [[4,2,2]] ¹⁷¹Yb: unconditional decay 1.9(4)× slower with erasure information (3.6(1)× is the post-selected hold) | Princeton | D[142]fact |
Same circuit: 2.14(13)×, d=3→5, four rounds. Dominant term: atom loss, not Pauli error.
Not published: the closing date and price of BTQ's full acquisition of QPerfect, whose option was exercised between 2025-04 and 2026-07, and a dated patent family for loss-aware or correlated decoding.
Manufacturing, materials & supply chain
No fab: classical compute already bought for matching. Latency sets scope: 144 µs/round fits a 1–4.5 ms atom cycle with 7–30× margin [739] but is ~130× over a 1.1 µs superconducting cycle — why this stays atom-specific. Loss-flag bandwidth is one bit per site per round, so the wall at 10³–10⁴ atoms is the ~0.5–1 ms imaging and a decode window scaling with logical depth, not the link. Inherited single points of failure: Hamamatsu qCMOS imaging fact and two AOD vendors fact.
Role in the stack
The primary decoder on both Rydberg tweezer arrays, alkali (Rb/Cs) and alkaline-earth(-like) (Yb/Sr). Requires high-rate concatenated codes with transversal gates; provides the decoding half of algorithmic fault tolerance, whose constant-round claim is otherwise unbacked on hardware. Derived clock = sum of the syndrome round (gates 1 µs, transport 800 µs, 1Q 10 µs, readout 501 µs) ≈ 1.3 ms, ~0.76 kHz; the decoder must return inside it, not set it. Verification: 1.73× is a decoder-vs-decoder ratio on one lab's data, unreplicated; 4% is simulation [739]. Four rounds test neither drift nor reloading; Atom Computing's toric code is the control, suppression vanishing with reloading (0.63% vs 0.64% per cycle) [148]. Princeton's 1.9(4)×/3.6(1)× discrepancy is resolved: one paper, two quantities fact.
Actors & economics
Who.
| Organisation | Role | Country | What exactly | Evidence |
|---|---|---|---|---|
| Harvard/MIT | research | US | Correlated decoding, superchecks, 1.73(13)× | D[4], [738] |
| QuEra | developer | US | Co-author; Libra 2028 assumes it | D[4]C[153] |
| QPerfect (BTQ) | supplier | FR | Correlated-loss decoder; aQCess twin | S[739]C[740] |
| Atom Computing | user | US | Erasure-native Yb; reloading counter-example | D[148]C[154] |
Money.
2025-04-09 · BTQ Technologies · €2 M into QPerfect at €10 M pre-money (16.67%) · term sheet P[741]
2026-07-22 · QPerfect · aQCess twin, Equipex+ ANR-21-ESRE-0032 · announced C[740]
2026-06-16 · Atom Computing · $100 M Series C (Third Point) + $100 M CHIPS LOI · closed + LOI C[154]fact
2025-11-06 · DARPA QBI Stage B · Atom Computing, QuEra among eleven · ≤$15 M each fact
Market & supply chain. No component market: GPU/FPGA cycles already bought for matching; concentration risk sits upstream, in imaging and AODs. Pays G3/G4 only.
IP & standards. No dated patent family names loss-aware or correlated decoding as of 4 Sep 2026; methods open, code academic.
Roadmaps & track record. O(d)→O(1) rounds (2024-03): in Nature 2025, shown only in a four-round circuit. QuEra 100 logical (2024-01, for 2026): now Libra 2028 fact. Physics on time, products late.
Strategic reading. If it holds, atoms turn their worst liability into a cheap accounted channel and transversal architectures beat lattice surgery on spacetime cost: QuEra, Atom Computing, Pasqal and Infleqtion gain, superconducting vendors lose decoder latency as a differentiator. Substitution threat: a Rydberg CZ past 99.95% shrinks the loss term. Non-rival: no supplier can rent it.
Outlook & open questions
Confirm if the QPerfect decoder runs on real syndromes or a second vendor publishes its own loss-aware gain; demote if the gain dies under reloading or past four rounds. Best case 2029: default across neutral-atom FT stacks; worst case, one group's architecture, never past 10³ atoms. Open: does 1.73× hold at 10⁴ atoms, at depths where the correlated graph outgrows memory, and on ions [667]?
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [8] Y. Wu, S. Kolkowitz, S. Puri, and J. D. Thompson, “Erasure conversion for fault-tolerant quantum computing in alkaline earth Rydberg atom arrays,” Nat. Commun., vol. 13, Art. no. 4657, 2022, doi: 10.1038/s41467-022-32094-6. arXiv:2201.03540. S
- [142] B. Zhang et al., “Logical qubits with erasure conversion using metastable neutral atoms,” Nat. Phys., vol. 22, no. 6, pp. 910–916, Jun. 2026, doi: 10.1038/s41567-026-03309-0. arXiv:2506.13724. D
- [148] Atom Computing and Collaborators, “Quantum error correction with the toric code,” arXiv:2606.04079, Jun. 2026. D
- [152] H. Zhou et al., “Low-Overhead Transversal Fault Tolerance for Universal Quantum Computation,” Nature, vol. 646, no. 8084, pp. 303–308, 2025, doi: 10.1038/s41586-025-09543-5. arXiv:2406.17653. S
- [153] QuEra Computing, “QuEra Expands $230 Million Financing Round Advancing Quantum-Accelerated Supercomputing,” Sep. 9, 2025. [Online]. Available: https://www.quera.com/
press-releases/ Cquera-expands-230-million-financing-round-advancing-quantum-accelerated-supercomputing - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [667] A. Paetznick et al., “Improved quantum processor logical error rates via correction and detection,” Nature, vol. 654, no. 8118, pp. 349–355, Jun. 2026, doi: 10.1038/s41586-026-10628-y. D
- [738] M. Cain et al., “Correlated decoding of logical algorithms with transversal gates,” arXiv:2403.03272, Mar. 2024. D
- [739] H. Perrin, G. Roger, and G. Pupillo, “Correlated Atom Loss as a Resource for Quantum Error Correction,” arXiv:2603.24237, Mar. 2026. S
- [740] BTQ Technologies, “BTQ Technologies' QPerfect Subsidiary and the University of Strasbourg Partner to Support France's First Public Neutral-Atom Quantum Computing Platform,” PR Newswire, Jul. 22, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cbtq-technologies-qperfect-subsidiary-and-the-university-of-strasbourg-partner-to-support-frances-first-public-neutral-atom-quantum-computing-platform-302831874.html - [741] C. Choucair, “BTQ Technologies to Invest Over $2 Million in QPerfect to Advance Neutral Atom Quantum Computing,” The Quantum Insider, Apr. 9, 2025. [Online]. Available: https://thequantuminsider.com/
2025/ P04/ 09/ btq-technologies-to-invest-over-2-million-in-qperfect-to-advance-neutral-atom-quantum-computing/
G Bluvstein et al. (Harvard/MIT/QuEra), Nature 649, 39 (online 2025-11-10; arXiv:2506.20661, 2025-06-25): surface code on up to 448 atoms, 2.14(13)× below threshold in a four-round c… · 2025-11-10 · https://www.nature.com/articles/s41586-025-09848-5
G Evered, Xu, Li, Geim, Bonilla Ataides, Kalinowski, Bluvstein, Maskara, Kokail, Greiner, Vuletic, Lukin (Harvard/MIT), "High-fidelity entangling gates and nonlocal circuits with neu… · 2026-04-28 · https://arxiv.org/abs/2604.25987
G Perrin, Roger, Pupillo (Univ. Strasbourg/CNRS, QPERFECT SAS), "Correlated Atom Loss as a Resource for Quantum Error Correction", arXiv:2603.24237 (2026-03): fast correlated-loss de… · 2026-03 · https://arxiv.org/html/2603.24237
G CONFLICT RESOLVED: the 1.9(4)x and 3.6x figures both appear in arXiv:2506.13724v2 (Princeton [[4,2,2]] metastable 171-Yb) and describe different quantities — the logical decay rate… · 2026-09-04 · https://arxiv.org/html/2506.13724v2
G Hamamatsu Photonics ORCA-Quest qCMOS is the named single-photon-sensitivity camera in the Harvard/QuEra 448-atom fluorescence-imaging line and in MIT, NIST/UMD and Osaka neutral-at… · 2026-09 · https://www.hamamatsu.com/us/en/news/events/2026/APS-DAMOP-2026.html
G Only two acousto-optic deflector suppliers are named across the sourced neutral-atom literature: AA Opto-Electronic (France; DTSX-400 crossed AODs in the Harvard 448-atom system, a… · 2026-09-04 · https://gandh.com/news-and-resources/g-and-h-acousto-optic-deflectors-in-nature-papers
G QuEra: Libra fault-tolerant system 2028 (>256 logical, 10⁻⁶, on Braket) and gigaquop system 2028–29 — its Jan-2024 roadmap had promised 100 logical qubits in 2026 · 2026-06-15 · https://www.quera.com/press-releases/quera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws
G Atom Computing: $100 M Series C (Third Point) plus $100 M DoC CHIPS LOI, total > $300 M, 2026-06-16 · 2026-06-16 · https://www.prnewswire.com/news-releases/atom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html
G DARPA QBI Stage B (announced 2025-11-06, ~12 months, up to $15 M each): Atom Computing, Diraq, IBM, IonQ, Nord Quantique, Photonic Inc., Quantinuum, Quantum Motion, QuEra, Silicon… · 2025-11-06 · https://www.darpa.mil/research/programs/quantum-benchmarking-initiative/stage-b-selection
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הטקסט בעברית נטען…
FPGA real-time decoders (LCD, Deltaflow)
Room-temperature FPGAs running clustering or matching decoders fast enough to clear surface-code syndromes inside the QEC cycle, ahead of GPU and cryogenic alternatives.
Verdict. Throughput under 1 µs per round is published to d=17, but live surface-code decoding is documented only to d=5 and closed-loop correction to d=3; the accuracy gap to neural decoders is real.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Classical hardware consuming syndrome bits and emitting corrections inside the code cycle. The lineage is the backlog argument: if mean decode time exceeds cycle time, undecoded rounds accumulate without bound and the classical hardware sets the logical error rate. FPGAs won for deterministic latency, not speed.
Attributes: a compute module, not a carrier (affinity 0.5); no time, readout, mobility, control or fabrication of its own.
Error structure it consumes: Pauli syndromes from the rotated surface code.
Physics & limits
Throughput must clear one round per cycle — 1.1 µs on Willow-class hardware D[1] — which Riverlane's clustering decoder meets to d=17 D[238]. Reaction latency gates every non-Clifford gate and only a closed loop measures it: Shenzhen's closed one in 550 ns at d=3, inside a 1.25 µs cycle D[729]. Accuracy pays for latency: LCD thresholds at 0.55% against 0.7% for software MWPM D[238], and on identical Willow syndromes matching gave Λ = 2.04 where a neural decoder gave 2.14 D[1]. Area is the other wall: LCD at d=17 takes ~6% of a Xilinx VU19P's logic LUTs (lookup tables) per logical qubit D[238] — ~16 such logical qubits per top-end part.
Engineering state of the art
table
IBM's Relay-BP for the gross code reports a 24 ns iteration and under 1 µs per cycle below p = 3×10⁻³, from simulated syndromes S[48].
IBM's Relay-BP FPGA figures come from simulated syndromes, and the abstract's 24 ns / <1 µs conflicts with the 480 ns per 12-cycle window reported elsewhere fact. Riverlane's Series C is $75 M in its 2024 release and $85 M in its 2026 roadmap. The IBM–AMD FPGA decoder collaboration is reported only by trade press; its terms are not published.
Manufacturing, materials & supply chain
No fab: a commercial FPGA card in the room-temperature rack. Every published real-time decoder runs on AMD/Xilinx silicon (VU19P for LCD D[238], VMK180 for Micro Blossom D[727]); the only merchant alternative changed hands when Intel's sale of 51% of Altera to Silver Lake at an $8.75 B valuation, announced in April 2025, closed on 2025-09-15 G[735] — a duopoly with one side under private equity. High-end FPGAs sit inside US export-control scope. The I/O burden is the syndrome pipe: trivial at 10³ qubits, but at 10⁴–10⁶ the rate forces predecoding at 4 K or many parallel cards.
Role in the stack
An alternate decoder on the transmon lattice with tunable couplers. Requires the rotated surface code and provides the correction stream fault tolerance needs; it replaces GPU decoding, whose tail latency is non-deterministic — 3.84 µs mean, 3.96 µs max just to cross NVQLink C[324]. Its contribution to the derived clock is a floor, not a term: it must stay under the 1.1 µs cycle, and does. Verification: these are decoder-in-isolation figures on replayed or simulated syndromes; only two loops are live — the d=3 one and the in-loop clustering decoder on Rigetti Ankaa-2, the register's one carrier; Micro Blossom's quoted 367 ns is a repository figure in no paper, the published number being 0.8 µs D[727].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Riverlane | supplier | UK | LCD and Deltaflow, the only merchant QEC stack | D[238] |
| AMD | supplier | US | The FPGA silicon under every published decoder | D[238] |
| user | US | 63 µs baseline at d=5 D[1], then neural decoding at d=7 | D[2] | |
| IQA Shenzhen | research | CN | First closed-loop neural FPGA decode on a live processor | D[729] |
Money.
2024-08-06 · Riverlane · Series C · $75 M · Planet First Partners lead · closed C[661]fact
2025-09-15 · Intel/Altera · divestment of 51% · $8.75 B enterprise valuation · Silver Lake · closed (announced 2025-04-14) G[735]fact
Market & supply chain. One merchant decoder vendor, one dominant FPGA vendor, NVIDIA pushing NVQLink as the alternative — open endpoint, single-sourced accelerator C[324]. Riverlane's stack ships integrated with Qblox control hardware C[659]. It pays into G3 and G4 only.
IP & standards. Riverlane GB 2641501 A "Quantum decoder" (published 2025-12-10) claims grouped processing elements running clustering on the decoding hypergraph — the LCD architecture itself G[662]. No decoder standard exists.
Roadmaps & track record. Riverlane (2026-03-12 · megaquop before 2030, teraquop from 2033 · LCD published on time C[658]). IBM (2025-10 · FPGA gross-code decoding · still simulation as of 2026-09-04 S[48]).
Strategic reading. Whoever owns the decoder sits between every superconducting QPU and fault tolerance — but the layer is thin enough that QPU vendors build it in-house, as IBM and Google did. AMD wins either way; the threat is NVQLink commoditising the interface.
Outlook & open questions
Confirm by end-2027: an FPGA decoder closing the loop on live syndromes at d ≥ 7 — no live d=7 decode by any decoder is documented, Google's neural d=7 result D[2] included — or Relay-BP on real gross-code hardware; demote if neither happens. Best case 2029: a portable interface with second-source silicon; worst case, per-vendor decoders nobody can compare. Does reaction latency or throughput bind first at d=17? Do decoder vendors survive QPU vendors building in-house? Does export control reach FPGAs?
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. S
- [238] A. B. Ziad et al., “Local clustering decoder as a fast and adaptive hardware decoder for the surface code,” Nat. Commun., vol. 16, no. 1, Art. no. 11048, Dec. 2025, doi: 10.1038/s41467-025-66773-x. D
- [324] S. Caldwell et al., “NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors,” NVIDIA Technical Blog, Nov. 17, 2025. [Online]. Available: https://developer.nvidia.com/
blog/ Cnvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/ - [658] Riverlane, “Riverlane publishes QEC Technology Roadmap that can accelerate quantum computing's path to utility scale by 3–5 years,” Mar. 12, 2026. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-publishes-qec-technology-roadmap - [659] Qblox; Riverlane, “Qblox and Riverlane Demonstrate Integration Enabling Real-Time Quantum Error Correction,” PR Newswire, Mar. 17, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cqblox-and-riverlane-demonstrate-integration-enabling-real-time-quantum-error-correction-302716254.html - [661] Riverlane, “Riverlane raises $75 million to meet surging global demand for quantum error correction technology,” Aug. 6, 2024. [Online]. Available: https://www.riverlane.com/
press-release/ Criverlane-raises-75-million-to-meet-surging-global-demand-for-quantum-error-correction-technology - [662] A. B. Ziad, A. Zalawadiya, B. Barber, and L. Skoric, “Quantum decoder,” Google Patents, Dec. 10, 2025. [Online]. Available: https://patents.google.com/
patent/ GGB2641501A/ en - [727] Y. Wu, N. Liyanage, and L. Zhong, “Micro Blossom: Accelerated Minimum-Weight Perfect Matching Decoding for Quantum Error Correction,” Proc. 30th ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS '25), vol. 2, Mar. 2025, doi: 10.1145/3676641.3716005. arXiv:2502.14787. Also https://github.com/
yuewuo/ . Dmicro-blossom - [729] X. Yang et al., “Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder,” arXiv:2605.04892, May 2026. Also https://arxiv.org/
html/ . D2605.04892 - [735] Altera, “Altera Closes Silver Lake Investment to Become World's Largest Pure-play FPGA Solutions Provider,” Sep. 15, 2025. [Online]. Available: https://www.altera.com/
newsroom/ Gnews/ press-release/ altera-silver-lake
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In-loop RL calibration / control steering
Detection events from the running code double as the reward signal for a reinforcement-learning agent that retunes control parameters during QEC, replacing scheduled recalibration.
Verdict. One team, one chip, one paper; it improves the point error at fixed distance and is not shown to change Λ, which is what the 10⁻⁶ milestone actually needs.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
RL as a control optimiser on superconducting qubits is not new: the widely quoted 99.92% CZ record between two fluxonium qubits coupled through a transmon is an RL-optimised mean of 99.922(9)% from 2023 fact, but offline and per-gate. Sivak, Morvan, Broughton, Cortiñas et al. (Google, arXiv 2025-11-11; Nature 655, 2026-07-08) changed the loop: detection events serve as both syndromes and learning signal, so calibration runs concurrently with computation [2].
a = 1.0, a fully engineered classical-control layer, f = coherent — it chases systematic drift (TLS, flux, temperature), not stochastic Pauli error [graph].
Physics & limits
No new physical floor: this tracks an existing floor without the dead time between calibrations. The load-bearing claim is architectural — optimisation speed independent of system size D[2], the only route past a per-parameter sweep that dies above ~10³ knobs. The limits follow from what the agent sees and what it turns: an averaged rate of detection events, and single-qubit and CZ gate parameters only D[2]. Willow's roughly hourly correlated bursts do produce detection events, but they decay within ~400 µs D[1], far faster than the agent can respond, and the paper leaves such fast correlated drift to hardware mitigation D[2]. Leakage out of the computational space, which Willow clears with a dedicated removal step after every round D[1], is not treated in the paper, and readout, at ~10⁻², is not among the tuned parameters. It does not change the exponent: no Λ is reported for the record d=7 run, so what moved is the point error at fixed distance, not the slope that decides whether d≈25 reaches 10⁻⁶.
The premise of in-loop recalibration is contested by a 2026 measurement: long-lived two-level systems (TLS) on a transmon give the environment 20 µs to 1 ms of memory — hundreds of ~1 µs error-correction cycles — so errors become history- and protocol-dependent, which the authors contrast with the Markovian (memoryless) assumption behind continuous calibration P[890].
Engineering state of the art
table
| Date | Figure | Who | Tag+key |
|---|---|---|---|
| 2026-07-08 | d=7 surface code decoded with AlphaQubit 2 (no live decode stated): 7.72(9)×10⁻⁴ per cycle; no Λ reported | Google Quantum AI | D[2]fact |
| 2026-07-08 | d=5 colour code, Tesseract decoder: 8.19(14)×10⁻³ per cycle; 3.5× stability against injected drift | Google Quantum AI | D[2] |
| 2024-12-09 | Λ = 2.14(2) with the neural decoder vs 2.04(2) with ensembled matching on identical Willow syndromes | Google Quantum AI | D[1]fact |
AlphaQubit 2's own real-time benchmarks (arXiv:2512.07737) ran on recorded data, and the reinforcement-learning paper does not state that its d=7 decode ran live.
Manufacturing, materials & supply chain
No dedicated silicon and, unlike matching or clustering decoders, no FPGA resource claim to audit fact. The cost is control-plane traffic — detection events out, parameter updates in, over the decoder's own link; NVQLink's 3.84 µs mean, 3.96 µs maximum round trip is the vendor-neutral version of it Cfact. Updates run on a slow timescale outside the 1.1 µs cycle, which is why it coexists with Willow where heavier in-loop computation would not. Supply is GPU/TPU capacity plus the control stack; no specific export rule.
Role in the stack
Requires no decoder inside its control loop — the reward is the detection-event rate; its decoder steering reweights a matching graph from logical-error estimates, not in real time, and the record d=7 run was decoded separately with the neural decoder AlphaQubit 2, published on its own only as a December 2025 preprint whose real-time speed was benchmarked on recorded or simulated data D[2]fact. Superconducting transmons only; derived round unchanged at 0.65 µs against the measured 1.1 µs QEC cycle, ~0.91 MHz. Verification: no Λ for the record run, no second-platform replication, and the only live closed-loop neural decoding anywhere is a d=3 demonstration with a 550 ns loop D[729]. No value conflict: the 20% and >1,000 parameters in trade press P[742] are the paper's own — about 20% further logical-error suppression after conventional calibration, over a thousand steered parameters — beside its 3.5× stability gain against injected drift D[2].
Actors & economics
Who.
| Organisation | Role | Country | What exactly | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | RL control, AlphaQubit 2, Willow | D[2] |
| Google DeepMind | developer | UK | Neural decoders, AlphaQubit line | D[657] |
| Q-CTRL | supplier | AU | Boulder Opal calibration software | C[743] |
| IQA Shenzhen | research | CN | Only live closed-loop neural decoding | D[729] |
Money.
2024-10-08 · Q-CTRL · Series B expanded · USD $113 M (AUD $166 M) · GP Bullhound lead · closed C[743]
2025-10-03 · Google Quantum AI · absorbed Atlantic Quantum, cold-stage control · undisclosed Pfact
2025-11-06 · DARPA QBI Stage B · IBM the only transmon vendor, Google absent · ≤$15 M each fact
Market & supply chain. No component market; the priced substitute is calibration software plus GPU/TPU cycles, sold only by Q-CTRL, on Diraq, Oxford Quantum Circuits and Rigetti C[743]. Pays G3/G4.
IP & standards. No dated patent family for RL-steered QEC calibration as of 4 Sep 2026; Google publishes the method and withholds the decoder — that is the moat.
Roadmaps & track record. Google's next milestone, a long-lived logical qubit at 10⁻⁶ (no date): 7.72×10⁻⁴ at d=7 is three orders short, needing d≈25 at Λ≈2 D[1]; Google is absent from QBI Stage B G. Q-CTRL shipped Boulder Opal on three platforms by 2024-10 — delivered, at nothing like Google's scale.
Strategic reading. Software margin on hardware someone else owns. If it diffuses, control vendors and Q-CTRL capture it and calibration headcount falls; if AlphaQubit 2 stays in-house, Google's advantage is the decoder, not the RL. Substitution threat: hardware that drifts less — fluxonium, cold-stage SFQ control — shrinks the problem.
Outlook & open questions
Confirm if RL-in-loop calibration appears on a second platform, or a Λ is published for an RL-steered run; demote if it stays Willow-only. Best case 2029: standard across superconducting FT stacks, sold by control vendors. Worst case: one unreplicated chip. Open: does size-independent optimisation survive outside simulation, and can the loop be made decoder-agnostic?
References
- [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
- [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
- [657] J. Bausch et al., “Learning high-accuracy error decoding for quantum processors,” Nature, vol. 635, no. 8040, pp. 834–840, Nov. 2024, doi: 10.1038/s41586-024-08148-8. D
- [729] X. Yang et al., “Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder,” arXiv:2605.04892, May 2026. Also https://arxiv.org/
html/ . D2605.04892 - [742] J. Burt, “Google Uses AI Reinforcement Learning For Quantum Error Correction,” The Next Platform, Jul. 20, 2026. [Online]. Available: https://www.nextplatform.com/
compute/ P2026/ 07/ 20/ google-uses-ai-reinforcement-learning-for-quantum-error-correction/ 5275023 - [743] Q-CTRL, “Q-CTRL Sets Global Quantum Technology Fundraising Record, Increasing Series B to USD $113M, Led by GP Bullhound,” Oct. 8, 2024. [Online]. Available: https://q-ctrl.com/
blog/ Cq-ctrl-sets-global-quantum-technology-fundraising-record-increasing-series-b-to-usd-113m-led-by-gp-bullhound - [890] J. R. Guimarães et al., “Quantum environment afterglow from broadband excitation spectroscopy in superconducting qubits,” arXiv:2609.31280, Sep. 2026. P
G AlphaQubit2 is named and described as "a scalable and real-time neural decoder for topological quantum codes" in Sivak, Morvan, Broughton et al. (Google Quantum AI), "Reinforcement… · 2026-07-08 · https://link.springer.com/article/10.1038/s41586-026-10759-2
G Google Quantum AI, "Quantum error correction below the surface code threshold" (Nature 638, 920; arXiv:2408.13687): the real-time decoder for the distance-5 10^6-cycle run is a spe… · 2024-12-09 · https://arxiv.org/abs/2408.13687
G Ding, Hays, Sung, ... Serniak, Oliver (MIT / MIT Lincoln Laboratory), Phys. Rev. X 13, 031035 (2023-09-25): fluxonium CZ with transmon coupler, peak CZ fidelities 99.85-99.9%, rein… · 2023-09-25 · https://journals.aps.org/prx/abstract/10.1103/PhysRevX.13.031035
G Ziad, Zalawadiya, Topal, Camps, Gehér, Stafford, Turner (Riverlane), "Local clustering decoder as a fast and adaptive hardware decoder for the surface code", Nature Communications… · 2025-12-17 · https://www.nature.com/articles/s41467-025-66773-x
G NVIDIA developer blog (2025-11-17) detail: RoCE round trip 3.84 us mean, 0.035 us standard deviation, 3.96 us MAXIMUM over 1,000 samples (a bounded tail, not just a mean); BP+OSD o… · 2025-11-17 · https://developer.nvidia.com/blog/nvidia-nvqlink-architecture-integrates-accelerated-computing-with-quantum-processors/
G Atlantic Quantum (fluxonium, cold-stage control) joined Google Quantum AI, 2025-10-03 · 2025-10-03 · https://thequantuminsider.com/2025/10/03/atlantic-quantum-joins-google-quantum-ai/
G DARPA QBI Stage B (announced 2025-11-06, ~12 months, up to $15 M each): Atom Computing, Diraq, IBM, IonQ, Nord Quantique, Photonic Inc., Quantinuum, Quantum Motion, QuEra, Silicon… · 2025-11-06 · https://www.darpa.mil/research/programs/quantum-benchmarking-initiative/stage-b-selection
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Microwave–optical transducer (useful efficiency)
A quantum-coherent microwave-to-telecom converter good enough to entangle superconducting processors in separate refrigerators; nothing in 2026 comes close.
Verdict. No device combines efficiency above 50%, added noise well below one photon and MHz repetition; IBM's analysis puts the gap at three orders of magnitude on all three axes at once.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The slot is a device converting an itinerant microwave photon at a transmon's frequency (4–10 GHz) into a telecom photon near 194 THz with the quantum state intact, and back, so two dilution refrigerators can be entangled over ordinary fibre instead of a cryogenic coaxial bridge. Three mechanisms compete, all parametric beamsplitter interactions driven by a strong optical pump: electro-optic in lithium niobate, piezo-optomechanical via a GHz phonon, and magneto-optic via a magnon in yttrium iron garnet. One quantity governs all three: cooperativity C = 4g²/κ₁κ₂ [775] — efficiency rises with C, input-referred added noise falls as N_add ∝ n_th/C. The line runs from cavity optomechanics of 2010–2013 to the first quantum-enabled microwave–optical interface, an electro-optic device at 60 mK with sub-photon added noise (2022, IST Austria) P[775].
Attributes. Carrier affinity: fully fabricated — a lithographic cavity. Characteristic time and determinism: no gate time defined; entanglement through the link is heralded, never deterministic. Readout: none of its own. Mobility: flying — the carrier leaves the refrigerator. Control at placement: electro-optic, pumped optically at millikelvin. Dominant error as the code sees it: loss — heralded photon loss (erasure), plus pump-induced thermal photons creating false heralds. Manufacturing: photonic integrated circuit on superconducting resonators.
Physics & limits
Everything hard here follows from one ratio: an optical photon is about 2×10⁴ times more energetic than a microwave one. A 1,550 nm photon carries 0.80 eV — roughly 9,300 K — and must be delivered in quantity to a stage whose cooling budget is 25–30 µW at 20 mK on commercial dilution refrigerators P[311]. Absorbed pump light breaks Cooper pairs and heats the phonon bath, and that heat reappears as thermal occupation in the mode carrying the qubit signal. Push the pump and efficiency rises together with added noise; back off and the device is quantum-limited but converts almost nothing. The trade shows up as duty cycle: the most efficient device in [786]'s comparison — an electro-opto-mechanical converter at 0.38, below the 47% of 2018 P[775] — ran at 5,000 µs repetition and 0.22 kHz bandwidth D[786].
The useful condition is η > 1/2 with N_add ≪ 1 S[775], and the asymmetry matters: loss can be heralded away at the cost of rate, excess noise cannot be removed at all. The code therefore sees erasure plus a rate penalty when the device is good, and irreducible infidelity when it is not. What would move the floor: more nonlinearity per watt dissipated, superconductors tolerating pump light, and protocols that stop demanding determinism — the QphoX/IST claim that heralding plus distillation reaches >99% Bell fidelity with transducers that already exist S[786], against IBM's calculation that 99.7% remote gates at MHz rates need "3 orders of magnitude in added noise, efficiency, and repetition rates" S[306]. That disagreement is the live question.
Engineering state of the art
Each record belongs to a different device; no two can be had at once.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2018 | Total efficiency 47%, added noise far above one photon | Higginbotham et al., NIST/JILA | P[775] |
| 2022 | Internal efficiency 99.5%, total 15%, added noise 0.16 photons at 60 mK, pulsed | Sahu et al., IST Austria | P[775] |
| 2022 | Efficiency 0.38 at 5,000 µs repetition, 2.2×10⁻⁴ MHz bandwidth | Brubaker et al., JILA | D[786] |
| 2024 | Total efficiency 3×10⁻⁶, ~10 µs repetition, 15 MHz bandwidth, 6 added photons | Weaver et al., QphoX | D[786] |
| 2025-02 | Optical readout of a superconducting qubit through a transducer | QphoX, Rigetti, Qblox | C[787] |
| 2025 | Added noise 0.12 photons at 30 MHz bandwidth (thin-film LiNbO₃) | Warner et al. | P[775] |
table
| Quantity | Best demonstrated | Needed | Shortfall |
|---|---|---|---|
| Total efficiency | 15% pulsed P[775]; 3×10⁻⁶ against a real qubit D[786] | > 50% S[775] | ~3× at 15%; ~5 orders at 3×10⁻⁶ |
| Added noise | 0.12–0.16 photons P[775] | ≪ 1 | in isolation only |
| Repetition | 5.9–10 µs at low efficiency D[786] | MHz, continuous | 1–3 orders |
| All three at once | none | — | 3 orders each S[306] |
The dominant budget term is pump-induced heating — efficiency per microwatt of pump, the metric [786] argues should replace efficiency, because cooling capacity rather than conversion physics caps channel count.
Manufacturing, materials & supply chain
Every published transducer is a single research die: no wafer-level yield or uniformity data for any platform as of 3 Sep 2026, and no foundry process of record. The candidate stacks — thin-film lithium niobate on insulator, silicon nitride, barium titanate, silicon optomechanical crystals — are the materials of the photonic-IC foundry slot this one requires, where 300 mm capability is proven for another purpose: PsiQuantum's Omega runs barium-titanate switches and superconducting nanowire detectors on GlobalFoundries 300 mm at median detector efficiency 93.4% D[169]. Nobody has put a transducer on that route. Lithium-niobate substrates come from a small, largely Chinese supplier base, refrigerators with optical feedthroughs from Bluefors and Oxford Instruments; the binding constraint is cooling power at 20 mK, which nobody sells more of. Export exposure: the US Bureau of Industry and Security interim final rule of 2024-09-06 controls quantum computers within its qubit-count and C-NOT-error bands, components and cryogenic equipment, but no ECCN names the transducer (mapping unverified below).
Control, readout & I/O burden
Per channel: a pump fibre into the mixing chamber, a microwave line, a filter chain, and photon-counting or heterodyne detection. Fibre carries almost no static heat load — the load is the pump, tens of microwatts to milliwatts per channel against 25–30 µW of cooling at 20 mK P[311]. At 10³ channels that budget is exceeded some 300- to 40,000-fold unless efficiency per microwatt improves comparably; 10⁴ and 10⁶ are not discussable. Heralding needs a round trip to a mid-point detector at ~5 ns per metre, so a 10 m link costs ~100 ns against 6–10 µs repetition D[786]: the transducer, not the speed of light, is the slow element.
Role in the stack
The only architecture served is superconducting transmons (Google, IBM, Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu). It requires the transmon and a photonic-IC foundry able to co-integrate electro-optic or optomechanical structures with superconducting resonators and detectors, and it replaces the cryogenic microwave link between refrigerators — competition, not complement: IBM delivered Loon with c-couplers on 2025-11-12 C[49] and reported two coupled cryogenic cells on 2026-08-19 C[50] while its own researchers publish the analysis showing optical links are three orders away S[306]. The node sits where superconducting qubits meet photonic fabrication, which is why no vendor owns it. Derived clock: transport dominates at about 1.0×10⁻⁵ s (the 6–10 µs repetition D[786]) against 159 ns of gate layers and 282 ns readout, so derived clock = sum of the syndrome round: gate layers + transport + readout + reset runs ~16× the 0.65 µs on-chip round. Neighbouring empty slots: the cryogenic microwave link at multi-refrigerator scale, and the photonic-IC foundry line.
Evidence — how the numbers were measured
Total efficiency is a calibrated scattering ratio between microwave and optical ports, so the number depends on where the reference planes sit — internal efficiency excludes coupling and is not what a link cares about. Added noise is input-referred with the pump running. The protocols miss duty cycle and thermal recovery time, routinely absent from headline claims, and end-to-end link fidelity with a real qubit at each end, never reported between two refrigerators. Conflicts: [775] lists 47% (2018) as the efficiency record while [786] tabulates 0.38 (2022) with the repetition time that makes it meaningful — both correct, incomparable; the figures reported alongside a duty cycle [786] are the ones to trust. The headline device in the technology-graph record (15% total, 0.16 photons) and the device used to read a qubit (3×10⁻⁶) differ by ~5×10⁴ P[775]D[786].
The per-platform records (Sahu 2022, Higginbotham 2018, Warner 2025, Sonar 2025) come from the tables of review [775], a preprint by authors with no experimental record in the field, not from the primary papers. [306] (IBM) requires three orders of magnitude of improvement in noise, efficiency and repetition rate, while [786] (QphoX/IST) claims >99% Bell fidelity with existing transducer performance through protocol design; the two remain unreconciled. The most recent primary device figures date to 2025. The title, authors, publication date and measured readout fidelity of the Nature Physics paper on the QphoX–Rigetti–Qblox optical readout are not given in [787], and [790] is paywalled. Not published: the ECCN for microwave-optical transducers under the BIS interim final rule of 2024-09-06; a dated patent-family count from a named database; QphoX's funding after 2024-01; and Nu Quantum's cumulative funding.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QphoX | developer | Netherlands | Piezo-optomechanical "quantum modem"; optical readout of a Rigetti transmon; multi-channel programme at the NQCC | C[788]C[789] |
| IST Austria (Fink) | research | Austria | Bulk-LiNbO₃ device holding the internal-efficiency and noise records; co-author of the optical-link architecture | P[775]S[786] |
| Stanford (Safavi-Naeini) | research | USA | Piezo-optomechanical silicon crystals; 2023 and 2025 noise and bandwidth records | P[775]D[786] |
| IBM | user / analyst | USA | Published the requirements analysis and a distillation protocol; building microwave links instead | S[306]C[50] |
| Rigetti | user | USA | Supplies Novera QPUs as the microwave side of optical-readout experiments | C[789] |
| NQCC | user / funder | UK | Hosts the multi-channel optical-readout system under an Innovate UK and RVO Eureka grant | C[789] |
| Nu Quantum | adjacent developer | UK | Quantum Networking Unit for data centres; performs no microwave-optical conversion | C[781] |
| Photonic Inc | substitution threat | Canada | Silicon T centres emit telecom photons natively, bypassing transduction | Pfact[186] |
| Bluefors | supplier | Finland | Refrigerators with optical feedthroughs; cooling power caps channel count | S[786] |
Money.
- 2024-01-17 · QphoX · Series A · €8 M · QDNL Participations (lead), EIC Fund, Quantonation, Speedinvest, High-Tech Gründerfonds, Delft Enterprises · cumulative €10 M with a €2 M 2021 seed · closed C[788]
- 2025-05-06 · QphoX, Rigetti and NQCC · Eureka grant (RVO and Innovate UK), 33 months, multi-channel optical readout of a 9-qubit Novera at the NQCC · undisclosed · announced C[789]
- 2025-11-06 · DARPA QBI Stage B · eleven teams, up to $15 M each — no transducer company listed, nor on Stage A · programme · announced fact[65]
- 2025-12-10 · Nu Quantum · Series A · $60 M · National Grid Partners (lead), Gresham House, Morpheus, Amadeus, IQ Capital, Ahren, NSSIF, Sumitomo/Presidio · closed C[781]
- 2026-05-12 · Photonic Inc · final close · $200 M at $2 B, $350 M total · Microsoft among returning investors · closed Pfact[186]
- 2026-06-02 · IBM · commitment · > $10 B over five years, funding the roadmap of 2025-06-10 R[67] · modularity money goes to microwave couplers, not optics · announced C[310]fact
The ledger is the finding: disclosed private capital in transduction as a product is about €10 M, at one company, closed two and a half years ago. Adjacent networking raised six times that in one round without touching conversion, and the largest benchmarking programme in the field funds no transducer team.
Market & supply chain. Nobody sells a transducer; QphoX's modem is a grant-funded research instrument. The enabling market is photonic — lithium-niobate substrates, silicon nitride and barium titanate foundry runs, nanowire detectors, cryogenic feedthroughs — with concentration risk highest in substrates and refrigerators. G6 networking pays first and G4 large-scale fault tolerance is the real prize, since multi-refrigerator scale-out is the only route past a few thousand transmons per fridge; G7 benefits indirectly as fibre replaces coax. G1, G2 and G5 do not pay for it at all, which is why venture money has not arrived.
IP & standards. No dated patent-family count from a named database was obtained (unverified below). No interoperability standard exists for a microwave-optical quantum link; the only fixed interface is the telecom fibre plant and the ITU wavelength grid, which is why serious designs target the C band.
Roadmaps & track record. QphoX (promised 2024-01 · optical readout of a commercial QPU · delivered, Nature Physics 2025-02 C[787]). QphoX–Rigetti–NQCC (promised 2025-05 · multi-channel readout of nine Novera qubits in 33 months, due early 2028 · no public result as of 2026-09-03 C[789]). Nu Quantum (promised · Networking Unit in 2025 · launched 2025-06-12 as a product-prototype, no measured rate or fidelity C[781]fact). IBM (promised 2025-06 · module couplers with Cockatoo in 2027 · Loon delivered 2025-11-12, two coupled cryogenic cells reported 2026-08-19, on schedule C[49]C[50]R[67]). QphoX has done the only thing a customer can inspect, on thin capital; IBM's analysis is credible precisely because IBM has no interest in an optimistic answer; Nu Quantum is well funded but solving the layer above. Nobody has published a dated roadmap to efficiency above one half with sub-photon noise, so 2030 in the technology graph is a placeholder.
Strategic reading. If the slot fills, superconducting vendors escape the single-refrigerator ceiling and microwave couplers become a stopgap; winners are photonic foundries, detector vendors and whoever owns the transducer IP, losers are cryogenic-cabling and very-large-refrigerator suppliers. If it stays empty, winners are the platforms whose carriers are already optical — trapped ions with frequency conversion, silicon T centres, neutral atoms. Bargaining power sits with the QPU vendors: they have an alternative and the suppliers do not.
Outlook & open questions
Confirm if any group publishes one device measured at total efficiency ≥ 5%, added noise ≤ 0.2 photons and duty cycle ≥ 10% simultaneously; if the QphoX–Rigetti–NQCC programme shows ≥ 4 simultaneous optical readout channels; or if heralded entanglement between transmons in two separate refrigerators is measured above 90% Bell fidelity. Demote the slot to "bypassed" if by September 2028 no remote optical Bell pair between transmons exists and IBM's Cockatoo couplers have shipped. Best case by 2029: a four-to-eight-channel module at roughly 10% efficiency, ~0.1 added photons, a few hundred kHz herald rate S[306]S[786]; worst case, single-channel laboratory demonstrations only and the slot still empty in 2030.
Open questions. (1) Does pump power per channel scale sub-linearly, or does the mixing chamber cap channel count at order ten? (2) Is η > 1/2 actually required, or does heralding plus distillation make η ≈ 10⁻² usable — the direct [306] versus [786] disagreement? (3) Which material wins, thin-film lithium niobate for bandwidth or silicon optomechanics for noise? (4) Who pays, given no transducer team in QBI and about €10 M of disclosed private capital? (5) Will a superconducting vendor acquire a transducer team or build in-house? Watch the NQCC multi-channel milestone and IBM's Cockatoo delivery in 2027.
References
- [49] IBM, “IBM Delivers New Quantum Processors, Software, and Algorithm Breakthroughs on Path to Advantage and Fault Tolerance,” Nov. 12, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance C - [50] C. Dundon, S. Hall, M. Hollister, and A. Lindler, “IBM's new modular architecture for cryogenic systems,” IBM Quantum Computing Blog, Aug. 19, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ modular-cryogenics - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [67] IBM, “IBM Sets the Course to Build World's First Large-Scale, Fault-Tolerant Quantum Computer at New IBM Quantum Data Center,” Jun. 10, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-06-10-IBM-Sets-the-Course-to-Build-Worlds-First-Large-Scale,-Fault-Tolerant-Quantum-Computer-at-New-IBM-Quantum-Data-Center R - [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [186] M. Abdel-Kareem, “Photonic Inc. Reaches $2B Valuation with $200M Final Close,” Quantum Computing Report, May 12, 2026. [Online]. Available: https://quantumcomputingreport.com/
photonic-inc-reaches-2b-valuation-with-200m-final-close/ P - [306] N. Dirnegger et al., “Distilled remote entanglement between superconducting qubits across optical channels,” arXiv:2503.10842, Mar. 2025. S
- [310] IBM, “IBM Commits More Than $10 Billion to Quantum Computing, Funding Its Roadmap from Today's Leading Systems to the World's First Fault-Tolerant Quantum Computers,” Jun. 2, 2026. [Online]. Available: https://newsroom.ibm.com/
2026-06-02-ibm-commits-more-than-10-billion-to-quantum-computing,-funding-its-roadmap-from-todays-leading-systems-to-the-worlds-first-fault-tolerant-quantum-computers C - [311] O. W. Kennedy et al., “Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits,” arXiv:2602.12773, Feb. 2026. P
- [775] T. A. Aditto, J. S. Ifty, and K. Zahin, “Toward Scalable Heterogeneous Quantum Networks: Microwave-Optical Transduction Across Platforms,” arXiv:2605.26976, May 2026. P
- [781] Nu Quantum, “Nu Quantum Raises $60M Series A in Largest Financing Round for Quantum Computer Networking,” Dec. 10, 2025. [Online]. Available: https://www.nu-quantum.com/
news/ Cnu-quantum-raises-60m-series-a-in-largest-financing-round-for-quantum-computer-networking - [786] M. J. Weaver, G. Arnold, H. Weaver, S. Gröblacher, and R. Stockill, “Scalable Quantum Computing with Optical Links,” arXiv:2505.00542, May 2025. D
- [787] Rigetti Computing, “Research from QphoX, Rigetti, and Qblox Demonstrating Optical Readout Technique for Superconducting Qubits Published in Nature Physics,” Rigetti Investor Relations, Feb. 11, 2025. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ research-qphox-rigetti-and-qblox-demonstrating-optical-readout - [788] QphoX, “QphoX raises €8m to bring quantum modem technology to market, building towards the quantum internet,” Jan. 17, 2024. [Online]. Available: https://qphox.eu/
news/ Cqphox-raises-e8m-to-bring-quantum-modem-technology-to-market-building-towards-the-quantum-internet/ - [789] Rigetti Computing, “QphoX, Rigetti and the NQCC Announce Collaboration on Multi-Channel Optical Readout of Quantum Processors,” Rigetti Investor Relations, May 6, 2025. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ qphox-rigetti-and-nqcc-announce-collaboration-multi-channel - [790] M. Abdel-Kareem, “QphoX, Rigetti, and Qblox Demonstrate Optical Readout Technique for Superconducting Qubits,” Quantum Computing Report, Feb. 14, 2025. [Online]. Available: https://quantumcomputingreport.com/
qphox-rigetti-and-qblox-demonstrate-optical-readout-technique-for-superconducting-qubits/ P
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Multi-chip modules / l-couplers (same cryostat)
Splitting a superconducting processor across several dies inside one cryostat, joined by bump-bonded chiplet links or metre-scale superconducting l-couplers.
Verdict. Chiplet tiling ships and costs fidelity — 99.5% at four chiplets, 99.1% at twelve; l-couplers have no published fidelity. Demote if no two-module entangling figure by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A multi-chip module partitions one processor across several superconducting dies sharing a single dilution refrigerator, with quantum-coherent links between them. Two different links wear the label. The short one is a chiplet join: dies flip-chip mounted on a common carrier at sub-millimetre pitch, coupled through indium bumps or vacuum-gap capacitors, so an inter-die coupler is electrically a slightly longer on-chip coupler. The long one is IBM's "l-coupler", a superconducting cable of centimetre-to-metre length carrying a microwave mode between separately packaged modules under one mixing chamber. Both differ from inter-fridge links, which cross a room-temperature gap, and from on-chip long-range couplers, which never leave the die.
Lineage: Rigetti entangled qubits across four separate silicon dies in 2021-09, iSWAP 99.1 ± 0.5% and CZ 98.3 ± 0.3%, with a Bell violation between dies D[747]; SUSTech linked five modules with aluminium coaxial interconnects in 2023-02 D[748]; IBM says l-couplers were "first demonstrated in 2024" on Flamingo C[481], and in 2024-09 published low-loss indium joins for the superconducting cables of such links, tested on 1 m of aluminium coax with no qubit measured through it D[750]. The graph record dates the node to 2025, when tiling became a shipped product rather than a demonstration.
Attributes. Affinity: fully fabricated, a packaging structure with no natural counterpart. Characteristic time and determinism: not applicable — the node carries no entangling primitive, it inherits the gate it transports. Readout: none. Mobility: long-range, the property it exists to supply. Control: microwave at millikelvin. Error structure as the code sees it: coherent. Manufacturing: superconducting lithography plus packaging steps.
Physics & limits
The short-link floor is frequency crowding, not loss. Each chiplet is a separate fabrication instance with its own junction-resistance distribution, so tiling k dies convolves k frequency distributions that were never co-targeted; collisions between qubit, coupler and inter-die modes are fixed at packaging time and cannot be tuned away. Hence the coherent error structure: a mis-set detuning is a deterministic phase, not a stochastic click. The bonds themselves are benign — Rigetti's multi-chip tunable couplers, built from vacuum-gap capacitors or indium bumps, reached a CZ of 99.13 ± 0.15% in 56 ns through a coupler bridging four chips, "at the same level" as a single-chip tunable coupler, with no coherence penalty from one or more bonds D[749].
The long-link floor is cable loss and mode density. A metre-scale cable is a multimode resonator whose free spectral range is of order 100 MHz, so tens of modes fall in the 3–5.5 GHz band the qubits use D[750]. Loss sets transfer error: at an internal quality factor of 1.24 × 10⁶ on an indium press-mold cable-to-chip join, photon lifetime is Q/ω ≈ 49 µs, so a 100 ns inter-module SWAP costs about 2 × 10⁻³ S[750]. Joins dominate in practice — contact resistances of 6 × 10⁻⁴ Ω at an inner-conductor splice and 8.5 × 10⁻⁴ Ω cable-to-chip are the measured levers D[750].
Underneath both is a yield argument: monolithic yield falls as y^N in qubit count, and tiling k chiplets of n qubits replaces one exponential with k smaller ones plus an assembly step. The price shows in the only shipped data, 99.5% at four chiplets against 99.1% at twelve C[36], [751]. Moving the floor needs co-targeted junction trimming across a chiplet set Dfact and joins whose loss and mode comb stay out of the way.
Engineering state of the art
Best demonstrated as of 2026-09-03: inter-module SWAP at the 99% level in under 100 ns between two modules in one cryostat, remote-entanglement error near 1% D[752]. Typical at scale: Rigetti's Cepheus-1-108Q, 108 qubits from twelve 9-qubit chiplets, median two-qubit 99.1%, single-qubit 99.9%, ~60 ns gates C[36]. No l-coupled processor exists; IBM's 2026 milestone is two coupled cryogenic cells with no qubits in them C[50].
Records timeline
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2021-09 | iSWAP 99.1 ± 0.5%, CZ 98.3 ± 0.3% across four dies; Bell violation | Rigetti | D[747] |
| 2023-02 | five modules on Al coax, Q 8.1 × 10⁵, transfer and Bell 99%, 12-qubit GHZ 55.8 ± 1.8% | SUSTech | D[748] |
| 2023-08 | CZ 99.13 ± 0.15% in 56 ns through a coupler bridging four chips | Rigetti | D[749] |
| 2024-09 | indium cable-to-chip join, Q 1.24 × 10⁶, contact resistance 8.5 × 10⁻⁴ Ω | IBM | D[750] |
| 2025-06 | inter-module SWAP 99% in < 100 ns, remote entanglement error ≈ 1% | Illinois | D[752] |
| 2025-07-16 | 36 qubits, four chiplets, median 2Q 99.5%, 2× error cut vs Ankaa-3 | Rigetti | C[751] |
| 2026-04-07 | 108 qubits, twelve chiplets, median 2Q 99.1% | Rigetti | C[36] |
| 2026-08-19 | two cryogenic cells coupled; 0.53 m² wiring, 2.75 m³ vacuum per cell | IBM | C[50] |
The dominant term is not the interconnect. Rigetti's own comparison isolates it: same chiplet, same join, three times as many, 40 basis points of two-qubit fidelity lost C[36], [751]. Nothing published attributes that loss, which makes frequency targeting across a tiled set the leading suspect and the leading unknown.
Manufacturing, materials & supply chain
Superconducting lithography plus a packaging line: flip-chip bonding, indium bumps or press-mold joins, through-silicon vias, a carrier. IBM builds on 300 mm at Albany NanoTech Cfact; QuantWare sells 3D vertical integration as a product — a stack of chiplet modules with chip-to-chip connections targeting 10,000 qubits, first delivery 2028, with a Kilofab in Delft opening 2026 to raise capacity 20× P[495]fact. Rigetti fabricates 9-qubit chiplets on its own line C[751].
The single points of failure sit outside the fab. The cryostat is one: IBM's cell architecture is a bespoke refrigerator programme, and the merchant alternative is Bluefors' KIDE, quoted at more than 4,000 RF lines and "over 1000 qubits" on nine pulse tubes Cfact. Bump-bond and TSV capacity for superconducting stacks sits with a handful of lines — Albany, Kilofab, GlobalFoundries under its CHIPS letter of intent fact, SkyWater now inside IonQ fact. Export exposure is uneven. The BIS rule of 2024-09-06 puts dilution refrigerators rated ≥ 600 µW at ≤ 0.1 K under ECCN 3A904, but a quantum computer under 4A906 only when its qubit count and its C-NOT (controlled-NOT gate) error fall in the same band — 34–99 qubits at ≤ 10⁻⁴, 100–199 at ≤ 10⁻³, the ceiling rising to 6 × 10⁻³ below 2,000 qubits, any error from 2,000 on fact. Rigetti's 108 qubits at a median two-qubit error near 9 × 10⁻³ C[36] fall outside 4A906, so a refrigerator of that class can be controlled while the tiled processor it cools is not.
Control, readout & I/O burden
Packaging does not reduce lines per qubit; it relocates them and buys wiring area. At 10³ qubits one merchant cryostat suffices — KIDE's 4,000-plus RF lines cover it Cfact. At 10⁴ the choice is 40,000 lines through vertical I/O, QuantWare's 2028 promise Pfact, or cold multiplexing. At 10⁶ neither works: many cells plus on-chip control generation, whose published pointer is millikelvin SFQ control at 1Q > 99% fact.
Latency is not the l-coupler's problem — the demonstrated inter-module SWAP is under 100 ns D[752] against a 280 ns readout at 99.94% fidelity D[38]. The decoder is: cross-module syndrome extraction must close inside a ~1 µs cycle while a parity check spans two packages, and no such demonstration exists as of 2026-09-03. NVQLink's 3.84 µs round trip Pfact is a host-QPU budget, far too slow for an intra-cryostat check.
Role in the stack
Three architectures use it: superconducting transmons, superconducting bosonic cat/GKP, superconducting dual-rail erasure. It requires superconducting-qubit lithography with multilayer routing and flip-chip packaging. It replaces inter-fridge cryogenic links, and the price is thermal: everything shares one cooling budget and one vacuum, so scaling stops at the fridge rather than at the network. Its contribution is manufacturability, not gate physics.
A fabricated carrier acquires far-range connectivity through packaging, where atoms and ions acquire it through motion. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: 0.65 µs, readout at ≈ 280 ns its largest term, and the < 100 ns inter-module SWAP D[752] is at most about 15% of the round (100 of 650 ns), so transport does not bind. Neighbouring empty slots: cross-module error correction, and a qLDPC code whose checks span modules — compilation for such machines exists only in simulation S[753].
Evidence — how the numbers were measured
Rigetti's 99.1% and 99.5% are company medians without error bars or a stated protocol C[36], [751]; the 2021 die-to-die numbers carry explicit uncertainties D[747]. SUSTech's 99% is a state-transfer and Bell-state fidelity, not a gate fidelity, and its 12-qubit GHZ at 55.8 ± 1.8% shows what five linked modules do at depth D[748]. The Illinois figure is a SWAP efficiency with a separately stated ~1% error called threshold-level; the two should not be conflated D[752]. IBM's coupled-cell result contains no qubits and no fidelity claim C[50]. No value conflicts were found; the gap is that nothing explains the 99.5% → 99.1% step.
Neither arXiv:2308.09240 (Rigetti; cross-chip CZ 99.13 ± 0.15% in 56 ns) nor arXiv:2409.04634 (IBM Quantum, T. J. Watson Research Center; cable joins, no qubit measured) has a journal version as of 2026-09-30. The 40,000 I/O lines of QuantWare's Bass-A10K (VIO-40K) rest only on QuantWare's own release of 2025-12-08 fact, which the trade-press page of 2025-12-10 P[495] omits, and no delivered device confirms them. Not published: a gate fidelity or latency through IBM's l-coupler, "first demonstrated in 2024" on Flamingo C[50], [481], whose cable joins were tested on 1 m of aluminium coax at internal Q ≈ 10⁶ D[750], as of 2026-09-30; and a dated assignee record for Rigetti's chiplet-packaging and QuantWare's vertical-I/O patent families.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IBM | developer | US | l-couplers between modules and their cable joins; modular cryogenic cells; Cockatoo 2027, Starling 2029 | C[50], [481] D[750] fact |
| Rigetti | developer | US | only shipped multi-chip system with published figures: 4- and 12-chiplet processors | C[36], [751] fact |
| QuantWare | supplier | Netherlands | merchant 3D-integrated chiplet stacks; VIO-40K, Kilofab Delft | P[495] fact |
| SUSTech | research | CN | five-module aluminium-coax interconnect network | D[748] |
| Univ. of Illinois Urbana-Champaign | research | US | interchangeable modules, 99% inter-module SWAP < 100 ns | D[752] |
| Bluefors | supplier | FI | KIDE platform, > 4,000 RF lines, the merchant multi-module fridge | Cfact |
| GlobalFoundries | supplier | US | multi-modality foundry under CHIPS letter of intent, $375 M | fact |
| DARPA | funder | US | QBI Stage B funds IBM's modular path; Rigetti not on the list | fact |
Money.
- 2025-11-06 · IBM · DARPA QBI Stage B selection · up to $15 M each · DARPA · announced fact
- 2026-05-05 · QuantWare · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners, no single lead · cumulative > $210 M · closed Pfact
- 2026-05-21 · Rigetti · CHIPS letter of intent · up to $100 M · Dept of Commerce, within a $2.013 B package (GlobalFoundries $375 M, IBM/Anderon $1 B) · LOI, non-binding fact
- 2026-07-31 · IonQ · acquisition of SkyWater Technology · ~$1.8 B at announcement · closed fact
- 2026-08 · Rigetti · Q2-2026 results · revenue $5.1 M, GAAP loss $52.6 M, cash $541.3 M · reported fact
Market & supply chain. No one sells an l-coupler; it is a captive design block. The merchant layer is one company deep — QuantWare is the only vendor selling 3D-integrated multi-chip QPUs to third parties P[495] — plus Bluefors for the enclosure and a short list of lines that can do superconducting flip-chip at volume. Who pays: G3 and G4 above all, since Starling depends on modules rather than a bigger die; G7 for deployable multi-cell systems; G2 through wider processors.
IP & standards. IBM holds US 12,517,856, "Modular quantum system with discrete levels of connectivity" (filed 2022-09-28, granted 2026-01-06), and US 12,587,192 on chains of resonators with tunable inductive couplers (granted 2026-03-24) fact — the l-coupler's cable joins are published D[750], a gate fidelity through one is not. For Rigetti's chiplet packaging and QuantWare's vertical I/O, no dated patent fact was found within budget. There is no inter-module interface standard and no open-source packaging stack.
Roadmaps & track record.
- IBM: promised 2025-06-10 · l-couplers demonstrated on Flamingo in 2024 · claimed delivered, no link fidelity published as of 2026-09-30 C[481].
- IBM: promised 2025-06-10 · Cockatoo 2027, entanglement between modules via the universal adapter; Nighthawk on nine l-coupled modules for 1,080 qubits by 2028 · pending R[481] fact.
- IBM: promised 2022-05-10 · Kookaburra, a 1,386-qubit multi-chip processor, for 2025 C[313]; re-promised 2025-06-10 for 2026 as the first module with a qLDPC memory R[481] · not delivered as of 2026-09-30 fact.
- Rigetti: promised 2025-07-16 · 100+ qubit chiplet system at median 99.5% before end-2025 · delivered 2026-04-07 at 99.1%, target moved to "later in 2026" C[36], [751].
- QuantWare: promised 2025-12-08 · VIO-40K (VIO is QuantWare's vertical-wiring architecture), 10,000 qubits, first delivery 2028 · pending Pfact.
Credibility: IBM meets its single-chip processor dates but not its multi-chip one — Kookaburra, promised for 2025, is undelivered — and publishes packaging as architecture rather than measurement, so its modular claims stay unfalsifiable until Cockatoo; Rigetti ships what it describes, a fidelity step behind its own target; QuantWare has money and a fab but no delivered multi-chip QPU at scale to judge.
Strategic reading. If multi-chip modules work, the decisive asset moves from lithography to packaging and cryogenics, and the winner is whoever controls bump-bond, TSV and fridge capacity — IBM by vertical integration, QuantWare by merchant supply, IonQ through SkyWater. The loser is any roadmap assuming a single ever-larger die. Substitution threats: on-chip long-range couplers, which buy connectivity without packaging risk, and inter-fridge links, which buy unlimited scale at the price of a room-temperature crossing. Supplier bargaining power is high: there are more credible qubit vendors than lines that can bond them.
Outlook & open questions
Confirm within 12–24 months if: IBM's Cockatoo demonstrates entanglement between two l-coupled modules with a published fidelity by end-2027 R[481]; Rigetti's 108-qubit system reaches median 99.5% C[36]; anyone runs a stabiliser round whose checks cross a module boundary. Demote if no l-coupler fidelity is published by end-2027. Best case by 2029: a few thousand qubits in coupled cells with cross-module error correction at Λ comparable to monolithic. Worst case: tiling saturates near 10² qubits because frequency targeting across dies does not scale.
Open questions: what causes the 40-basis-point tiling tax, per-join or per-calibration? Can a metre-scale cable's mode comb be pushed out of band without shortening it? What is an l-coupler's fidelity, two years after the claim? Does a qLDPC check spanning modules survive the extra transport error? Watch Rigetti's roadmap update, IBM's first Cockatoo measurement, QuantWare's Kilofab yield, and any paper benchmarking a chiplet boundary as such.
References
- [36] Rigetti Computing, Inc., “Rigetti Announces General Availability of 108-Qubit System,” Apr. 7, 2026. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ rigetti-announces-general-availability-108-qubit-system - [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
- [50] C. Dundon, S. Hall, M. Hollister, and A. Lindler, “IBM's new modular architecture for cryogenic systems,” IBM Quantum Computing Blog, Aug. 19, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ modular-cryogenics - [313] J. Gambetta, “Expanding the IBM Quantum roadmap to anticipate the future of quantum-centric supercomputing,” IBM Quantum Blog, May 10, 2022. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ ibm-quantum-roadmap-2025 - [481] R. Mandelbaum et al., “How IBM will build the world's first large-scale, fault-tolerant quantum computer,” IBM Quantum Computing Blog, Jun. 10, 2025. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ large-scale-ftqc - [495] M. Abdel-Kareem, “QuantWare Debuts VIO-40K™ Architecture to Enable 10,000-Qubit Superconducting Processors,” Quantum Computing Report, Dec. 10, 2025. [Online]. Available: https://quantumcomputingreport.com/
quantware-debuts-vio-40k-architecture-to-enable-10000-qubit-superconducting-processors/ P - [747] A. Gold et al., “Entanglement across separate silicon dies in a modular superconducting qubit device,” npj Quantum Inf., vol. 7, no. 1, Art. no. 142, Sep. 2021, doi: 10.1038/s41534-021-00484-1. arXiv:2102.13293. Also https://arxiv.org/
abs/ . D2102.13293 - [748] J. Niu et al., “Low-loss interconnects for modular superconducting quantum processors,” Nat. Electron., vol. 6, no. 3, pp. 235–241, Feb. 2023, doi: 10.1038/s41928-023-00925-z. arXiv:2302.02751. D
- [749] M. Field et al., “Modular Superconducting Qubit Architecture with a Multi-chip Tunable Coupler,” arXiv:2308.09240, Aug. 2023. D
- [750] Y. Martin et al., “Mechanically-intermixed indium superconducting connections for microwave quantum interconnects,” arXiv:2409.04634, Sep. 2024. D
- [751] Rigetti Computing, “Rigetti Demonstrates Industry's Largest Multi-Chip Quantum Computer; Halves Two-Qubit Gate Error Rate,” Rigetti Investor Relations, Jul. 16, 2025. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ rigetti-demonstrates-industrys-largest-multi-chip-quantum - [752] M. Mollenhauer, A. Irfan, X. Cao, S. Mandal, and W. Pfaff, “A high-efficiency elementary network of interchangeable superconducting qubit devices,” Nat. Electron., vol. 8, no. 7, pp. 610–619, Jul. 2025, doi: 10.1038/s41928-025-01404-3. D
- [753] Z. Du et al., “Hardware-aware Compilation for Chip-to-Chip Coupler-Connected Modular Quantum Systems,” arXiv:2505.09036, May 2025. S
Русский текст загружается…
הטקסט בעברית נטען…
Cryogenic microwave link between refrigerators
Superconducting waveguide held below 50 mK along its whole length, carrying itinerant 5–7 GHz photons or squeezed states between two independently cooled dilution refrigerators.
Verdict. Two groups hold the headlines: ETH Zürich for photon transfer and Bell tests — 30 m, Bell fidelity 80.4% at 12.5 kHz, loophole-free — and TU Munich with VTT for squeezed states over 6.6 m. Loss sits in the demountable joints, not the waveguide, and no architecture puts this on a fault-tolerance critical path.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A superconducting waveguide cooled far below aluminium's superconducting transition (≈1.2 K) along its whole length, carrying itinerant ~5–7 GHz photons between two separately cooled dilution refrigerators — not between chips in one cryostat. Wallraff's group at ETH Zürich introduced it in 2020: 5 m, state transfer 85.8%, remote Bell pairs 79.5% D[772]. The 30 m successor carried the first loophole-free superconducting Bell test in 2023 D[305]; the 2026 paper documents it as a reproducible modular assembly D[773]. TU Munich with VTT runs the only independent second line, sending squeezed Gaussian states over 6.6 m D[774]. Attributes: d = long-range inter-cryostat connectivity, the only layer entry spanning separate refrigerators; e/f/g = millikelvin microwave drive at both fridges, loss and coherent phase rather than Pauli errors, superconducting lithography with demountable interfaces (graph record).
Physics & limits
The waveguide is not the limit: attenuation is α < 1 dB/km, under 0.03 dB across the full 30 m — the same figure in the 2023 and 2026 papers D[305], [773]. End-to-end photon transfer loss is nonetheless 0.55–0.65 dB (12–14%), which the 2026 paper attributes to the interfaces between modules, not the line D[773]: every one of the 26 demountable joints costs transmission.
Second, thermal occupation. At 5.6 GHz a photon is worth 0.27 K, so a 50 mK channel holds 4.6×10⁻³ residual photons, while the 1 K channel centre at which Munich/VTT still resolved entanglement holds ≈3.3 D[774]. Fock transfer degrades roughly linearly in that occupation; Gaussian squeezed states tolerate it, so squeezing is the cheaper carrier to lengthen. Third, phase: two mechanically independent cryostats need a common reference, and no source quantifies the residual phase noise — the term that would bound a repeatered link. What moves the floor: welded or bump-bonded joints replacing demountable flanges.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2023-05 | 30 m link, Bell fidelity 80.4% at 12.5 kHz, CHSH S = 2.0747 ± 0.0033 | ETH Zürich | D[305] |
| 2025-05 | 6.6 m squeezed link, 2.10 ± 0.02 dB squeezing, negativity 0.501 ± 0.011 | TU Munich | D[774]fact |
| 2026-04 | 30 m modular assembly, 26 modules, 6.5 d cooldown, 0.55–0.65 dB transfer loss | ETH Zürich | D[773] |
Interface loss dominates, ~20× the waveguide's own contribution D[773]; no chained (≥3-fridge) link, no link run during gate execution, and no independent 30 m replication as of 2026-09-04.
Manufacturing, materials & supply chain
Every link is bespoke. The ETH 30 m assembly is 26 modules plus two nodes and a central cooling unit, holding the 4 K stage under 6 K across the span; the 6.5-day cooldown, not fidelity, is what makes iteration slow, and simulation puts one cooling unit per ~15 m out to 120 m D[773]S[773]. Base cryostats come from a concentrated market: Bluefors closed its Cryomech acquisition (pulse-tube and Gifford-McMahon cryocoolers) on 2023-03-28, giving ~600 staff and revenue above EUR 160 M C[524]; ULVAC is a Japanese third source built with IBM input C[525]fact. Export exposure is inherited: ECCN 3A904 (BIS, 2024-09-06) covers refrigerators sustaining ≥600 µW at 0.1 K for 48 h; no ECCN names a link G[301]fact.
Control, readout & I/O burden
Each attempt needs a flux-tunable coupler at both ends and microwave sources phase-locked across two cryostats. The 2023 Bell test carries this report's hardest real-time constraint: 32.824 m of separation leaves a 109 ns window in which basis choice, gate, readout and record must all complete D[305]. The 12.5 kHz repetition rate — 80 µs per attempt — is set by reset and pulse shaping, not time of flight. Nothing is published at 10³–10⁶ qubits; the binding quantities are cryoplant count and independent phase references.
Role in the stack
The only architecture is superconducting transmon (Google, IBM, Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu); it requires superconducting-qubit lithography. It competes with same-fridge modularity — IBM coupled two cryogenic cells in 2026-08, l-couplers at "one meter scale", with no qubits and no fidelity reported C[50]fact — and with microwave-optical transduction, best total efficiency 47% and nothing at η > ½ with sub-unity added noise P[775]fact. Derived clock: 80 µs per entanglement attempt (2 s.f.) against a 1.1 µs surface-code cycle — ~73× slower, under two orders of magnitude. Adjacent empty slot: a cryogenic microwave switch, absent which N fridges need N(N−1)/2 waveguides.
Evidence — how the numbers were measured
A loophole-free violation of the CHSH (Clauser–Horne–Shimony–Holt) Bell inequality with space-like separated measurements is device-independent, not tomographic — unusually strong verification for this layer D[305]. Munich rests on homodyne tomography D[774]; the two are not comparable, neither replicated, and both ran with local processors idle. Conflict: the graph record's 75–79% transfer efficiency is not what 0.55–0.65 dB implies alone (86–88%).
Not published: the residual phase noise between the two cryostats.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| ETH Zürich | Research | Switzerland | Built the 5 m, 30 m and modular links; holds the photon-transfer and Bell-test headlines | D[305], [772], [773] |
| TU Munich | Research | Germany | 6.6 m squeezed-state link with VTT — the independent second line, with its own headline | D[774] |
| Bluefors | Supplier | Finland | Refrigerator and cryocooler vendor; KIDE is the rival path | C[303]fact |
| ULVAC Cryogenics | Supplier | Japan | ~10 mK refrigerator with IBM input, tested at Poughkeepsie | C[525]fact |
| IBM | Developer | USA | Runs the competing intra-fridge modular-cryogenics line | C[50]fact |
Money. 2023-03-28 · Bluefors · M&A (Cryomech) · undisclosed · combined revenue > EUR 160 M · closed C[524]. 2024-09-06 · US BIS · ECCN 3A904 rule · n/a · in force G[301]. 2025-03-20 · ULVAC · ~10 mK refrigerator programme with IBM · undisclosed · "early 2026" target passed, no shipment confirmed as of 2026-09-30 C[525]. No round, grant or acquisition specific to an inter-fridge link exists as of 2026-09-04.
Market & supply chain. There is no link market, only a refrigerator market in which a link consumes two units instead of one; Oxford Instruments is the second merchant source C[525]. Bluefors plus Cryomech supplies the dilution stage and the pulse tubes beneath it with no alternative at that volume C[524]. G6 (networking) pays directly; G4 pays only once a cryostat's line budget runs out, which KIDE's >4,000 RF lines are designed to postpone C[303]fact.
IP & standards. No patent family specific to cross-cryostat microwave links in any named database and no standards body addressing cryogenic microwave interfaces — no dated fact found; module geometry is published openly D[773].
Roadmaps & track record. ETH Zürich: (2023-05 · 30 m Bell test · delivered); (2026-04 · 120 m via cooling units per ~15 m · simulated only) S[773]. ULVAC/IBM: (2025-03 · refrigerator "early 2026" · target passed, unconfirmed as of 2026-09-30) C[525]. IBM: (2026-08 · two coupled cells · delivered, no qubits in them) C[50]. ETH has met every milestone it announced; both vendor timelines are unverified.
Strategic reading. If this works the cryostat suppliers capture the value, not the QPU vendor. If it fails nothing breaks — every published superconducting roadmap scales inside one cryostat first. Substitution runs both ways: l-couplers remove the need below ~1,000 qubits per cell C[50], transduction removes the distance limit above it. No independent link vendor exists to bargain with.
Outlook & open questions
Falsifiable (12–24 months): confirm if any group publishes a three-cryostat chained link, or a 30 m link run while both processors execute gates, by end-2027; demote if interface loss is not below 0.3 dB by then. Best case 2029: per-hop efficiency above 90% and an architecture that needs two fridges. Worst case: intra-cryostat modularity absorbs all growth through 2030 and this stays a Bell-test instrument. Open questions: residual inter-cryostat phase noise; whether joints can be non-demountable and still serviceable; whether anyone builds a cryogenic microwave switch. Watch: ETH follow-ons, IBM's first coupled cells with qubits in them.
References
- [50] C. Dundon, S. Hall, M. Hollister, and A. Lindler, “IBM's new modular architecture for cryogenic systems,” IBM Quantum Computing Blog, Aug. 19, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ modular-cryogenics - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [303] Bluefors, “KIDE Cryogenic Platform — For Large-Scale Quantum Computing,” Jun. 16, 2026. [Online]. Available: https://bluefors.com/
products/ Ckide-cryogenic-platform/ - [305] S. Storz et al., “Loophole-free Bell inequality violation with superconducting circuits,” Nature, vol. 617, no. 7960, pp. 265–270, May 2023, doi: 10.1038/s41586-023-05885-0. D
- [524] Bluefors, “Bluefors closes the acquisition of Cryomech,” Mar. 28, 2023. [Online]. Available: https://bluefors.com/
press-releases/ Cbluefors-closes-the-acquisition-of-cryomech/ - [525] ULVAC, “ULVAC Developing Next-Generation Dilution Refrigerator for Quantum Computing by 2026,” Nasdaq (JCN Newswire), Mar. 20, 2025. [Online]. Available: https://www.nasdaq.com/
press-release/ Culvac-developing-next-generation-dilution-refrigerator-quantum-computing-2026-2025-03 - [772] P. Magnard et al., “Microwave Quantum Link between Superconducting Circuits Housed in Spatially Separated Cryogenic Systems,” Phys. Rev. Lett., vol. 125, no. 26, Art. no. 260502, Dec. 2020, doi: 10.1103/PhysRevLett.125.260502. arXiv:2008.01642. D
- [773] J. D. Schär et al., “A Modular Cryogenic Link for Microwave Quantum Communication Over Distances of Tens of Meters,” arXiv:2604.15971, Apr. 2026. D
- [774] W. K. Yam et al., “Cryogenic microwave link for quantum local area networks,” npj Quantum Inf., vol. 11, no. 1, Art. no. 87, May 2025, doi: 10.1038/s41534-025-01046-5. D
- [775] T. A. Aditto, J. S. Ifty, and K. Zahin, “Toward Scalable Heterogeneous Quantum Networks: Microwave-Optical Transduction Across Platforms,” arXiv:2605.26976, May 2026. P
Русский текст загружается…
הטקסט בעברית נטען…
Ion–photon link
Heralded ion–photon entanglement over fibre links separate ion traps into one machine; best published rate 250 s⁻¹ against a ~10⁴ s⁻¹ need.
Verdict. Real: remote Bell pairs at 9.7–250 s⁻¹, 94–97% fidelity, teleported CZ 86%. Unverified: IonQ's networked-systems claim carries no rate or fidelity. Demote if nothing exceeds 10³ s⁻¹ by end-2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An ion decaying from an excited state emits a photon entangled with its qubit state; interfere two such photons from two traps on a beamsplitter and a coincident detection projects the distant ions into a Bell pair — heralded and probabilistic, unlike an in-trap gate, and the only mechanism coupling ions in separate vacuum systems. First shown in 2007 by Monroe's group (Michigan, later Maryland/Duke) — the lineage that holds today's rate record, not the Wineland/NIST line.
Attributes. Mobility: flying — the photon, not the ion, carries entanglement. Control modality @ placement: optical, room temperature — collection, interference and detection sit outside the trap's vacuum envelope.
Physics & limits
The rate is the whole problem. Success probability per attempt goes as η², where η is collection solid angle × branching ratio × fibre coupling × detector efficiency, since both photons must survive; two in η is four in rate. With free-space objectives η sits in the low per cent, so published rates are 9.7 s⁻¹ over a 2-m link D[115] and 250 s⁻¹ at the record D[116] against the ~10⁴ s⁻¹ a QEC cycle would consume — 40× at best, closing quadratically through collection, not electronics.
Fidelity is the healthier budget: two-photon interference visibility, detector dark counts and jitter, and residual ion motion cap heralded fidelity at 94–97% D[115], [116]. Because failures are heralded, the error the code sees is loss, so low η costs throughput, not infidelity — an erasure channel at the interconnect layer. What moves the floor: cavity (Purcell) enhancement, waveguide-integrated collection in photonic-chip traps, telecom frequency conversion, emitter multiplexing per module, and quantum memories that let attempts accumulate rather than retry in lockstep.
Engineering state of the art
Best demonstrated is a distributed computation, not just a Bell pair: Oxford ran a teleported CZ at 86.2(9)% and a distributed Grover search across a 2-m link D[115].
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024 | Remote entanglement rate record, 250 s⁻¹ at fidelity >94% | Duke/Maryland | D[116] |
| 2025-02 | 2-m link: remote Bell 96.89(8)% at 9.7 s⁻¹, teleported CZ 86.2(9)% | Oxford | D[115] |
| 2025-06 | Lightsynq (photonic interconnect + quantum memory, >20 patents and applications) acquired | IonQ | C[776] |
| 2026-04 | Two commercial ion systems linked; no rate, fidelity or distance disclosed | IonQ | C[589] |
Dominant gap: throughput. Published rates sit 40× (the record) to ~10³× below the ~10⁴ s⁻¹ a networked QEC cycle needs; fidelity is not the blocker.
Manufacturing, materials & supply chain
No fab and no wafer statistic — the "yield" is optical collection efficiency, an alignment and numerical-aperture figure. A link is a high-NA objective or in-vacuum cavity, single-mode fibre and polarisation control, a Bell-state-measurement apparatus with two single-photon detectors, and coincidence logic. Traps come from elsewhere: Infineon is the merchant trap foundry for IonQ/Oxford Ionics, eleQtron and Universal Quantum, Honeywell fabricates Quantinuum's in house Cfact. The concentrated input is detectors: the merchant SNSPD base is five vendors — Single Quantum, ID Quantique (owned by IonQ), Photon Spot, Quantum Opus and Moscow's Scontel Pfact. Cost per link is not quotable. Export exposure is indirect: the BIS rule of 2024-09-06 names no interconnect optics G[301]; it reaches only the machine, under 4A906, and only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact.
Control, readout & I/O burden
Per link: one collection channel per ion, two detectors, a phase-stable optical path, a coincidence gate. Heralding latency is sub-µs, so the electronics limit nothing — the attempt rate does. At ~10 modules a handful of point-to-point links works; at 10⁴ any-to-any needs a switch fabric plus enough pair generation to feed inter-module lattice surgery, and no published design states a link count. Quantinuum's in-trap alternative exchanges ions at 2.5 kHz and transports through junctions at 4 m/s D[113] — an order faster than the best photonic link, which is why QCCD vendors have not adopted the technology.
Role in the stack
It requires the trapped atomic ion and single-photon detection (SNSPD/TES) and provides for nothing downstream: a terminal capability, the exit from single-trap scaling. Architectures served: all three trapped-ion architectures, as primary — QCCD (Quantinuum), the linear Paul trap with laser addressing (AQT, Maryland/Duke, Quantum Art) and electronic-gate, chip-controlled ions (IonQ/Oxford Ionics, eleQtron). The graph lists no replacement or conflict, but in-trap transport is the functional rival and currently wins. Derived-clock contribution: dominant where used — at 250 s⁻¹ one inter-module pair costs 4.0×10⁻³ s, comparable to a full-width ion layer; at 9.7 s⁻¹ it is 1.0×10⁻¹ s.
Evidence — how the numbers were measured
Heralded fidelity is tomography or parity oscillation conditioned on a successful click, so 94–97% describes the links that happened, not the channel including loss; the honest figure of merit is rate × fidelity, which nobody reports. Published rates come from different species, distances and collection geometries and are not directly comparable. The weakest evidence is commercial: IonQ's release states it "validated the generation, transmission, and detection of photons used to enable quantum entanglement" — wording that stops short of reporting a measured Bell state, with no rate, fidelity or distance and no replication C[589]. Among peer-reviewed results there is no conflict.
The ">20 patents and patent applications" Lightsynq brought is IonQ's own count, with no family names, assignees or filing years. Not published: the Lightsynq deal terms, and a link count or switch-fabric topology for a 10⁴-module ion machine.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| University of Oxford | research | UK | 2-m link, teleported CZ and distributed Grover | D[115] |
| Duke University | research | US | Co-holder of the 250 s⁻¹ record | D[116] |
| IonQ | developer | US | Networked two systems; owns Lightsynq and ID Quantique | C[589] |
| Quantinuum | developer | US | Scales by in-trap transport; photonic link only as Apollo's stated direction | D[113] |
| ID Quantique | supplier | CH | SNSPD vendor, acquired by IonQ | Pfact |
| Single Quantum | supplier | NL | Merchant SNSPD supplier, independent | Pfact |
| AFRL | user | US | Partner on IonQ's April-2026 milestone | C[589] |
| DARPA | investor | US | QBI Stage B funds both ion vendors | G[65] |
Money.
- 2025-05-06 · IonQ · M&A, ID Quantique (single-photon detectors) · undisclosed · — · closed Pfact
- 2025-06-03 · IonQ · M&A, Lightsynq (interconnect, quantum memory, >20 patents) · undisclosed · Harvard/AWS founders · closed C[776]
- 2025-09-17 · IonQ · M&A, Oxford Ionics · $1.075 B · — · closed C[18]
- 2025-11-06 · DARPA · QBI Stage B · up to $15 M each · IonQ and Quantinuum among eleven G[65]
- 2026-06-03 · Quantinuum · IPO, Nasdaq QNT · $1.68 B gross · — · closed G[123]
- 2026-07-31 · IonQ · M&A, SkyWater Technology · ~$1.8 B · — · closed C[19]
Market & supply chain. There is no market yet — five merchant detector houses and a few optics suppliers — and the largest natural customer owns one of the five. IonQ has bought the vertical: Lightsynq for interconnect and memory, ID Quantique for detectors, Oxford Ionics for gates, SkyWater for fabrication. Unit economics are not quotable. G6 pays directly; G4 pays as the way past single-trap ceilings; the rest do not.
IP & standards. The only dated IP fact is IonQ's statement that Lightsynq brought "over 20 patents and patent applications" in photonic interconnect and quantum memory — a company count with no family, assignees or filing years C[776]. No named patent family was found for ion–photon link hardware; no standards body governs it.
Roadmaps & track record. IonQ (promised 2025-06 · 2 M physical, 40–80 k logical by 2030 · status 2026-09-03: needs an interconnect ~40× faster than the best published rate) R[132]; its 2020 roadmap missed 4,000 qubits by 2026 by ~40×. Quantinuum (promised 2024-09 · Sol 2027, Apollo 2029 · no dated photonic-interconnect commitment) R[118]; Helios launched on schedule, so its dates carry weight.
Strategic reading. If heralded links reach production rates the single-trap ceiling stops mattering and every ion vendor becomes modular; IonQ wins that world because it owns each layer, and merchant detector vendors lose their largest customer to a competitor. If rates stay put, Quantinuum wins by ignoring the technology — in-trap transport at 4 m/s is already faster. Supplier power is negligible today and would rise only if link counts grew with module counts.
Outlook & open questions
Confirm by end-2027 if any group publishes above 10³ s⁻¹, or IonQ discloses rate, fidelity and distance. Demote the networking-ready framing if by end-2028 nothing exceeds 10³ s⁻¹, four times the 250 s⁻¹ record. Best case by 2029: cavity or waveguide collection plus telecom conversion reaches 10³–10⁴ s⁻¹ and a three-node network appears. Worst case: rates stay at 10²–10³ s⁻¹ and modular ion machines use in-trap transport instead. Open questions: what did IonQ's link achieve; does cavity enhancement cost interference visibility; can frequency conversion survive the fidelity budget?
References
- [18] IonQ, “IonQ Completes Acquisition of Oxford Ionics, Rapidly Accelerating Its Quantum Computing Roadmap,” Sep. 17, 2025. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-oxford-ionics-rapidly-accelerating-its-quantum - [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [113] R. D. Delaney et al., “Scalable Multispecies Ion Transport in a Grid-Based Surface-Electrode Trap,” Phys. Rev. X, vol. 14, Art. no. 041028, Nov. 2024, doi: 10.1103/PhysRevX.14.041028. arXiv:2403.00756. D
- [115] D. Main et al., “Distributed quantum computing across an optical network link,” Nature, vol. 638, no. 8050, pp. 383–388, Feb. 2025, doi: 10.1038/s41586-024-08404-x. D
- [116] J. O'Reilly et al., “Fast photon-mediated entanglement of continuously-cooled trapped ions for quantum networking,” Phys. Rev. Lett., vol. 133, Art. no. 090802, Aug. 2024, doi: 10.1103/PhysRevLett.133.090802. arXiv:2404.16167. D
- [118] Quantinuum, “Quantinuum Unveils Accelerated Roadmap to Achieve Universal, Fully Fault-Tolerant Quantum Computing by 2030,” Sep. 10, 2024. [Online]. Available: https://www.quantinuum.com/
press-releases/ Rquantinuum-unveils-accelerated-roadmap-to-achieve-universal-fault-tolerant-quantum-computing-by-2030 - [123] Quantinuum, “Quantinuum Announces Pricing of Upsized Initial Public Offering,” Jun. 3, 2026. [Online]. Available: https://www.quantinuum.com/
press-releases/ Gquantinuum-announces-pricing-of-upsized-initial-public-offering - [132] IonQ, “IonQ's Accelerated Roadmap: Turning Quantum Ambition into Reality,” Jun. 13, 2025. [Online]. Available: https://www.ionq.com/
blog/ Rionqs-accelerated-roadmap-turning-quantum-ambition-into-reality - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [589] IonQ, “IonQ Achieves Key Photonic Interconnect Milestone, Demonstrating Networked Quantum Systems Using Entanglement,” Apr. 14, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-achieves-key-photonic-interconnect-milestone-demonstrating-networked-quantum-systems-using-entanglement - [776] IonQ, “IonQ Completes Acquisition of Lightsynq, Accelerating Quantum Computing and Networking Roadmap,” Jun. 3, 2025. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-lightsynq-accelerating-quantum-computing-and
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Spin–photon solid-state link (SiV, NV, T centre)
Heralded photonic entanglement between separated solid-state spin registers — diamond NV and SiV centres, silicon T centres — through deployed telecom fibre.
Verdict. Inter-cryostat gates exist on both hosts, unconditionally on NV (63–64%) and only post-selected on T centres. Rates of 0.0075–1 Hz sit 10⁵–10⁷ below the ~200 kHz reported as Photonic Inc.'s architecture target, an unverified figure; loss, not coherence, is why.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Each node is a spin qubit in a solid — a nitrogen-vacancy or silicon-vacancy centre in diamond, or a silicon T centre — whose optical transition emits a photon entangled with the spin. Photons from two nodes interfere on a beamsplitter; a detection pattern heralds spin–spin entanglement without trusting the channel, so loss costs attempts, not fidelity. Delft demonstrated the first heralded solid-state version across 3 m in 2013 D[783]; everything since has pushed that protocol into deployed telecom fibre.
- Mobility: the carrier flies (a photon in fibre); both spins stay fixed.
- Error structure: loss-dominated; conditional fidelity and unconditional rate must be quoted together.
Physics & limits
The floor is the product of collection, conversion and transmission efficiencies, entering the rate quadratically for two-photon protocols and linearly for the single-photon protocol Delft uses at metropolitan scale D[784]. The coherent zero-phonon line carries ~3% of an NV centre's emission, ~23% of a T centre's and 65–90% of an SiV's Dfact, and a 35 km deployed urban loop costs a further 17 dB D[209]. Wavelength decides whether conversion is needed — NV at 637 nm and SiV at 737.2 nm require it (Harvard converts to 1,350 nm), while a T centre emits natively near 1,326 nm, skipping that stage but paying with a weaker transition P[363]. Spin coherence is not the constraint: nuclear memories hold entanglement beyond 2 s D[209], far longer than the 0.25–0.35 ms fibre round trip. The one lever that moves the floor is cavity enhancement — a fibre microcavity around one NV raised resonant collection roughly tenfold, ~0.05% to ~0.5%, keeping echo coherence above 100 µs D[359]; one more such step would pass the ~2% per-attempt photon success that 0.8-NA objectives give a trapped ion D[116].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-04 | NV, nodes 10 km apart over 25 km deployed fibre with telecom L-band conversion: F = 0.534 at 0.022 s⁻¹ | QuTech/Delft | D[784] |
| 2024-05 | SiV: F = 0.69(7) between nuclear memories over a 35 km deployed Boston loop; 0.86(3) electron–electron at 20 m, ≤1 Hz | Harvard | D[209] |
| 2024-06 | T centre, two modules in separate cryostats over ~40 m fibre: Bell F = 0.60(8), ~7.5 mHz; teleported-CNOT sequence post-selected, no gate fidelity | Photonic Inc. | P[363] |
| 2026-05 | Unconditional teleported CNOT between NV registers in separate cryostats: 4-qubit GHZ 64(4)%, CNOT-mediated state 63(4)% | QuTech/Delft | Dfact |
The dominant term is collection and heralding efficiency, not spin coherence or in-node gate error.
Manufacturing, materials & supply chain
Diamond nodes need quantum-grade CVD material, for which Element Six (UK) is the reference supplier Pfact, plus nanophotonic cavities whose yield is the blocker and is unpublished: a 2026 Delft tin-vacancy study characterised 327 cavities on two chips at room temperature, found coupled centres in 7 of the 9 it cooled and measured two above cooperativity one Dfact — no chip-wide fraction, the number any 10²-node proposal needs. Silicon T centres trade emitter quality for process maturity: implantation into enriched ²⁸Si on a CMOS line, with the centres operated at ~1.5–4 K, not millikelvin P[785]. Both ends depend on nanowire detectors from a five-vendor merchant base — Single Quantum, ID Quantique (owned by IonQ), Photon Spot, Quantum Opus and Moscow's Scontel Pfact. No export-control classification names spin–photon links.
Control, readout & I/O burden
Per node: a cryostat, microwave spin control, resonant lasers for initialisation and readout, a conversion stage unless the emitter is already telecom, phase-stabilised fibre to the midpoint, and detectors. The binding burden is duty cycle, not latency: at 0.022 s⁻¹ one link spends 45 s per Bell pair while stabilisation loops run continuously. Ten nodes are an experiment; 10² at sub-Hz cannot serve a distributed processor, and 10³ needs multiplexed emitters and detector arrays nobody has fielded.
Role in the stack
It requires a colour-centre spin register and single-photon detection; without low-dark-count detectors heralding fails outright. It provides for nothing further and tops the defect-spin network architecture. On any distributed architecture it is the pacing term: no code runs on the defect architecture, so in place of a sum of the syndrome round: gate layers + transport + readout + reset the clock is 45 s at Delft's metropolitan rate and 1.0 s at Harvard's best. The comparison that matters is the competing interconnect: Oxford's trapped-ion link reached 96.89(8)% Bell fidelity at 9.7 s⁻¹ with an 86.2(9)% teleported CZ Dfact — against Harvard's best SiV link, 0.86(3) at up to 1 Hz over 20 m, about ten times the rate and 11 points higher, and its teleported gate 23 points above QuTech's unconditional 63(4)% D[209]Dfact. Solid-state's counter-argument is manufacturability, not performance.
Evidence — how the numbers were measured
The teleported-CNOT attribution resolves, and not as a mis-attribution: both results exist and differ in kind. Photonic Inc. entangled two T-centre modules in separate cryostats over ~40 m and ran a teleported-CNOT sequence, but forwent feed-forward and post-selected on a photon detection, reporting a truth table rather than a gate fidelity; still a 2024 preprint as of 4 Sep 2026 P[363]. QuTech's 2026 result is unconditional — real-time feed-forward, no post-selection — at 63(4)% and 64(4)% Dfact. Quoting the two together without that distinction overstates the T-centre platform. Elsewhere fidelities are conditional on a herald, and Harvard rejects ~23% of data on reflectance-contrast thresholds D[209]. No result here has a second-group replication.
Not published: a dated patent-family count for spin–photon links.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuTech | Research | Netherlands | Metropolitan NV link; the only unconditional inter-cryostat gate | Dfact |
| Photonic Inc. | Developer | Canada | Silicon T-centre modules, native telecom emission | P[363] |
| Harvard University | Research | USA | SiV nanophotonic nodes over a 35 km deployed loop | D[209] |
| Fujitsu | Funder | Japan | Funds the Delft modular-computer joint programme | Pfact |
| Microsoft | Investor, partner | USA | Networking collaboration since 2023; returning investor | Cfact |
| Single Quantum | Supplier | Netherlands | Merchant nanowire detectors, the heralding dependency | Pfact |
Money. 2025-11-06 · Photonic Inc. · DARPA QBI Stage B, ~12 months · up to $15 M USD · programme fact. 2026-05-12 · Photonic Inc. · final close · $200 M USD at $2 B valuation, $350 M cumulative · Microsoft returning · closed Cfact. Ongoing · QuTech · Fujitsu joint programme PPS2007, EU Quantum Internet Alliance grant 101080128, NWO Spinoza · not itemised · ongoing Pfact.
Market & supply chain. No one sells a spin–photon link; the sold goods are detectors, diamond, enriched ²⁸Si, conversion modules and leased metro fibre. Detector supply is the shared bottleneck — five merchant vendors, one now owned by IonQ — and diamond comes mostly from one supplier, Element Six. It pays for G6 by definition and G7 where a modular machine needs inter-module links; not for G1–G5, which is why its money is programme funding — DARPA QBI, the Fujitsu–Delft joint programme, the EU Quantum Internet Alliance, NWO — plus one venture-backed developer, Photonic Inc.
IP & standards. No patent family specific to spin–photon links was located in a named dated database as of 4 Sep 2026; Photonic Inc.'s T-centre position originates in Simon Fraser University work, but no assignee-and-date record was retrieved. No standards body governs heralding interfaces; the EU Quantum Internet Alliance is the nearest coordinating structure.
Roadmaps & track record. Photonic Inc. (promised 2023 · distributed fault tolerance "within five years", ~2028 · status 4 Sep 2026: no multi-node system, the 2024 link still post-selected), with a target of ~200 kHz at 99.8% R[785] — seven orders of magnitude in rate and 40 points above its own published result, so an architecture target, not a roadmap. QuTech publishes no roadmap and delivers a Nature-class result roughly annually — credible on delivery, honest about rates.
Strategic reading. If this link matures the winners are modular architectures that cannot scale monolithically, and Microsoft gains optionality on a layer it need not build. Losers are monolithic roadmaps assuming on-chip scaling suffices. The substitution threat is ahead on points: trapped-ion links are faster and cleaner, and microwave-to-optical transduction targets the same slot. Bargaining power sits with detector and diamond suppliers.
Outlook & open questions
Confirm by 2028 if any group sustains > 1 Hz heralded entanglement above F = 0.8 over > 20 km of deployed fibre, or if Photonic Inc. publishes an unconditional inter-module gate with a fidelity; demote if T-centre results stay post-selected preprints. Best case 2029: cavity enhancement plus multiplexing reaches 10–100 Hz at metropolitan distance. Worst case: sub-Hz rates, fidelity near 0.7, ion-photon links taking the slot. Open questions: does native telecom emission beat conversion once T-centre photon yield is counted; what fraction of a chip's cavities exceeds cooperativity one, and can it reach what a 100-node network needs; does anyone multiplex across emitters.
References
- [116] J. O'Reilly et al., “Fast photon-mediated entanglement of continuously-cooled trapped ions for quantum networking,” Phys. Rev. Lett., vol. 133, Art. no. 090802, Aug. 2024, doi: 10.1103/PhysRevLett.133.090802. arXiv:2404.16167. D
- [209] C. M. Knaut et al., “Entanglement of nanophotonic quantum memory nodes in a telecom network,” Nature, vol. 629, no. 8012, pp. 573–578, May 2024, doi: 10.1038/s41586-024-07252-z. D
- [359] J. Fischer et al., “Spin-photon correlations from a Purcell-enhanced diamond nitrogen-vacancy center coupled to an open microcavity,” Nat. Commun., vol. 16, no. 1, Art. no. 11680, Nov. 2025, doi: 10.1038/s41467-025-66722-8. D
- [363] F. Afzal et al., “Distributed Quantum Computing in Silicon,” arXiv:2406.01704, Jun. 2024. P
- [783] H. Bernien et al., “Heralded entanglement between solid-state qubits separated by three metres,” Nature, vol. 497, no. 7447, pp. 86–90, May 2013, doi: 10.1038/nature12016. D
- [784] A. J. Stolk et al., “Metropolitan-scale heralded entanglement of solid-state qubits,” Sci. Adv., vol. 10, no. 44, Art. no. eadp6442, Oct. 2024, doi: 10.1126/sciadv.adp6442. arXiv:2404.03723. D
- [785] M. Ivezic, “Photonic Inc,” PostQuantum.com, Nov. 13, 2025. [Online]. Available: https://postquantum.com/
quantum-computing-companies/ Pphotonic-inc/
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Atom–photon cavity interface
An optical cavity around tweezer-trapped neutral atoms Purcell-enhances atom–photon coupling so an atom's state can be written onto a flying photon.
Verdict. Single-pair efficiency is high (~90% generation-to-detection) but far from the 99.9% a fault-tolerant link wants; remote entanglement has joined single-atom nodes, never two multi-atom tweezer processors, so the interconnect claim is unproven — falsifiable the day one reports a rate.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
An optical resonator around tweezer-trapped neutral atoms, enhancing coupling to a single photonic mode so emission into that mode is near-deterministic rather than a few percent of 4π. Cavity QED with single atoms is decades old; what dates from 2024 is a tweezer-assembled, individually addressable register inside one cavity, with multiplexed atom–photon entanglement at a generation-to-detection efficiency approaching 90% D[777]. Attributes: d = mobility "flying", moving information from a stationary atom onto a photon that leaves the module; f = dominant error is loss, not Pauli, so a failure is a heralded absence and the trial is retried.
Physics & limits
The controlling parameter is single-atom cooperativity C = g²/κγ, coherent coupling against cavity decay and free-space scattering. Emission into the cavity mode goes as C/(1+C), so pushing efficiency from 90% (C ≈ 9) toward the 99.9% a fault-tolerant link wants (C ≈ 999) costs two orders of magnitude in C — smaller mode volume or higher finesse, both tightening mirror-loss and atom-positioning tolerances. End-to-end efficiency is a product of cavity emission, outcoupling, fibre transmission and detection; 90% D[777] is close to what bulk optics allows. Loss is heralded, which is why this interface pairs naturally with erasure-native alkaline-earth(-like) qubits. What moves the floor: fibre-tip and nanophotonic microcavities with higher C; direct telecom emission that removes lossy frequency conversion D[778]; and channel counts that track array size.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-07 | Tweezer register in a cavity, multiplexed atom–photon entanglement at ~90% generation-to-detection | MPQ (Rempe group) | D[777] |
| 2025-09-12 | Parallelised telecom (1389 nm) atom–photon entanglement from a ¹⁷¹Yb array; rate scales with channel count | Illinois (Covey group) | D[778] |
| 2026-08-31 | 10-channel chip-scale 780 nm waveguide array at 25 µm pitch, visibility 0.87; 75–94% per-channel efficiency in trade press | Osaka University | DfactP[779] |
No group has published an entanglement rate between two multi-atom neutral-atom processors; the remote links on record join single-atom nodes — MPQ's cavity nodes (2012), a gate between modules 60 m apart (2021) and LMU's atoms over 33 km of fibre (2022) Dfact. Efficiency and fidelity are respectable; throughput, the only figure an architect can use, is unmeasured.
Manufacturing, materials & supply chain
Bench optics, not lithography — high-finesse mirror coatings, fibre-tip or nanophotonic microcavities, vacuum, and tweezer optics shared with the processor, all tuned per system. There is no cavity yield statistic, and the nearest nanocavity-plus-emitter study publishes none: QuTech's tin-vacancy work P[362] characterised 327 cavities at room temperature, found coupled centres in 7 of the 9 it cooled and measured two above cooperativity one Dfact. The interesting direction is chip-scale integration: Osaka's glass waveguide array (with NICT and Hamamatsu) couples ten tweezer sites into ten channels at 25 µm pitch P[779]; Chicago's 2024 platform had already combined up to 64 tweezers with a chip of more than 100 nanophotonic cavities D[579]. Named suppliers are thin: Hamamatsu for detectors, Nu Quantum for photonic switching P[780]. No COTS product exists, so no unit economics are quotable; no export-control classification specific to this hardware was found.
Control, readout & I/O burden
Trapping and addressing lasers are shared with the array; this interface adds cavity locking, a photon path and detector channels. The burden is per-link, not per-qubit: one cavity mode serves one module today, and multiplexing is the open problem — Osaka's 10 channels at 25 µm pitch, targeting ~100, are a step toward making channel count track array size P[779]. At 10³ atoms per module nobody needs it yet. At 10⁴–10⁶ distributed operation is the stated architecture of every neutral-atom vendor, and nothing published says how many simultaneous links a module needs. Heralding latency is unpublished; the retry loop is set by detector dead time and classical feedback.
Role in the stack
Serves both Rydberg tweezer arrays — alkali (Rb/Cs) and alkaline-earth(-like) (Yb/Sr) — and requires a tweezer-trapped atom plus the optical-assembly layer that builds the cavity. Within neutral atoms its only competitor is free-space collection, simpler and much less efficient; across modalities it races ion–photon and spin–photon links, and the defect-spin route is visibly harder — a fibre microcavity buys about 10× in NV photon collection, ~0.05% to ~0.5% D[359]. It contributes nothing to the derived clock today because no multi-module architecture exists: for one module, sum of the syndrome round: gate layers + transport + readout + reset is 1.31 ms per QEC round, set by transport with imaging behind it, against a 270 ns CZ D[4]. Any slower link becomes the clock the moment it is used. Empty slot: a two-module link with a rate.
Evidence — how the numbers were measured
The three results are not on a common scale. MPQ's ~90% is generation-to-detection efficiency for one atom–photon pair in a bulk cavity D[777]; Osaka's 0.87 visibility, a correlation between atomic state and photon polarisation, comes from a chip-integrated array with no cavity enhancement, published in Optica on 2026-08-31, while its 75–94% per-channel efficiency appears only in trade press DfactP[779]; Covey's telecom result is a fibre-array scheme claiming proportionality with channel count, not an absolute rate D[778]. None measures what a link needs: heralded events per second between two processors, with fidelity after heralding overhead.
The "cavity-carved Bell-state fidelity of 91%" sometimes attributed to arXiv:2407.09109 is not in its abstract, which states only the ~90% generation-to-detection efficiency. Not published: a measured entanglement rate or fidelity for Nu Quantum's two roadmap prototypes fact, and an export-control classification specific to cavity optics or atom–photon interfaces.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| MPQ | research | Germany | Tweezer register in a cavity, ~90% generation-to-detection | D[777] |
| University of Illinois | research | USA | Parallelised telecom atom–photon entanglement from a Yb array | D[778] |
| Osaka University | research | Japan | 10-channel chip-scale collection array, with NICT and Hamamatsu | P[779] |
| Atom Computing | developer | USA | Yb systems; networking deals with Nu Quantum and Cisco | P[780] |
| Nu Quantum | supplier | UK | Qubit–photon interface and photonic networking units | C[781] |
| Cisco | supplier | USA | Quantum-networking hardware and distributed-computing software | P[782] |
Money.
2025-07-17 · QuNorth · order, "Magne" from Atom Computing/Microsoft · EUR 80 M · 50 logical qubits · ordered G[11]
2025-11-06 · DARPA · QBI Stage B, Atom Computing and QuEra among eleven · up to USD 15 M each · official G[65]
2025-12-10 · Nu Quantum · Series A · USD 60 M · National Grid Partners lead, with Amadeus, IQ Capital, NSSIF, Sumitomo/Presidio · closed C[781]
2026-05-21 · US Dept of Commerce · CHIPS letter of intent, Atom Computing · USD 100 M · non-binding LOI G[300]
2026-06-16 · Atom Computing · Series C (Third Point) · USD 100 M · > USD 300 M cumulative · closed G[154]
Market & supply chain. There is no market: nobody sells an atom–photon cavity interface, and the money here is processor money (Atom Computing) or adjacent networking money (Nu Quantum, Cisco). Nu Quantum is the only company targeting this function directly; it has raised a USD 60 M Series A and published no measured rate or fidelity C[781]. Detector and photonic-integration supply is the plausible chokepoint. Pays for G6 today and, if it works, G4 and G7; pays for none of G1–G3.
IP & standards. No named patent family or dated patent-database count specific to atom–cavity interfaces was found — no dated fact found. No consortium or standard governs the interface; the MPQ, Illinois and Osaka results are academic devices, not products.
Roadmaps & track record. Nu Quantum's roadmap had two items and both arrived on time as prototypes — the Qubit–Photon Interface on 2024-10-14, the Quantum Networking Unit on 2025-06-12 — neither with a measured rate or fidelity: the unit's "up to 99.7%" is the ceiling its optical path allows C[781]fact. Atom Computing–Nu Quantum (2026-06-17) and Atom Computing–Cisco (2026-03-25) carry no dated targets P[780]P[782]; Osaka's ~100-channel target carries no date P[779]. As of 4 Sep 2026 no actor here has a promise specific enough to score — itself the finding.
Strategic reading. If chip-scale collection matures faster than bulk cavity QED, this interface inherits a photonic-foundry supply chain instead of bespoke lab hardware, and the advantage goes to whoever partnered with a photonic-integration group early — among vendors, Atom Computing. If not, distributed neutral-atom computing stays a slide and every roadmap past ~10⁴ atoms loses its scaling story. The substitution threat is across modalities: ion–photon and spin–photon links chase the same milestone, and the first to publish a usable rate sets the narrative.
Outlook & open questions
Confirm by end-2027 if any group publishes a heralded entanglement rate between two multi-atom neutral-atom modules; demote the interconnect claim if new results are still single-pair efficiencies. Best case by 2029: multiplexed collection reaches ~100 channels and a two-module logical operation is shown. Worst case: efficiency plateaus near 90%, channel counts stay in the tens, and the networking agreements never convert into a dated target. Open questions: what rate does a distributed neutral-atom architecture require; can chip-scale collection reach bulk-cavity cooperativity; does direct telecom emission beat cavity enhancement plus conversion.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [11] Novo Nordisk Foundation, “New quantum computer with great potential to boost Nordic research and innovation,” Novo Nordisk Fonden, Jul. 17, 2025. [Online]. Available: https://novonordiskfonden.dk/
en/ Gnews/ new-quantum-computer-with-great-potential-to-boost-nordic-research-and-innovation/ - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Gatom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
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Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring)
A millikelvin router die, an on-die multiplexer or 3D stacked wiring that turns a few cold input lines into the tens to thousands of gate voltages a spin-qubit array needs.
Verdict. The parts exist — Intel's 64-terminal Pando Tree, Quantum Motion's 1,024-dot multiplexed chip, Delft's 648-device demultiplexer — but no gate fidelity measured through a millikelvin router has been published as of 2026-09-26, and at Delft's ~1.25 µW per generated voltage a milliwatt of millikelvin cooling holds ~800 voltages: 10³ qubits only with shared control.
MXC = mixing chamber, the coldest refrigerator stage; SET = single-electron transistor; DRAM = dynamic random-access memory; FinFET = fin field-effect transistor; 22FDX = GlobalFoundries' 22 nm fully depleted silicon-on-insulator process; PDK = process design kit; Rent's rule T = t·g^p (T terminals, g components, t terminals per component, p the Rent exponent); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Every gate of a spin qubit is a line. Fan-out routes the few lines a refrigerator carries to those gates: a router die at the MXC (Intel), multiplexers on the qubit die (Quantum Motion, Equal1), or qubit chip and control electronics stacked vertically (Hitachi). Vandersypen et al. (2017) judged wiring ~10⁸ sub-100 mK qubits to room temperature "impractical" and put electronics beside the qubits D[761]. Li et al. shared the lines — "the control lines define the qubit grid" D[762]; Schaal et al. and Paquelet Wuetz et al. put CMOS switches at millikelvin D[763]D[764]. Intel described Pando Tree on 2024-06-20 C[272]; the register's first dated fan-out record is from 2025.
Attributes: static interconnect; low-frequency signals at mK and 4 K; coherent error; CMOS fabrication.
Physics & limits
Lines. In 2019 every platform wired each qubit directly, p = 1, against 0.36 for Intel's x86 processors; in Franke et al.'s example an added spin qubit costs two gates, t = 2 D[765] — 2×10⁶ lines at g = 10⁶. A crossbar gives T = 6√g − 1, 23 terminals for 16 dots D[520], ~6×10³ at 10⁶ S. At a 90 nm gate pitch D[197] routing must happen on or beside the die.
Heat. Large dilution refrigerators give "beyond 1 mW at 100 mK" D[761]. Delft generated and demultiplexed 96 voltages onto 648 devices at 66 mK for under 120 µW D[552]: ~1.25 µW per voltage, so a milliwatt holds ~800 — ~400 directly wired qubits or ~1.8×10⁴ crossbar dots S. Switching costs ∝ C·V²·f: strobing commercial multiplexers at 8 kHz lifted a 50 mK stage to 130 mK D[764]. A demultiplexer visits terminals in turn, each holding charge meanwhile — Schaal's cell stores it on the dot gate like a one-transistor–one-capacitor DRAM cell D[763] — so refresh rate trades droop against heat S.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2020-05-19 | Commercial CMOS multiplexers at 50 mK: 16 channels × 6 lines | QuTech / Intel | D[764] |
| 2023-08-28 | 16-dot germanium crossbar, 23 terminals | QuTech | D[520] |
| 2024-05-01 | 300 mm cryoprober: 232 twelve-dot arrays, electron temperature 1.6 ± 0.2 K | Intel | D[766] |
| 2024-06-20 | Pando Tree: bias and pulses to 64 terminals, 10–20 mK | Intel | C[272] |
| 2025-01-03 | 1,024 dots on one on-chip multiplexer, 22FDX, <1 K, mapped in <10 min | Quantum Motion | D[767] |
| 2025-03-16 | Bell-1, renamed RacQ in 2026: six qubits and control in one rack, 0.3 K, 1,600 W | Equal1 | C[768] fact |
| 2025-07 | 648 devices from 96 voltages, 66 mK, <120 µW, 22 nm FinFET | TU Delft / Intel | D[552] |
No row is a gate benchmark through a router: Pando Tree shares a circuit board with a Tunnel Falls chip C[272], with no fidelity measured through it found, as of 2026-09-26. Nearest: a 32-cell millikelvin pulse chip costing ~0.07% single-qubit fidelity D[551] — generation, not routing. Dominant term: heat per addressed voltage.
Manufacturing, materials & supply chain
Router dies are foundry CMOS run cold: 22 nm FinFET from Intel for Delft D[552], 22FDX for Quantum Motion D[767] and Equal1 C[273], Intel 18A for Hitachi's quantum PDK, "the first such interface for a 1.8nm-class process" P[769]. Tunnel Falls comes off a 300 mm line with extreme-ultraviolet lithography D[199]. Three routes compete: a separate router die (Intel), monolithic multiplexers (Quantum Motion, Equal1), and "stacking qubit chips and control electronics vertically" (Hitachi) P[769]. Cold wafer test gates all three — Intel's cryoprober is the published instance D[766] — and imec's SPINS pilot line adds 300 mm spin-qubit runs, PDKs and cryo-CMOS C[770]. Router and bond yields are unpublished as of 2026-09-26.
Control, readout & I/O burden
Pando Tree delivers "both constant voltage bias and high-speed voltage pulsing for up to 64 qubit terminals" from nine digital signals and one line from the 4 K Horse Ridge II controller C[272]: ten lines for 32 qubits at two terminals each (t = 2), ~0.3 lines per qubit S. The register's 0.0156 lines per qubit counts only the analogue line and reads terminals as qubits S. Intel's "approximately 20 cables" for a million qubits C[272] carries no heat or bandwidth budget, as of 2026-09-26. Readout fans in too: Diraq reads eight qubits through two SETs D[197]. At 1.25 µW per voltage and two terminals per qubit S, 10³ qubits need ~2.5 mW wired directly, ~0.2 mW on a crossbar; 10⁶ need ~2.5 W, or ~7.5 mW shared — only the combination nears one refrigerator's budget.
Role in the stack
Slot 9, the only layer-9 entry, of "Silicon / germanium quantum-dot spins". It requires fab_cmos (foundry CMOS) — "a CMOS router die at cryogenic temperature" — and ct_cryocmos (cryogenic CMOS control), which generates what this technology routes; cx_crossbar (layer 4) shares lines inside the array. No provides edge is recorded. ic_mcm (coupled multi-chip modules) replaces it; neither spin architecture has an inter-module link, as of 2026-09-26. Four register machines carry it (4 as primary): Tunnel Falls, Hitachi × Intel 18A, RacQ (Bell-1) and QM-One — those whose makers name an artefact. Tunnel Falls' cell is ✅, on the Pando Tree demultiplexer; the others are inferred and 🔎. Gap G-spinl9, answered in part: slot 9 of the quantum-dot architecture now holds this technology, the proposed ic_router; slot 9 of the donor-spin architecture is still empty.
Evidence — how the numbers were measured
The figures of merit — channels per die, heat per line at the MXC, hold droop, refresh rate, switching crosstalk — sit in no register cell. The record is component-level: Delft's held voltages drift 60 µV/s to 18 mV/s D[552], slow coherent error that randomised benchmarking averages away S; the cryoprober and the 1,024-dot chip measure devices, not gates D[766]D[767]. Equal1's page lists 99.3% average two-qubit fidelity C[273], which the register holds beside a press survey's 98.4%; neither names the fan-out behind it. Missing, as of 2026-09-26: a benchmark through a millikelvin router, and Pando Tree's dissipation.
Not published: the process node of Intel's Pando Tree and any qubit fidelity measured through it, and the fan-out plans of SQC, Quobly and Groove Quantum.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Intel | developer | US | Pando Tree router; 300 mm cryoprober | C[272]D[766] |
| Hitachi | developer | JP | Qubit chips and control stacked vertically; 18A PDK | P[769] |
| Quantum Motion | developer | UK | 1:1,024 on-chip multiplexer; tiles with on-chip control and readout | D[767]C[200] |
| Equal1 | developer | IE | Qubits and control electronics in 22FDX at 0.3 K | C[273] |
| TU Delft / QuTech | research | NL | Millikelvin demultiplexing; germanium crossbar | D[552]D[520] |
Money.
- 2026-01-15 · Equal1 · round led by the Ireland Strategic Investment Fund, system "onto a single chip" · USD 60 M · announced C[771]
- 2026-03-18 · Rhonexum · pre-seed led by QDNL Participations · USD 1 M · announced P[560]
- 2026-04-03 · imec-led consortium · SPINS pilot line, EU Chips Joint Undertaking co-funding · EUR 50 M · launched C[770]
- 2026-05-07 · Quantum Motion · Series C, fan-out not named · USD 160 M · announced C[355]
Market & supply chain. Fan-out is bought with the qubit die; the one merchant entrant found, Lausanne's Rhonexum, is at pre-seed P[560]. Scarce inputs — cold device models, cold wafer test, foundry slots — are shared with ct_cryocmos. It serves G4 and G7 on the quantum-dot architecture.
IP & standards. No fan-out patent count from a named database and no interface standard, as of 2026-09-26; the nearest artefacts are PDKs — SPINS' C[770] and Hitachi's intended 18A kit P[769].
Roadmaps & track record. Intel: ~20 cables per million qubits, undated C[272]; no qubit data through Pando Tree since 2024-06-20, as of 2026-09-26. Hitachi: cloud access in fiscal 2027, 100 qubits in fiscal 2028, 1,000 in fiscal 2030 P[769]. Diraq: 150,000 physical qubits by 2029, over 2 million by 2031, fan-out unstated R[211]. No fan-out milestone has come due; nothing to score yet.
Strategic reading. Intel's separate router and the monolithic dies of Equal1 and Quantum Motion are rival bets on the millikelvin milliwatt. If routers fall well below a microwatt per voltage, value moves to foundries with cold device models and to cold wafer test; if not, qubits run hotter — Equal1 at 0.3 K C[768] — or split into modules, and ic_mcm takes the slot S.
Outlook & open questions
Confirm if, by 2027-12-31, a peer-reviewed spin-qubit gate benchmark runs through a millikelvin router or on-die multiplexer and reports heat per channel; demote if Hitachi's fiscal-2028 prototype or Diraq's 2029 system ships with per-gate lines from 4 K or room temperature. Open questions. (1) What does Pando Tree dissipate per switched terminal? (2) What hold droop do exchange gates tolerate between refreshes? (3) Does time-multiplexed pulsing cap gate parallelism below what a surface-code round needs? (4) Can crossbar sharing and millikelvin routing share one die? (5) Will spin modules (ic_mcm) take the slot before routers reach 10⁴ channels?
References
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newsdesk/ Rdiraq-sets-roadmap-for-utility-scale-quantum-computing-with-millions-of-qubits-on-a-single-silicon-chip - [272] S. Subramanian and S. Pellerano, “Intel's Millikelvin Quantum Research Control Chip Provides Denser Integration with Qubits,” Intel Community, Jun. 20, 2024. [Online]. Available: https://community.intel.com/
t5/ CBlogs/ Tech-Innovation/ Data-Center/ Intel-s-Millikelvin-Quantum-Research-Control-Chip-Provides/ post/ 1608558 - [273] Equal1, “UnityQ.” [Online]. Available: https://www.equal1.com/
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innovation/ Cnews-and-events/ 2026/ equal1-announces-funding-round/
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הטקסט בעברית נטען…
Multi-die packaging in one module (flip-chip, bump-bonded control die)
A qubit die bump-bonded face to face with a second superconducting die that carries wiring, resonators, a second material or control logic, inside one package, across a vacuum gap of a few to ~20 µm.
Verdict. Seven of the register's twelve carriers document a two-die stack in a source that was opened and checked (✅); it moves the wiring wall onto a second die but joins no modules, and as of 2026-09-30 no carrier has published bump yield — Chalmers alone has published a bump count and a gap spread.
In = indium; TSV = through-silicon via; SFQ = single flux quantum, digital superconducting logic; T1, T2,echo = relaxation and echoed dephasing times; Q = quality factor; G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two superconducting dies face each other across a vacuum gap, joined by indium bumps: one carries the qubits, the other wiring, resonators, another material or control logic — the interconnect below the module scale, with no coherent link leaving the package. Sycamore used "indium for bump-bonds between two silicon wafers" D[291]; Zuchongzhi 3.0 puts 105 qubits and 182 couplers on one sapphire chip, "all the control lines and readout resonators" on the other D[35]; Ocelot bonds an aluminium junction die to a tantalum resonator die D[80]; SEEQC sets a 5 × 5 mm qubit chip on a 10 × 10 mm SFQ die D[304]. Root: MIT Lincoln Laboratory's 2017 flip-chip of flux qubits onto a readout-and-control chip D[754]. Not ic_mcm, which tiles qubit dies into one lattice, nor ct_vio, which brings lines through the chip face.
Attributes: fabricated, static; microwave at millikelvin; coherent error; superconducting lithography.
Physics & limits
The gap is a circuit element. Coherence survives a cap — bonded flux qubits kept T1 20.9 µs, T2,echo 24.6 µs with galvanic, capacitive and inductive coupling between chips D[754]; transmons at (7.8 ± 0.8) µm average above 90 µs D[755] — but frequencies follow the spacing: 1 µm moves a 6 GHz resonator ~2%, ~120 MHz D[755]. With f ∝ C^−1/2, a cap holding a fraction p of a transmon's capacitance shifts f by ≈ ½p·δd/d — for p = 0.2 and ±0.8 µm on 7.8 µm, ~50 MHz at 5 GHz S; hence SEEQC's aluminium hard stop fixing 10 µm D[304]. Facing ground planes form a parallel-plate guide with lateral modes near c/2L ≈ 7.5 GHz on a 20 mm die, unless ground bumps stitch them at millimetre pitch S.
Bumps. In on a TiN barrier over aluminium is superconducting throughout (Tc 1.1 K), mean critical current 26.8 mA, robust under shear and thermal cycling D[756]. Loss sits at interfaces: electroplated-In transmons reach Q ≈ 10⁶ (T1 ≈ 32 µs at 5 GHz S), most likely limited by the gold contact layer D[757]. Mismatch shears a bump ∝ Δα·ΔT·r/h (r from die centre, h bump height): nil for like substrates, worst for unlike pairs and large dies S.
Quasiparticles. A separate control die cuts the phonon path: an SFQ die on In bumps reached 1.2(1)% error per Clifford, tenfold better than earlier SFQ control D[249]; SEEQC's aluminium-rich bumps double as quasiparticle traps D[304].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2017-10 | Flux qubits flip-chipped to a control chip; In pillars 8–30 µm; T1 20.9 µs | MIT Lincoln Laboratory | D[754] |
| 2019-10 | 53 qubits; Al metallisation and junctions, In bump bonds between two Si wafers | D[291] | |
| 2022-06 | Two-die transmon modules, gap (7.8 ± 0.8) µm; CZ (98.66 ± 0.08)% | Chalmers | D[755] |
| 2023-07 | SFQ die + qubit die on In bumps; error per Clifford 1.2(1)% | Liu et al. | D[249] |
| 2024-12 | 105 qubits + 182 couplers on one sapphire die, control and readout on the other | USTC | D[35] |
| 2025-02 | Al junction die 16 × 14 mm² on Ta resonator die 20 × 20 mm² | AWS | D[80] |
| 2025-03 | Qubit chip on SFQ die, 10 µm gap; single-qubit fidelity to 99.9% | SEEQC | D[304] |
| 2026-08 | Electroplated In bumps; flip-chip transmon Q ≈ 10⁶ | Shih et al. | D[757] |
The dominant term is the partition the bump permits: Zuchongzhi 3.0 splits tantalum and aluminium between its sapphire chips, which "enhances the relaxation time" D[35]; Ocelot puts junctions, transmons, couplers and buffers on aluminium, storage, readout and Purcell resonators on tantalum D[80].
Manufacturing, materials & supply chain
One process family: In bumps on a TiN barrier D[756], 8 µm pillars at Chalmers D[755], In on an aluminium hard stop at SEEQC D[304], electroplated In that needs gold and pays in loss D[757]; Si–Si at Google D[291], sapphire–sapphire at USTC D[35]. Vias join when lines must leave: MIT Lincoln Laboratory's 10 × 20 × 200 µm superconducting TSVs carried control and readout in a bump-bonded stack D[540]; IBM's Eagle bonds a qubit wafer to an interposer with three-level wiring and through-substrate vias C[758]. No source opened names a bonding supplier or cycling yield, as of 2026-09-26.
Control, readout & I/O burden
A second die moves the wiring wall, not the line count. With k lines per qubit and c per inter-qubit gap, edge routing of an m × m lattice closes at m = 4c/k (the ct_vio estimate); as N = m², doubling c quadruples the ceiling, but lines still leave through a perimeter ∝ √N — only vias or cold control remove that S. The exception is a die that makes pulses: SEEQC's SFQ die demultiplexes so qubits share lines, 2.375 nW per qubit at 1:8 against 5.5 nW for the paper's rf case and 2.5 µW for cryo-CMOS, with "no signal delivery through bump bonds" — all coupling crosses the vacuum gap D[304]. At 10³ qubits a routing die is necessary, not sufficient; at 10⁴–10⁶ it is the substrate for vias or cold logic S.
Role in the stack
An alternate in slot 9 of "Transmon lattice with tunable couplers", "Bosonic cavity qubits — cat and GKP" and "Dual-rail erasure qubits". It requires fab_sc ("bump-bonded superconducting dies"); no provides edge is recorded; the graph has ic_mcm replace it ("module-to-module vs die-to-die"), yet both use one bump process and a tiled processor can stack each tile — a boundary, not a substitution S. It sits under ct_vio: a stack exits at its edge unless vias pierce it. Twelve register machines carry it (12 as primary). ✅: Sycamore-53 D[291], Zuchongzhi 3.0 D[35], Ocelot D[80], SEEQC on its Supp. §A D[304], IBM Quantum Eagle r1-r3 C[758], WACQT quantum computer (Chalmers 25-qubit flip-chip processor; 2,900 indium bumps between its two tiers Dfact), SUSTech's four-dual-rail-qubit processor, a qubit chip flip-chipped onto a carrier chip D[406], and Alice & Bob's planned Lithium, "qubits packed on one side and their connections printed on the other" Rfact. The 72-qubit Sycamore stays 🔎 — its paper names no bump, flip-chip or package D[602]; Tianyan-287 inherits by resemblance, a "Zuchongzhi 3.0-like" processor C[708], and Alice & Bob's Beryllium by succession from Lithium, its source not restating the flip-chip; Academia Sinica's "chip-stacking methods" C[759] and Kaveri's "flip-chip integrated technology" P[760] name no bumps; Zuchongzhi 3.2's source was not opened. Gap G-multidie, answered: all seven ✅ carriers document a two-die stack, each partitioned by function or material, none tiling a lattice; the ledger's dual-rail placement is carried by the SUSTech processor.
Evidence — how the numbers were measured
Coherence under a cap is shown at few-qubit scale D[754]D[755]; stack gate data are small: CZ (98.66 ± 0.08)% D[755], single-qubit fidelity to 99.9% under SFQ control D[304]. Large carriers' benchmarks hide the package. Missing as of 2026-09-26: one design measured with and without a cap; gap maps across a >100-qubit die against frequency-targeting error; bump continuity over thermal cycles; a control figure for Zuchongzhi 3.0's T1 gain.
Tianyan-287's abstract names no packaging, and Zuchongzhi 3.2's packaging is unconfirmed. Shih et al.'s T1 ≈ 32 µs assumes a 5 GHz qubit frequency, which the source does not give. Not published: bump yield or thermal-cycle failures for any carrier machine; the one bump count is the WACQT processor's 2,900, whose inter-chip gap was checked by electron microscopy but not reported fact.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Google Quantum AI | developer | US | Two-wafer In-bump Sycamore; qubit-compatible bump process | D[291]D[756] |
| USTC | developer | CN | Qubit/coupler die on control-and-readout die, Ta/Al split | D[35] |
| AWS Center for Quantum Computing | developer | US | Al nonlinear die on Ta linear die (Ocelot) | D[80] |
| SEEQC | developer | US | Qubit chip on SFQ control die, 10 µm gap | D[304] |
| IBM | developer | US | Qubit wafer on wired interposer (Eagle) | C[758] |
| MIT Lincoln Laboratory | research | US | Flip-chip flux qubits; TSVs in bump-bonded stacks | D[754]D[540] |
| Chalmers University of Technology | research | SE | Two-die transmon modules, gap metrology | D[755] |
| Academia Sinica | research | TW | "Chip-stacking" in a 20-qubit system | C[759] |
| QpiAI | developer | IN | Kaveri, flip-chip named in press | P[760] |
| SUSTech | research | CN | Four-dual-rail-qubit processor: qubit chip flip-chipped onto a carrier chip | D[406] |
| Alice & Bob | developer | FR | Flip-chip planned for the Lithium cat-qubit chip | Rfact |
Money. No dated, sourced financial item specific to multi-die packaging was found as of 2026-09-26.
Market & supply chain. Every documented stack is built by its processor's developer or lab S. Pays into G2–G4 on the transmon architecture, G3–G4 on the cat and dual-rail architectures.
IP & standards. No patent count from a named database is given here; no source opened names a bonding standard, as of 2026-09-26.
Roadmaps & track record. No carrier publishes a dated packaging milestone as of 2026-09-26; Academia Sinica "continues to enhance chip-stacking methods" C[759]; Kaveri targets ~100 µs coherence and ~10⁻² error P[760].
Strategic reading. Documented large transmon lattices — Sycamore, Zuchongzhi 3.0, Eagle — route through a second die; it buys materials freedom and routing, not scale. Value moves to gap control and bump yield at 10³–10⁴ bumps and, for SFQ, to the one second die that removes lines.
Outlook & open questions
Confirm if, by 2027-12-31, a carrier above 100 qubits publishes bump count, gap spread and frequency-targeting error; demote if no carrier above 100 qubits publishes those numbers by then. Open questions. (1) What is bump continuity per thermal cycle at 10⁴ bumps? (2) How much fixed-frequency targeting error is gap non-uniformity? (3) Does the bump interface set a loss floor near Q ≈ 10⁶? (4) Can an SFQ die under the qubits keep its error contribution below 10⁻³? (5) Do Sycamore's successors, Zuchongzhi 3.2 and Tianyan-287 keep the two-die stack the register infers?
References
- [35] D. Gao et al., “Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor,” Phys. Rev. Lett., vol. 134, Art. no. 090601, Mar. 2025, doi: 10.1103/PhysRevLett.134.090601. arXiv:2412.11924. D
- [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [249] C. Liu et al., “Single Flux Quantum-Based Digital Control of Superconducting Qubits in a Multichip Module,” PRX Quantum, vol. 4, no. 3, Art. no. 030310, Jul. 2023, doi: 10.1103/PRXQuantum.4.030310. D
- [291] F. Arute et al., “Quantum supremacy using a programmable superconducting processor,” Nature, vol. 574, no. 7779, pp. 505–510, Oct. 2019, doi: 10.1038/s41586-019-1666-5. D
- [304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at millikelvin temperature,” Nat. Electron., vol. 9, no. 3, pp. 287–294, Mar. 2026, doi: 10.1038/s41928-026-01576-6. D
- [406] W. Huang et al., “Logical multi-qubit entanglement with dual-rail superconducting qubits,” Nat. Phys., vol. 22, no. 4, pp. 591–597, Mar. 2026, doi: 10.1038/s41567-026-03211-9. arXiv:2504.12099. D
- [540] D.-R. W. Yost et al., “Solid-state qubits integrated with superconducting through-silicon vias,” npj Quantum Inf., vol. 6, Art. no. 59, 2020, doi: 10.1038/s41534-020-00289-8. arXiv:1912.10942. D
- [602] R. Acharya et al., “Suppressing quantum errors by scaling a surface code logical qubit,” Nature, vol. 614, pp. 676–681, Feb. 2023, doi: 10.1038/s41586-022-05434-1. D
- [708] T. Q. Group, “Tianyan: Cloud services with quantum advantage,” arXiv:2512.10504, Dec. 2025. C
- [754] D. Rosenberg et al., “3D integrated superconducting qubits,” npj Quantum Inf., vol. 3, Art. no. 42, Oct. 2017, doi: 10.1038/s41534-017-0044-0. arXiv:1706.04116. D
- [755] S. Kosen et al., “Building blocks of a flip-chip integrated superconducting quantum processor,” Quantum Sci. Technol., vol. 7, no. 3, Art. no. 035018, Jun. 2022, doi: 10.1088/2058-9565/ac734b. arXiv:2112.02717. D
- [756] B. Foxen et al., “Qubit compatible superconducting interconnects,” Quantum Sci. Technol., Aug. 2017, doi: 10.1088/2058-9565/aa94fc. arXiv:1708.04270. D
- [757] Y.-A. Shih et al., “Flip-chip integrated superconducting qubits using electroplated bump bonds,” arXiv:2608.07306, Aug. 2026. D
- [758] O. Dial, “Eagle's quantum performance progress,” IBM Quantum Computing Blog, Mar. 23, 2022. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ eagle-quantum-processor-performance - [759] Academia Sinica, “Academia Sinica Unveils 20-Qubit Superconducting Quantum Computer: Manufacturing Capabilities Reach Global Top-Tier,” Jan. 29, 2026. [Online]. Available: https://www.sinica.edu.tw/
en/ Cnews_content/ 55/ 3655 - [760] N. Pereira, “QpiAI Unveils Kaveri, India's First Aatmanirbhar 64-Qubit Quantum Chip,” Sify, Feb. 26, 2026. [Online]. Available: https://www.sify.com/
science-tech/ Pqpiai-unveils-kaveri-indias-first-aatmanirbhar-64-qubit-quantum-chip/
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הטקסט בעברית נטען…
Fibre links between photonic modules
Telecom fibre carrying heralded entanglement between photonic chips and racks — priced per connector, not per metre, and with no published rate.
Verdict. Real: 99.72% chip-to-chip Bell fidelity over 42 m (PsiQuantum, 2025), the fibre span itself costing ~8 mdB. Unproven: any inter-module entanglement rate. Demote if none is published by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Commodity telecom single-mode fibre carrying single photons or heralded entangled pairs between photonic chips, racks or modules. PsiQuantum published chip-to-chip Bell fidelity 99.72 ± 0.04% over 42 m in Omega D[169]; Aurora networks 35 chips over fibre at ~14 dB total loss D[173]. The same physics underwrites metropolitan entanglement distribution, where rates are published. Attributes: flying photons, no deterministic timing, loss-dominated error; room-temperature electro-optic interfaces, photonic-IC fibre coupling.
Physics & limits
Attenuation is not the binding term at machine scale. Forty-two metres at 0.2 dB/km is ~8 mdB, while the two fibre-to-chip transitions bracketing it cost 52 ± 12 mdB each D[169] — ~104 mdB, a fifth of a ~0.5 dB per-photon budget, spent on connectors rather than span. Modularity here is priced per interface, unlike matter-qubit links. What distance costs is time: 42 m is ~206 ns one way at group index 1.47, longer than the best 2026 feed-forward electronics, so separation eats the decision budget before the loss budget. Rate is the term no computing vendor publishes, and its exchange against loss is brutal: 0.7 coincidences/s through 66 dB of metropolitan fibre versus 132/s on the 93 km leg P[791]. At rack-scale loss the ceiling reverts to source brightness and multiplexing depth.
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2025-01 | 35 chips networked over fibre, ~14 dB total loss | Xanadu | D[173] |
| 2025-02 | Chip-to-chip Bell fidelity 99.72 ± 0.04% over 42 m | PsiQuantum | D[169] |
| 2025-02 | Fibre-to-chip coupling 52 ± 12 mdB | PsiQuantum | D[169] |
| 2026-06-10 | Edge coupling 0.085 dB/facet, claimed a benchmark | Xanadu | C[172] |
The 2026 benchmark claim does not survive comparison: PsiQuantum's 52 mdB is ~39% lower at the same interface a year earlier D[169]C[172]. Fidelity is past 99.7%; the missing number is throughput.
PsiQuantum's 99.72% chip-to-chip Bell fidelity has no independent replication. The ~206 ns per 42 m latency and the ~104 mdB two-interface cost are derived from published figures, not measured.
Manufacturing, materials & supply chain
No new fabrication: fibre, connectors and edge-coupled arrays are commodity telecom, with Corning fibre arrays and DISCO singulation behind Xanadu's coupling figure C[172]. The scaling variable is attachment count: every module boundary is two attachments, each a yield event and a 52 mdB loss event, so at 10³ modules packaging throughput sets the build rate; at 10⁴ bundle volume and timing calibration bind; nothing addresses 10⁶. I/O burden sits upstream, in the source and the fusion measurement. The machine falls under BIS ECCN 4A906 only if its qubit count and C-NOT error land in one of the rule's bands, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact.
Role in the stack
Two photonic architectures depend on it — fusion (PsiQuantum, Quandela, QuiX) and continuous-variable/GKP (Xanadu) — to scale past one chip's mode count, contributing ~0.21 µs per 42 m to the derived clock, comparable to the whole feed-forward term. Verification: the 99.72% is a conditional Bell fidelity on heralded events, channel loss excluded D[169], so it says nothing about link efficiency, and it is single-source as of 2026-09-04.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| PsiQuantum | developer | US | Highest published chip-to-chip Bell fidelity over 42 m | D[169] |
| Xanadu | developer | CA | 35-chip fibre-networked system; coupling benchmark | D[173] |
| Quandela | developer | FR | Fielded 12-qubit Lucy coupled to Joliot-Curie HPC | C[792] |
| Corning | supplier | US | Fibre arrays for photonic chip packaging | C[172] |
Money.
2025-09-10 · PsiQuantum · Series E · USD 1 B at USD 7 B · BlackRock, Temasek, Baillie Gifford · closed Cfact
2026-03-26 · Xanadu · SPAC merger · ~USD 302 M gross, ~40% below plan · Crane Harbor · closed Cfact
2026-05-21 · PsiQuantum · CHIPS letter of intent · USD 100 M · US Commerce · LOI fact
Market & supply chain. Fibre and connectors are commodity; the concentrated input is precision fibre-array attachment, where Corning and a few packaging houses set loss and throughput alike. No cost per link is public. Pays for G3/G4, G6.
IP & standards. No dated patent family specific to inter-module photonic fibre linking surfaced as of 2026-09-04; ETSI QKD standards govern the physical layer, no computing-side interconnect standard exists.
Roadmaps & track record. PsiQuantum's 99.72% is unchanged since 2025-02, its 2026 progress visible only through DARPA V&V D[169]. Xanadu marketed a coupling benchmark it does not hold C[172]. No actor has published a dated inter-module rate target — a roadmap gap, not a slipped promise.
Strategic reading. While rate stays unpublished, every photonic logical-qubit roadmap rests on an unaudited number and buyers cannot compare vendors. Whoever publishes fidelity and rate together sets the benchmark; packaging houses, not chip designers, capture the margin, since loss and yield live at the connector.
Outlook & open questions
Confirm by 2028: a vendor publishing an inter-module rate with its fidelity; demote if the field still reports fidelity alone. Best case 2029: multiplexed links close a stated rate gap at rack scale. Worst case: rate stays unmeasured. Open: is 99.72% reproducible outside PsiQuantum; does multicore fibre help inside a machine.
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [172] Xanadu, “Xanadu sets new industry benchmark in photonic chip packaging,” PR Newswire, Jun. 10, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cxanadu-sets-new-industry-benchmark-in-photonic-chip-packaging-302796562.html - [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [791] J. Du et al., “Entanglement distribution over 155 km metropolitan fiber using a CMOS-compatible silicon chip,” arXiv:2409.17558, Sep. 2024. P
- [792] M. U. Rehman, “Quandela Deploys Photonic Quantum Computer Integrated with HPC System,” The Quantum Insider, Apr. 14, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ C04/ 14/ quandela-photonic-quantum-hpc/
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הטקסט בעברית נטען…
300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)
Industrial 300 mm CMOS lines fabricating quantum-dot spin qubits, cryo-CMOS controllers and superconducting wiring; the only qubit manufacturing route with wafer-scale yield statistics.
Verdict. Uniformity is proven (96% device yield, sub-nm CD); fidelity is not yet a foundry deliverable. Demote if no 300 mm device with >20 qubits and all-pairs 2Q ≥ 99.5% appears by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
This node is a manufacturing regime, not a qubit: 300 mm CMOS production lines making gate-defined quantum-dot arrays (Si/SiGe, SiMOS, Ge), their cryo-CMOS ASICs, and superconducting qubit and wiring layers. A quantum dot is an accumulation-mode transistor at single-electron occupancy; at 45–100 nm pitch the foundry supplies uniformity, interface quality and isotopic control, not resolution, across tens of thousands of devices per wafer with cryogenic wafer-level test.
CEA-Leti opened the route in 2016 with a spin qubit in a 28 nm FD-SOI flow D[793]. Intel and QuTech made the first all-optically patterned 300 mm qubits in March 2022 D[794], fixing since 2022; Intel added EUV arrays and 1.6 K wafer statistics in 2024 D[199], [766]. imec produced 300 mm transmons in 2024 D[293] and, with Diraq, unit cells above 99% in 2025 D[189]. GlobalFoundries' 22FDX became the merchant option in 2025 D[767], ST started ²⁸Si FD-SOI lots in December 2025 P[795], and US CHIPS letters of intent followed in May 2026 G[300].
Attributes (technology graph):
a, carrier affinity: fabricated, 1.0; the node is fabrication itself.
b, characteristic time: none; no gate time or entangling mode.
c, readout: none.
d, mobility and connectivity: none.
e, control modality: none.
f, error structure: coherent; device-to-device variability read as calibration error.
g, manufacturing: CMOS.
Physics & limits
Mechanism. The fab fixes four inherited quantities: geometric uniformity, critical dimension within 0.5 nm at 45–100 nm pitch D[199]; electrostatic disorder, a random threshold-voltage spread of 59 mV on Intel Si/SiGe D[766]; isotopic purity, 800 ppm residual ²⁹Si at Intel D[199] and 400 ppm at imec D[189]; and interface quality, which sets charge noise and, in Si/SiGe, the valley-splitting distribution.
Scales. T2*/T2echo reach 5/205 µs on ²⁸Si Si/SiGe against 0.6/98 µs on natural silicon D[766]; Hahn-echo T2 reaches 1.31 ms on imec SiMOS D[197].
Floor. For spins it is material: residual ²⁹Si, interface charge noise and the Si/SiGe valley-splitting tail that turns some dots into leakage sinks. For transmons it is junction targeting: across a 300 mm wafer qubit frequencies spread 5–7%, i.e. 10–14% in junction resistance at qubit junction sizes (the ~8% resistance spread is that of large junctions) D[293], an order above collision-free lattice needs; alternating-bias annealing (97.4% targeting D[294]) is post-fabrication, not a foundry property.
As the code sees it: coherent, calibratable error (HRL attributes about 80% of CNOT error on its 54-dot array to control and calibration D[190]) plus leakage and slow drift; nothing is erasure-convertible; wafer gradients D[293] become spatially correlated error. Moving the floor needs 10-ppm-class ²⁸Si, engineered valley splitting (simulation only S[796]), Ge/SiGe holes or in-flow junction trimming.
Engineering state of the art
Best demonstrated: four Diraq/imec unit cells, every operation above 99% (1Q 99.97%, CZ 99.04–99.56%, SPAM 99.95% at 100 µs), gate-set tomography, September 2025 D[189]fact. Typical at scale: Intel's 232 twelve-dot devices on one wafer gave 99.8% dot and 96% full-device yield, May 2024 D[766]; unmodified 22FDX gave 28–40% "good dot" yield over 1,024 dots, January 2025 D[767]; imec's eight-qubit array validated one pair of four, July 2026 D[197].
table
| year | figure | who | tag+key |
|---|---|---|---|
| 2016 | spin qubit in a 300 mm 28 nm FD-SOI flow | CEA-Leti | D[793] |
| 2022-03 | >10,000 dot arrays per wafer; 1Q 99.0–99.1% | Intel/QuTech | D[794] |
| 2024-09 | 300 mm transmons: median T1 75 µs, 98.25% yield | imec/KU Leuven | D[293] |
| 2024-12 | >24,000 devices per wafer, CD < 0.5 nm (EUV) | Intel | D[199] |
| 2025-01 | 1,024 dots on 22FDX, 1:1,024 cryo-CMOS mux, < 10 min | Quantum Motion/GF | D[767] |
| 2025-09 | CZ 99.04–99.56% on 300 mm SiMOS, 4 of 4 devices > 99% | Diraq/imec | D[189] |
| 2026-04 | 4 K CMOS controller (366 DACs, ≤ 3.5 W) runs d=5 repetition code, Λ = 4.7 | HRL | D[190]fact |
Dominant error term: the 2Q plateau at 99.0–99.6% is charge noise plus exchange calibration D[189], [190]; 100 µs readout for 99.9%-class SPAM D[189] sets a 100–300 µs cycle; no 300 mm device above twelve qubits has published all-pairs 2Q; for transmons the limit is junction spread, not coherence D[293].
Manufacturing, materials & supply chain
Platforms. Intel D1: Si/SiGe wells, immersion and EUV lithography, cryo-prober screening D[199], [766]. imec: SiMOS with overlapping polysilicon gates below 100 nm pitch on 400 ppm ²⁸Si D[189], plus a transmon flow with dry-etched overlap junctions D[293]. FD-SOI: GlobalFoundries 22FDX (Quantum Motion D[767]; Equal1 C[797]) and ST 28 nm at Crolles on Soitec ²⁸Si substrates, first lots December 2025 P[795]. HRL and SkyWater run 200 mm D[190]C[19].
Yield. 96% device yield on a quantum-optimised flow D[766] against 28–40% on a merchant flow D[767] is this node's central number.
Cost and energy. No foundry publishes a quantum wafer price; Diraq's < $1 per qubit target R[211] and vendors' rack-scale claims C[200], [355], [771] are unaudited.
Supply chain. Lines: Intel (captive); imec, coordinator of the EU SPINS pilot line G[770]; GlobalFoundries' Quantum Technology Solutions unit C[353]; IBM Albany, becoming Anderon for superconducting wiring, TSVs and bumps C[798]; SkyWater, 200 mm, IonQ-owned since 2026-07-31 C[19]. Materials: enriched ²⁸Si, historically Russian, now also from ASP Isotopes in Pretoria (commercial since 2025-03-27) C[347] and from ORNL and PNNL as 99.9999% ²⁸Si silane (US DOE, announced 2026-07-16) G[348]; Silex completed a plant for up to 20 kg per year in June 2026, commissioning late 2026, for SQC C[799]. Equipment: cryogenic wafer probers from Bluefors/Afore (< 2 K, 300 mm, 768 DC, 48 RF lines) C[800] and FormFactor C[801]. Single points of failure: EUV dots only at Intel and imec; a prober duopoly; ²⁸Si from a handful of enrichers.
Export control. BIS's rule of 2024-09-06 controls cryogenic CMOS ICs for ≤ 4.5 K (ECCN 3A901), cryogenic systems ≥ 600 µW at ≤ 0.1 K (3A904), cryogenic wafer probers (3B904) and quantum computers by qubit count and C-NOT error together, from 34 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906) fact, with License Exception IEC for allies G[301]fact; EU and UK lists match. The same rule controls silicon and germanium enriched beyond set isotope fractions — epitaxial layers, hydrides such as silane, bulk and oxides (3C907–3C909) G[301].
Control, readout & I/O burden
Multiplexing moves on-die or in-package: a 1:1,024 cryo-CMOS multiplexer on 13 lines D[767]; imec's multiplexer routing transmon pulses below 15 mK with > 99.9% 1Q preserved D[802]; a 32-cell 28 nm FD-SOI chip at 7 mK, ~20 nW/MHz per cell D[551]; HRL's 4 K controller, 366 DACs at ≤ 3.5 W (~10 mW per channel), running a repetition code D[190]; IBM's 4 K controller at 23 mW per qubit D[296]. Crossbar sharing needs T = 6√g − 1 lines for a square array of g dots (23 for 16) D[520].
Walls. 10³: per-qubit lines suffice; the burden is tune-up time. 10⁴: at IBM's 23 mW per qubit D[296] the 4 K load is 230 W, at HRL's 3.5 W per 18 qubits D[190] about 2 kW — over a hundred times the 2 W 4 K stage of a Bluefors XLD1000sl, and above the 200 W of Fermilab's Colossus, the largest plant in the resource review S[550] — forcing ≥ 10:1 multiplexing or millikelvin nW-class cells. 10⁶: only crossbar sharing (~6,000 lines D[520]) plus millikelvin CMOS or SFQ closes; whether shared control keeps coherent error below threshold is open. Latency: spin cycles are readout-bound, 100 µs integration D[189].
Role in the stack
A layer-10 root: it requires nothing and provides the dot arrays and cryo-ASICs the quantum-dot spin architecture assumes, its primary home; it is an alternate on the transmon lattice with tunable couplers, trapped-ion QCCD and trapped ions with electronic gates. It replaces STM-lithography donor fabrication (11-qubit registers, serial, no foundry route D[192]); for ion traps it is the alternative to MEMS trap fabs, the switching price being CMOS re-qualification, paid by Oxford Ionics (part of IonQ since 2025-09-17), whose 99.99% two-qubit fidelity on standard-fab chips is reported in an IonQ release C[446]fact. Here natural carriers (trapped ions) inherit semiconductor manufacturing. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture; this node adds no term; the quantum-dot spin architecture's derived round is 8.5 µs, readout-set, against a measured 100–300 µs cycle D[189]. Conveyor shuttling over an effective 10 µm (back and forth) at 99.5% D[196], shown on a Delft-made device, is what uniform 300 mm gates must reproduce. Neighbouring empty slots: no spin-module interconnect (300 mm photonics is the candidate, unproven at millikelvin) and no fabricated cryogenic decoder; a cryo-CMOS predecoder design claims 3,780× syndrome-bandwidth reduction below 0.56 mW S[733].
Evidence — how the numbers were measured
Yield numbers come from cryo-probers at 1.6–1.7 K (automated tune-up, turn-on/pinch-off and charge-sensing criteria D[199], [766]): transistor statistics. Fidelities come from few devices in dilution refrigerators: gate-set tomography (12,263 sequences) for the unit cells D[189], randomised benchmarking on Tunnel Falls D[199], T1/T2 wafer maps for transmons D[293].
Not captured: (1) 1.6 K probing cannot see valley splitting, exchange or coherence, so device yield says nothing about qubit yield; (2) selection: 4 of 20 imec devices characterised D[189], 6 of > 10,000 arrays cooled in 2022 D[794]; (3) criteria: 28–40% and 96% define "working" differently D[766], [767]; (4) no simultaneous all-pairs 2Q on any 300 mm array D[197]; (5) ageing: 3.7% junction drift in 146 days D[293] is absent from fidelity claims.
Replication: imec's SiMOS numbers reproduce across four devices and two institutions D[189]; Intel's are single-vendor. Flagged: Quantum Motion's "first full-stack silicon CMOS quantum computer" without published fidelities C[200]; Equal1's commercial-process dots without qubit metrics C[797].
SPAM for the imec/Diraq unit cells is 99.95% at 100 µs [189], against 99.9% recorded for imec's 300 mm line (2025). Intel's yield figures all come from [766], on 232 twelve-dot devices of one wafer — 99.8% of dots, 96% of full devices, 91% charge-sensing success; [199] restates the 96%, citing [766]. Not published: the dates of Silex's A$5.1 M Defence Trailblazer and A$4.35 M SQC funding [799].
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Intel | developer; captive supplier | US | Si/SiGe EUV arrays; cryo-prober wafer statistics; 12-qubit chip at Argonne | D[199], [766]; G[207] |
| imec | research; supplier | BE | 300 mm SiMOS dots, transmons, millikelvin multiplexer; SPINS coordinator | D[189], [293], [802]; G[770] |
| GlobalFoundries | supplier (merchant foundry) | US | 22FDX dots and cryo-CMOS; Quantum Technology Solutions unit; $375 M LOI | C[353], [803]; G[300] |
| IBM | developer; supplier | US | Anderon: 300 mm superconducting wafers, TSVs, bumps; $1 B LOI | C[10], [798]; G[300] |
| Diraq | developer | AU | SiMOS unit cells at imec; QBI Stage B; CHIPS LOI up to $38 M | D[189], [197]; G[65], [300] |
| Quantum Motion | developer | UK | 22FDX 1,024-dot arrays; NQCC system; QBI Stage B | D[767]; C[200]; G[65] |
Money.
| date | actor | event | amount | lead or programme | cumulative | status |
|---|---|---|---|---|---|---|
| 2025-11-06 | Diraq; Quantum Motion; SQC | grant | up to $15 M each | DARPA QBI Stage B | — | definitive G[65]fact |
| 2026-01-15 | Equal1 | round | $60 M | ISIF | > $85 M | closed C[771]fact |
| 2026-04-03 | imec + 25 partners | grant | €50 M | EU Chips JU SPINS pilot line | — | announced G[770] |
| 2026-05-07 | Quantum Motion | Series C | $160 M | DCVC, Kembara | — | closed C[355]fact |
| 2026-05-21 | GlobalFoundries | CHIPS LOI | $375 M | US Commerce ($2.013 B over nine LOIs) | — | LOI, non-binding G[300]C[353]fact |
| 2026-05-21 | IBM (Anderon) | CHIPS LOI | $1 B + $1 B IBM cash | US Commerce | — | LOI, non-binding G[300]C[798] |
| 2026-05-21 | Diraq | CHIPS LOI | up to $38 M | US Commerce | > $100 M raised Pfact | LOI, not awarded G[300] |
| 2026-06-03 | Quobly | Series A | €115 M | Bpifrance, SEALSQ, STMicroelectronics | €134 M | closed P[804]fact |
| 2026-06 | Silex Systems | Q-Si plant completed | A$5.1 M + A$4.35 M | Defence Trailblazer; SQC | — | commissioning late 2026 C[799] |
| 2026-07-23 | IBM | M&A: HRL Laboratories | undisclosed | — | — | announced; closed 2026-08-26; potential plans for spin qubits at Anderon C[10]factfact |
| 2026-07-31 | IonQ | M&A: SkyWater | $15.00 + 0.4883 IonQ shares per share (~$1.8 B) | — | — | closed C[19]fact |
Market & supply chain. Quantum is immaterial to foundry revenue. Concentration: two EUV-capable dot lines, one merchant FD-SOI option (ST entering), a prober duopoly, a handful of ²⁸Si enrichers. Unit economics: unpublished beyond Diraq's target R[211]. Payers: G4 for 10⁶-qubit CMOS density; G7, as of 3 Sep 2026, for rack-scale spin systems; superconducting vendors buy Anderon/GF wiring for G2–G4; ion vendors buy standard-fab traps for G2, G3, G7.
IP & standards. Portfolios: Intel, HRL, Diraq/UNSW, Quantum Motion/UCL, Quobly (CEA/CNRS licences), Equal1; no litigation public; no dated family count from a named database found. SPINS promises quantum PDKs and multi-project-wafer access G[770]; GF markets FDX cryogenic models C[353]; no open cryogenic device-model standard exists.
Roadmaps & track record. Intel (promised 2022 · wafer-scale qubits · delivered 2024, Argonne 2026-01-06 G[207]fact; no successor or roadmap as of 2026-09-03). Diraq (promised 2026-07-09 · "thousands" by 2029, restated 2026-08-27 as 150,000 physical · eight qubits shown D[197]R[211]fact). Quantum Motion (promised 2025-01 · NQCC system · delivered 2025-09-15, no published fidelity C[200], [803]). Quobly (promised 2025-12 · ST-lot metrics Q1 2026 P[795] · none found as of 2026-09-03). GF, Anderon: no wafer dates promised C[353], [798]. Credibility: imec/Diraq (peer-reviewed, replicated) first; Intel manufactures without a product path; Quantum Motion and Equal1 deliver systems without peer-reviewed metrics (Equal1's RacQ, sold as Bell-1 until May 2026, is installed at ESA's Frascati centre, announced by ESA on 2026-07-15 fact and by Equal1 on 2026-07-31 Cfact), Quobly none yet; roadmap slides last.
Strategic reading. Success rewards foundries and suppliers (GF, imec, ST/Soitec, Bluefors) and spin vendors whose bill of materials shrinks to wafers plus racks; bespoke routes (STM lithography, university lift-off) and MEMS trap fabs lose. Supplier bargaining power is high (few lines, quantum revenue immaterial), but three or four substitutable lines and state money cap what foundries extract. Substitution threats: Ge/SiGe holes, photonic-interconnect fabs, SFQ against cryo-CMOS.
Outlook & open questions
Milestones, 12–24 months: (1) a 300 mm device with > 20 qubits and published all-pairs 2Q ≥ 99.5% confirms; none by end-2027 demotes; (2) SPINS multi-project-wafer runs with a public quantum PDK; (3) GF's LOI made definitive, a named 22FDX quantum product; (4) a spin-qubit lot at Anderon from HRL, IBM-owned since 2026-08-26; (5) Intel naming a Tunnel Falls successor or exiting.
2029 best case: two merchant 300 mm lines with quantum PDKs, 10³-dot arrays with on-die multiplexing, 2Q ≥ 99.5% typical, a below-threshold spin memory. Worst: merchant yields at tens of percent, 2Q at 99–99.6%, roadmaps cut again, GF's unit reduced to packaging for superconducting and photonic customers.
Open questions: can valley splitting and charge noise be made wafer-uniform, or must every array be post-selected? What is the qubit-fidelity yield of a 300 mm flow? Does shared control keep coherent error below threshold? Can in-flow junction targeting reach sub-percent? Watch the first fidelity-yield number, SPINS' first multi-project wafer, definitive CHIPS awards, Intel.
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off-the-wire/ Pquobly-raises-e115m-series-a-to-industrialize-silicon-quantum-computing/
Русский текст загружается…
הטקסט בעברית נטען…
Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)
A CMOS foundry flow putting low-loss nitride waveguides, electro-optic switches, single-photon detectors and fibre attach on one 300 mm wafer.
Verdict. Demonstrated once, by one line (GlobalFoundries Fab 8 for PsiQuantum, 2025), with wafer-scale uniformity published but no die yield or ageing statistic; single-source risk defines the layer.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The photonic IC foundry supplies the optics a photonic quantum computer is made of — SiN waveguides and delay lines, barium-titanate (BTO) or thin-film lithium niobate (TFLN) electro-optic switches, on-die superconducting nanowire single-photon detectors (SNSPDs), cryo-compatible fibre attach — on a 300 mm CMOS line with wafer-scale process control. A photonic qubit is never stored, only transmitted, so the figure of merit is a loss budget in decibels, not a coherence time. Lineage: ultra-low-loss dielectric waveguides (early 2010s, LioniX and UCSB), foundry access from about 2015 (AIM Photonics, imec), the first full quantum stack on 300 mm in 2025 D[169].
Attributes: carrier affinity natural-leaning (0.25), the line hosting no qubit but the modes that carry one; characteristic time not applicable, entangling downstream heralded, not deterministic; readout none intrinsically, but it supplies the on-chip SNSPDs, whose counting is destructive; mobility none — fixed lithography is what buys the photons theirs; control modality none, though it supplies the switches; error structure loss, seen by the code as heralded erasure; manufacturing a photonic-IC process line.
Physics & limits
Everything converts into one currency. Single-mode SiN routing at 1.8 ± 0.2 dB/m D[169] costs 34% of the photons per metre of on-chip delay; the wider multimode waveguide in the same process reaches 0.5 dB/m D[169]. Against an architectural budget near 0.5 dB for a whole fusion path, one BTO switch at 100 mdB spends a fifth of it, a fibre-to-chip transition at 52 ± 12 mdB a tenth, a median on-chip SNSPD at 93.4% efficiency 0.30 dB by itself D[169]. The dielectric floor is Rayleigh scattering from sidewall roughness, scaling with the mode's overlap with the etched interface, plus N–H absorption near 1520 nm that a 1150 °C anneal drives out. Both are beaten by weakening confinement: the 0.060 dB/m record used a 40 nm-thin core on a 100 mm wafer D[810], a geometry with millimetre bend radii. That is the trade — loss is bought with area, area with wafers — so a foundry routing waveguide is thirty times lossier than the record and must be. The other failure mode is phase: thermal gradients and stress birefringence detune interferometers, so a line that cannot hold film thickness ships chips needing per-die trimming. Moving the floor needs an electro-optic material whose Pockels coefficient shrinks switches faster than their loss grows — BTO's exceeds 1,000 pm/V against about 30 pm/V for lithium niobate D[169], which is why PsiQuantum and DARPA bet on it P[181].
Engineering state of the art
Best demonstrated is one wafer run; typical at scale is only partly defined, since Omega publishes spreads but no die yield D[169].
Records timeline
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2018-09-24 | TFLN modulator: Vπ 1.4 V at 20 mm, insertion loss < 0.5 dB, 210 Gbit/s | Harvard (Lončar group) | D[811] |
| 2021-02-10 | SiN loss 0.060 dB/m, intrinsic Q 422 M (100 mm wafer, 40 nm core) | UCSB / Honeywell | D[810] |
| 2025-02-26 | 300 mm quantum PIC: SiN 1.8 ± 0.2 dB/m single-mode and 0.5 dB/m multimode, splitter 0.5 ± 0.2 mdB, BTO switch 100 mdB, median SNSPD 93.4%, fibre-to-chip 52 ± 12 mdB, fusion Bell 99.22 ± 0.12%, at ~2 K | PsiQuantum + GlobalFoundries | D[169] |
| 2026-06 | Edge coupling 0.085 dB per facet | Xanadu | C[172] |
The dominant budget term is not the waveguide but switch insertion loss, facet coupling and detector inefficiency — everything happening where the photon changes medium. The second is invisible: with no yield statistic, nobody can distinguish a process from a good die.
Manufacturing, materials & supply chain
The demonstrated flow is a 300 mm CMOS line with LPCVD (low-pressure chemical vapour deposition) nitride and a high-temperature anneal, BTO as an integrated active layer, SNSPDs patterned in situ, cryo-compatible fibre attach, at ~2 K rather than millikelvin D[169]. TFLN is made differently — ion-sliced bulk lithium niobate bonded to oxide — which is why HyperLight and Lightium are separate companies rather than modules in that line P[518]. The merchant market is otherwise 200 mm or smaller: LIGENTEC runs nitride on X-FAB's automotive-qualified 200 mm line and added X-FAB's SOI platform in 2026 C[812]; LioniX supplies TriPleX modules; imec and AIM Photonics run research lines.
Omega does publish spreads: on-chip SNSPD efficiency averages 88.9 ± 3.5% against its 93.4% median (screened detectors), BTO film thickness holds 3σ < 3% across the 300 mm wafer, and waveguide loss is 0.5 ± 0.3 dB/m multimode and 1.8 ± 0.2 dB/m single-mode D[169]. No die yield or 2 K thermal-cycle ageing data exists, and no foundry publishes quantum MPW or mask-set pricing, so cost per mode is unquotable as of 3 Sep 2026. Single points of failure: one 300 mm line has demonstrated the full stack; BTO deposition tooling is no merchant market; TFLN wafer supply is thin and concentrated; integrated SNSPDs exist at one vendor. Export-control exposure is indirect but real — the BIS interim final rule of 2024-09-06 created ECCNs 3A901 (cryogenic CMOS below 4.5 K), 3A904 (cryocoolers ≥ 600 µW below 0.1 K), 3B904 (cryogenic wafer probing), 3D901/3E901 and 4A906, with License Exception IEC G[301]. PIC processes and SNSPDs are not named; the cryogenic test equipment is.
A second, smaller line serves the near-visible band that atom and ion control needs: at 780 nm, silicon nitride (Si₃N₄) microresonators from a CMOS-compatible 150 mm multi-project-wafer process (deep-ultraviolet lithography, 1,200 °C anneal) reach a most-probable intrinsic quality factor Q₀ = 9.5 × 10⁶ over 721 measured resonances, a propagation loss of 6.3 dB/m P[886].
Control, readout & I/O burden
The I/O burden is fibre and bias lines. At 52 mdB per facet D[169] per-channel loss is affordable; the wall is assembly throughput, since 10⁶ modes need of order 10⁵–10⁶ alignment steps. Detection adds a bias line and an amplifier per SNSPD at 2 K, which by 10⁴ channels forces cryogenic readout ASICs — the cryo-CMOS controlled under 3A901 G[301] and now sold as a GlobalFoundries product line C[353]. Feed-forward must drive the switch within a delay line's lifetime, at MHz–GHz; the 100 mdB BTO switch at 2 K is both the enabling device and the item DARPA is paying to validate P[181]. At 10³ modes nothing binds; at 10⁴ fibre attach and channel count bind; at 10⁶ the constraints are wafer-scale integration, the cryoplant, and an unpublished yield.
Role in the stack
The layer floors two architectures as their primary process: fusion-based photonic computing (PsiQuantum, Quandela, QuiX) and continuous-variable/GKP computing (Xanadu); it is an alternate on five more — the boson sampler, colour-centre spin network nodes, trapped-ion QCCD, the linear Paul trap with laser addressing and the alkali Rydberg tweezer array. It provides single photons and squeezed modes, switches for routing and feed-forward, modulators, chip-to-fibre coupling, and the electro-optic chips transducers are built from. Its reach across families is a prospect, not yet a record: ion laser delivery and chip-generated atom tweezers are photonic-IC products too, and GlobalFoundries names trapped ions among the modalities its quantum unit serves C[353], but Quantinuum's ion waveguides come from Sandia's research complex (ct_ionlaser) and the atom chips on record use glass waveguides or Aeponyx's nitride with no foundry named (ct_pic_trap). If a 300 mm line takes those on, capital spent here stops being modality-specific — the least-correlated bet in the manufacturing layer. It replaces the bulk-optics table, and switching back costs area, alignment drift and any path past a few hundred modes. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset — undefined on a fusion architecture, which runs none; this layer contributes only transport, roughly 5 ns per metre of on-chip delay, negligible against the 100 ns-class feed-forward the architecture needs D[169]. Neighbouring empty slots: a merchant 300 mm BTO switch process, a second source for integrated SNSPDs, any published wafer-level acceptance statistic.
Evidence — how the numbers were measured
Loss is measured two incompatible ways. Ring-resonator intrinsic Q gives the 0.060 dB/m record D[810] — one mode, one geometry, no routing. Spiral cut-back on a production reticle gives 1.8 dB/m D[169] — the waveguide the machine uses, and the only manufacturing number. Note that the main report's "0.5 dB/m" is the multimode figure from the Omega paper while the single-mode routing waveguide in the same paper is 1.8 ± 0.2 dB/m: both must be stated, they are not competing measurements D[169]. Fusion Bell fidelity, HOM visibility and detector efficiency are component metrics on selected dies, with no protocol converting them into a loss budget an architecture can be scored against, and no ageing data. No second group has reproduced any Omega figure on a second line; the only third-party check is DARPA's Stage C validation of the BTO switches, packaging and cryogenics, whose results are not public P[181]. The one conflict between sources is the PIXEurope budget: ≈€400 M per imec/ICFO G[582] against €380 M in trade press P[813]; trust the consortium release.
PIXEurope's budget is ≈€400 M in G[582] and €380 M in the consortium release P[813]. The dominance of a single Chinese ion-slicing supplier of TFLN wafers is widely cited but stated only qualitatively. Not published: dated 2025–2026 funding, capacity or loss figures for LioniX International; AIM Photonics' founding federal award and the wafer diameter of its Albany line; quantum MPW and mask-set prices at 300 mm, from any foundry, so no cost per mode can be quoted; and wafer-level yield or 2 K thermal-cycle ageing for BTO switches and integrated SNSPDs, from any actor — uniformity is public only as Omega's film-thickness, efficiency and loss spreads.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| GlobalFoundries | supplier (foundry) | US | Fab 8, Malta NY: the 300 mm line carrying Omega; Quantum Technology Solutions launched 2026-05-21 | C[353]D[169] |
| PsiQuantum | developer / customer | US, AU | Qualified the SiN + BTO + SNSPD + fibre-attach stack at 2 K | D[169] |
| imec | research foundry | BE | 300 mm CMOS and photonics, BTO-on-SOI heritage, PIXEurope partner | D[189]G[582] |
| LIGENTEC | supplier | CH, FR, BE | SiN on X-FAB's 200 mm line; added SOI 2026 | C[812] |
| LioniX International | supplier | NL | TriPleX SiN waveguides, module assembly | Cfact |
| HyperLight | supplier | US | TFLN modulators, Harvard spin-off | P[518] |
| AIM Photonics | research / foundry | US | DoD ManTech institute; PDK and Assembly Design Kit, 2026-05-25 | C[814] |
| Xanadu | developer | CA | TFLN/SiN CV chips; 0.085 dB/facet packaging; Toronto factory | C[172]C[178] |
| Quandela | developer | FR | GaAs quantum-dot sources; Lucy delivered to CEA/TGCC | C[176]fact |
| QuiX Quantum | developer | NL | SiN processors; Carina delivered to DLR, 2026-07 | C[177] |
Money.
- 2024-09 · HyperLight · Series B · $37 M · Summit Partners · closed P[518]
- 2024-09 · Lightium · seed · $7 M · Vsquared Ventures, Lakestar · closed P[518]
- 2024-11-24 · PIXEurope · EU pilot line · ≈€400 M · Chips JU, Spain, Catalonia · announced G[582]
- 2025-09-10 · PsiQuantum · Series E · $1 B at $7 B · BlackRock, Temasek, Baillie Gifford · closed fact
- 2026-03-26 · Xanadu · SPAC with Crane Harbor · ≈$302 M gross · Nasdaq/TSX XNDU · closed fact
- 2026-05-21 · GlobalFoundries · CHIPS letter of intent · $375 M · US Dept of Commerce · LOI, non-binding G[300]
- 2026-05-21 · PsiQuantum · CHIPS letter of intent · $100 M · US Dept of Commerce · LOI, non-binding G[300]
- 2026-07-22 · PsiQuantum · QBI Stage C expansion (BTO switches, packaging, cryogenics) · $125 M · DARPA · definitive fact
- 2026-08-28 · Xanadu · federal funding, Toronto factory · CAD 195 M · Government of Canada · announced C[178]
Market & supply chain. The enabling equipment is ordinary semiconductor capital (LPCVD/PECVD, immersion lithography, CMP, wafer bonding, MBE/PLD) from ASML, Lam, ASM, EVG and SUSS, in a market where quantum is a rounding error: good for cost, bad for influence. Concentration risk sits at the process, not the tool; unit economics are unquotable. G3 and G4 pay for this layer, G6 through fibre links and transducer chips, G7 through 2 K over millikelvin; G1 and G2 only via ion and atom optics, nothing in G5.
IP & standards. No dated patent count from a named database was retrieved for the PIC-foundry families; the one photonic family verified for this report is ORCA Computing's US 12,437,225 on linear-optical GHZ measurements, granted 2025-10-07 fact. There is no cross-foundry PDK standard — every design kit is proprietary and incompatible, the practical reason a customer cannot second-source. AIM Photonics publishes the most open kit C[814].
Roadmaps & track record. PsiQuantum, a commercially useful machine in Brisbane (promised 2024-04 · for end-2027 · groundbreaking slipped to 2026-06-17 and moved to Moreton Bay, cryoplant delivery due 2H 2027 Cfact, no 2026 hardware publication) Pfactfact; its DARPA tasking of 2026-07-22 frames the goal as a fault-tolerant machine "before 2033" P[181]. Xanadu loss 24.1× above threshold → 1.0× in 2030 (promised 2026-08-31 · nothing yet due) C[178]. PIXEurope pilot line (promised 2024-11 · for 2025 onward · no open-access run reported) G[582]. GlobalFoundries Quantum Technology Solutions (promised 2026-05-21 · LOI not yet definitive) C[353]G[300]. GlobalFoundries alone has a record of qualifying a process to production discipline; PsiQuantum has one paper and no second line; the European suppliers deliver at 200 mm, not at the loss-times-scale fault tolerance needs.
Strategic reading. If the layer succeeds the winner is the foundry, not the modality: GlobalFoundries collects a per-wafer annuity across five qubit technologies C[353] while PsiQuantum's differentiation narrows to architecture and cryogenics. If single-mode loss sticks near 1–2 dB/m both architectures stall and the value migrates to ion laser delivery, atom tweezers and networking — which is why it is worth funding either way. Substitution: bulk optics below a few hundred modes. Bargaining power sits with the foundry: switching lines means full requalification and a new PDK.
Outlook & open questions
Confirm if by end-2027 any actor publishes a wafer-level yield distribution for BTO switches or integrated SNSPDs at 300 mm; if a second line (imec, AIM Photonics, a PIXEurope member) publishes single-mode SiN loss ≤ 1.8 dB/m with monolithic detectors; or if Xanadu's loss factor falls below 10× threshold. Demote if PsiQuantum publishes no hardware result beyond Omega by mid-2027, or if the $375 M CHIPS LOI lapses. Best case by 2029: two qualified 300 mm lines, routing below 1 dB/m, switches under 50 mdB, published wafer maps. Worst case: one vendor, one paper, an LOI that never converts.
Open questions. (1) What is the die yield of an integrated SNSPD array on 300 mm, and why has nobody published it? (2) Is BTO manufacturable at volume, or a hero-die material DARPA is paying to find out about? (3) Who second-sources this layer if GlobalFoundries reprioritises?
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [172] Xanadu, “Xanadu sets new industry benchmark in photonic chip packaging,” PR Newswire, Jun. 10, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Cxanadu-sets-new-industry-benchmark-in-photonic-chip-packaging-302796562.html - [176] Quandela, “Quandela delivers Lucy, the most advanced photonic quantum computer worldwide, to EuroHPC and GENCI at CEA's TGCC,” Oct. 23, 2025. [Online]. Available: https://www.quandela.com/
about-us/ Cnewsroom/ quandela-delivers-lucy-the-most-advanced-photonic-quantum-computer-worldwide-to-eurohpc-and-genci-at-ceas-tgcc/ - [177] QuiX Quantum, “QuiX Quantum Delivers Carina Core Hardware Platform to DLR QCI, Advancing Europe's Universal Photonic Quantum Computing Roadmap,” Jul. 14, 2026. [Online]. Available: https://www.quixquantum.com/
news/ Cquix-quantum-delivers-carina-core-hardware-platformto-dlr-qci - [178] Xanadu Quantum Technologies Limited, “Xanadu Charts Path to Over 1,000 Logical Qubits by 2031,” GlobeNewswire, Aug. 31, 2026. [Online]. Available: https://www.globenewswire.com/
news-release/ C2026/ 08/ 31/ 3353211/ 0/ en/ xanadu-charts-path-to-over-1-000-logical-qubits-by-2031.html - [181] M. Abdel-Kareem, “PsiQuantum Secures $125 Million Expanded Agreement with DARPA under QBI Program,” Quantum Computing Report, Jul. 22, 2026. [Online]. Available: https://quantumcomputingreport.com/
psiquantum-secures-125-million-expanded-agreement-with-darpa-under-qbi-program/ P - [189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fidelity,” Nature, vol. 646, no. 8083, pp. 81–87, Sep. 2025, doi: 10.1038/s41586-025-09531-9. D
- [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [353] GlobalFoundries, “GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing,” May 21, 2026. [Online]. Available: https://gf.com/
gf-press-release/ Also https://investors.gf.com/globalfoundries-launches-quantum-technology-solutions-to-scale-us-quantum-manufacturing/ news-releases/ . Cnews-release-details/ globalfoundries-launches-quantum-technology-solutions-scale-us - [518] optics.org, “Lithium niobate in vogue as thin-film developers raise cash,” Sep. 24, 2024. [Online]. Available: https://optics.org/
news/ Plithium-niobate-in-vogue-as-thin-film-developers-raise-cash - [582] imec, “The European Commission and Chips JU select the PIXEurope consortium to lead the European Pilot Line on Advanced Photonic Integrated Circuits,” Nov. 24, 2024. [Online]. Available: https://www.imec-int.com/
en/ Gpress/ european-commission-and-chips-ju-select-pixeurope-consortium-lead-european-pilot-line - [810] M. W. Puckett et al., “422 Million intrinsic quality factor planar integrated all-waveguide resonator with sub-MHz linewidth,” Nat. Commun., vol. 12, no. 1, Art. no. 934, Feb. 2021, doi: 10.1038/s41467-021-21205-4. D
- [811] C. Wang et al., “Integrated lithium niobate electro-optic modulators operating at CMOS-compatible voltages,” Nature, vol. 562, no. 7725, pp. 101–104, Oct. 2018, doi: 10.1038/s41586-018-0551-y. D
- [812] LIGENTEC, “About us_2026 - LIGENTEC.” [Online]. Available: https://www.ligentec.com/
about-our-story/ C - [813] PIC Magazine, “EU to establish €380 million pilot line for photonic integrated circuits,” Jan. 6, 2026. [Online]. Available: https://picmagazine.net/
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news C - [886] W. Sun et al., “A photonic integrated comb engine for ultracold quantum gases,” arXiv:2609.28294, Sep. 2026. P
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הטקסט בעברית נטען…
Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm)
300 mm junction lithography and post-fabrication frequency trimming (laser annealing, ABAA) set the frequency spread every superconducting architecture inherits.
Verdict. Real: 300 mm optical lithography yields 393/400 working qubits, at 5–7% frequency spread (10–14% in junction resistance); trimming lands 97.4% on target. Anderon is an LOI — demote if no non-IBM wafer ships by end-2027.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A Josephson junction is two superconductors across a ~1–2 nm oxide barrier whose area and oxidation fix the critical current and hence the qubit frequency. This node is the process patterning those junctions and their niobium wiring at wafer scale — not a qubit. Lineage: e-beam Dolan-bridge Al/AlOx/Al junctions from the 2007 transmon (Koch et al., Yale), then 193 nm immersion lithography and etch on CMOS lines D[293].
Attributes. Carrier affinity 1.0 — fully fabricated: the manufacturing step itself, with no carrier, mobility, readout or control. Manufacturing — Nb wiring and Al/AlOx junctions on 200→300 mm silicon or sapphire; the error passed downstream is coherent (frequency offset, collision), not stochastic.
Physics & limits
Ambegaokar–Baratoff ties critical current to normal-state resistance, and f01≈(√8EJEC-EC)/h, so Rn spread reaches frequency at half weight. imec measured ~8% RSD in junction resistance across a 300 mm wafer (7,872 test structures) and ~4% within a die, both for large junctions; at qubit junction sizes the area scatter adds, and qubit frequencies spread 5–7% RSD — 10–14% in resistance D[293]. That is a lattice problem, not a device problem: fixed-frequency neighbours must clear collision windows tens of MHz wide on a ~5 GHz qubit, so 5% spread (≈250 MHz, 1σ) leaves no collision-free yield at lattice scale. Trimming is a precondition, not an optimisation — alternating-bias assisted annealing moves junction resistance >70% and lands 97.4% of junctions on target D[294].
The second floor is dielectric loss: amorphous AlOx and interface oxides host two-level systems capping T1 in the tens-to-low-hundreds of µs. imec's 300 mm devices give median T1 75 µs, best 161 µs, best T2e 245 µs, over a 42–113 µs centre-to-edge gradient that is a process signature, not scatter D[293]. TLS drift hourly, and quasiparticle bursts set a floor lithography cannot touch Dfact. What moves it: epitaxial barriers and Ta/Nb base metal; tuneable couplers ease the first floor's frequency collisions, not the loss.
Engineering state of the art
Best on a genuine 300 mm CMOS line: 393 of 400 qubits functional D[293] — but at the frequency spread above, so trimming or tuneability is still required downstream.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-08 | ABAA trimming: 97.4% targeting success, >70% tuning range | Rigetti | D[294] |
| 2024-09 | 300 mm optical-litho transmons: 393/400 functional, median T1 75 µs, frequency RSD 5–7% | imec | D[293] |
| 2025-11 | Loon on 300 mm Albany: c-couplers, multilayer low-loss routing | IBM | C[49] |
| 2026-02 | Wafer-scale package: >500 qubits per 3-inch sapphire die, readout 97.5% median (n=54) | OQC | P[311] |
| 2026-05 | Anderon, pure-play 300 mm quantum foundry: $1 B CHIPS + $1 B IBM | IBM / US DoC | G[798] |
Dominant error term: coherent frequency error — spread, collisions, drift. TLS-limited T1 is what the process cannot remove.
Manufacturing, materials & supply chain
Dolan-bridge shadow evaporation still produces most published qubits; the CMOS route means 193i patterning, RIE, Nb wiring, TSVs, bump bonds. Its advantage is statistics and throughput, not coherence: imec's median T1 matches e-beam devices, its metrology does not. Trade press claims ~30× device output versus 200 mm; IBM's release states no multiple P[299]. Tooling is unremarkable, so the scarce asset is recipe and trimming capability; single points of failure are refrigerator capacity, high-resistivity silicon and sapphire, and Nb etch expertise shared with the SFQ chain. Cost per wafer is not quotable. Export exposure is indirect: the BIS rule of 2024-09-06 controls cryogenic wafer probers (3B904), sub-4.5 K cryogenic electronics (3A901) and quantum computers by qubit count and C-NOT error together, from 34 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906) fact, but no ECCN names junction lithography G[301].
Control, readout & I/O burden
No control or readout of its own; it sets the ceiling others hit, through escape density and frequency targeting. OQC's package is the current bound: >500 qubits on one die, out-of-plane coax, no wire bonds, 56 nine-to-one readout multiplexing cells — and no per-qubit control lines as measured P[311], so it is a packaging result, not a processor. At 10³ per die the constraint is collisions; at 10⁴ escape density and routing, what Loon targets C[49]; at 10⁶ no fabricated design exists.
Role in the stack
Root node of the superconducting family: it requires nothing upstream and provides for transmon, fluxonium, the rf-SQUID flux qubit and planar bosonic modes, plus long-range c-couplers, millikelvin SFQ control, flux-DAC multiplexing, vertical signal delivery, multi-die packaging, multi-chip modules with l-couplers, and cryogenic microwave links. Architectures served: transmon, bosonic cat/GKP, dual-rail erasure, annealing. For a bosonic mode it is the planar alternative to machined 3D cavities. Fan-in is zero, yet its fan-out is the family's widest and every downstream node inherits its spread and yield. It adds nothing to the derived clock (derived clock = sum of the syndrome round: gate layers + transport + readout + reset, 0.65 µs on the transmon lattice) but bounds how many qubits reach it.
Evidence — how the numbers were measured
Frequency is predicted from junction resistance via Ambegaokar–Baratoff, then confirmed spectroscopically after packaging, so the statistic that matters is Rn RSD — published by nobody except imec D[293]. RB, XEB and cycle benchmarking measure a calibrated lattice, blind to dies discarded and pre-trim collision rates. ABAA's 97.4% is a targeting-success rate from an optimised study, not a worst-case bound D[294]. OQC's numbers are sub-sampled: readout over 54 of >500 sites, 105/108 operational on the characterised subset P[311]. Conflict: OQC's abstract gives a ~100 µs median for T1 and T2e together; its body gives T1 97 µs and T2e 129 µs over 105 qubits P[311].
IBM's 2026-05-21 release gives Anderon as a letter of intent subject to definitive documents, with no execution announced by 4 Sep 2026, yet IBM's 2026-08-26 HRL release already calls Anderon "its quantum wafer foundry". The "≈30× device output versus 200 mm" appears only in trade press [299]; IBM's own release states no multiple. The PatSnap H10N 60 counts [312] are portfolio-wide patent records. Not published: a per-wafer or per-qubit cost for any 300 mm superconducting-qubit line; a dated patent family specific to Nb/Al junction lithography at 300 mm; whether Google's Goleta purchase is fab capacity, and the wafer size of its Santa Barbara fabrication facility [805]; and whether the Nb wiring stack of imec's 300 mm line, which uses Al/AlOx/Al overlap junctions, matches IBM's approach.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Anderon | supplier | US | Proposed pure-play 300 mm quantum wafer foundry | G[798] |
| IBM | developer | US | Fabricates Nighthawk and Loon on 300 mm Albany | C[49] |
| imec | research | BE | 300 mm optical-litho transmons, published yield | D[293] |
| Rigetti | developer | US | ABAA junction trimming on its own line | D[294] |
| OQC | developer | UK | Wafer-scale package, >500 qubits per die | P[311] |
| GlobalFoundries | supplier | US | $375 M CHIPS LOI, multi-modality foundry | G[300] |
| US Dept of Commerce | regulator | US | CHIPS letters of intent, $2.013 B | G[300] |
Money.
- 2026-05-21 · Anderon · CHIPS LOI plus IBM equity · $1 B CHIPS + $1 B IBM cash and IP · US Dept of Commerce · within $2.013 B across nine firms · LOI, unexecuted G[798]fact
- 2026-05-21 · GlobalFoundries · CHIPS LOI, multi-modality foundry · $375 M · US Dept of Commerce · — · LOI G[300]
- 2026-06-02 · IBM · commitment, quantum overall · >$10 B / 5 yr · — · announced C[57]
- 2026-08-26 · IBM · HRL acquisition completed, naming an Anderon collaboration · undisclosed · — · completed C[204]
Market & supply chain. No merchant superconducting-qubit foundry operates as of 4 Sep 2026: the 300 mm lines with published qubit data are IBM's captive Albany line and imec's research pilot, Google fabricates captively in Santa Barbara at an unpublished wafer size P[805], and the proposed merchant line is funded by its prospective customers' largest competitor. Binding scarcities are refrigerator capacity and process know-how, not tools; unit economics are not quotable. G3 and G4 pay directly, G7 indirectly; G1, G2, G5, G6 fund nothing.
IP & standards. PatSnap's landscape of 2026-06-30 counts 783 IBM and 357 Google patent records in superconducting devices (IPC H10N 60) P[312]fact. No patent family specific to 300 mm junction lithography carries a named assignee and year; no standards body governs these processes.
Roadmaps & track record. Anderon (promised 2026-05-21 · foundry serving vendors worldwide · status 2026-09-03: LOI only, yet IBM's 2026-08-26 release calls it "its quantum wafer foundry") G[798]C[204]. Rigetti/ABAA (2024-08 · production frequency targeting · in use under the 108-qubit product, whose 99.5% two-qubit target slipped to "later 2026") D[294]C[36]. IBM's fabrication milestones land on schedule; its merchant-access promise has no record.
Strategic reading. If 300 mm superconducting fab scales, IBM wins twice — vertically integrated, and landlord to everyone else's capacity. Fabless vendors win only with a neutral foundry, which does not exist. Losers are vendors whose differentiator is fabrication skill, not architecture. The threat is capture, not substitution: every superconducting architecture needs this node, and equipment suppliers have no bargaining power against its owner.
Outlook & open questions
Confirm by end-2027 if Anderon executes definitive CHIPS documents and fabricates for a named non-IBM customer; demote the merchant-foundry framing if only IBM designs emerge. Best case by 2029: two or more independent 300 mm lines with published cross-foundry uniformity and post-trim residuals below 1% frequency RSD. Worst case: Anderon stays captive. Open questions: does any line publish post-trim collision yield; can epitaxial barriers lift median T1 above 200 µs; does a merchant European or Asian line emerge?
References
- [36] Rigetti Computing, Inc., “Rigetti Announces General Availability of 108-Qubit System,” Apr. 7, 2026. [Online]. Available: https://investors.rigetti.com/
news-releases/ Cnews-release-details/ rigetti-announces-general-availability-108-qubit-system - [49] IBM, “IBM Delivers New Quantum Processors, Software, and Algorithm Breakthroughs on Path to Advantage and Fault Tolerance,” Nov. 12, 2025. [Online]. Available: https://newsroom.ibm.com/
2025-11-12-ibm-delivers-new-quantum-processors,-software,-and-algorithm-breakthroughs-on-path-to-advantage-and-fault-tolerance C - [57] IBM Quantum, “Why IBM is investing $10 billion into quantum computing,” Jun. 2, 2026. [Online]. Available: https://www.ibm.com/
quantum/ Cblog/ 10-billion-investment-faq - [204] IBM, “IBM Completes Acquisition of HRL Laboratories to Accelerate the Future of Quantum,” Aug. 26, 2026. [Online]. Available: https://newsroom.ibm.com/
2026-08-26-ibm-completes-acquisition-of-hrl-laboratories-to-accelerate-the-future-of-quantum C - [293] J. Van Damme et al., “Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers,” Nature, vol. 634, no. 8032, pp. 74–79, Oct. 2024, doi: 10.1038/s41586-024-07941-9. D
- [294] D. P. Pappas et al., “Alternating-bias assisted annealing of amorphous oxide tunnel junctions,” Communications Materials, vol. 5, no. 1, Art. no. 150, Aug. 2024, doi: 10.1038/s43246-024-00596-z. D
- [299] L. James, “IBM spins off America's first quantum chip foundry with $2 billion in federal and private funding — newly-minted 'Anderon' foundry to offer 300mm quantum wafer fab and manufacturing services,” Tom's Hardware, May 26, 2026. [Online]. Available: https://www.tomshardware.com/
tech-industry/ Pquantum-computing/ ibm-spins-off-americas-first-quantum-chip-foundry-with-2-billion-in-federal-and-private-funding - [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/
news-events/ Gnews/ 2026/ 05/ department-commerce-announces-letters-intent-9-companies-2-billion - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [311] O. W. Kennedy et al., “Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits,” arXiv:2602.12773, Feb. 2026. P
- [312] PatSnap, “Quantum Computing Patent Landscape 2026,” Jun. 30, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ quantum-computing-patent-landscape/ - [798] IBM, “IBM and U.S. Department of Commerce Announce America's First Purpose-Built Quantum Foundry, Supported by Proposed $1 Billion CHIPS Award,” May 21, 2026. [Online]. Available: https://newsroom.ibm.com/
ibm-and-u-s-department-of-commerce-announce-americas-first-purpose-built-quantum-foundry G - [805] I. Hamm, “Google Buys 83,000-Square-Foot Campus in Goleta for $32.5M,” The Santa Barbara Independent, Aug. 24, 2026. [Online]. Available: https://www.independent.com/
2026/ P08/ 24/ google-buys-83000-square-foot-campus-in-goleta-for-32-5m/
Русский текст загружается…
הטקסט בעברית נטען…
Ion-trap fabrication (surface-electrode chips; machined 3D blade traps)
Planar rf/DC electrode chips that confine and shuttle ions, built on MEMS lines or, increasingly, on merchant semiconductor foundry wafers.
Verdict. Falsifiable — if no vendor publishes wafer-level heating or yield data by end-2027, trap fabrication stays craft, and Sol/Apollo schedule risk sits in signal count and packaging, not gate physics.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A surface-electrode trap flattens the Paul trap into one lithographic plane — electrodes side by side, the ion held tens of micrometres above — so trap geometry becomes mask layout. NIST demonstrated it in 2006, holding ²⁴Mg⁺ about 40 µm above planar gold and measuring the heating rate directly D[806]. The machined 3D trap persists beside it: AQT's Pine trap has four blade electrodes and two endcaps machined from gold-plated titanium on an alumina holder, the blades 0.57 mm from the trap axis D[253]. It is the layer beneath the ion carrier: it fixes electrode count, zone and junction geometry, and the surface chemistry above it.
Attributes: carrier affinity a = 0.0, natural — the carrier served is the ion; the trap itself is fabricated, but MEMS trap-making is the natural carriers' default, so the technology sits in the natural half of the map. Manufacturing g = MEMS lithography moving onto merchant 6–12-inch semiconductor lines C[320].
Physics & limits
The floor is anomalous field noise from the electrode surface, not lithographic resolution. Over ion heights of 30–3,000 µm it falls roughly as d⁻⁴ D[807]: halving the height to pack zones costs ~16× in heating. Heating becomes gate error, since entangling gates ride a shared motional mode for tens to hundreds of microseconds, and forces re-cooling between transport steps. The noise is an adsorbate layer, not a bulk property: cooling gold traps to 6 K suppressed heating ~7 orders of magnitude D[808]; argon-ion bombardment cut it 100-fold on an already-clean trap D[809]. The error structure the code sees is coherent and correlated — stray charge on dielectric gaps gives micromotion and phase drift shared across a zone, and one open electrode kills that zone. What moves the floor: niobium electrodes, in-vacuum cleaning, shielded dielectric, cryogenics by default.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2006 | ²⁴Mg⁺ ~40 µm above planar gold; heating first measured | NIST | D[806] |
| 2012 | 100× field-noise reduction, in-situ argon-ion cleaning | NIST | D[809] |
| 2025-10 | 2Q error 8.4×10⁻⁵, laser-free, commercial-fab chip | Oxford Ionics | D[102] |
| 2025-11 | 1,228 electrodes, 273 independent signals, 8 zones | Quantinuum | D[97] |
Helios's chip is the largest fielded trap; most groups still run bespoke traps of tens to ~100 electrodes. Nobody publishes yield, defect rate or cost per trap, so the layer has no public quality metric, and measured error stays dominated by heating, micromotion and calibration load, not lithographic defects.
Manufacturing, materials & supply chain
Two lineages. Research MEMS lines (Sandia's MESA complex, GTRI, university cleanrooms) put gold or niobium on sapphire, fused silica or oxidised silicon at one-off volumes G[501]. The live shift is merchant fabrication: Infineon's Villach platform runs 6–12-inch wafers with anodic bonding for Oxford Ionics, eleQtron C[129], Innsbruck and ETH Zürich; its Gen-3 out-of-plane electrodes claim ~10× confinement with no heating rate published C[320]. Honeywell fabricates Quantinuum's traps captively, Sol's grid trap included R[118]; IonQ closed SkyWater on 2026-07-31 for design, fabrication and packaging on US lines C[19]. Infineon is the single point of failure: one merchant fab, several vendors, no second source named. Export exposure is mild — the 2024-09-06 BIS rule enumerates quantum computers (4A906) and sub-4.5 K electronics (3A901), but no ECCN names traps G[301].
Control, readout & I/O burden
The trap sets the wiring floor before any optical or microwave line exists: 273 independent signals for 98 ions, 2.8 per qubit, for confinement and transport alone D[97], each a DAC channel, filter and feedthrough. At that ratio 10³ ions needs ~3,000 DC lines, past practical feedthrough counts, and 10⁶ is impossible without switching under the trap. The published escape is on-chip switching: Oxford Ionics' WISE drives 1,000 fully connected ions from ~200 sources, with no chip built and no dissipation budget S[325].
Role in the stack
This layer underlies all three trapped-ion architectures — QCCD (Quantinuum), the linear Paul trap with laser addressing (IonQ, AQT, Quantum Art P[125]) and electronic gates with chip control (IonQ/Oxford Ionics, eleQtron) — providing the carrier, the junction and grid geometry, and traces for chip-integrated microwave control. It replaces bespoke MEMS with foundry fabrication, priced in design-rule and UHV qualification and re-measured heating, not physics. Its clock contribution is indirect and large: derived clock = sum of the syndrome round: gate layers + transport + readout + reset, and transport is 9.0 ms of the 9.7 ms round derived for QCCD, against a ~70 µs gate D[97]; measured on H2, transport took 60% of circuit time on average D[110] — so zone count and junction quality buy more clock than gate speed. No neighbouring empty slot in the technology graph.
Evidence — how the numbers were measured
Electrode and signal counts are vendor-reported and unaudited. Heating is published per trap at one operating point, never as a wafer or batch distribution, and no vendor discloses yield. The 8.4×10⁻⁵ gate is a two-ion measurement without ground-state cooling, not a fleet average, unreplicated externally as of 4 Sep 2026 D[102]. No dated dispute between vendors over fabrication claims was found.
No ECCN names ion traps, and no BIS advisory opinion places a bare ion-trap die inside or outside 4A906. Not published: the defect rate and cost per trap, from IonQ, Quantinuum, Infineon, AQT or eleQtron, as of 2026-09-04; whether Infineon fabricated the chip behind the 8.4×10⁻⁵ result — the Oxford Ionics–Infineon link is asserted at company level only; and a heating rate for Infineon's Gen-3 out-of-plane electrodes, so their ~10× confinement gain is unmeasured.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IonQ | developer | US | Owns trap design house and a US foundry | C[19] |
| Oxford Ionics | developer | UK | Electronic-gate trap chips on commercial fab lines | D[102] |
| Infineon Technologies | supplier | Austria | Merchant trap fab, Villach, 6–12-inch wafers | C[320] |
| SkyWater Technology | supplier | US | US foundry, eight quantum-computing engagements in 2025, IonQ-owned since 2026-07-31 | G[576]C[19] |
| Quantinuum | developer | US | Fields the 1,228-electrode trap; Sol in validation | D[97] |
Money.
- 2025-09-17 · IonQ · M&A (Oxford Ionics) · $1.075 B · — · closed fact
- 2026-07-31 · IonQ · M&A (SkyWater) · ~$1.8 B ($15.00 cash + 0.4883 IonQ shares per share) · — · closed C[19]fact
- 2026-02-25 · SkyWater · FY2025 results (year to 2025-12-28) · $442.1 M revenue, 19.7% GAAP gross margin, quantum-related revenue +30% YoY · filed G[576]
- 2025-11-06 · DARPA · QBI Stage B (IonQ, Quantinuum of eleven) · ≤$15 M each · announced G[65]fact
Market & supply chain. Enabling equipment is ordinary semiconductor capital plus UHV parts, none concentrated; concentration sits in the fab — Infineon merchant, Honeywell captive, Sandia research-only, plus an IonQ–Sandia co-design MOU on 2026-08-04 C[584]. Trap unit economics are unpublished; the nearest number is SkyWater's 19.7% GAAP gross margin on $442.1 M of FY2025 revenue G[576]. G3 and G4 pay for this layer, G7 for rack modules.
IP & standards. PatSnap's 2026 review names MIT Lincoln Laboratory's chip-integrated voltage-source and photonics families (2016, 2019) and ETH Zürich's cryogenic co-fabricated optics (2020) as core integration IP, with no count isolated to trap fabrication P[375]. The key wiring architecture is published, not fenced S[325]; no litigation, no acceptance standard.
Roadmaps & track record. Quantinuum: Sol on a Honeywell-fabricated grid trap (promised 2024-09-10 · for 2027 · in validation as of 2026-09-03) R[118]; Helios shipped on time, so fab-linked credibility is good. IonQ: SkyWater (promised 2026-01-26 · for Q2–Q3 2026 · closed 2026-07-31) C[19], but 10,000 ions on one chip in 2027 rests on no published 2D-trap heating or yield data, and the 2020 roadmap missed its 2026 count ~40×.
Strategic reading. If foundry fabrication works, the differentiator moves off trap craft onto control electronics, packaging and codes. Winners: IonQ, which removes a fab dependency; Quantinuum, already captive-supplied; Infineon, which gains everyone else's volume. Losers: national-lab lines lose their monopoly. The substitution threat is not a rival trap but the clock — fabrication cannot fix a layer time 10³–10⁵× slower than superconducting unless it multiplies zones. Power sits with the fab; IonQ bought one, and carries its ~20% gross margin.
Outlook & open questions
Confirm or demote by end-2027: does a SkyWater-fabricated trap hold ions in a shipped system; does Sol validate on schedule at 1,200+ electrodes in 2D; does anyone publish a yield or per-wafer heating distribution. Best case 2029: merchant trap wafers with published acceptance data and switching that cuts signals per ion five-fold. Worst case: electrode counts plateau near 10³ because feedthroughs and DAC channels are the wall, and tighter 2D geometry raises heating enough to push Apollo right. Open questions: does a 2D grid keep the linear trap's heating rate; can switching run at 4 K inside a dissipation budget; will Infineon stay merchant.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Cionq-completes-acquisition-of-skywater-technology - [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/
research/ Gprograms/ quantum-benchmarking-initiative/ stage-b-selection - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [102] A. C. Hughes et al., “Trapped-ion two-qubit gates with >99.99% fidelity without ground-state cooling,” arXiv:2510.17286, Oct. 2025. D
- [110] S. A. Moses et al., “A Race Track Trapped-Ion Quantum Processor,” Phys. Rev. X, vol. 13, Art. no. 041052, Dec. 2023, doi: 10.1103/PhysRevX.13.041052. arXiv:2305.03828. D
- [118] Quantinuum, “Quantinuum Unveils Accelerated Roadmap to Achieve Universal, Fully Fault-Tolerant Quantum Computing by 2030,” Sep. 10, 2024. [Online]. Available: https://www.quantinuum.com/
press-releases/ Rquantinuum-unveils-accelerated-roadmap-to-achieve-universal-fault-tolerant-quantum-computing-by-2030 - [125] M. Abdel-Kareem, “Quantum Art Extends Series A to $140M to Scale Trapped-Ion Architecture,” Quantum Computing Report, Apr. 27, 2026. [Online]. Available: https://quantumcomputingreport.com/
quantum-art-extends-series-a-to-140m-to-scale-trapped-ion-architecture/ P - [129] A. Cordes, “Quantum computing scale-up eleQtron secures €57 million in one of the largest Series A funding rounds worldwide,” eleQtron, May 5, 2026. [Online]. Available: https://eleqtron.com/
en/ Cquantum-computing-scale-up-eleqtron-secures-57-million-in-one-of-the-largest-series-a-funding-rounds-worldwide/ - [253] I. Pogorelov et al., “Compact Ion-Trap Quantum Computing Demonstrator,” PRX Quantum, vol. 2, no. 2, Art. no. 020343, Jun. 2021, doi: 10.1103/PRXQuantum.2.020343. arXiv:2101.11390. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [320] Infineon Technologies AG, “Trapped ion quantum computing.” [Online]. Available: https://www.infineon.com/
promo/ Ctrapped-ions - [325] M. Malinowski, D. Allcock, and C. Ballance, “How to Wire a 1000-Qubit Trapped-Ion Quantum Computer,” PRX Quantum, vol. 4, no. 4, Art. no. 040313, Oct. 2023, doi: 10.1103/PRXQuantum.4.040313. arXiv:2305.12773. S
- [375] PatSnap, “Trapped Ion Quantum Computing: Technology Landscape 2026,” Apr. 23, 2026. [Online]. Available: https://www.patsnap.com/
resources/ Pblog/ rd-blog/ trapped-ion-quantum-computing-2026-patsnap-eureka/ - [501] T. Rummler, “In the Mountain West, a quantum computing collaboration announces major results,” Sandia Lab News, Aug. 27, 2026. [Online]. Available: https://www.sandia.gov/
labnews/ G2026/ 08/ 27/ in-the-mountain-west-a-quantum-computing-collaboration-announces-major-results/ - [576] SkyWater Technology, “SkyWater Technology Reports Fourth Quarter and Full Fiscal Year 2025 Results,” U.S. Securities and Exchange Commission, Feb. 2026. [Online]. Available: https://www.sec.gov/
Archives/ Gedgar/ data/ 1819974/ 000181997426000005/ skyt-20251228xex991.htm - [584] IonQ, “IonQ and Sandia National Laboratories Sign MOU to Accelerate Quantum Co-Design for National Security Applications,” Aug. 4, 2026. [Online]. Available: https://www.ionq.com/
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Русский текст загружается…
הטקסט בעברית נטען…
Optical / mechanical assembly (lasers, vacuum, objectives)
The laser, ultra-high-vacuum and imaging-optics stack that traps, cools, addresses and reads out both trapped-ion and neutral-atom qubits — infrastructure, not a qubit.
Verdict. Serves two platform families, ions and atoms — the photonic-IC and CMOS foundries serve more — so its vendors are modality-agnostic; supply concentrates in beam steering, two AOD houses, while lasers have a leader (TOPTICA) among six named vendors, and free-space delivery is the wall past ~10⁴ sites.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
The shared laser, ultra-high-vacuum and imaging-optics infrastructure under trapped ions (Quantinuum, AQT, IonQ) and neutral-atom tweezer arrays (Harvard with QuEra, Pasqal, Atom Computing, Infleqtion, Google). It holds no qubit and performs no gate: it supplies cooling and addressing light, vacuum confinement, high-NA objectives and the beam-steering that places atoms. It became a separate discipline with dedicated vendors from about 2016.
Attributes: no carrier, no entangling time, no readout channel and no mobility of its own — the physical layer other nodes ride on.
Manufacturing category optics and mechanical assembly; the error it contributes downstream is coherent — drift, vibration, pointing and frequency noise, not stochastic Pauli noise.
Physics & limits
Laser frequency and intensity noise convert into coherent dephasing on every gate driven by that light. Background-gas pressure sets the atom lifetime — one source of atom loss beside gates and imaging — and in the 448-atom system loss makes up over 80% of all leakage: detectable, therefore erasure-convertible, which turns loss control, the vacuum included, into a code-level asset D[4]. Objective numerical aperture sets tweezer pitch and crosstalk. Beam steering sets rearrangement speed under two limits that pull against each other — a deflector resolves as many spots as its rf bandwidth times the acoustic transit across the beam, and that transit bounds how fast a trap is re-pointed — while liquid-crystal modulators reframe only at tens of hertz. The harder scaling term is power: Rydberg and Raman light is divided among sites, so an array becomes power-limited before it becomes optics-limited. What moves the floor is photonic integration and higher-bandwidth deflectors; neither removes the vacuum or the objective.
Engineering state of the art
Continuous operation is the headline result: two optical-lattice conveyor belts carry atom reservoirs into the science region, atoms are extracted into tweezers at 300,000 per second, and from that flux the system creates over 30,000 initialised qubits per second, enough to hold an array of more than 3,000 atoms for over two hours while stored qubits keep T2 above a second — 1.34 s undisturbed, 1.15 s while the magneto-optical trap loads new atoms, 1.09 s during imaging and sorting D[144]. Both rates are correct and differently scoped. Elsewhere: 11,000 atoms in 18,225 metasurface tweezers with no gates D[145], and 6,100 atoms with 12.6 s coherence D[138]. Pasqal quotes 3 kW average power and 2,500 kg for a room-temperature Orion Gamma rack C[438] — a brochure figure, not an audited one.
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2024-03 | 6,100-atom tweezer array, 12.6 s coherence | Caltech | D[138] |
| 2025-11 | 3 kW average power, 2,500 kg, room temperature | Pasqal Orion Gamma | C[438] |
| 2025-09 | 300,000 atoms/s into tweezers, 30,000 initialised qubits/s, >3,000 atoms held >2 h | Harvard with QuEra | D[144] |
| 2026-06 | 11,000 atoms in 18,225 metasurface tweezers, no gates | Tsinghua | D[145] |
Manufacturing, materials & supply chain
Lasers have a leader, not a monopoly: TOPTICA Photonics (Munich) states EUR 140 M revenue and 600 staff and calls quantum technology its founding market C[815], and is named the principal supplier to ion builders alongside MOGLabs, Menlo Systems, Coherent, Thorlabs and NKT P[322]. Beam steering is where supply concentrates, a duopoly in practice: only two deflector houses appear across the sourced neutral-atom literature — AA Opto-Electronic, whose crossed DTSX-400 AODs sit in the 448-atom system beside a Hamamatsu modulator and camera, Spectrum Instrumentation waveform generators, a Rohde & Schwarz source and a 0.65-NA Special Optics objective D[4], and Gooch & Housego, in the 3,000- and 6,100-atom papers P[504]. Vacuum is more diversified (Pfeiffer, Edwards and Leybold under Atlas Copco, Agilent, Kurt J. Lesker, VACOM) but consolidating, with a Universal Quantum–Atlas Copco MoU in December 2025 P[502]. Export exposure is oblique: the 2024-09-06 BIS rule controls assembled quantum computers under ECCN 4A906 only when qubit count and two-qubit (C-NOT) error fall in the same band — from 34–99 qubits at ≤ 10⁻⁴ to any error at 2,000 qubits and more — and no ECCN names ion traps, atom-array vacuum or tweezer optics G[301]: no quantum-specific entry reaches the subsystems, and a finished machine is caught only inside those bands.
Control, readout & I/O burden
This tier imposes I/O rather than bearing it. Helios needs at least seven wavelengths — its paper names six, from 369 to 1762 nm, and loads both barium and ytterbium by photoionisation — against 1,228 trap electrodes D[97]; a tweezer array needs one deflector order or hologram per addressed site. At 10³ sites, addressing optics and power splitting are already the dominant integration cost; at 10⁴, steering bandwidth and optical power bind; at 10⁶, free-space delivery is not credible — which is why photonic-integrated delivery is the watched path.
Role in the stack
It sits under six architectures — as the primary assembly under alkali and alkaline-earth tweezer arrays and the neutral-atom analogue simulator, and as an alternate under all three trapped-ion architectures (QCCD, the linear Paul trap with laser addressing, electronic gates) — providing lasers and vacuum to ions, tweezers to both atom families, clock lasers to alkaline earths and cavities to the atom–photon link. It requires nothing upstream, replaces nothing and conflicts with nothing: shared in economic terms, invisible in architectural ones. It sets no derived clock but bounds every architecture's through laser-lock, imaging and rearrangement time — imaging alone is 0.5–1 ms of a 1–4.5 ms atom cycle. No empty slot is flagged.
Evidence — how the numbers were measured
Pasqal's power and mass carry a company-claim tag, not a measurement tag C[438]. TOPTICA's revenue and headcount are corroborated by its own page C[815]; "dominant supplier" rests on one secondary source P[322].
Special Optics, maker of the 448-atom system's 0.65-NA objective, is the only objective vendor named in the published literature; none is named for an ion system. Only two AOD vendors appear across the published literature, which does not establish that only two exist.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| TOPTICA Photonics | supplier | Germany | Lasers for ion and atom platforms; EUR 140 M revenue, 600 staff | C[815] |
| AA Opto-Electronic | supplier | France | Crossed DTSX-400 AODs in the 448-atom system | D[4] |
| Gooch & Housego | supplier | UK | Deflectors in the 3,000- and 6,100-atom papers | P[504] |
| Atlas Copco (Edwards, Leybold) | supplier | Sweden | MoU to industrialise high-vacuum systems | P[502] |
| Pasqal | user | France | Orion Gamma rack: 3 kW, 2,500 kg, room temperature | C[438] |
| Harvard with QuEra | user | US | Conveyor reload holding >3,000 atoms >2 h | D[144] |
| Quantinuum | user | US-UK | Helios: ≥7 wavelengths over 1,228 electrodes | D[97] |
Money.
- 2022-11-02 · Universal Quantum · government contract · EUR 67 M · DLR · closed P[328]
- 2023-12-05 · Alpine Quantum Technologies · system sale to Leibniz Supercomputing Centre · ≈EUR 9.8 M for 20 qubits · closed C[323]
- 2026-06 · Atom Computing · equity plus CHIPS letter of intent · >USD 300 M incl. USD 100 M LOI · closed C[154]
- 2026-08-28 · Pasqal · SPAC completion · ~USD 360 M cash, EUR 16.5 M 2025 revenue · closed P[156]
Market & supply chain. It serves two platform families, ions and atoms, so its vendors are indifferent to which wins. Unit economics differ about 7.5-fold between the two ends: QuNorth ordered the 1,225-physical, 50-logical Magne system from Atom Computing and Microsoft for EUR 80 M, ~EUR 65 k per atom P[12], while AQT delivered 20 trapped ions for EUR 9.8 M, ~EUR 0.5 M per ion C[323]. Tweezer optics amortise across thousands of sites; ion optics scale closer to per-ion. All of G1–G7 pays for this tier.
IP & standards. No dated patent-family fact specific to laser, vacuum or objective IP was found as of 2026-09-04. No standards body covers this tier; vacuum-flange, laser-safety and optical-mount standards predate quantum computing — the components are commodity, the integration is not.
Roadmaps & track record. Universal Quantum (promised 2022-11 · two computers for DLR within four years, so by 2026-11 · no delivery announced as of 2026-09-30) P[328] — at risk, not yet overdue. Pasqal (promised 2024-03 · 10,000 physical in 2026 · slipped to 2028) R[166]. QuEra (promised 2024-01 · 100 logical in 2026 · replaced by Libra in 2028) R[162]. The supplier side publishes no checkable roadmap.
Strategic reading. Suppliers here hold bargaining power no carrier- or gate-specific vendor has: a bet on TOPTICA or Atlas Copco is a bet on both ions and atoms. The threat is not a competitor but a change of form factor — if photonic-integrated delivery arrives, value migrates to PIC foundries and the AOD duopoly is the exposed link. Builders integrating optics in-house trade cost for control; outsourcers trade control for a supplier's industrialisation budget.
Outlook & open questions
Falsifiable in 12–24 months: confirm/demote that Universal Quantum and Atlas Copco ship a vacuum system past MoU stage; that a second laser vendor is named in a production ion system; that any free-space array rearranges beyond ~10⁴ sites at the pace of error correction. Best case by 2029: photonic-integrated delivery removes pointing sensitivity and per-site optics cost falls. Worst case: supply stays concentrated and this tier's coherent error stays the dominant infidelity term. Open: does anyone displace TOPTICA; does an objective vendor beyond Special Optics appear in the literature; does the ion-versus-atom unit-cost gap persist.
References
- [4] D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature, vol. 649, no. 8095, pp. 39–46, Nov. 2025, doi: 10.1038/s41586-025-09848-5. arXiv:2506.20661. D
- [12] M. Abdel-Kareem, “Denmark's QuNorth to Acquire 50-Logical-Qubit Magne Quantum Computer from Atom Computing and Microsoft,” Quantum Computing Report, Jul. 17, 2025. [Online]. Available: https://quantumcomputingreport.com/
denmarks-qunorth-to-acquire-50-logical-qubit-magne-quantum-computer-from-atom-computing-and-microsoft/ P - [97] A. Ransford et al., “A 98-qubit trapped-ion quantum computer with all-to-all connectivity,” Nature, vol. 655, no. 8121, pp. 81–86, Jun. 2026, doi: 10.1038/s41586-026-10676-4. arXiv:2511.05465. D
- [138] H. J. Manetsch, G. Nomura, E. Bataille, K. H. Leung, X. Lv, and M. Endres, “A tweezer array with 6100 highly coherent atomic qubits,” Nature, vol. 647, pp. 60–67, 2025, doi: 10.1038/s41586-025-09641-4. arXiv:2403.12021. D
- [144] N.-C. Chiu et al., “Continuous operation of a coherent 3,000-qubit system,” Nature, vol. 646, no. 8087, pp. 1075–1080, Sep. 2025, doi: 10.1038/s41586-025-09596-6. D
- [145] Y. Wang et al., “Trapping 11,000 Atoms in a Tweezer Array Generated by a Single Metasurface,” arXiv:2606.02715, Jun. 2026. D
- [154] Atom Computing, “Atom Computing Raises More Than $300 Million to Accelerate Deployment of Fault-Tolerant, Neutral-Atom Quantum Computers,” PR Newswire, Jun. 16, 2026. [Online]. Available: https://www.prnewswire.com/
news-releases/ Catom-computing-raises-more-than-300-million-to-accelerate-deployment-of-fault-tolerant-neutral-atom-quantum-computers-302800832.html - [156] M. Swayne, “Pasqal Completes SPAC Merger With $360 Million in Cash,” The Quantum Insider, Aug. 28, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P08/ 28/ pasqal-completes-spac-merger-with-360-million-in-cash/ - [162] QuEra Computing, “QuEra Announces 2028 Fault-Tolerant Quantum Computer and Expanded Multi-Year Strategic Collaboration with AWS,” Jun. 15, 2026. [Online]. Available: https://www.quera.com/
press-releases/ Rquera-announces-2028-fault-tolerant-quantum-computer-and-expanded-multi-year-strategic-collaboration-with-aws - [166] Pasqal, “Pasqal Releases 2025 Roadmap Showcasing Upgradable Platform from Today's Quantum Solutions to Tomorrow's Fault-Tolerant Systems,” Jun. 12, 2025. [Online]. Available: https://www.pasqal.com/
newsroom/ Rpasqal-releases-2025-roadmap/ - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [322] M. Ivezic, “The Optical Table's Hidden Supply Chain: Who Really Wins If Trapped-Ion Quantum Computing Wins,” PostQuantum.com, Oct. 1, 2025. [Online]. Available: https://postquantum.com/
quantum-ecosystem/ Ptrapped-ion-quantum-ecosystem/ - [323] AQT, “AQT lands million euro contract,” Dec. 5, 2023. [Online]. Available: https://www.aqt.eu/
aqt-lands-million-euro-contract/ C - [328] A. Ingall, “German government tasks Sussex spin-out with building a powerful quantum computer in €67M contract,” University of Sussex Broadcast, Nov. 2, 2022. [Online]. Available: https://www.sussex.ac.uk/
broadcast/ Pread/ 59206 - [438] Pasqal and O. Q.-C. P. brochure, “The Power of Neutral Atom Quantum Processors by Pasqal — Unlock Quantum Computing for Real-World Solutions,” Pasqal, product brochure (PDF). [Online]. Available: https://www.pasqal.com/
wp-content/ Cuploads/ 2025/ 11/ 2509_Pasqal_Quantum-Computing-Processor_Brochure-RVB-V8.pdf - [502] M. Abdel-Kareem, “Universal Quantum and Atlas Copco Partner to Industrialize Vacuum Systems for Scalable Quantum Computers,” Quantum Computing Report, Dec. 18, 2025. [Online]. Available: https://quantumcomputingreport.com/
universal-quantum-and-atlas-copco-partner-to-industrialize-vacuum-systems-for-scalable-quantum-computers/ P - [504] Gooch & Housego (G&H), “G&H Acousto-Optic Deflectors Referenced in Nature Papers Demonstrating 3,000 & 6,100 Qubit Quantum Systems,” G&H, Mar. 2026. [Online]. Available: https://gandh.com/
news-and-resources/ Pg-and-h-acousto-optic-deflectors-in-nature-papers - [815] TOPTICA Photonics, “About the TOPTICA Group.” [Online]. Available: https://www.toptica.com/
company C
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הטקסט בעברית נטען…
3D machined superconducting cavities
CNC-machined aluminium or niobium resonator bodies with internal Q above 0.5×10⁹; the cm-scale body per mode is the structural cost of cavity-based bosonic codes.
Verdict. The process buys the best error structure in superconducting hardware and pays for it in volume; no vendor has published a yield, cost or density roadmap as of 2026-09-04.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Precision-machined bulk metal bodies — λ/2 or λ/4 coaxial-stub and waveguide geometries in high-purity aluminium or niobium — that host the bosonic mode. Yale's 2013 aluminium cavities reached Q > 0.5×10⁹ and a 10 ms photon lifetime, making the process qubit-grade D[318]. A manufacturing step, not an operating device: no control modality, readout or gate time. It fixes photon loss in the mode it hosts.
Physics & limits
The advantage is geometric: the field lives in vacuum rather than at a lithographed metal–dielectric interface, so the surface participation ratio — and the two-level-system loss that caps planar resonators — falls by orders of magnitude D[318]. What remains is surface oxide, seam conductance and radiative leakage, answered by electropolishing, indium seals and individual tuning. Those are craft steps, which is why the floor moves slowly in cavities built for qubit experiments: 10 ms photon lifetime in 2013, 25.6 ms with 34 ms coherence in 2023 — a factor of 2.6 in lifetime in a decade D[318]D[319]. Accelerator technology shows how low the floor can go: Fermilab's niobium cavities, their niobium-oxide two-level-system loss suppressed by vacuum heat treatment at 340–450 °C, kept photons for 0.5–2 s at about 10 mK, measured down to a few photons — bare, with no qubit or ancilla attached Dfact. Carrying that into a qubit memory needs surface treatment and seamless geometry, plus decoupling the mode from its ancilla D[319].
Engineering state of the art
table
| Date | Figure | Who | Tag |
|---|---|---|---|
| 2013 | Machined aluminium cavity, Q > 0.5×10⁹, photon lifetime 10 ms | Yale | D[318] |
| 2020-03 | Niobium accelerator cavities, no qubit attached: photon lifetime 0.5–2 s at ~10 mK | Fermilab | Dfact |
| 2023-09 | Cavity qubit: T1 25.6 ms, T2 34 ms | Weizmann Institute | D[319] |
| 2026-08 | Paired λ/4 coaxial bodies for dual-rail qubits | Quantum Circuits | D[84] |
The limiting figure is volume, not Q: no per-body yield, cost or tuning-time number has been published.
The 34 ms figure is the Weizmann Institute's (T1 25.6 ms, T2 34 ms), not a Yale-lineage group's. The 2013 Q > 0.5×10⁹ has been exceeded independently — Fermilab's niobium accelerator cavities kept photons for 0.5–2 s at about 10 mK, with no qubit or ancilla attached fact — but the 2023 cavity-qubit lifetime has no independent replication. AWS [80] uses no machined body. Not published: whether the Weizmann cavity is niobium-coated; a per-body yield, tuning time or cost, from any vendor; which package components JPL fabricated, or any role in cavity-body machining [281]; and how Nord Quantique makes its high-purity aluminium double-post cavity body [82].
Manufacturing, materials & supply chain
Bodies are CNC-machined (computer numerical control) or EDM-machined from high-purity stock, polished, sealed and tuned one at a time. The binding constraint is cryostat volume, not wafer area — the inverse of a planar roadmap. Nothing is integrated on chip, so each mode carries its own coax to room temperature; at 10³ modes the wall is coax count and cold-plate area, and 10⁴–10⁶ is out of reach. The two cat-qubit vendors build planar: AWS's Ocelot holds its bosonic modes in coplanar-waveguide resonators on two bump-bonded dies D[80], and Alice & Bob's chips are tantalum-on-sapphire circuits, Boson 3's memory a quarter-wave coplanar resonator fact; Nord Quantique's GKP mode stays in a double-post cavity of high-purity aluminium D[82]. Machining is in-house at every vendor, with no third-party cavity foundry found; the one named external supplier nearby, NASA's Jet Propulsion Laboratory, fabricated key components of D-Wave's cryogenic-control multi-chip package, not bodies C[281]. Refrigerators concentrate on Bluefors, which also owns Cryomech fact. No export rule specific to cavity bodies was found; exposure runs through general machine-tool controls.
Role in the stack
Provides the bodies for the bosonic cavity mode and hence cat and GKP encodings, dual-rail erasure and ancilla-mediated gates. It replaces planar lithography and conflicts with dense 2D tiling: cm-scale bodies cannot follow transmons to 10⁴–10⁶ on a die. It contributes nothing to the derived clock — 1.44 µs derived against a measured 2.8 µs on the cat architecture, 2.8 µs derived against ~2 µs measured on dual-rail — setting lifetime, not timing. The adjacent empty slot is a batch or wafer-scale bosonic-mode process. Verification: the 2023 lifetime is a single-group result; the 2013 Q has since been exceeded independently, by Fermilab's niobium cavities with no ancilla attached Dfact; the 2026 λ/4 bodies report cavity lifetimes of 231–652 µs, a Q of 1–3×10⁷ D[84].
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| Nord Quantique | developer | CA | GKP qubit in a double-post cavity of high-purity aluminium | D[82] |
| D-Wave | developer | US | New Haven bench builds paired λ/4 coaxial cavities for dual-rail qubits; material and machining not published | D[84] |
| NASA JPL | supplier | US | Fabricated key components of D-Wave's cryogenic-control multi-chip package | C[281] |
| Bluefors | supplier | FI | Dilution refrigerators, the volume these bodies compete for | fact |
Money.
2026-01-20 · D-Wave · M&A of Quantum Circuits · $550 M · — · closed fact
2026-01-06 · D-Wave · on-chip cryogenic control, key package components fabricated at JPL · — · announced C[281]
2026-08-06 · D-Wave · Q2 report · H1 bookings $35.5 M, obligations $40.7 M · reported fact
Market & supply chain. There is no cavity-machining market: each vendor runs a small internal shop, which is the single point of failure. Bargaining power sits with the fridge makers. G1 and G3 pay; G4 does not.
IP & standards. No dated patent family specific to the machining process was found, and no standard covers cavity qualification.
Roadmaps & track record. No cavity density or cost roadmap exists. D-Wave's DR17 → DR49 → DR181 ladder implies rising body counts with no fabrication plan Rfact, silent where an ASIC roadmap would be explicit.
Strategic reading. This process is why bosonic error structure is good and bosonic density is bad; it becomes a liability the moment planar dual-rail or on-chip GKP match its erasure fractions.
Outlook & open questions
Confirm by 2028 if a vendor publishes a per-body yield figure or a sub-cm body at comparable Q; demote if the bench stays silent while planar erasure qubits scale. Best case 2029: batch-fabricated cavity arrays. Worst case: hand-machined bodies indefinitely, capping the branch near 10² modes. Open: does seamless machining raise Q; what is the real cost per mode? Watch D-Wave's DR49 and whether Nord Quantique goes beyond one cavity mode.
References
- [80] H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature, vol. 638, no. 8052, pp. 927–934, Feb. 2025, doi: 10.1038/s41586-025-08642-7. D
- [82] S. Turcotte et al., “Quantum error correction of a grid-state qubit with state preparation and measurement errors below 10⁻³,” arXiv:2607.06718, Jul. 2026. D
- [84] N. Mehta et al., “An entangling gate for dual-rail erasure qubits,” Nature, vol. 656, no. 8126, pp. 47–53, Aug. 2026, doi: 10.1038/s41586-026-10822-y. arXiv:2503.10935. D
- [281] D-Wave, “D-Wave Demonstrates First Scalable, On-Chip Cryogenic Control of Gate-Model Qubits,” Jan. 6, 2026. [Online]. Available: https://www.dwavequantum.com/
company/ Cnewsroom/ press-release/ d-wave-demonstrates-first-scalable-on-chip-cryogenic-control-of-gate-model-qubits/ - [318] M. Reagor et al., “Reaching 10 ms single photon lifetimes for superconducting aluminum cavities,” arXiv:1302.4408, Feb. 2013. D
- [319] O. Milul et al., “Superconducting Cavity Qubit with Tens of Milliseconds Single-Photon Coherence Time,” PRX Quantum, vol. 4, no. 3, Art. no. 030336, Sep. 2023, doi: 10.1103/PRXQuantum.4.030336. D
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Bulk-optics and fibre assembly (photonic samplers)
Photonic processors assembled from discrete parts — free-space squeezers and interferometers, fibre delay loops, fibre-coupled modulators and cryogenic single-photon detectors — aligned and locked by hand and servo rather than patterned on a wafer.
Verdict. The lowest-loss way to buy delay and squeezing, and how every beyond-classical photonic sampler, Jiuzhang 1.0 (2020) to Jiuzhang 4.0 (2026), was built; as of 2026-09-26 no published fault-tolerant photonic design assembles its processor this way, and only fibre delays and links carry over to the chip machines.
OPO = optical parametric oscillator; (PP)KTP = (periodically poled) potassium titanyl phosphate; EOM = electro-optic modulator; MZI = Mach–Zehnder interferometer; SNSPD = superconducting nanowire single-photon detector; TES = transition-edge sensor; PIC = photonic integrated circuit; ECCN = US Export Control Classification Number; USTC = University of Science and Technology of China; G1–G7 = the report's goal classes (G1: analogue and NISQ simulation).
Identity & lineage
Crystals in free-space cavities squeeze light, beamsplitters or fibre couplers interfere it, fibre spools delay it, fibre-coupled cryogenic detectors count it. Jiuzhang 1.0 fed 50 squeezed states into a 100-mode "ultralow-loss" interferometer, the whole set-up phase-locked D[460]; Borealis moved interference into time, with fibre loops of 1, 6 and 36 bins at a 6 MHz clock D[270]; Jiuzhang 4.0 joins three 16-mode interferometers through two arrays of 16 fibre delays D[175]. ORCA sells racks of "telecoms-grade optical fibre components" at room temperature C[464]. Attributes: carrier affinity 0.25 (hosts modes, not qubits); no characteristic time, readout, mobility or control modality of its own; loss error; optics manufacturing.
Physics & limits
Fibre is nearly free per metre: ≤0.18 dB/km at 1550 nm, group index 1.4682 G[816]. Borealis's 36-bin loop (6.0 µs, ≈1.2 km) thus costs ≈0.22 dB in the glass, Jiuzhang 4.0's longest delay (12 µs, ≈2.4 km) ≈0.44 dB S[175], [270]; foundry silicon nitride at 0.5–1.8 dB/m would charge ~600–2,200 dB for 1.2 km S[169]. Delay stays in fibre; loss sits at transitions and active parts. Loss also caps squeezing: at transmission η the measured quadrature variance η·e^(−2r) + (1 − η) cannot fall below 1 − η — a 16.0 dB ceiling at η = 0.975, the efficiency behind the 15 dB record from a free-space PPKTP cavity D[344], but 1.7 dB at Borealis's ~33% S[270]. Phase is the second limit: Borealis's residual loop phase noise grows with length — 0.02, 0.03 and 0.15 rad for loops 0–2 D[270]. Assembly has no scaling term — each element is placed, coupled and locked singly — while Xanadu reckons fault tolerance would take a 20–30× cut, in decibels, in every component's insertion loss S[173].
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2016-09-06 | 15 dB squeezing observed; 9.3 mm PPKTP half-monolithic cavity; total detection efficiency 0.975 | Vahlbruch et al., AEI Hannover | D[344] |
| 2020-11-23 | Fibre-coupled SNSPD, system detection efficiency 98.0 ± 0.5% at 1550 nm | NIST | D[618] |
| 2020-12-18 | 50 squeezed states, 100 modes, 100 detectors, set-up phase-locked | USTC, Jiuzhang 1.0 | D[460] |
| 2022-06-01 | 216 modes from three fibre loops; 16 TES at 95%; net transmittance ~33%; 10 kHz | Xanadu, Borealis | D[270] |
| 2025-01-22 | Chip machine linked by stabilised fibre delay modules; ~14 dB loss | Xanadu, Aurora | D[173] |
| 2026-05-13 | 8,176 modes; source 92%, system 51%, 16 SNSPDs at 93%; phase held to ~λ/200 | USTC, Jiuzhang 4.0 | D[175] |
With Jiuzhang 4.0's source (92%) and detectors (93%) near unity, the ~40% (≈2.2 dB) lost between them sits in filters, meshes, delays and couplings S[175]; its filter stage of three unbalanced MZIs transmits 99.8% D[175]. Borealis loses ~20% in its filter stack and ~15% in its demultiplexer D[270]. Dominant term: transitions and switching, not propagation.
Manufacturing, materials & supply chain
Borealis's squeezer is a 10 mm KTP crystal in an OPO pumped at 775 nm; its loop beamsplitters are custom EOMs from QUBIG GmbH; its TES detectors reach 95%, with NIST Boulder's Lita, Gerrits and Nam among the authors D[270]. SNSPD supply is a handful of firms: Single Quantum (Netherlands) reported its 400th SNSPD system in July 2026 P[621]; Photon Spot (US) quotes ">90% quantum efficiency near 1550nm" C[630]; ID Quantique passed to IonQ, a computer maker, through a controlling stake C[633]. ORCA's PT-2 page names a Eurostars-funded collaboration with Pixel Photonics (detectors), Sparrow Quantum and the Niels Bohr Institute (sources) C[465]. The US rule of 2024-09-06 defines 4A906 quantum computers by ≥34 physical qubits and C-NOT error and names no single-photon detector, squeezer or photonic item G[301]; a sampler, with neither, is not obviously covered S[301].
Control, readout & I/O burden
The load is servo, not gates. Borealis locks each loop with a counter-propagating laser, piezos and lock-in detection, re-locking for 35 µs of every 100 µs — hence 10 kHz D[270]; Jiuzhang 4.0 sets delay phases with fast piezo stretchers and its meshes thermally D[175]. The electro-optic load (ct_eo) is small: three EOM-driven loop beamsplitters and a 1-to-16 demultiplexer of 15 EOMs, extinction above 200:1 D[270]. Time multiplexing is the one scaling lever: 16 detectors read 216 or 8,176 modes, and Jiuzhang 4.0's 43 ns SNSPD recovery sets its 50 ns bin D[175], [270]. Only detectors are cryogenic.
Role in the stack
Manufacturing slot of the Boson sampler architecture (ph_sampler, G1), shared with fab_pic. It requires ct_eo — fibre-coupled modulators and delay loops; it provides no edge; it replaces nothing, while fab_pic replaces it (photonic foundry vs bulk-optics assembly). The replacement is partial: Aurora moved squeezing and interference onto chips yet links them with fibre delay modules D[173]. This answers gap G-bulkoptics — the record samplers were built neither in a 300 mm PIC foundry nor with fab_optics's ion and atom optics; the Atlas added this technology rather than extend fab_optics to ph_cv and ph_fusion, whose processors are lithographed D[169], [173]. The register lists seven carriers, seven of them primary: Borealis (Xanadu, deployed 2022-06), Jiuzhang 1.0, 2.0 and 3.0 (USTC, demonstrated 2020–2023, now retired), Jiuzhang 4.0 (USTC, demonstrated 2026-05-13), PT-1 (ORCA, deployed 2023) and PT-2 (ORCA, deployed 2024–2026).
Evidence — how the numbers were measured
Three cells are ✅. Two rest on architecture papers: Borealis's Methods (fibre delay lines, EOM beamsplitters, fibre coupling above 97%) D[270] and Jiuzhang 4.0's Extended Data Fig. 1 (free-space unbalanced MZI on a PZT-mounted mirror), whose text confirms fibre delay loops but says only that the 16-mode interferometers "incorporate thermal tunability" D[175]; PT-1's rests on ORCA's product page, "rack-mounted, room temperature and built with optical fibre components" Cfact. PT-2 stays 🔎: its page gives no architecture C[465], and the fibre reading rests on ORCA's technology page C[464]. Jiuzhang 1.0–3.0 stay 🔎 too: their cells are inferred from the lineage, not read from a figure. As of 2026-09-26 no sampler has published an assembly yield, a per-element loss distribution or a realignment interval.
Jiuzhang 4.0's 99.8% may be per filter MZI or for the cascade; its arXiv v3 does not say which. No entry in the 2024-09-06 US rule names SNSPDs, TES or squeezers. Not published: Borealis's per-loop transmission — its Nature text gives only ~33% net, ~20% filter stack, ~15% demultiplexer and fibre coupling above 97% — so no dB-per-loop figure is given; the SNSPD maker for Jiuzhang 4.0; and the completion of ORCA's purchase of GXC, or any PT product using GXC technology.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| USTC | developer | CN | Jiuzhang: free-space filters, fibre delay arrays, SNSPD readout | D[175] |
| Xanadu | developer | CA | Borealis fibre loops; fibre delay modules kept in Aurora | D[173], [270] |
| ORCA Computing | developer | UK | PT racks of telecom fibre parts; bought GXC's integrated photonics division | C[464]P[817] |
| NIST Boulder | research | US | Borealis TES; 98% SNSPD | D[270], [618] |
| QUBIG GmbH | supplier | DE | Custom EOMs in Borealis's loops | D[270] |
| Single Quantum; Photon Spot; ID Quantique | suppliers | NL; US; CH | SNSPD systems | P[621]C[630]C[633] |
Money.
- 2024-01-30 · ORCA Computing · acquisition of GXC's integrated photonics division, Austin, Texas · undisclosed · announced P[817]
- 2025-05-06 · IonQ · controlling stake in ID Quantique · undisclosed in the release · closed C[633]
Market & supply chain. Of the seven carriers only ORCA's PT-1 and PT-2 are sold as systems; USTC is academic, though Jiuzhang 4.0 lists Jiuzhang Quantum Technology Co. Ltd. among its affiliations D[175]; Borealis was offered through the cloud rather than sold, and the register lists it as deployed, its roadmap field noting that Aurora superseded it. Scarce inputs: number-resolving detectors, low-loss squeezers. Pays into G1 only.
IP & standards. No assembly-specific patent count or standard found as of 2026-09-26.
Roadmaps & track record. USTC went from 100 to 8,176 modes in 2020–2026 by multiplexing, not by adding parts D[175], [460]; Xanadu left assembly within three years of Borealis, keeping the fibre D[173]; ORCA framed GXC as a step toward "scalable, fault-tolerant quantum computing" P[817], with no PT product on it published as of 2026-09-26.
Strategic reading. Assembly wins where the figure of merit is one machine's transmission on the day; fault tolerance needs that loss replicated with statistics, which only lithography offers — so the sampler architecture ends here while the CV and fusion architectures moved to PICs. Durable value sits with suppliers of fibre delays, squeezers and detectors, which chip machines still buy.
Outlook & open questions
Confirm if, by 2027-12-31, an assembled sampler beats Jiuzhang 4.0's 51% end-to-end efficiency at ≥8,000 modes, or ORCA publishes PT loop count and loss; demote if the next Jiuzhang or PT-3 puts its interferometers on a chip, leaving the technology only delays and detectors. Open questions. (1) What is each Borealis loop's round-trip transmission? (2) Are Jiuzhang 4.0's 16-mode interferometers bulk, fibre or integrated? (3) How often must a loop sampler be realigned, at what cost in uptime? (4) Can on-chip delay approach fibre's ~0.2 dB/km, or will every photonic computer keep fibre spools? (5) Does any export-control entry beyond the 2024 US quantum ECCNs capture SNSPD or TES systems?
References
- [169] K. Alexander et al., “A manufacturable platform for photonic quantum computing,” Nature, vol. 641, no. 8064, pp. 876–883, Feb. 2025, doi: 10.1038/s41586-025-08820-7. D
- [173] H. A. Rad et al., “Scaling and networking a modular photonic quantum computer,” Nature, vol. 638, no. 8052, pp. 912–919, Jan. 2025, doi: 10.1038/s41586-024-08406-9. D
- [175] H.-L. Liu et al., “Gaussian boson sampling with 1,024 squeezed states in 8,176 modes,” Nature, vol. 653, no. 8115, pp. 687–692, May 2026, doi: 10.1038/s41586-026-10523-6. arXiv:2508.09092. D
- [270] L. S. Madsen et al., “Quantum computational advantage with a programmable photonic processor,” Nature, vol. 606, no. 7912, pp. 75–81, Jun. 2022, doi: 10.1038/s41586-022-04725-x. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [344] H. Vahlbruch, M. Mehmet, K. Danzmann, and R. Schnabel, “Detection of 15 dB Squeezed States of Light and their Application for the Absolute Calibration of Photoelectric Quantum Efficiency,” Phys. Rev. Lett., vol. 117, no. 11, Art. no. 110801, Sep. 2016, doi: 10.1103/PhysRevLett.117.110801. D
- [460] H.-S. Zhong et al., “Quantum computational advantage using photons,” Science, vol. 370, no. 6523, pp. 1460–1463, Dec. 2020, doi: 10.1126/science.abe8770. arXiv:2012.01625. D
- [464] ORCA Computing, “Technology — ORCA Computing.” [Online]. Available: https://orcacomputing.com/
technology/ C - [465] ORCA Computing, “ORCA PT-2 — ORCA Computing.” [Online]. Available: https://orcacomputing.com/
orca-pt-2/ C - [618] D. V. Reddy, R. R. Nerem, S. W. Nam, R. P. Mirin, and V. B. Verma, “Superconducting nanowire single-photon detectors with 98% system detection efficiency at 1550 nm,” Optica, vol. 7, no. 12, p. 1649, Dec. 2020, doi: 10.1364/OPTICA.400751. D
- [621] TipRanks, “Single Quantum Hits 400-System Milestone as It Deepens European Quantum Partnerships,” Jul. 4, 2026. [Online]. Available: https://www.tipranks.com/
news/ Pprivate-companies/ single-quantum-hits-400-system-milestone-as-it-deepens-european-quantum-partnerships - [630] Photon Spot, “Photon Spot — Cryogenic & Quantum Detection Systems.” [Online]. Available: https://www.photonspot.com/ C
- [633] IonQ, “IonQ Completes Acquisition of ID Quantique, Cementing Leadership in Quantum Networking and Secure Communications,” May 6, 2025. [Online]. Available: https://investors.ionq.com/
news/ Cnews-details/ 2025/ IonQ-Completes-Acquisition-of-ID-Quantique-Cementing-Leadership-in-Quantum-Networking-and-Secure-Communications/ default.aspx - [816] Corning Incorporated, “Corning® SMF-28® Ultra Optical Fiber — Product Information (PI-1424-AEN),” Jul. 2025. [Online]. Available: https://www.corning.com/
media/ Gworldwide/ coc/ documents/ Fiber/ product-information-sheets/ PI-1424-AEN.pdf - [817] Tech.eu, “ORCA Computing acquires GXC's integrated photonics division,” Jan. 30, 2024. [Online]. Available: https://tech.eu/
2024/ P01/ 30/ orca-computing-acquires-gxcs-integrated-photonics-division/
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III-V MBE heterostructures (InAs–Pb wires, QD sources)
Molecular beam epitaxy of III-V nanostructures with vacuum-unbroken superconductor shells for Majorana wires, and of quantum dots for single-photon sources.
Verdict. The process works and is single-source; falsified as a reproducible platform unless a group outside Microsoft publishes an independently grown InAs–Pb device with comparable parity signatures by 2028.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Two unrelated devices share a tool class. The first is a III-V nanowire or 2DEG (two-dimensional electron gas) grown by molecular beam epitaxy (MBE) with a superconductor deposited in the same vacuum, so the interface is never exposed: aluminium through 2025, lead in the 2026 tetron as the higher-gap shell D[21]. The second is GaAs-based quantum dots as single-photon sources, same reactors, different physics fact. The lineage dates to 2015, when Copenhagen grew aluminium epitaxially on InAs nanowires without breaking vacuum Dfact; the field's 2018 headline, quantised Majorana conductance in InSb–Al wires, was retracted on 2021-03-08 D[365].
a mostly fabricated (0.75) · b a process, not a clock · c none · d none
e none · f disorder-dominated · g molecular beam epitaxy
Physics & limits
The floor is disorder. Unintentional doping, interface roughness and shell strain produce trivial sub-gap Andreev states whose signatures mimic Majorana zero modes (MZMs), which is the Nature dispute: Legg argues the regions used for parity readout are disordered and gapless D[22]. Lead raises the gaps above aluminium's: in Microsoft's tetron stack the lead film's own gap is ≈1.3 meV and the gap it induces in the wire ≈570 µeV, against 295 µeV and 129 µeV with aluminium, while the topological gap, taken at the top quintile of its measured values, only doubles, from ~30 to ~70 µeV D[21], fact; epitaxial Pb on InAs nanowires holds a hard 1.25 meV gap to 8.5 T (Copenhagen, 2021) Dfact. Moving the floor means a mean free path well above the coherence length, verified by a published mobility or disorder metric rather than device outcomes. Microsoft published such metrics for InAs–Al — mobility 60,000–100,000 cm²/V·s, a charged-defect density of 2.7 × 10¹² cm⁻² Dfact — and for the Pb stack only Hall-bar values of its active region, a surface charge density of ≈2 × 10¹² cm⁻² and a buried-well mobility above 350,000 cm²/V·s D[21]; none is measured on a device, which is why the materials argument runs through transport data.
Engineering state of the art
table
| Year | Figure | Who | Tag+key |
|---|---|---|---|
| 2018 | Quantised-conductance Majorana claim in InSb–Al wires; retracted 2021-03-08 | Delft (Kouwenhoven et al.) | D[365] |
| 2025-02 | InAs–Al stack supports 1% parity assignment error | Microsoft Azure Quantum | D[13] |
| 2026-06 | InAs–Pb stack, higher-gap shell, ~20 s parity switching, one wire | Microsoft Quantum | D[21] |
No yield or uniformity figure is published for either stack, and the Pb one's disorder figures come from Hall bars, not devices; the only public scaling aid is an rf method resolving wire-end-state splitting to µeV for per-device bring-up D[21].
For InAs–Al, Microsoft published an induced gap of 129 µeV, topological gaps of 20–60 µeV, a mobility and a charged-defect density (Physical Review B, 2023) fact, from a gap protocol whose reading Legg disputes D[22]; for the InAs–Pb stack the tetron paper gives the lead film's gap (≈1.3 meV), the induced gap (≈570 µeV), a top-quintile topological gap (~70 µeV) and Hall-bar charge density and mobility [21]. ECCN 3C907 covers only silicon or germanium with an isotopic impurity below 0.08% G[301]; whether a given III-V stack falls under 3C001.d depends on its layers and doping, and no BIS ruling addresses it. Not published: a yield metric for either stack, and a dated revenue or market-share figure for merchant MBE tool vendors.
Manufacturing, materials & supply chain
Growth needs a III-V MBE reactor under ultra-high vacuum with in-situ superconductor deposition, keeping the interface clean enough for a hard gap. Microsoft's recipe is in-house, and since 2025-11-13 the full Majorana chip core is fabricated at Lyngby in Denmark Pfact; nobody outside has grown an equivalent stack, so one recipe in one building is the architecture's single point of failure D[22]. An independent III-V base exists for another geometry: Eindhoven-grown InSb wires carry QuTech's Kitaev devices D[216]. Export exposure predates the quantum rules: MBE growth equipment has long been on the Wassenaar dual-use list (US Export Control Classification Number 3B001.a.3), and a III-V hetero-epitaxial wafer falls, if anywhere, under 3C001.d fact; the BIS rule of 2024-09-06 added 3C907 only for epitaxial layers of isotopically enriched silicon or germanium, which leaves an InAs–Pb stack outside it G[301]P[818].
Role in the stack
Everything in the topological architecture stands on this stack: encoding, readout and the unbuilt gate inherit its disorder. It provides no clock and no fidelity, only the ceiling on everyone else's; its one load-bearing fact is negative: no independent replication D[22]. The same tool class supplies quantum-dot single-photon sources to the fusion-based photonic architecture fact. The register lists four machines using it, among them Lucy, Belenos, Majorana 1 and Majorana 2. Verification here is materials verification and does not exist: the Nature exchange of 2026-06-24 disputes transport data from one laboratory's wafers, Microsoft conceding nothing D[22]; no second laboratory has grown the planar Pb stack, though Copenhagen put epitaxial Pb on InAs nanowires in 2021 Dfact.
Actors & economics
Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Grows and consumes the InAs–Pb stack; fab in Lyngby | Pfact |
| DARPA | investor | US | Funds both users: US2QC final stage, QBIT Stage A | fact |
Money. 2025-02-06 · Microsoft · US2QC enters its final stage · undisclosed · DARPA · announced fact. 2025-11-13 · Microsoft · Lyngby (DK) Majorana chip-core fab · >DKK 1 bn national total, Microsoft's outlay undisclosed · announced Pfact. 2026-06-16 · Quandela · DARPA QBIT Stage A selection · announced fact.
Market & supply chain. MBE reactors are a small merchant market, but the tool is not the bottleneck: the recipe is, and it is not for sale. G3/G4 pay for the wires, G6 for the photon sources.
IP & standards. No dated patent count specific to this process as of 4 Sep 2026; no standard covers these interfaces.
Roadmaps & track record. (three wire generations, InSb–Al 2018 → InAs–Al 2025 → InAs–Pb 2026, promised as the base for fault tolerance by 2029; status 4 Sep 2026: materials delivered, no yield metric published) C[215]. Lyngby opened as announced; the retracted 2018 result is why outsiders discount later ones.
Strategic reading. While the recipe stays secret every claim above it is unfalsifiable from outside; independent replication either way is worth more than another Microsoft device. Success means a stack nobody can second-source; failure moves value to the InSb base.
Outlook & open questions
Falsifiable in 12–24 months: an outside lab publishing an independently grown planar InAs–Pb device with parity readout; a published yield, or a disorder metric measured on Microsoft's Pb devices rather than Hall bars. Confirm on the first; without it the dispute is unresolvable. Best case, an academic group reproduces the stack; worst case, the recipe stays proprietary and the architecture unauditable to 2029. Open: the spread of topological gaps behind the top-quintile ~70 µeV; yield per wafer; whether anyone outside Microsoft grows the planar Pb stack.
References
- [13] Microsoft Azure Quantum, “Interferometric single-shot parity measurement in InAs–Al hybrid devices,” Nature, vol. 638, no. 8051, pp. 651–655, Feb. 2025, doi: 10.1038/s41586-024-08445-2. D
- [21] M. Aghaee et al., “20 Second Parity Lifetime in an InAs–Pb Tetron Device,” arXiv:2606.03884, Jun. 2026. D
- [22] H. F. Legg, “On the robustness of topological gap detection via transport,” Nature, vol. 654, no. 8120, pp. E22–E26, Jun. 2026, doi: 10.1038/s41586-026-10567-8. arXiv:2503.08944. D
- [215] C. Nayak, “Majorana 2 – Microsoft's Scalable Quantum Processor With Reliable, Long-Lasting Qubits,” Microsoft Quantum. [Online]. Available: https://quantum.microsoft.com/
en-us/ Cinsights/ blogs/ majorana-2-scalable-quantum-processor - [216] N. van Loo et al., “Single-shot parity readout of a minimal Kitaev chain,” Nature, vol. 650, no. 8101, pp. 334–339, Feb. 2026, doi: 10.1038/s41586-025-09927-7. D
- [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [365] H. Zhang et al., “Quantized Majorana conductance,” Nature, vol. 556, no. 7699, pp. 74–79, Mar. 2018, doi: 10.1038/nature26142. Retracted: Nature, vol. 591, p. E30, Mar. 2021, doi: 10.1038/s41586-021-03373-x. D
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en/ Pperspectives/ advisories/ 2024/ 09/ semiconductor-additive-manufacturing-and-quantum-computing
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Diamond growth / implantation (NV, SiV, SnV)
Plasma CVD growth of single-crystal diamond, ion implantation and annealing to form NV, SiV or SnV centres, and undercut etching to build the nanophotonics around them.
Verdict. Two independent lotteries — where the ion stops and how the cavity lands on it — set device yield, and nobody publishes it: QuTech characterised 327 SnV cavities at room temperature, found coupled centres in 7 of the 9 it cooled, and measured two above cooperativity one.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
Plasma CVD grows single-crystal diamond on a seed; nitrogen, silicon or tin is implanted; a high-temperature anneal mobilises vacancies that bind the impurity into a colour centre; the optical structure is then cut from the bulk. That last step is the defining constraint: there is no diamond-on-insulator wafer and no sacrificial layer, so cavities are released by undercut etching of the same crystal that hosts the defect. Implantation-based fabrication matured around 2010; QuTech's 2026 SnV cavity study sets the benchmark Dfact.
Attributes: engineered placement of a natural defect, no mobility and no control step, Pauli error once fabricated, diamond fabrication with no CMOS analogue.
Physics & limits
Three independent things must go right at one site. The ion must stop where intended: straggle is tens of nanometres, an order worse than STM donor placement. It must convert into an optically good centre — only a fraction take the wanted charge state, and residual damage broadens the line. Then the etched cavity must put its field maximum on that centre: cooperativity goes as g²/κγ, with g set by position inside a mode a few hundred nanometres across. The three partial yields multiply, and none is published over a whole chip: of 327 cavities characterised at room temperature, 9 were cooled, 7 of them held a coupled SnV, and the two measured in full reached coherent cooperativity 8.3 and 1.6 Dfact. Only deterministic single-ion implantation with event detection, or in-growth delta doping with registration, moves that floor; neither exists at device scale.
Engineering state of the art
table
| year | figure | who | tag+key |
|---|---|---|---|
| 2024-05-15 | implanted SiV nanophotonic nodes at 0.69(7) over 35 km of fibre | Harvard | D[209] |
| 2025-11-27 | fibre microcavity around a bulk NV raises collection ~0.05% → ~0.5% | QuTech | D[359] |
| 2026-06 | 327 SnV nanocavities on two chips, mean Q 1.1×10⁴ at room temperature; coupled centres in 7 of 9 cooled; coherent cooperativity up to 8.3 | QuTech | Dfact |
Dominant term: device yield. The fibre microcavity is a fabrication answer as much as an optical one: the resonator sits outside the crystal, removing the undercut-etch lottery.
The 327-cavity SnV study, first reported in a news item [362], is published in Physical Review X fact: its 327 cavities were characterised at room temperature, only 9 were cooled, and the two emitter–cavity devices measured in full exceeded cooperativity one; the result is single-source and unreplicated. Its ¹²⁰Sn implant at 350 keV reaches a depth of 88 ± 16 nm fact, a spread of tens of nanometres. Element Six's lead as the diamond source of most NV-centre companies rests on a secondary survey [364]. Not published: the fraction of the 327 cavities above cooperativity one, so device yield is unknown; the lateral implantation straggle and an ion-to-usable-centre conversion yield; a dated capacity, revenue or investment figure for Element Six's quantum segment; and a cost per device, wafer count or throughput for any diamond quantum process.
Manufacturing, materials & supply chain
Element Six is the main merchant supplier, selling plates by catalogue; its DNV-B1 grade (2020-06-15) targets NV ensembles, while single-defect work needs electronic-grade single crystal C[361]. Its growth capacity sits in the UK and California C[361]; two smaller sources are Diatope, an Ulm University spin-out (2021) selling engineered NV diamond, and Quantum Brilliance's quantum-diamond foundry in Melbourne, opened in 2025 to make quantum-grade diamond at scale P[364]. Implantation runs on general-purpose accelerators; ¹²C-enriched growth costs more. Nothing is on a 300 mm path: millimetre-scale plates processed individually, with no published wafer count, cost or throughput. Export exposure is not nil: since 2022-08-15 the US Export Control Classification Number (ECCN) 3C005.a names diamond semiconductor substrates, ingots and boules above 10⁴ Ω·cm, and 3C006 an epitaxial diamond layer on such a substrate fact; whether an electronic-grade quantum plate counts as a semiconductor substrate has not been ruled on, and no ECCN names colour centres. Burden passed upward: a laser and a detector per site.
Role in the stack
Provides the host crystal colour-centre spins and their gates require, hence the defect-node architecture. It is the counterpart of STM hydrogen-resist lithography, not a substitute: implantation buys area throughput at an order of magnitude of placement precision, and neither route publishes a yield distribution. Verification: the 327-cavity study is one institution's, announced in a news release P[362] and peer-reviewed in Physical Review X Dfact, with nothing to replicate it against.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| QuTech | research | Netherlands | SnV nanocavity fabrication and cryogenic characterisation | Dfact |
| Element Six | supplier | UK | Merchant CVD diamond plates | C[361] |
| Diatope | supplier | Germany | Engineered NV diamond; Ulm University spin-out (2021) | P[364] |
| Harvard | research | USA | Implanted SiV nanophotonics | D[209] |
| Quantum Brilliance | developer | Australia | Room-temperature units; quantum-diamond foundry in Melbourne (2025) | P[364] |
| QuantumDiamonds | developer | Germany | NV microscopy, Munich | P[364] |
Money. 2026-07 · QuantumDiamonds · grant and equity · EUR 91 M, EUR 76 M of it EU Chips Act · financing a EUR 152 M Munich facility · closed P[364]. 2025-01 · Quantum Brilliance · Series A · USD 20 M · ~USD 58 M cumulative · closed P[364]. No QBI stage names diamond manufacturing.
Market & supply chain. One dominant substrate supplier is the concentration risk, its two alternatives dating only from 2021 and 2025; accelerators and etch tools are generic. Unit economics are unpublished. Pays into G6 and sensing.
IP & standards. No dated patent family from a named database as of 4 Sep 2026; Element Six's DNV grades are a de facto benchmark.
Roadmaps & track record. QuTech (modular-computing programme · on schedule) P[362]. QuantumDiamonds (Munich facility, 2026-07 · too new to judge) P[364]. Quantum Brilliance (units at three laboratories · delivered, dates unstated) P[364]. No actor publishes a dated yield target.
Strategic reading. Element Six wins in every scenario: it sells substrate to actors who compete with each other, not it. The fibre microcavity is the quiet threat — a resonator outside the crystal removes most of the nanofabrication problem.
Outlook & open questions
Confirm/demote (12–24 months): deterministic single-ion implantation with event detection, or a published chip-wide fraction of cavities above cooperativity one, confirms; two more years without either demotes this to a research process. Best case 2029: chip-scale arrays with tens of usable nodes. Worst case: every node stays hand-selected. Open: (1) can implantation precision approach one nanometre; (2) do Diatope or Quantum Brilliance's foundry grow into a second source at Element Six's scale; (3) does external-cavity coupling displace monolithic nanophotonics.
References
- [209] C. M. Knaut et al., “Entanglement of nanophotonic quantum memory nodes in a telecom network,” Nature, vol. 629, no. 8012, pp. 573–578, May 2024, doi: 10.1038/s41586-024-07252-z. D
- [359] J. Fischer et al., “Spin-photon correlations from a Purcell-enhanced diamond nitrogen-vacancy center coupled to an open microcavity,” Nat. Commun., vol. 16, no. 1, Art. no. 11680, Nov. 2025, doi: 10.1038/s41467-025-66722-8. D
- [361] Element Six, “Element Six launches DNV-B1™ – its first commercially-available, general-purpose quantum grade diamond,” Jun. 15, 2020. [Online]. Available: https://www.e6.com/
en/ Cabout/ news/ dnv-b1-launch - [362] QuTech, “Coherent coupling of diamond colour centre to a nanocavity,” Jun. 25, 2026. [Online]. Available: https://qutech.nl/
2026/ P06/ 25/ a-step-toward-faster-quantum-networks/ - [364] M. U. Rehman, “Top Diamond NV-Centre Quantum Computing Companies in 2026,” The Quantum Insider, Jul. 10, 2026. [Online]. Available: https://thequantuminsider.com/
2026/ P07/ 10/ 8-quantum-computing-companies-working-with-nv-centre-in-diamond-technology/
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STM hydrogen-resist lithography (donors)
A scanning-tunnelling tip desorbs hydrogen from passivated Si(100) to open single sites, phosphine dopes them, and epitaxial silicon buries the donors — atom-precise, serial, and without a foundry equivalent.
Verdict. Eleven qubits at atom precision prove the physics; with one practitioner, no merchant tool and no published parallel-write scheme, this stays a boutique process whatever the 2033 target says.
Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).
Identity & lineage
A hydrogen-terminated Si(100) surface is the resist. The tip removes hydrogen from selected dimers by electron-stimulated desorption; phosphine adsorbs only on the bare silicon; an anneal incorporates phosphorus substitutionally; low-temperature epitaxy buries the result. Hydrogen-resist patterning predates its qubit use by two decades; UNSW's Simmons group made a single-atom transistor in 2012 D[357] and SQC — branding the flow PAQMan — an 11-qubit processor in 2025 D[192].
Attributes: engineered placement of a natural dopant, no mobility and no control step, Pauli error once fabricated, a fabrication class with no CMOS analogue.
Physics & limits
Throughput is the floor, structurally: one tip visits one site at a time, so the process scales as O(N) in qubits where photolithography scales as O(1) in wafers. In-plane registration inside the desorption window is near a lattice constant, but the donor's final position carries ~3 nm of uncertainty from segregation and diffusion during incorporation and encapsulation: the limiting step is thermal, not lithographic. Encapsulation temperature is the real trade: hot enough for good epitaxy moves donors, cold enough to freeze them leaves defects that dephase the electron. Only parallel exposure changes the scaling law.
Engineering state of the art
table
Dominant term: device count. Every STM-donor device is fabricated individually; no parallel process exists at any scale and no placement-yield distribution is published.
Not published: a primary measurement of the incorporated-donor position distribution behind the ~3 nm placement precision; the amounts of the Firgun Ventures investment, the SkyWater agreement and the AMD collaboration, and the split of the A$60 M NRFC total by tranche; a parallelisation scheme for STM donor placement, by SQC or any other group; and any SQC statement on IonQ's acquisition of SkyWater.
Manufacturing, materials & supply chain
No vendor sells a turnkey donor-placement tool: the equipment (UHV STM, phosphine handling, epitaxy) is merchant, the recipe is not, so no second source can be procured. Feedstock is no longer scarce: enriched ²⁸Si from ASP Isotopes and, from 2026-07-16, US DOE silane at 99.9999% ²⁸Si P[348]. SkyWater supplies US resonators and packaging (2025-11-20) C[276], and IonQ, a competing platform vendor, closed its ~USD 1.8 B acquisition of SkyWater on 2026-07-31 G[19] — the sharpest supply risk here. Export control bites on the feedstock, not the tool: no Export Control Classification Number (ECCN) covers STM lithography, but the US rule of 2024-09-06 created ECCNs for isotopically enriched silicon and germanium — silicon qualifies below 0.08% of the nuclear-spin isotope ²⁹Si — as epitaxial layers (3C907), hydrides such as silane (3C908) and bulk material or oxide (3C909), which takes in the DOE silane; its quantum-computer ECCN, 4A906, starts at 34 qubits and, below 2,000, applies only under a two-qubit (C-NOT) error ceiling set for each size band — out of reach of an eleven-qubit device G[301]. Burden at scale is unknown — no device beyond eleven qubits exists.
Role in the stack
The manufacturing layer of donor spins in silicon: provides the donor-spin carrier and, through it, hyperfine-gated registers and spin-to-charge readout; it substitutes for foundry CMOS at placement, trading wafer throughput for unmatched precision. Nothing else in the stack requires it — the strategic weakness: a defect here cannot be routed around, and no other node gains from progress on it. Verification: the 11-qubit fidelities come from one paper by the only group practising the process D[192] — no second fabricator, and three fidelity framings across preprint, journal and main report.
Actors & economics
Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| SQC | developer | Australia | Sole practitioner of STM donor placement | D[192] |
| SkyWater Technology | supplier | USA | Resonators and packaging | C[276] |
| IonQ | supplier | USA | Owns SkyWater since 2026-07-31 | G[19] |
| NVIDIA | supplier | USA | NVQLink interconnect, SQC among 17 builders | C[531] |
| AMD | supplier | USA | Hardware for qubit control and readout, and compute for simulation (collaboration announced 2026-04-07) | C[358] |
Money. 2025-11-06 · SQC · QBI Stage B · up to USD 15 M · DARPA · awarded fact. 2026-03-24 and 2026-06-11 · SQC · equity · A$60 M combined · Australia's NRFC · closed fact. 2026-06-11 · SQC · investment · undisclosed · Firgun Ventures · announced C[358]. 2026-07-31 · IonQ · acquisition of supplier SkyWater · ~USD 1.8 B · closed G[19].
Market & supply chain. There is no market: one operator, no merchant process. Cost per placed donor is unpublished, so unit economics cannot be checked against the 2033 target. Funds G2 and G3; G4 needs parallelisation that does not exist.
IP & standards. Foundational patents trace to the UNSW/Simmons line; no dated family count from a named database as of 4 Sep 2026, and no standard covers atom-precision placement.
Roadmaps & track record. SQC (2026-06 · commercial scale by 2033 Rfact · unmet, eleven qubits published). "Continuous scaling" and "a million qubits" appear in company material with no published mechanism C[358], so the target is unfalsifiable rather than ambitious.
Strategic reading. If a parallel-write scheme appears, a decade of recipe knowledge compounds into a real moat. Without one, the precision that makes the process attractive is what caps it, and value migrates to whoever puts donors in a foundry flow.
Outlook & open questions
Confirm/demote (12–24 months): a dated parallel-fabrication announcement or a device beyond eleven qubits confirms a path past boutique scale; neither by 2028 demotes this to a physics tool. Best case 2029: above fifty donors with published yield. Worst case: a single-laboratory capability. Open: (1) is multi-tip or templated exposure feasible; (2) does SkyWater's new owner keep the relationship; (3) does anyone publish a placement-yield distribution.
References
- [19] IonQ, “IonQ Completes Acquisition of SkyWater Technology,” Jul. 31, 2026. [Online]. Available: https://www.ionq.com/
news/ Gionq-completes-acquisition-of-skywater-technology - [192] H. Edlbauer et al., “An 11-qubit atom processor in silicon,” Nature, vol. 648, no. 8094, pp. 569–575, Dec. 2025, doi: 10.1038/s41586-025-09827-w. arXiv:2506.03567. D
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news/ Cskywater-and-sqc-advancing-hybrid-quantum-classical-computing - [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/
documents/ G2024/ 09/ 06/ 2024-19633/ commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies - [348] U.S. Department of Energy, “DOE Advances Domestic Supply of Silicon, Germanium Isotopes for Quantum Computing,” HPCwire, Jul. 16, 2026. [Online]. Available: https://www.hpcwire.com/
off-the-wire/ Pdoe-advances-domestic-supply-of-silicon-germanium-isotopes-for-quantum-computing/ - [357] M. Fuechsle et al., “A single-atom transistor,” Nat. Nanotechnol., vol. 7, no. 4, pp. 242–246, Apr. 2012, doi: 10.1038/nnano.2012.21. D
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news/ C - [531] NVIDIA, “NVIDIA Introduces NVQLink — Connecting Quantum and GPU Computing for 17 Quantum Builders and Nine Scientific Labs,” Oct. 28, 2025. [Online]. Available: https://nvidianews.nvidia.com/
news/ Cnvidia-nvqlink-quantum-gpu-computing
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9References
A number stands for one work throughout the Atlas — here, in every technology brief and in later editions. This list holds all 900 works the Atlas cites, in that shared numbering: 1–347 are the works the report cites, in order of first citation; the works after them entered through the technology briefs, which repeat their own entries under their text. Online sources were accessed in September 2026.
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Technology-graph sources (§7) — every 'defines' row in §7.8 carries its own URL; the graph JSON (graph.json) is the machine-readable source list.
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