Intel

quantum-vendor · computing-hardware · Santa Clara, CA, United States · intel.com

Machines in the Atlas (1)

• Tunnel Falls — DEMONSTRATED / DISTRIBUTED, 12 q, Jun 2023 (Argonne Jan 2026)

Machines it co-developed (filed under another organisation) (1)

• Hitachi x Intel 18A spin programme — Hitachi + Intel K.K. + AIST (G-QuAT)

Technologies its machines use

• Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · 1
• Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · 1
• Exchange gate (spins; incl. shuttled-spin CZ) · 1
• Static nearest-neighbour lattice · 1
• Room-temperature electronics + per-qubit coax/flex · 1
• Cryo-CMOS controller (4 K / mK) · 1
• Spin-to-charge conversion + rf reflectometry · 1
• Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) · 1
• 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · 1

Architectures

• Silicon / germanium quantum-dot spins

Mentioned in the briefs of

• Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring)
• 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)
• Cryo-CMOS controller (4 K / mK)
• Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge)
• Single-spin (Loss–DiVincenzo) / nuclear-spin encoding
• Exchange gate (spins; incl. shuttled-spin CZ)
• Spin shuttling (conveyor mode)
• Relay-BP for qLDPC (FPGA)
• Static nearest-neighbour lattice
• Baseband electrical control (spins, Majorana)
• FPGA real-time decoders (LCD, Deltaflow)
• GPU decoding via NVQLink
• Transmon
• Tunable-coupler CZ / iSWAP
• Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring
• Dispersive microwave readout (+TWPA, Purcell)
• Spin-to-charge conversion + rf reflectometry
• Multi-chip modules / l-couplers (same cryostat)