FPGA real-time decoders (LCD, Deltaflow) dec_fpga

Classical hardware consuming syndrome bits and emitting corrections inside the code cycle. The lineage is the backlog argument: if mean decode time exceeds cycle time, undecoded rounds accumulate without bound and the classical hardware sets the logical error rate. FPGAs won for deterministic latency, not speed.
Attributes: a compute module, not a carrier (affinity 0.5); no time, readout, mobility, control or fabrication of its own.
Error structure it consumes: Pauli syndromes from the rotated surface code.

Throughput must clear one round per cycle — 1.1 µs on Willow-class hardware D[1] — which Riverlane's clustering decoder meets to d=17 D[238]. Reaction latency gates every non-Clifford gate and only a closed loop measures it: Shenzhen's closed one in 550 ns at d=3, inside a 1.25 µs cycle D[729]. Accuracy pays for latency: LCD thresholds at 0.55% against 0.7% for software MWPM D[238], and on identical Willow syndromes matching gave Λ = 2.04 where a neural decoder gave 2.14 D[1]. Area is the other wall: LCD at d=17 takes ~6% of a Xilinx VU19P's logic LUTs (lookup tables) per logical qubit D[238] — ~16 such logical qubits per top-end part.

IBM's Relay-BP for the gross code reports a 24 ns iteration and under 1 µs per cycle below p = 3×10⁻³, from simulated syndromes S[48].

IBM's Relay-BP FPGA figures come from simulated syndromes, and the abstract's 24 ns / <1 µs conflicts with the 480 ns per 12-cycle window reported elsewhere fact. Riverlane's Series C is $75 M in its 2024 release and $85 M in its 2026 roadmap. The IBM–AMD FPGA decoder collaboration is reported only by trade press; its terms are not published.

No fab: a commercial FPGA card in the room-temperature rack. Every published real-time decoder runs on AMD/Xilinx silicon (VU19P for LCD D[238], VMK180 for Micro Blossom D[727]); the only merchant alternative changed hands when Intel's sale of 51% of Altera to Silver Lake at an $8.75 B valuation, announced in April 2025, closed on 2025-09-15 G[735] — a duopoly with one side under private equity. High-end FPGAs sit inside US export-control scope. The I/O burden is the syndrome pipe: trivial at 10³ qubits, but at 10⁴–10⁶ the rate forces predecoding at 4 K or many parallel cards.

An alternate decoder on the transmon lattice with tunable couplers. Requires the rotated surface code and provides the correction stream fault tolerance needs; it replaces GPU decoding, whose tail latency is non-deterministic — 3.84 µs mean, 3.96 µs max just to cross NVQLink C[324]. Its contribution to the derived clock is a floor, not a term: it must stay under the 1.1 µs cycle, and does. Verification: these are decoder-in-isolation figures on replayed or simulated syndromes; only two loops are live — the d=3 one and the in-loop clustering decoder on Rigetti Ankaa-2, the register's one carrier; Micro Blossom's quoted 367 ns is a repository figure in no paper, the published number being 0.8 µs D[727].

Money.
2024-08-06 · Riverlane · Series C · $75 M · Planet First Partners lead · closed C[661]fact
2025-09-15 · Intel/Altera · divestment of 51% · $8.75 B enterprise valuation · Silver Lake · closed (announced 2025-04-14) G[735]fact

Market & supply chain. One merchant decoder vendor, one dominant FPGA vendor, NVIDIA pushing NVQLink as the alternative — open endpoint, single-sourced accelerator C[324]. Riverlane's stack ships integrated with Qblox control hardware C[659]. It pays into G3 and G4 only.

IP & standards. Riverlane GB 2641501 A "Quantum decoder" (published 2025-12-10) claims grouped processing elements running clustering on the decoding hypergraph — the LCD architecture itself G[662]. No decoder standard exists.

Roadmaps & track record. Riverlane (2026-03-12 · megaquop before 2030, teraquop from 2033 · LCD published on time C[658]). IBM (2025-10 · FPGA gross-code decoding · still simulation as of 2026-09-04 S[48]).

Strategic reading. Whoever owns the decoder sits between every superconducting QPU and fault tolerance — but the layer is thin enough that QPU vendors build it in-house, as IBM and Google did. AMD wins either way; the threat is NVQLink commoditising the interface.

Confirm by end-2027: an FPGA decoder closing the loop on live syndromes at d ≥ 7 — no live d=7 decode by any decoder is documented, Google's neural d=7 result D[2] included — or Relay-BP on real gross-code hardware; demote if neither happens. Best case 2029: a portable interface with second-source silicon; worst case, per-vendor decoders nobody can compare. Does reaction latency or throughput bind first at d=17? Do decoder vendors survive QPU vendors building in-house? Does export control reach FPGAs?