Cryogenic / on-chip decoder (cryo-CMOS, SFQ) dec_cryo

A cryogenic decoder evaluates the syndrome-to-correction map inside the refrigerator instead of shipping every syndrome bit up the harness. Two substrates compete: single-flux-quantum (SFQ) logic switching quantised flux pulses at tens of GHz at millikelvin, and CMOS characterised at 4 K. The lineage is architectural: a per-qubit SFQ decoder in 2020 S[744], an online SFQ surface-code decoder in 2021 S[745], then in 2025–26 an inversion — compressing syndromes at 4 K rather than decoding them S[733]S[746].

• Control and placement: cold digital logic at the millikelvin or 4 K stage.
• Manufacturing: Nb multilayer lithography or 4 K-characterised CMOS; no decoder-specific process exists.

The limit is thermal bookkeeping. An SFQ junction transition dissipates of order I_cΦ₀ ≈ 10⁻¹⁹ J, so a 10⁵-junction decoder at 2 GHz sits in the tens of µW — 2.78 µW is the published point S[745] — against a dilution unit delivering hundreds of µW at 100 mK. Cryo-CMOS trades that for a ≈2 W plant at 4 K S[550], of which one design spends 1.5 W to serve 2,668 logical qubits at d=21 S[733]. Neither floor is fundamental: each is an allocation against a budget control already claims, and it moves with the logic family — lower-power cryo-CMOS, SFQ at ~1.6 µW per qubit, adiabatic quantum-flux-parametron (AQFP) logic lower still S[550]. The dominant failure mode is not a Pauli error — a decoder whose throughput falls below the syndrome rate accumulates unbounded backlog, so latency and bandwidth set the design. SFQ near the qubit die adds a second mechanism: pulse edges radiate, and photon-mediated quasiparticle poisoning measured 1.2(1)% error per Clifford on a separate-die SFQ driver that switches far less than a decoder would Dfact.

All decoder figures are post-synthesis; the last row is the nearest fabricated analogue.

The dominant budget term is classical: off-cryostat bandwidth and round-trip latency.

Both cryo-CMOS designs run on 22 nm FD-SOI characterised at 4 K, and both took that PDK from Semiwise Ltd (UK) S[746] — one small supplier between every academic group and a tape-out. GlobalFoundries' 22FDX is the volume path behind it Cfact. The SFQ path depends on SEEQC's multilayer Nb foundry in Elmsford NY Dfact, the only merchant line of its class. No yield or unit cost exists: nothing has taped out. ECCN 3A901.a covers CMOS ICs "designed to operate at" ≤4.5 K — design intent, not performance — so the layout is controlled pre-fabrication fact.

The node exists to cut I/O. The superconducting QEC cycle is 1.1 µs D[1] and a distance-d logical qubit emits d²−1 syndrome bits per round — ≈0.4 Gb/s at d=21. At 10³ physical qubits nothing binds — a local clustering decoder holds under 1 µs per round to d=17 on a Xilinx VU19P using ≈6% of its LUTs (lookup tables) Dfact, and exact FPGA matching averages 0.8 µs at d=13 D[727]. The wall at 10⁴–10⁶ is mechanical before computational: feedthrough count, harness heat load, serialiser bandwidth crossing 4 K. Compression attacks that term.

An alternate decoder on the transmon lattice with tunable couplers. It requires millikelvin SFQ or 4 K cryo-CMOS control first, provides for nothing downstream, and blocks no one. It replaces room-temperature FPGA decoding: an FPGA is reprogrammable as codes and noise models change, a cold ASIC is fixed-function, competes with control for cold watts, and is export-controlled from the design file. The argument for an ASIC is supply-side: merchant high-end FPGAs are an AMD/Altera duopoly, one side private-equity-controlled since 2025 fact. As a predecoder it adds ≈0.10 µs per round Sfact outside derived clock = sum of the syndrome round: gate layers + transport + readout + reset, which stays ≈0.65 µs against the measured 1.1 µs cycle; only the cabling cost changes.

Every decoder number is post-synthesis power/performance/area on a cryo-characterised PDK plus vector simulation, syndromes drawn from noise models rather than a device; the 2025 predecoder is at least evaluated under circuit-level rather than code-capacity noise, and neither study is replicated outside an overlapping author set. Power per qubit at 4 K has no shared definition — 23 mW measured by IBM driving a two-qubit gate, against an "optimistic" 5 mW and sub-2 mW claims Sfact; only 23 mW is tied to a running gate. The repeated 367 ns FPGA matching latency comes from a repository with no code distance and no paper; the peer-reviewed figure is 0.8 µs at d=13 D[727], used here.

Not published: SEEQC's offering size and price range, still blank in its S-1 amendment of 2026-09-11 fact, and a patent family specific to cryogenic decoding.

Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| University of Michigan | Research | USA | Authored both cold predecoder and compressor designs | Sfact |
| SEEQC Inc. | Developer, supplier | USA | Nb foundry and millikelvin SFQ control; only credible SFQ host | Dfact |
| HRL Laboratories | Developer | USA | Only fabricated cold logic inside a QEC loop | Dfact |
| IBM | Developer, acquirer | USA | Cryo-CMOS flux-bias ASICs on 156 qubits; acquired HRL | Cfactfact |
| Semiwise Ltd | Supplier | UK | Sole source of the 4 K 22 nm FD-SOI PDK used | S[746] |
| Riverlane | Developer, rival | UK | Room-temperature FPGA decoding incumbent | Dfact |
| US Bureau of Industry and Security | Regulator | USA | Controls ≤4.5 K CMOS ICs by design intent | fact |

Money. 2025-12/2026-06 · University of Michigan · DOE ARQC award DE-SC0025633, amount undisclosed · funds both studies · ongoing S[746]. 2026-05-21 · GlobalFoundries · CHIPS letter of intent · $375 M USD · US Commerce · non-binding fact. 2026-05-26 · SEEQC · Form S-4 for a Nasdaq listing through a 2026-01-16 Allegro merger agreement · $75 M offering plus $65 M PIPE at ~$1 B enterprise value · filed G[575]; the merger was terminated 2026-08-25, and SEEQC's separate S-1 IPO (filed 2026-06-29) had not priced by 30 Sep 2026 fact; SEEQC's amended S-1 of 2026-08-28 reports 2025 revenue of $4.2 M, a 2025 net loss of $12.2 M and $18.1 M in cash at 2026-06-30 fact. 2026-07-23 · IBM · acquisition of HRL Laboratories · terms undisclosed · closed 2026-08-26 Cfactfact. No programme funds cryogenic decoding directly.

Market & supply chain. Nobody sells this. The enabling goods sit one layer down: cryo-PDKs, 22FDX capacity, Nb multilayer runs, and the racks a cold decoder would displace. Concentration is severe at both ends; no unit economics are quotable. Only G4 pays for this.

IP & standards. No patent family specific to cryogenic decoding was found in a named dated database. The nearest is Riverlane's GB 2641501 A "Quantum decoder" (published 2025-12-10), claiming room-temperature hardware clustering fact. No standard exists for a syndrome interface across the 4 K boundary; NVIDIA's NVQLink standardises the warm side instead.

Roadmaps & track record. Michigan predecoder and compressor (2025-12-10, 2026-06-29 · no tape-out date · design-only as of 4 Sep 2026) — real PDK data, no fabrication commitment. SEEQC SFQ control (peer-reviewed 2026-03-10 · decode absent from its roadmap) — the only actor with its own process line and, should its pending IPO price, the proceeds to fund a tape-out. IBM cryo-CMOS control (abstracts 2026-03-16 · no preprint) — unproven at publication standard.

Strategic reading. If cold decoding works the winners already own cold silicon and cooling budget — SEEQC on SFQ, IBM/HRL and GlobalFoundries on CMOS — because decode folds into a chip they ship anyway. Losers are standalone decoder vendors whose value is reprogrammability, and accelerator vendors betting decode migrates to GPUs over a warm link. Bargaining power sits with the substrate owner.

Confirm by 2028 if any cryogenic predecoder tapes out with measured silicon; demote if the 2027 literature is still post-synthesis. Best case 2029: a compressor at 4 K inside a QBI-adjacent system absorbs syndrome traffic before the harness. Worst case: room-temperature decoding scales with qLDPC codes and faster links. Open questions: which power baseline should size a cold decoder; can decode logic share a stage with control without reintroducing quasiparticle poisoning; does any platform hit the feedthrough wall before 10⁴ qubits. Watch the SEEQC listing and IBM's post-HRL roadmap.

The junction budget that sizes a single-flux-quantum (SFQ) decoder is falling on the design side: a clock-free xSFQ cell library with built-in fan-out amplifiers cuts the Josephson-junction count 2.7–3.4× (63–71%) on standard single-cycle logic benchmarks and 41–66% on pipelined ones, with one cell fabricated and verified at 4.2 K P[897]. No decoder was built; the figures are for generic logic.