Transmon lattice with tunable couplers on the map bar: Transmon lattice

The architecture in the report (§8.3)

8.3.1 Transmon lattice — Transmon lattice with tunable couplers (sc)

The idea. A transmon (transmon) is a capacitively shunted Josephson junction whose two lowest levels serve bare as the qubit (enc_bare). The architecture tiles transmons in a lithographic lattice (cx_nn), switches neighbour exchange with flux-tuned couplers (g_tc), drives them from room-temperature racks (ct_rt), reads them dispersively (ro_disp) and corrects with the rotated surface code, whose weight-4 checks are the lattice's own neighbourhoods. A circuit atom is drawn, not found: gates take tens of nanoseconds [G] and the QEC cycle 1.1 µs [D][1], the map's fastest clock (§7.4). The price is coherence (T1 68 µs on Willow [D][32]), identical qubits and any coupling beyond the neighbour. The bet: speed and wafer fabrication outrun the error budget; links between chips come later.

What it needs. Everything rests on fab_sc: the transmon requires junction lithography, so its frequency spread is fixed at fabrication; the trimming that repairs it has no technology yet. The surface code requires only neighbour checks. Bivariate bicycle codes keep 12 logical qubits in 288 physical where the surface code needs nearly 3,000, but need a degree-6 graph [S][248]: code_qldpc requires long-range couplers (cx_lr) and conflicts with cx_nn, open since 2024-03. Readout and reset are two-thirds of the 651 ns derived round [S] (§7.4). Four control technologies replace one another per signal, not per machine — a Heron r2 ran cryo-CMOS flux ASICs in hybrid with room-temperature rf (Mar 2026) [C]. Both cold routes conflict with the transmon: cryo-CMOS (ct_cryocmos) on the mixing chamber's heat budget, SFQ (ct_sfq) on quasiparticles — its switching photons break Cooper pairs, 0.96(2)% of a 1.2(1)% error per Clifford in 2023 [D][249], mitigation projected, not yet independently measured. Encoding has one option; the microwave–optical transducer slot is empty.

Where it stands. 78 of the register's 184 machines and 62 devices (Table 8.3): 39 deployed, 18 demonstrated, 7 retired, 13 announced or planned, 1 other; IBM supplies 16 rows, China 18. The largest benchmarked device is IBM Quantum Osprey — 413 of its 433 qubits usable on the cloud for four months of 2023 as an exploratory technical demonstration, with performance IBM called consistent with Eagle r1 and no published gate figure beyond the platform's calibration [C][292]; the largest chip, IBM Quantum Condor (1,121 qubits), unveiled in December 2023 as an innovation milestone and never offered to users, is a scale demonstrator whose gate IBM only described as comparable to Osprey [C][292]. The best 2Q error, 1.0×10⁻³ on Origin Wukong-180 (4th gen), is a company figure [C] (Table 8.3); Willow's device mean is 99.88% [D][32]. Willow ran d=7 at Λ = 2.14 [D][1], then 7.72×10⁻⁴ per cycle (Jul 2026) [D][2]; Zuchongzhi 3.2 d=7 at Λ = 1.40 [D][3]. Code, decoder and interconnect slots are empty on 54, 66 and 59 machines; 12 rows publish no gate mechanism; 327 of 843 evidence cells are documented.

Exceptions and borrowings. No machine falls off the slots or fits another architecture better; alternates carry the direction. Wiring leaves the chip edge (ct_vio) on RIKEN 64, RIKEN–Fujitsu 256, OQC Toshiko and QuantWare Bass-A10K (VIO-40K), racks still warm; control goes cold only in part or at small scale: cryo-CMOS flux ASICs in hybrid with room-temperature rf on Heron r2 and as alternate on Starling and Blue Jay, SFQ on SEEQC's five-qubit system (single-qubit gates only); QuamCore's SFQ-controlled design stays unlisted until the company dates a first device. Sycamore and Zuchongzhi stack dies (ic_multidie); modules (ic_mcm) ship only on Rigetti Cepheus, at 99.6%→99.1% [C][36]. IBM's utility line sits in mitigation (code_mitig: Eagle, Heron r3, Nighthawk r2) and detection (code_detect: Falcon, Heron r2/r3, Origin Wukong 3rd gen); qLDPC runs only on Kunlun. Nominal members: Osprey, Eagle, Condor, Falcon and LBNL AQT use cross-resonance (g_cr), not tunable couplers; targets (Amaravati, CSCS, KRISS 50); plans (Kookaburra to Blue Jay, Fujitsu 10,000); component testbeds (Toshiba coupler, Loon); undisclosed stacks (Tianyan-504, RIKEN–Fujitsu 256, Toshiko). Gap cells show the architecture drawn too narrowly: a central-resonator bus (IQM Star 24, VLQ, DRDO–TIFR), leakage-removal units (Willow, Zuchongzhi 3.2), post-fabrication frequency trimming (Willow, Cepheus, Academia Sinica). Dual-rail borrows transmon, ct_vio and ic_mcm; cat ic_multidie; spins ct_cryocmos.

The next test. Expectations to 31 Mar 2028 (§5.2). A bivariate bicycle memory on c-couplers, Kookaburra or a Kunlun successor, reports a logical error per cycle below its physical idle error; Kunlun's 8.91% [P][72]–[74] is the baseline. If Kookaburra is undelivered again by end-2027, the qLDPC branch is demoted and the architecture stays a surface-code machine at >10³ physical qubits per logical at 10⁻⁶ [S] (§2.1). And a gate-capable device above 433 qubits with published two-qubit errors, plus cryo-CMOS or SFQ control of ≥50 qubits; if neither appears and readout stays near 10⁻², scale by fabrication is demoted to scale by modules.

What the builders say. Google argues that superconducting processors scale in circuit depth, with microsecond cycles, while neutral atoms scale in qubit count [C][2], [9], and expects commercially relevant superconducting machines by the end of this decade, naming no qubit count [R][2], [9]. Rigetti targets about 1,000 qubits at 99.9% two-qubit fidelity in roughly three years, built from chiplets [R][61]. Fujitsu is building a machine of more than 10,000 physical and 250 logical qubits for fiscal 2030 [R][75], [76]. IBM chose a qLDPC code (a low-density parity-check code whose checks join distant qubits) because it corrects as well as the surface code with ten times fewer qubits [D][481]; it plans Kookaburra, the first qLDPC module, for 2026 and Starling, 100 million gates on 200 logical qubits, for 2029 [R][481].

Machines of this architecture (register: 78, of them 62 devices, 52 gate-capable). IBM — IBM Quantum Starling (planned, 22,000), IBM Quantum Condor (demonstrated, 1,121), IBM Quantum Osprey (retired, 433), IBM Quantum Heron r2 (deployed, 156), IBM Quantum Heron r3 (ibm_pittsburgh) (deployed, 156), IBM Quantum Heron r1 (retired, 133), IBM Quantum Eagle r1-r3 (retired, 127), IBM Quantum Nighthawk r1 (deployed, 120), IBM Quantum Nighthawk r2 (deployed, 120), IBM Quantum Loon (demonstrated, 112), IBM Quantum Egret (retired, 33), IBM Quantum Falcon r5.11 (retired, 27), IBM Quantum Blue Jay (planned), IBM Quantum Cockatoo (planned), IBM Quantum Flamingo (l-coupler proof of concept) (demonstrated), IBM Quantum Kookaburra (planned); Beijing Academy of Quantum Information Sciences — Baihua (Quafu platform) (deployed, 156), ScQ-136 "Baiwang" (deployed, 136), Dongling (Quafu platform) (deployed, 130), Haituo (Quafu platform) (deployed, 117), Shenglian (BAQIS) (demonstrated, 84); IQM Quantum Computers — IQM Halocene (announced, 150), IQM Emerald (IQM Crystal 54) (deployed, 54), IQM Star 24 (deployed, 24), IQM Garnet (IQM Crystal 20) (deployed, 20), IQM six-qubit star QPU (Deneb-class) (demonstrated, 6); Rigetti Computing — Rigetti Cepheus-1-108Q (deployed, 108), Rigetti Ankaa-2 (deployed, 84), Rigetti Ankaa-3 (deployed, 84), Rigetti Cepheus-1-36Q (deployed, 36), Rigetti Novera (deployed, 9); Google Quantum AI — Willow (demonstrated, 105), Sycamore-class 72-qubit processor (demonstrated, 72), Sycamore (retired, 53); Origin Quantum — Origin Wukong-180 (4th gen) (deployed, 180), Origin Wukong 102 (deployed, 102), Origin Wukong (3rd gen) (deployed, 72); QuantWare — QuantWare Bass-A10K (VIO-40K) (announced, 10,000), QuantWare Tenor-D64 (other, 64), QuantWare Contralto-A17 (deployed, 17); USTC / Hefei National Laboratory — Zuchongzhi 3.2 (demonstrated, 107), Zuchongzhi 3.0 (demonstrated, 105), Zuchongzhi 2.1 (retired, 66); Korea Research Institute of Standards and Science — KRISS 50-qubit-class superconducting system (announced, 50), KRISS domestic superconducting QPU (deployed, 20); QpiAI — QpiAI Kaveri (announced, 64), QpiAI Indus (deployed, 25); RIKEN RQC + Fujitsu — RIKEN-Fujitsu 256-qubit superconducting quantum computer (deployed, 256), RIKEN RQC-Fujitsu 64-qubit superconducting quantum computer (deployed, 64); Academia Sinica — Academia Sinica 20-qubit superconducting quantum computer (demonstrated, 20); Anyon Systems — Anyon MonarQ (deployed, 24); Barcelona Supercomputing Center (Quantum Spain; installed by Qilimanjaro-GMV) — Quantum Spain quantum computer at BSC (deployed, 35); Basque Government (BasQ) - IBM-Euskadi Quantum Computational Center — IBM Quantum System Two, Donostia-San Sebastian (deployed, 156); CAS / Peking University — Zhuangzi 2.0 (Chuang-tzu 2.0) (demonstrated, 78); Chalmers University of Technology (WACQT) — WACQT quantum computer (Chalmers 25-qubit flip-chip processor) (demonstrated, 25); China Telecom Quantum Group + CAS + QuantumCTek — Tianyan-504 / "Xiaohong" chip (deployed, 504); China Telecom Quantum Group + QuantumCTek — Tianyan-176 / Tianyan-176 II (and Tianyan-24 sibling) (deployed, 66); China Telecom Quantum Group / QuantumCTek / CAS — Tianyan-287 (deployed, 105); DRDO DYSL-QT with TIFR and TCS — 6-qubit superconducting quantum processor (demonstrated, 6); ETH Zurich (Quantum Device Lab) — Surface-17 (demonstrated, 17); Fraunhofer-Gesellschaft — IBM Quantum System One, Ehningen (deployed, 27); Fujitsu (+ RIKEN) — Fujitsu 1,000-qubit machine (planned, 1,000); Fujitsu + AIST + RIKEN — Fujitsu >10,000 physical / ~250 logical (STAR) (announced, 10,000); IBM with ETH Zurich (CSCS) and Lockheed Martin — IBM Quantum System Two at CSCS (Swiss Quantum Innovation Hub) (announced, 120); IBM with TCS and the Government of Andhra Pradesh — IBM Quantum System Two at Amaravati Quantum Valley Tech Park (announced, 156); IQM Quantum Computers with Instituto de Pesquisas Eldorado — IQM Spark at Eldorado Research Institute (announced, 5); IT4Innovations National Supercomputing Center (VSB - Technical University of Ostrava) — VLQ (deployed, 24); Israeli Quantum Computing Center (Quantum Machines + QuantWare + Qolab + ORCA) — IQCC superconducting facility (deployed, 25); Lawrence Berkeley National Laboratory — Advanced Quantum Testbed (AQT) (deployed, 8); Oxford Quantum Circuits — OQC Toshiko (deployed, 32); Qolab — Qolab devices at the IQCC (deployed); RIKEN with AIST, NICT, Osaka University, Fujitsu, NTT — RIKEN 64-qubit superconducting processor (deployed, 64); SEEQC — SEEQC SFQ-controlled 5-qubit system (demonstrated, 5); SpinQ Technology — SpinQ Ursa Major (25 q / 103 q) (deployed, 25); Toshiba + RIKEN RQC + University of Tokyo — Toshiba double-transmon coupler (demonstrated, 2); Tsinghua University IIIS (D.-L. Deng) with Zhejiang University (H. Wang, C. Song groups) — Kunlun (demonstrated, 32); VTT Technical Research Centre of Finland — VTT Q50 (deployed, 50); Zhejiang University + Graduate School of China Academy of Engineering Physics (Beijing) — Zhejiang University 125-qubit surface-code processor (demonstrated, 125).

Cells outside the architecture's slots (25). Academia Sinica 20-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; Academia Sinica 20-qubit superconducting quantum computer: L10 ∅G-calib (Atlas gap — post-fabrication laser trimming tunes qubit frequencies (same slot as Rigetti ABAA / IQM P); Quantum Spain quantum computer at BSC: L3 undisclosed where the architecture expects a technology; Tianyan-504 / "Xiaohong" chip: L3 undisclosed where the architecture expects a technology; 6-qubit superconducting quantum processor: L3 undisclosed where the architecture expects a technology; 6-qubit superconducting quantum processor: L4 ∅G-bus (Atlas gap — ring-resonator design invented at TIFR: qubits sit around one shared ring resonator used a); Fujitsu >10,000 physical / ~250 logical (STAR): L5 undisclosed where the architecture expects a technology; Fujitsu >10,000 physical / ~250 logical (STAR): L7 ∅G-analogrot (Atlas gap — STAR: arbitrary-angle rotations by direct state injection, no distillation; 10⁴ q at p=1e-); Fujitsu 1,000-qubit machine: L3 undisclosed where the architecture expects a technology; Willow: L6 ∅G-lru (Atlas gap — DQLR + 4 dedicated leakage-removal qubits in the 101-qubit d=7 patch; leakage rate not pub); Willow: L10 ∅G-calib (Atlas gap — Snake optimiser splits ~3N-dim frequency problem; ~3.7× cycle-error suppression, mean cycl); IQM Halocene: L4 ∅G-bus (Atlas gap — Constellation option: Star cells, each a central computational resonator giving all-to-all); IQM Star 24: L4 ∅G-bus (Atlas gap — Star topology: central computational resonator bus giving all-to-all within the cell (degr); IQM six-qubit star QPU (Deneb-class): L4 ∅G-bus (Atlas gap — star topology: all six qubits coupled only to the central computational resonator, effecti); VLQ: L3 undisclosed where the architecture expects a technology; VLQ: L4 ∅G-bus (Atlas gap — star topology: 24 qubits connected to one central resonator, all-to-all through it); KRISS 50-qubit-class superconducting system: L3 undisclosed where the architecture expects a technology; OQC Toshiko: L3 undisclosed where the architecture expects a technology; Rigetti Cepheus-1-108Q: L10 ∅G-calib (Atlas gap — ABAA (alternating-bias assisted annealing) post-fab JJ frequency targeting, 97.4% success ); Rigetti Cepheus-1-36Q: L10 ∅G-calib (Atlas gap — ABAA (alternating-bias assisted annealing) post-fab JJ frequency targeting, 97.4% success ); RIKEN 64-qubit superconducting processor: L3 undisclosed where the architecture expects a technology; RIKEN-Fujitsu 256-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; RIKEN RQC-Fujitsu 64-qubit superconducting quantum computer: L3 undisclosed where the architecture expects a technology; SEEQC SFQ-controlled 5-qubit system: L3 undisclosed where the architecture expects a technology; Zuchongzhi 3.2: L6 ∅G-lru (Atlas gap — all-microwave leakage-reduction units on data qubits; leakage population suppressed 72× to).