IBM Quantum Loon

Raveh Neeman

doi:10.5281/zenodo.22674814

IBM

IBM Quantum Loon

IBM · superconducting circuits · DEMONSTRATED (component testbed) (Nov 2025) · 112 physical qubits · access: lab-only

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: fixed-frequency transmon

gate mechanism: tunable couplers

connectivity: c-couplers giving up to degree 6 - a Tanner-graph connectivity testbed, not a regular lattice

control: room-temperature RF

control placement: room-temp

readout: dispersive; integrated qubit reset gadgets

gate evidence: no published figure

codes: gross

flags: no published error rates

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▥ Fig. (chip photos: 'IBM Quantum Loon (Credit: IBM)', 3 images); §Building our fault-tolerant architecture ✅ fixed-frequency transmon; IBM published no qubit count, secondary sources say ~112 (unconfirmed)
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▨ 🔎 tunable couplers
4 Connectivity / transport	Long-range on-chip couplers (c-couplers, mm-scale) · primary ▥ §Building our fault-tolerant architecture (6-way qubit connections; physically longer couplers; more routing layers) ✅ c-couplers: long-range on-chip couplers giving up to degree 6, as [[144,12,12]] needs; Tanner-graph connectivity testbed, not a regular lattice (Nov 2025)
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▨ 🔎 room-temperature RF control
6 Readout	Fast unconditional / dissipative qubit reset · primary ▥ §Building our fault-tolerant architecture (reset gadgets that quickly reset the qubit to the ground state) ✅ integrated on-chip qubit reset gadgets alongside dispersive readout (Nov 2025) Dispersive microwave readout (+TWPA, Purcell) · alternate ▨ 🔎 dispersive readout; integrated qubit reset gadgets
7 Code	Non-local qLDPC codes (bivariate bicycle, 'gross') · alternate ▥ §Building our fault-tolerant architecture (key components needed to implement our qLDPC codes) ✅ not run; target code is [[144,12,12]] gross qLDPC, whose degree-6 connectivity the chip provides; feeds Kookaburra — none — nothing in this layer ▥ §Building our fault-tolerant architecture (proof-of-concept processor for qLDPC components; 'almost out of fabrication') ✅ no QEC run as of Sep 2026; component testbed proving all key processor components for fault tolerance on one die
8 Decoder	Relay-BP for qLDPC (FPGA) · alternate ▣ Fig. 2 (Relay-BP FPGA decoder architecture); Fig. 5 (XCVU19P floorplan); §4 🔎 not run on Loon; target Relay-BP for [[144,12,12]] on AMD VU19P FPGA, <1 µs per cycle, on stored syndromes only — none — nothing in this layer ▨ 🔎 no decoder run on Loon; no QEC experiment (targets dec_relaybp)
9 Interconnect	— none — nothing in this layer ▥ §Building our fault-tolerant architecture (extra routing layers on the chip surface; longer on-chip couplers) ✅ monolithic single die, no inter-module link; long couplers cross via multi-layer routing + TSV-style vertical interconnect on-chip
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▥ Fig. ('IBM researcher holding a 300mm IBM Quantum Loon wafer'); §Building our fault-tolerant architecture ✅ 300 mm; multiple high-quality low-loss routing layers + TSV-style vertical interconnect so long couplers cross without interference

Standard records

connectivity degree → 6 neighbours · best (on-chip c-couplers)

exactly what [[144,12,12]] needs · Nov 2025 · source

evidence: ✅ 7 / 13