Bare physical qubit (no encoding) enc_bare

Using the lowest two levels of a Josephson circuit directly as a qubit is as old as the Cooper-pair box (Nakamura, 1999); the transmon (Koch et al., 2007) made it the default by buying charge insensitivity with lower anharmonicity — which is what creates the leakage problem.
Attributes: it adds no characteristic time, readout, mobility, control or fabrication of its own — each is the carrier's.
Error structure as the code sees it: unbiased Pauli plus leakage out of the subspace.

The scale that matters is α ≈ −E_C ≈ 2π × 200–300 MHz: it sets the minimum gate time and the leakage per gate, which DRAG (derivative removal by adiabatic gate) pulse shaping suppresses but cannot remove. Raising α costs charge dispersion, which grows as exp(−√(8E_J/E_C)); that trade is the floor here. Leakage persists where a Pauli fault does not: the second excited state survives tens of QEC cycles at Willow's 1.1 µs D[1], feeding the decoder correlated wrong syndromes. Hence dedicated removal: USTC's all-microwave scheme suppresses leakage 72×, to a residual 6.4(5)×10⁻⁴ after 40 cycles D[3]. What moves the floor is leakage-aware decoding and faster multi-level reset.

Best in class is one characterised IQM pair, CZ 99.93% over 40 h D[38]; typical at scale is IBM's fleet EPLG 3.7×10⁻³, best 1.9×10⁻³ D[34], and Rigetti's 108-qubit median 99.1% C[36].

The 72× leakage suppression and the 6.4(5)×10⁻⁴ residual come from one USTC device, unreplicated as of 2026-09-04; the paper does not name the processor, and the "Zuchongzhi 3.2" label comes from outside it. Not published: a leakage figure for IBM's fleet, whose EPLG aggregates all error mechanisms.

Nothing of its own: it inherits the carrier's 300 mm Nb/Al lithography, yield spread and one drive plus one readout line per qubit. That is the whole commercial argument — dual-rail erasure adds a rail and a check per qubit (384 ns, 2.54×10⁻² erasure D[85]), cat codes a pump and buffer mode. The I/O wall is the carrier's: coax per qubit, ~10³ qubits per fridge. What this encoding adds at 10⁴–10⁶ is leakage removal inside every 1.1 µs cycle and the decoder bandwidth to use it. Export exposure is the carrier's (US EAR ECCN 3A901).

The default Layer-2 encoding on the transmon lattice with tunable couplers (IBM, Google, Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu). Dual-rail erasure or cat encoding replaces it when a vendor trades control complexity for a friendlier error structure: Alice & Bob, AWS and D-Wave/Quantum Circuits have, IBM and Google have not. The price is quantifiable: measured dual-rail gate errors simulate to Λ ≈ 27 against 14 for 0.1% depolarising noise S[84], where this encoding measures 2.14 and 1.40(6) D[1], [3]. It adds nothing to the derived clock, which stays the carrier's 0.65 µs round inside its measured 1.1 µs cycle. Verification: the 72× is one unreplicated USTC device, and leakage is self-reported with no cross-vendor protocol.

Money.
2026-06-02 · IBM · investment commitment · > $10 B over five years · announced G[57]fact
2026-07-02 · IQM · Nasdaq and Helsinki listing · pro-forma cash €337 M · closed C[58]fact

Market & supply chain. No supply chain of its own; concentration sits one layer down, in Nb/Al lithography and dilution refrigerators. Being free, it is what every G1–G4 budget on this architecture buys.

IP & standards. No dated patent family found for bare-subspace leakage mitigation as of 2026-09-04; PatSnap's 2026-06-30 counts are not encoding-specific Pfact.

Roadmaps & track record. IBM (2025-06-10 · Starling, 200 logical / 10⁸ gates in 2029 · Nighthawk on plan, Kookaburra slipped a year fact). Google (2025 · long-lived logical qubit at 10⁻⁶ · no successor to Willow). Neither publishes a leakage target.

Strategic reading. Its edge is that it is free, so the fork is capital allocation: money spent switching to erasure is not spent scaling the bare fleet. If Λ stays near 2, erasure encodings win on physical qubits per logical; otherwise incumbents keep the field.

Confirm by end-2027: ≥ 50× leakage suppression in a below-threshold code outside USTC, or leakage published as a line item in a vendor's logical error budget; otherwise demote it to a single-device claim. Best case 2029: leakage falls under the correlated-event floor (≈10⁻¹⁰, hourly bursts on Willow D[1]); worst case, Λ stays near 2 and physical-per-logical above 10³. Does leakage or 2Q error dominate at 10⁴ qubits? Can removal keep up at 10⁶? Does erasure conversion ever cross over commercially?