IBM Quantum Eagle r1-r3

Raveh Neeman

doi:10.5281/zenodo.22674814

IBM

IBM Quantum Eagle r1-r3

IBM · superconducting circuits · RETIRED (launched Nov 2021) · 127 physical qubits · access: was cloud service

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: fixed-frequency transmon

gate mechanism: echoed cross-resonance (ECR)

connectivity: heavy-hex; QV 128

control: room-temperature RF; first IBM multi-level wiring + TSVs

control placement: room-temp

readout: multiplexed dispersive

gate evidence: a published figure (source class not yet tagged)

codes: floquet_color, google_dynamic_surface, heavy_hex, honeycomb_floquet, quantum_repetition, stab_4_2_2, xzzx

flags: claim rebutted

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▣ Fig. 4 (ibm_sherbrooke layout + readout error map); §III.5 ✅ fixed-frequency transmon; 127 q monolithic die (DEPLOYED Nov 2021, now RETIRED)
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	Cross-resonance (fixed-frequency, all-microwave) · primary ▤ §III.5 (native gates incl. ECR); Fig. 4 caption (median ECR error) ✅ echoed cross-resonance (ECR); median ECR error 7.5×10⁻³ (Oct 2024)
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▣ Fig. 3 (Eagle heavy-hex qubit layout); §III.5 ✅ heavy-hex, degree ≤3; QV 128
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▤ §III.5 (Eagle) ✅ room-temperature RF; first IBM device with multi-level wiring + TSVs, routing under the qubit plane (enabled 127 q)
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▣ Fig. 4 (readout error map of ibm_sherbrooke) ✅ multiplexed dispersive
7 Code	Rotated surface code (+ yoked variants) · primary ▤ Fig. 9 (data taken on sherbrooke) ✅ 3CX surface code d=3 embedded in heavy-hex, 2–6 rounds; heavy-hex code d=3/5 memory on brisbane/cusco/nazca/sherbrooke (arXiv:2311.15146) (sweep 7 Oct 2026, source read) Error mitigation in the code slot (ZNE, PEC) — not a code · alternate ▤ 🔎 error mitigation (ZNE) in the code slot; 127-q Ising-dynamics "utility" experiments (2023)
8 Decoder	— none — nothing in this layer ▤ 🔎 no decoder; no QEC run
9 Interconnect	Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▦ O. Dial, 23 Mar 2022, §packaging ✅ qubit wafer bump-bonded to an interposer wafer; three-level multi-layer wiring in the interposer carries control and readout; through-substrate vias in both chips
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ §III.5 (Eagle) ✅ IBM 200 mm superconducting-qubit lithography; multi-level wiring + TSVs

Standard records

2Q error under full-width parallel operation → 7.40e-3 · typical (median ECR, ibm_sherbrooke)

Eagle r3 fleet spans 7.1e-3 to 1.24e-2 · Oct 2024 · source

evidence: ✅ 8 / 11

Pictures

Every picture carries the story of what it shows and its credit line.

File:Keynote - Entering the Era of Quantum Utility (IBM Research) 09.png — A frame from a keynote video showing a slide: a 2016–2021 timeline and a computer render of the package lid of IBM's Eagle processor, printed '127 QUBITS' and 'PACKAGING'. Published by IBM Research on 2023-12-05 from the keynote 'Entering the Era of Quantum Utility'; the footer reads IBM Quantum Summit 2023. It marks the 2021 Eagle superconducting processor as a roadmap milestone, but it is a render of the closed package; no chip or qubits are visible. “Keynote - Entering the Era of Quantum Utility (IBM Research) 09” by IBM Research, commons.wikimedia.org/wiki/File:Keynote_-_Entering_the_Era_o…, CC BY 3.0 (creativecommons.org/licenses/by/3.0/)

File:Keynote - Entering the Era of Quantum Utility (IBM Research) 06.png — A frame from a keynote video: a slide titled 'Tunable Coupler architecture – Performance' with a small render of an IBM Quantum processor, a line drawing of a heavy-hex qubit layout, and text comparing Eagle R3 with Heron R1. It comes from IBM Research's keynote 'Entering the Era of Quantum Utility' (IBM Quantum Summit 2023). It contrasts fixed-frequency cross-resonance (ECR) gates with tunable-coupler CZ gates on superconducting processors: notice Heron's 96 ns CZ versus Eagle's 537 ns ECR, allowing more gates despite a shorter mean T1. “Keynote - Entering the Era of Quantum Utility (IBM Research) 06” by IBM Research, commons.wikimedia.org/wiki/File:Keynote_-_Entering_the_Era_o…, CC BY 3.0 (creativecommons.org/licenses/by/3.0/)

Fig. 3 — NL-based benchmarking using LR-QAOA for WMC problems; (a) QPU layouts used in each experiment — Three-panel paper figure made of drawings and data plots, from an arXiv paper by J. A. Montanez-Barrera, Kristel Michielsen and David E. Bernal Neira (2025-05-28) on benchmarking processors with linear-ramp QAOA. Panel (a) draws the qubit coupling graphs of 5-, 20-, 127-, 133- and 156-qubit processors, including IBM Heron devices; panels (b) and (c) plot approximation ratio against the number of QAOA layers. Notice the fixed nearest-neighbour lattices: the sparse heavy-hex patterns versus the denser square lattice limit which qubits can interact directly. “Fig. 3 — NL-based benchmarking using LR-QAOA for WMC problems; (a) QPU layouts used in each…” by J. A. Montanez-Barrera, Kristel Michielsen, David E. Bernal Neira, arxiv.org/abs/2502.06471, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)