← Quantum Technology AtlasTechnologies · Machines · Architectures · OrganisationsРусскийעברית

Transmon transmon

Capacitively shunted Josephson junction (Koch 2007); the carrier behind Willow, Heron/Nighthawk and Zuchongzhi, with the fastest deterministic gate and QEC cycle of any demonstrated qubit.

Transmon

transmon · layer 1 Qubit carrier · demonstrated · since 2007
Open on the map

Anharmonic LC oscillator; ~200–300 MHz anharmonicity bounds gates at ~10 ns; T1 ~70–100 µs.

Brief →

Key references

[282] J. Koch et al., “Charge-insensitive qubit design derived from the Cooper pair box,” Phys. … · 2007
[283] H. Paik et al., “Observation of High Coherence in Josephson Junction Qubits Measured in a … · 2011
[284] R. Barends et al., “Superconducting quantum circuits at the surface code threshold for fau… · 2014
[291] F. Arute et al., “Quantum supremacy using a programmable superconducting processor,” Natur… · 2019
[292] J. Gambetta, “The hardware and software for the era of quantum utility is here,” IBM Quant… · 2023

Design space — attributes

(a) carrier affinity
fabricated
(b) time · entangling
10 ns · deterministic
(c) readout
dispersive microwave · 316 ns · non-destructive · mid-circuit
(d) mobility
static nearest-neighbour wiring
(e) control
microwave @ room temperature
(f) error structure
leakage, stochastic Pauli, correlated bursts, coherent / calibration
(g) manufacturing
superconducting lithography

Evaluation space — dated attributes

Willow mean T1 / T2,CPMG → 68 µs / 89 µs (QEC chip)
defines: error channel · 2024-12 · source
Willow mean simultaneous CZ error → 0.33 ± 0.18% (spec sheet)
defines: error channel · 2024-12 · source
correlated burst rate → ~1 per hour on the 72-qubit processor (d=29 repetition code, 3×10⁹ cycles); decay ~400 µs; 10⁻¹⁰ logical floor
defines: error channel · 2024-12 · source

Willow 105 q; IBM Heron/Nighthawk 156/120 q; Zuchongzhi 3.x 105–107 q.

Standard records

T1 relaxation → 68 µs · typical
Willow 105-qubit QEC chip: mean operating T1 = 68 us (spec sheet: 68 +/- 13 us; RCS chip 98 +/- 32 us) · 2024-12 · source [D] ⓘ
T1 relaxation → 1.7 ms · best
Princeton Ta-on-Si 2D transmons: T1 up to 1.68 ms; median time-averaged Q_avg 9.7e6 across 45 qubits · 2025-11 · source [D] ⓘ
T2 coherence (echo/DD) → 89 µs · typical
Willow 105-qubit QEC chip: mean T2,CPMG = 89 us · 2024-12 · source [D] ⓘ
1Q gate time → 25 ns · typical
Willow 105 q: all XY single-qubit rotations 25 ns (72-q processor: pi 35 ns, pi/2 18 ns) · 2024-08 · source [D] ⓘ
idle / memory error per round → 9.00e-3 · typical
Google 72-q surface-code error budget: data-qubit idle error 0.9e-2 per cycle, weight 10, 20% of 1/Lambda · 2024-08 · source [D] ⓘ
leakage per gate → 2.00e-4 · typical
Google error budget: CZ leakage 2.0e-4 per gate; a separate 'leakage (heating)' term is 2.5e-4 · 2024-08 · source [D] ⓘ
correlated-burst rate → 2.8e-4 Hz · typical
72-q processor, distance-29 repetition code: correlated error bursts approx. once an hour (3e9 cycles), decay ~400 us · 2024-08 · source [D] ⓘ

Actors & goals — annotations

Transmon lattice with tunable couplers — IBM (Heron, Nighthawk), Google (Willow), Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu/RIKEN, QuantWare · G2 G3 G4
Dual-rail erasure qubits (alternate) — D-Wave/QCI, AWS, SUSTech · G3 G4

Edges

needs: Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm)
needed by: Tunable-coupler CZ / iSWAP°, Cross-resonance (fixed-frequency, all-microwave), Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter)·, Bare physical qubit (no encoding)°, Dispersive microwave readout (+TWPA, Purcell)°, Microwave–optical transducer (useful efficiency), Fast unconditional / dissipative qubit reset, Dual-rail (erasure) encoding°
alternatives: Fluxonium
conflicts with:
SFQ digital control (4 K / mK) open — no mitigation shown at scale
SFQ switching photons cause quasiparticle poisoning unless shielded (0.96% error source in 2023 MCM)
price photons emitted by switching junctions lie above the aluminium gap (2Δ ≈ 90 GHz) and break Cooper pairs in the qubit film: T1 decay plus correlated, non-Pauli bursts; 0.96(2)% of the 1.2(1)% error per Clifford in the 2023 multi-chip module
mitigation driver on a separate die, pulse-bandwidth limiting (projected 0.1%), quasiparticle traps / gap engineering, mm-wave shielding; SEEQC 2026 reports no detectable poisoning at 5 qubits (press, not independently measured) · 2023-09
GPU decoding via NVQLink open — no mitigation shown at scale
GPU decoding over NVQLink adds a ~4 µs round trip to a ~1 µs surface-code cycle
price NVQLink's measured round trip is 3.84 µs mean / 3.96 µs max, i.e. 3–4 surface-code cycles of a Willow-class transmon (~1.1 µs): syndromes queue faster than any single-cycle reaction, so real-time feed-forward (non-Clifford, teleportation) must wait
mitigation windowed / streaming decoding with an FPGA predecoder at the fridge, deferring only the reaction-critical decisions; slower carriers (atoms, ions: ms cycles) do not see the conflict · 2025-11
Microwave–optical transducer (useful efficiency) open — no mitigation shown at scale
the transducer's optical pump at the millikelvin stage creates quasiparticles and heats the qubit chip
price the optical pump light that drives the conversion reaches the mixing chamber: its stray light breaks Cooper pairs and heats the stage, so the first qubit-to-photon transduction ran the pump pulsed at a low duty cycle
mitigation pulsed, low-duty-cycle pumping; the transducer on a separate chip or module with filtered optical access · 2020-12
Cryo-CMOS controller (4 K / mK) mitigated at small scale
milliwatt-class CMOS dissipation at the mixing chamber against a cooling budget of tens of microwatts
price a full CMOS controller dissipates milliwatts; the mixing chamber of a dilution refrigerator offers tens of microwatts, so the controller sits at 3–4 K (< 2 mW per channel set, 2019) and only microwatt-class parts — multiplexers, switches — go beside the transmons
mitigation the controller at the 4 K stage with wiring down to the qubits; a millikelvin multiplexer that routes pulses without generating them; spin qubits operated at ~1 K do not see the conflict · 2019-11
° one of several that would do · the usual route, not a strict need

Used by 84 machines (84 primary · 0 alternate)

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 3 — Figure 3: cQAD device based on a microring cavity. a, Schematic of the flip-chip assembly. The phononic microring cavity is fabricated on a top chip…
A seven-panel paper figure: a 3D render of two stacked chips (11 mm and 15 mm square), optical micrographs of a phononic ring resonator and of the qubit chip, and data plots. It comes from the arXiv paper "Circuit Quantum Acoustodynamics in a Scalable Phononic Integrated Circuit Architecture" by Weiting Wang, Luyan Sun and co-authors. It shows a superconducting transmon qubit on one chip talking to a sound resonator on another: an interdigital transducer on the ring and facing capacitor pads link the two across the flip-chip gap. “Fig. 3 — Figure 3: cQAD device based on a microring cavity. a, Schematic of the flip-chip assembly. The phononic microring cavity is fabricated on a top chip of 11 mm…” by Weiting Wang et al., arxiv.org/abs/2512.04953, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1 — Figure 1: (a) CAD rendering of the transmon emitter/detector (TED) layout and (b) its corresponding circuit, indexed by x∈{s,m}x\{s,m\} to distingui…
A four-panel figure: a CAD rendering of a superconducting chip layout (200 µm scale bar), its circuit diagram, a measured plot of frequency against applied flux, and a block schematic of source and detector devices. It comes from the arXiv paper "Transmon Architecture for Emission and Detection of Single Microwave Photons" by Daniel L. Campbell and co-authors. It shows three coupled transmons — storage, waveguide-linked, and a flux-driven coupler between them — that release or catch single microwave photons; notice the storage transmon's frequency barely moves. “Fig. 1 — Figure 1: (a) CAD rendering of the transmon emitter/detector (TED) layout and (b) its corresponding circuit, indexed by x∈{s et al., arxiv.org/abs/2601.11378, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1a — False-colored optical microscope image of a transmon qubit (tantalum capacitor islands on sapphire)
A four-panel paper figure: (a) a false-coloured optical micrograph of a transmon, two large tantalum capacitor pads (blue) separated by a narrow gap on sapphire (grey); (b) the chip with its meander readout resonator and circuit; (c) an energy-decay curve with T1 = 0.36 ± 0.01 ms; (d) resistance versus temperature, stepping near 4.4 K. From Place, Rodgers, Mundada et al. (Princeton, Houck and de Leon groups), Nature Communications 12, 1779 (2021). The Josephson junction sits in the gap, shunted by the pads; tantalum was chosen to lengthen coherence. “Fig. 1a — False-colored optical microscope image of a transmon qubit (tantalum capacitor islands on sapphire)” by Alexander P. M. Place, Lila V. H. Rodgers, Pranav Mundada, et al. (Princeton, Houck / de Leon groups), www.nature.com/articles/s41467-021-22030-5, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
transmon · layer 1 Qubit carrier · centrality 10.9 · demonstrated · since 2007 · updated 2026-09-30

Transmon

Capacitively shunted Josephson junction (Koch 2007); the carrier behind Willow, Heron/Nighthawk and Zuchongzhi, with the fastest deterministic gate and QEC cycle of any demonstrated qubit.

Verdict. Best-funded and fastest carrier, capped by ~10⁻³ two-qubit and ~10⁻² readout errors at scale and hourly correlated bursts. Confirm if a ≥100-qubit lattice shows Λ ≥ 3 with median 2Q error < 10⁻³ by 2028; otherwise demote to component status.

Key references

Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).

Identity & lineage

A transmon is an Al/AlOx/Al Josephson junction shunted by a large capacitor so that EJ/E_C ≈ 50–100 D[282]. Charge dispersion falls exponentially in √(8E_J/E_C), removing 1/f charge noise at the price of a weak anharmonicity α ≈ −EC ≈ −200 to −300 MHz; the qubit is the lowest two levels of a 4–6 GHz oscillator D[282]. Koch et al. proposed it in 2007 D[282]; the 3D transmon (2011) D[283] and the UCSB/Google Xmon (2014) D[284] fixed the two lineages still in use, fixed-frequency (IBM) and flux-tunable (Google, IQM, USTC).

Attributes (technology graph):

  • a: affinity 1.0, fabricated (no natural counterpart).
  • b: characteristic time 10⁻⁸ s, deterministic entangling; the 1/α leakage bound puts the pulse floor near 10 ns.
  • c: readout dispersive microwave, ≈ 320 ns (10^−6.5 s), non-destructive, mid-circuit capable.
  • d: mobility static, nearest-neighbour wiring.
  • e: control microwave from room-temperature electronics; cold-stage variants (cryo-CMOS or SFQ) at ≤ 5 qubits.
  • f: error structure leakage + stochastic Pauli + correlated bursts + coherent/calibration.
  • g: manufacturing superconducting lithography.

Physics & limits

Residual thermal population (0.1% at 35 mK in a 3D transmon D[285], ≈ 1% at 40–60 mK for a 5 GHz qubit S[285]) makes reset and readout the SPAM floor. Anharmonicity bounds single-qubit gates at 10–25 ns and tunable-coupler CZ at 25–50 ns D[1], [37]P[286]; cross-resonance takes ≈ 200–500 ns D[287].

The floor is decoherence over gate time: with Willow's mean T1 = 68 µs D[1] a 40 ns CZ carries ≈ 6×10⁻⁴ of incoherent error S[1]; at the record T1 = 1.68 ms of a single Ta-on-Si test transmon D[288] it falls below 5×10⁻⁵ S[288]. Loss is dominated by two-level systems (TLS) in amorphous interface oxides D[288], with quasiparticles, Purcell decay and flux noise below.

Most of the twirled channel is stochastic Pauli, so Willow's Λ = 2.14 D[1] matches theory. Leakage to |2⟩ accumulates under QEC unless removed each cycle (USTC's all-microwave reset cut it 72×, to 6.4×10⁻⁴, on 107 qubits D[3]). Coherent errors (residual ZZ, TLS drift) forced reinforcement-learning recalibration inside Google's 2026-07 QEC run D[2]. Correlated bursts (ionising particles flooding the chip with quasiparticles) hit all qubits at once — roughly one per 10 s on Sycamore in 2021 D[289], about one per hour on Willow after gap engineering D[1], [290] — truncating long memory runs by bursts, not distance. Moving the floor means new materials (Ta, encapsulated Nb), fluxonium-scale anharmonicity, radiation management or erasure conversion (dual-rail).

Long-lived TLS are not specific to fluxonium junction chains: a flux-tunable transmon at Forschungszentrum Jülich showed 44 of them per GHz, spread uniformly over 3–4.5 GHz and each blocking about 2 MHz, so about 9% of the tunable band is affected; the memory they give the environment spans 20 µs to 1 ms, and 58% of them outlive the qubit P[890]. Energy stored in them re-excites the qubit after it is driven, an error that T1 and relaxation spectroscopy do not show.

Engineering state of the art

Best isolated devices: T1 1.68 ms, Q 2.5×10⁷, 1Q 99.994% D[288]; CZ 99.93% and 280 ns readout at 99.94% on a two-qubit IQM chip D[38]; Toshiba's double-transmon coupler CZ 99.90% in 48 ns D[37].

Typical at ≥ 100 qubits: Willow, 105 q — mean T1 68 µs, CZ error 0.33%, readout 99.5%, QEC cycle 1.1 µs D[1]C[32]; IBM fleet error-per-layered-gate 3.7×10⁻³ typical, 1.9×10⁻³ best (2026-07) C[34]; Zuchongzhi 3.0, 105 q — 2Q 99.62%, readout 99.13% D[35]; Rigetti Cepheus-1-108Q, twelve 9-qubit chiplets C[36] — median 2Q 99.1% Cfact.

table
Year Figure Who Evidence
2019 Sycamore 53 q, simultaneous 2Q error 0.62% Google D[291]
2023 Condor, 1,121 qubits on one chip IBM C[292]
2024 Willow 105 q, Λ = 2.14 Google D[1]
2025 2D transmon T1 1.68 ms Princeton D[288]
2026 d=7 logical error 7.72×10⁻⁴ per cycle Google D[2]

At scale the two-qubit gate is the largest error term (~40% of Google's colour-code budget) D[41], then readout (~10⁻² on fleets C[34]) and leakage; the lattice tail matters more than the median.

Manufacturing, materials & supply chain

Process: Nb or Ta on high-resistivity Si or sapphire; shadow-evaporated Al/AlOx/Al junctions; flip-chip 3D integration. On 300 mm CMOS tooling imec/KU Leuven reported 393 of 400 working transmons (98.25%), median T1 ≈ 75 µs (42–113 µs) D[293]fact: uniformity, not coherence. Fixed-frequency lattices must also hit frequency targets (junction scatter becomes collisions) by laser annealing (IBM), alternating-bias annealing (Rigetti, 97.4% success) D[294] or tunable couplers.

Cost and energy: no vendor publishes $/qubit; proxies are IQM's €33 M LUMI contract P[295] and IBM's 14 nm cryo-controller at 23 mW per qubit at 4 K D[296] — tens of watts at 10³ qubits; SFQ control claims nW per qubit C[54].

Supply chain: dilution refrigerators from Bluefors (FI), Oxford Instruments (UK), FormFactor and Maybell (US); ³He from tritium decay in state inventories (US: NNSA G[297]), no merchant producer; 4 K HEMT (high-electron-mobility transistor) amplifiers effectively one vendor (Low Noise Factory, SE); control electronics competitive (Quantum Machines, Qblox, Zurich Instruments); merchant QPUs from QuantWare (NL) P[298]; foundries Anderon (IBM Albany spin-off, 2026-05; $1 B CHIPS letter of intent, $1 B IBM cash stated separately) P[299]G[300] and GlobalFoundries ($375 M LOI) G[300].

Export controls: the BIS interim final rule of 2024-09-06 covers dilution refrigerators ≥ 600 µW at 0.1 K for 48 h (3A904), cryogenic wafer probers (3B904), parametric amplifiers (3A901.b) and quantum computers (4A906) only where qubit count and C-NOT error fall in the same band — 34–99 qubits at ≤ 10⁻⁴, 100–199 at ≤ 10⁻³, the ceiling rising to 6 × 10⁻³ below 2,000 qubits, any error from 2,000 on G[301]fact; Chinese vendors therefore build 10 mK refrigerators domestically (2026-05-15) P[302].

Control, readout & I/O burden

A tunable lattice needs one XY and one Z line per qubit plus one per coupler (Sycamore: ≈ 3.6 control lines per qubit before readout D[291]); readout multiplexes ≈ 6–10 qubits per feedline D[1]; each line is a DAC channel plus attenuated coax, so cost and heat scale with N.

Latency: the QEC cycle is 1.1 µs; Google's real-time decoder ran at 63 µs mean latency for d=5 D[1]; IBM's Relay-BP targets < 1 µs per cycle in simulation S[48] for the gross code (IBM's [[144,12,12]] bivariate bicycle qLDPC code, 12 logical qubits in 288 physical D[248]).

Walls: 10³ reached (Condor, 1,121 qubits C[292]); Bluefors' KIDE (> 4,000 RF lines, > 1,000 qubits; product page, 2026-06) C[303] is one cryostat's ceiling. 10⁴ needs 4 K cryo-CMOS (HRL: d=5 repetition code from a ≤ 3.5 W controller D[190]fact) or millikelvin SFQ (SEEQC: 1Q up to 99.9% on ≤ 5 qubits D[304]fact) plus multi-cryostat modules (IBM coupled two cells, 2026-08 C[50]). 10⁶ has no closed design: on-chip flux DACs, cold decoding and inter-fridge links (ETH: 30 m at 80.4% Bell fidelity D[305]) are sub-scale.

Role in the stack

Architectures: the transmon lattice with tunable couplers and the dual-rail erasure architecture (transmon as ancilla or one rail). Requires superconducting lithography; provides the carrier for tunable-coupler and cross-resonance gates, the ancilla for bosonic-cavity gates, the bare-qubit subspace, the dispersive shift for microwave readout and the microwave side of the optical transducer. Replaced by fluxonium, which buys anharmonicity and T1 for a flux bias per qubit, sub-GHz control and redesigned readout. Conflicts with SFQ control: switching photons poisoned qubits with quasiparticles in the 2023 multi-chip module (0.96 of 1.2% error per Clifford) D[249]; SEEQC claims it engineered away C[54], so the conflict stands until an independent lattice-scale check. Derived clock of the transmon-lattice architecture ≈ 6.5×10⁻⁷ s (651 ns; derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture), readout 282 ns of it and readout-plus-reset two-thirds, against the measured 1.1 µs Willow cycle D[1] — the fastest demonstrated architecture, which G4 (large-scale fault tolerance) pays for. Bordering empty slots: the microwave–optical transducer (≈ 3 orders of magnitude short of remote gates S[306]) and cryogenic decoding.

Evidence — how the numbers were measured

Headline numbers come from Clifford RB/IRB, simultaneous XEB (Google), IBM's layer fidelity/EPLG and readout assignment matrices; Λ is a fit of logical error vs distance under one decoder. Missed here: isolated vs simultaneous operation (record chips are isolated); coherent errors averaged into a depolarising number; leakage, invisible to RB and often post-selected away; drift between calibration and use; and conventions (Rigetti quotes medians, IBM its best device, IQM a two-qubit chip). IBM's 2026-07 "70 logical qubits" is an error-detecting, post-selected result D[46], not fault tolerance.

Replication: below-threshold scaling reproduced by USTC on 107 qubits with Λ = 1.40 D[3]. Disputes: 2019 supremacy sampling reproduced by tensor networks D[307]; the 2023 IBM "utility" experiment simulated classically within weeks D[308], [309]; Google's 2026-07 paper reports no Λ for the d=7 run D[2]. Value conflict: imec's 300 mm T1 is often quoted as "> 100 µs"; the paper's median is ≈ 75 µs D[293]fact, used here.

The ≈ 200–500 ns cross-resonance gate time is a fleet-typical range inferred from a single-device paper [287]. That 4 K HEMT amplifiers come effectively from one vendor (Low Noise Factory) is a market observation without a database source. Not published: a launch date for Bluefors KIDE (> 4,000 RF lines / > 1,000 qubits), whose product page was revised 2026-06-16.

Actors & economics

Who.
Organisation Role Country Activity Evidence
Google Quantum AI developer US Willow 105 q, Λ = 2.14; d=7 memory D[1], [2]
IBM developer US Heron/Nighthawk fleet; Starling roadmap; Anderon spin-out C[34], [67]P[299]
Rigetti developer US Cepheus-1-108Q chiplets; own fab C[61]
IQM developer FI 26 systems sold, 17 installed C[58]fact
USTC research CN Zuchongzhi 3.x, 105 q; Λ = 1.40 D[3], [35]

Money.

  • 2025-11-06 · DARPA · QBI Stage B (up to $15 M each) · IBM the only transmon-lattice vendor of eleven; Google and Rigetti stayed at Stage A G[65]factfact
  • 2026-01-20 · D-Wave · M&A, Quantum Circuits (dual-rail cavities on transmon ancillae) · $550 M (stock + cash) · closed C[14]factfact
  • 2026-05-05 · QuantWare (merchant QPUs; VIO-40K roadmap — VIO is its vertical-wiring architecture Rfact) · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners (new investors, no lead) · > $210 M cumulative · closed P[298]
  • 2026-05-18 · Nord Quantique · growth-equity financing · $30 M at a $1.4 B valuation · closed C[89]fact
  • 2026-05-21 · US Dept of Commerce · CHIPS letters of intent ($2.013 B, nine companies) · IBM/Anderon $1 B, GlobalFoundries $375 M, Rigetti ≤ $100 M, D-Wave $100 M · non-binding LOI G[300]fact
  • 2026-06-02 · IBM · commitment · > $10 B over five years, the $1 B cash into Anderon stated separately · announced C[310]fact
  • 2026-06-03 · OQC (coaxmon developer D[311]) · Series C · £260 M (~$350 M) · led by Bullhound · valuation undisclosed · closed C[60]fact
  • 2026-07-02 · IQM · listing, Nasdaq and Helsinki · pro-forma cash €337 M · closed Cfact
  • 2026-08-04 · IQM · H1-2026 results · revenue €8.9 M (+47%), cash €309 M · reported P[295]
  • 2026-08-06 · Rigetti · Q2-2026 results · revenue $5.1 M, GAAP loss $52.6 M, cash $541.3 M · reported C[61]

Market & supply chain. Enabling equipment is more concentrated than the QPU market. Unit economics are unpublished; the €33 M IQM contract P[295] and the $550 M Quantum Circuits price Cfact are the only quotable points. Paying goals: G7 (deployable systems) and G2 (error-mitigated utility) today; G3 (early fault tolerance) via QBI-style programmes from 2027 fact; G4 (large-scale fault tolerance) after 2029 Rfact; G1 (analogue simulation), G5 (optimisation) and G6 (networking) bring no transmon-specific revenue.

IP & standards. PatSnap's landscape published on 2026-06-30: IBM 4,388 quantum patent families, Google 2,385, Microsoft 1,175; superconducting devices (H10N 60) IBM 783, Google 357 P[312]fact. No litigation found; no transmon-specific family verified. Open stacks commoditise the layer above: Qiskit (IBM claims ≈ 70% of developers C[310]), Cirq/Stim, OpenQASM 3, NVQLink Cfact.

Roadmaps & track record.

  • IBM Kookaburra (2022-05-10 · 2025, as a 1,386-qubit multi-chip processor C[313]; re-promised 2025-06-10 · 2026, as the first qLDPC module R[67] · not delivered as of 2026-09-03 R[72]fact).
  • IBM Nighthawk (2025-06-10 · 2025 · delivered 2025-12) and Starling (2025-06-10 · 2029, 200 logical / 10⁸ gates · open) Rfact.
  • Google milestone 3, 10⁻⁶ logical error (undated · no Willow successor published; neutral-atom track opened 2026-03-24) R[2]fact.
  • Rigetti 108 q at 99.5% (promised for end-2025 · GA 2026-04-07 at median 99.1%; 99.5% moved to "later 2026") Cfact.
  • Fujitsu/RIKEN 1,000 qubits (promised 2025-04-22 · fiscal 2026 · not launched as of 2026-09-03) R[75]fact.
    Credibility: IBM high on cadence, weak on its first qLDPC module and on "advantage" claims; Google high on physics, opaque on schedule; Rigetti chronic slips; Fujitsu unproven.

Strategic reading. If transmons win, foundry owners and cryogenic suppliers win regardless of vendor; fabless transmon start-ups lose — consolidation (Atlantic Quantum → Google, 2025-10-03 P[55]fact; Quantum Circuits → D-Wave) is visible. Substitution threats: fluxonium in the same fab, dual-rail/bosonic encodings that demote the transmon to an ancilla, atoms and spins for density. ³He, HEMT and fridge suppliers hold bargaining power; platform vendors escape by vertical integration.

Outlook & open questions

Milestones, 12–24 months: (1) Kookaburra runs a gross-code memory below break-even — confirm; nothing by end-2027 demotes IBM's 2029 date Rfact. (2) Google publishes Λ ≥ 3 or a 10⁻⁶ logical memory at d ≥ 9 — confirm; a second year without a Willow successor demotes D[2]. (3) QBI Stage C (expected around Q4 2026 factP[314]) promotes a transmon vendor. (4) cryo-CMOS or SFQ drives ≥ 50 transmons without a fidelity penalty D[190], [304]. Best case 2029: a Starling-class 200-logical machine Rfact and a d ≥ 11 Google memory; worst: Λ near 2, readout at 10⁻², bursts cap distance, the transmon survives only as an ancilla and capital rotates to atoms and spins. Open questions: does millisecond Ta/Si coherence survive a 100-qubit process with couplers; is the at-scale 2Q floor coherent (calibration) or incoherent; can readout reach 10⁻³ in < 300 ns across a lattice. Watch: Google's next paper, Kookaburra, the Stage C list.

References
  1. [1] Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature, vol. 638, no. 8052, pp. 920–926, Dec. 2024, doi: 10.1038/s41586-024-08449-y. D
  2. [2] V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature, vol. 655, no. 8124, pp. 879–884, Jul. 2026, doi: 10.1038/s41586-026-10759-2. D
  3. [3] T. He et al., “Experimental Quantum Error Correction below the Surface Code Threshold via All-Microwave Leakage Suppression,” Phys. Rev. Lett., vol. 135, no. 26, Art. no. 260601, Dec. 2025, doi: 10.1103/rqkg-dw31. D
  4. [14] D-Wave Quantum Inc., “D-Wave Announces Agreement to Acquire Quantum Circuits Inc., Establishing World's Leading Quantum Computing Company,” Jan. 7, 2026. [Online]. Available: https://www.dwavequantum.com/company/newsroom/press-release/d-wave-to-acquire-quantum-circuits-inc-establishing-world-s-leading-quantum-computing-company/ C
  5. [32] Y. Chen and M. Devoret, “Our quantum hardware: the engine for verifiable quantum advantage,” Google Blog, Oct. 22, 2025. [Online]. Available: https://blog.google/innovation-and-ai/technology/research/quantum-hardware-verifiable-advantage/ C
  6. [34] IBM Quantum, “What's new at IBM Quantum - Q2 2026.” [Online]. Available: https://www.ibm.com/quantum/blog/whats-new-q2-2026 C
  7. [35] D. Gao et al., “Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor,” Phys. Rev. Lett., vol. 134, Art. no. 090601, Mar. 2025, doi: 10.1103/PhysRevLett.134.090601. arXiv:2412.11924. D
  8. [36] Rigetti Computing, Inc., “Rigetti Announces General Availability of 108-Qubit System,” Apr. 7, 2026. [Online]. Available: https://investors.rigetti.com/news-releases/news-release-details/rigetti-announces-general-availability-108-qubit-system C
  9. [37] R. Li, K. Kubo, Y. Ho, Z. Yan, Y. Nakamura, and H. Goto, “Realization of High-Fidelity CZ Gate Based on a Double-Transmon Coupler,” Phys. Rev. X, vol. 14, no. 4, Art. no. 041050, Nov. 2024, doi: 10.1103/PhysRevX.14.041050. arXiv:2402.18926. D
  10. [38] F. Marxer et al., “Above 99.9% Fidelity Single-Qubit Gates, Two-Qubit Gates, and Readout in a Single Superconducting Quantum Device,” PRX Quantum, vol. 7, Art. no. 020333, 2026, doi: 10.1103/n86s-2b88. arXiv:2508.16437. D
  11. [41] N. Lacroix et al., “Scaling and logic in the color code on a superconducting quantum processor,” Nature, vol. 645, no. 8081, pp. 614–619, May 2025, doi: 10.1038/s41586-025-09061-4. arXiv:2412.14256. D
  12. [46] S. Martiel et al., “Sampling hard circuits with verifiably high fidelity,” arXiv:2607.25941, Jul. 2026. D
  13. [48] T. Maurer et al., “Real-time decoding of the gross code memory with FPGAs,” arXiv:2510.21600, Oct. 2025. S
  14. [50] C. Dundon, S. Hall, M. Hollister, and A. Lindler, “IBM's new modular architecture for cryogenic systems,” IBM Quantum Computing Blog, Aug. 19, 2026. [Online]. Available: https://www.ibm.com/quantum/blog/modular-cryogenics C
  15. [54] M. Abdel-Kareem, “SEEQC and IBM Collaborate on SFQ Control Integration Under DARPA's Quantum Benchmarking Initiative,” Quantum Computing Report, Jun. 12, 2025. [Online]. Available: https://quantumcomputingreport.com/seeqc-and-ibm-collaborate-on-sfq-control-integration-under-darpas-quantum-benchmarking-initiative/ C
  16. [55] M. Swayne, “Atlantic Quantum Joins Google Quantum AI,” The Quantum Insider, Oct. 3, 2025. [Online]. Available: https://thequantuminsider.com/2025/10/03/atlantic-quantum-joins-google-quantum-ai/ P
  17. [58] IQM Quantum Computers, “IQM Quantum Computers Becomes First European Quantum Computing Company Listed on a Major U.S. Exchange,” Jul. 2, 2026. [Online]. Available: https://iqm.tech/press-releases/iqm-quantum-computers-becomes-first-european-quantum-computing-company-listed-on-a-major-u-s-exchange/ C
  18. [60] A. Curbison, “OQC raises £260m in Europe's largest ever private quantum computing funding round,” OQC, Jun. 2, 2026. [Online]. Available: https://oqc.tech/company/newsroom/series-c C
  19. [61] Rigetti Computing, “Rigetti Computing Reports Second Quarter 2026 Financial Results,” Rigetti Investor Relations, Aug. 6, 2026. [Online]. Available: https://investors.rigetti.com/news-releases/news-release-details/rigetti-computing-reports-second-quarter-2026-financial-results C
  20. [65] DARPA, “Stage B selection,” Nov. 6, 2025. [Online]. Available: https://www.darpa.mil/research/programs/quantum-benchmarking-initiative/stage-b-selection G
  21. [67] IBM, “IBM Sets the Course to Build World's First Large-Scale, Fault-Tolerant Quantum Computer at New IBM Quantum Data Center,” Jun. 10, 2025. [Online]. Available: https://newsroom.ibm.com/2025-06-10-IBM-Sets-the-Course-to-Build-Worlds-First-Large-Scale,-Fault-Tolerant-Quantum-Computer-at-New-IBM-Quantum-Data-Center C
  22. [72] IBM, “Quantum Roadmap.” [Online]. Available: https://www.ibm.com/roadmaps/quantum/ R
  23. [75] Fujitsu, “Fujitsu Quantum.” [Online]. Available: https://global.fujitsu/en-global/technology/research/quantum R
  24. [89] Nord Quantique, “Nord Quantique Reaches $1.4 Billion USD Valuation with Latest Investment,” Business Wire, May 18, 2026. [Online]. Available: https://www.businesswire.com/news/home/20260518358351/en/Nord-Quantique-Reaches-$1.4-Billion-USD-Valuation-with-Latest-Investment C
  25. [190] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216, Apr. 2026. D
  26. [248] S. Bravyi et al., “High-threshold and low-overhead fault-tolerant quantum memory,” Nature, vol. 627, no. 8005, pp. 778–782, Mar. 2024, doi: 10.1038/s41586-024-07107-7. arXiv:2308.07915. D
  27. [249] C. Liu et al., “Single Flux Quantum-Based Digital Control of Superconducting Qubits in a Multichip Module,” PRX Quantum, vol. 4, no. 3, Art. no. 030310, Jul. 2023, doi: 10.1103/PRXQuantum.4.030310. D
  28. [282] J. Koch et al., “Charge-insensitive qubit design derived from the Cooper pair box,” Phys. Rev. A, vol. 76, no. 4, Art. no. 042319, Oct. 2007, doi: 10.1103/PhysRevA.76.042319. arXiv:cond-mat/0703002. D
  29. [283] H. Paik et al., “Observation of High Coherence in Josephson Junction Qubits Measured in a Three-Dimensional Circuit QED Architecture,” Phys. Rev. Lett., vol. 107, no. 24, Art. no. 240501, Dec. 2011, doi: 10.1103/PhysRevLett.107.240501. arXiv:1105.4652. D
  30. [284] R. Barends et al., “Superconducting quantum circuits at the surface code threshold for fault tolerance,” Nature, vol. 508, no. 7497, pp. 500–503, Apr. 2014, doi: 10.1038/nature13171. arXiv:1402.4848. D
  31. [285] X. Y. Jin et al., “Thermal and Residual Excited-State Population in a 3D Transmon Qubit,” Phys. Rev. Lett., vol. 114, no. 24, Art. no. 240501, Jun. 2015, doi: 10.1103/PhysRevLett.114.240501. arXiv:1412.2772. D
  32. [286] C. Choucair, “Oxford Researchers Demonstrate Fast, 99.8% Fidelity Two-Qubit Gate Using Simplified Circuit Design,” The Quantum Insider, Mar. 26, 2025. [Online]. Available: https://thequantuminsider.com/2025/03/26/oxford-researchers-demonstrate-fast-99-8-fidelity-two-qubit-gate-using-simplified-circuit-design/ P
  33. [287] A. Kandala et al., “Demonstration of a High-Fidelity CNOT Gate for Fixed-Frequency Transmons with Engineered ZZ Suppression,” Phys. Rev. Lett., vol. 127, no. 13, Art. no. 130501, Sep. 2021, doi: 10.1103/PhysRevLett.127.130501. D
  34. [288] M. P. Bland et al., “2D transmons with lifetimes and coherence times exceeding 1 millisecond,” arXiv:2503.14798, Mar. 2025. D
  35. [289] M. McEwen et al., “Resolving catastrophic error bursts from cosmic rays in large arrays of superconducting qubits,” Nat. Phys., vol. 18, no. 1, pp. 107–111, Dec. 2021, doi: 10.1038/s41567-021-01432-8. arXiv:2104.05219. D
  36. [290] M. McEwen et al., “Resisting High-Energy Impact Events through Gap Engineering in Superconducting Qubit Arrays,” Phys. Rev. Lett., vol. 133, no. 24, Art. no. 240601, Dec. 2024, doi: 10.1103/PhysRevLett.133.240601. arXiv:2402.15644. D
  37. [291] F. Arute et al., “Quantum supremacy using a programmable superconducting processor,” Nature, vol. 574, no. 7779, pp. 505–510, Oct. 2019, doi: 10.1038/s41586-019-1666-5. D
  38. [292] J. Gambetta, “The hardware and software for the era of quantum utility is here,” IBM Quantum Computing Blog, Dec. 4, 2023. [Online]. Available: https://www.ibm.com/quantum/blog/quantum-roadmap-2033 C
  39. [293] J. Van Damme et al., “Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers,” Nature, vol. 634, no. 8032, pp. 74–79, Oct. 2024, doi: 10.1038/s41586-024-07941-9. D
  40. [294] D. P. Pappas et al., “Alternating-bias assisted annealing of amorphous oxide tunnel junctions,” Communications Materials, vol. 5, no. 1, Art. no. 150, Aug. 2024, doi: 10.1038/s43246-024-00596-z. D
  41. [295] Investing.com, “IQM Q2 2026 slides: backlog surges 52%, revenue up 47% in H1,” Aug. 4, 2026. [Online]. Available: https://www.investing.com/news/company-news/iqm-q2-2026-slides-backlog-surges-52-revenue-up-47-in-h1-93CH-4834587 P
  42. [296] D. Underwood et al., “Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate,” PRX Quantum, vol. 5, no. 1, Art. no. 010326, Feb. 2024, doi: 10.1103/PRXQuantum.5.010326. D
  43. [297] U.S. Government Accountability Office, “Managing Critical Isotopes: Weaknesses in DOE's Management of Helium-3 Delayed the Federal Response to a Critical Supply Shortage,” U.S. Government Accountability Office, May 2011. [Online]. Available: https://www.gao.gov/products/gao-11-472 G
  44. [298] M. Ivezic, “QuantWare Raises $178M Series B — What It Means for Quantum Open Architecture,” PostQuantum.com, May 6, 2026. [Online]. Available: https://postquantum.com/industry-news/quantware-178m-series-b-qoa/ P
  45. [299] L. James, “IBM spins off America's first quantum chip foundry with $2 billion in federal and private funding — newly-minted 'Anderon' foundry to offer 300mm quantum wafer fab and manufacturing services,” Tom's Hardware, May 26, 2026. [Online]. Available: https://www.tomshardware.com/tech-industry/quantum-computing/ibm-spins-off-americas-first-quantum-chip-foundry-with-2-billion-in-federal-and-private-funding P
  46. [300] National Institute of Standards and Technology, “Department of Commerce Announces Letters of Intent With 9 Companies for $2 Billion to Accelerate U.S. Leadership in Quantum Computing,” NIST News, May 21, 2026. [Online]. Available: https://www.nist.gov/news-events/news/2026/05/department-commerce-announces-letters-intent-9-companies-2-billion G
  47. [301] US Department of Commerce, Bureau of Industry and Security, “Commerce Control List Additions and Revisions; Implementation of Controls on Advanced Technologies Consistent With Controls Implemented by International Partners,” Federal Register, vol. 89, p. 72926, Sep. 6, 2024. [Online]. Available: https://www.federalregister.gov/documents/2024/09/06/2024-19633/commerce-control-list-additions-and-revisions-implementation-of-controls-on-advanced-technologies G
  48. [302] M. U. Rehman, “Top Chinese Quantum Computing Companies in 2026,” The Quantum Insider, May 15, 2026. [Online]. Available: https://thequantuminsider.com/2026/05/15/10-plus-companies-leading-the-quantum-technologies-race-in-china/ P
  49. [303] Bluefors, “KIDE Cryogenic Platform — For Large-Scale Quantum Computing,” Jun. 16, 2026. [Online]. Available: https://bluefors.com/products/kide-cryogenic-platform/ C
  50. [304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at millikelvin temperature,” Nat. Electron., vol. 9, no. 3, pp. 287–294, Mar. 2026, doi: 10.1038/s41928-026-01576-6. D
  51. [305] S. Storz et al., “Loophole-free Bell inequality violation with superconducting circuits,” Nature, vol. 617, no. 7960, pp. 265–270, May 2023, doi: 10.1038/s41586-023-05885-0. D
  52. [306] N. Dirnegger et al., “Distilled remote entanglement between superconducting qubits across optical channels,” arXiv:2503.10842, Mar. 2025. S
  53. [307] F. Pan, K. Chen, and P. Zhang, “Solving the Sampling Problem of the Sycamore Quantum Circuits,” Phys. Rev. Lett., vol. 129, no. 9, Art. no. 090502, Aug. 2022, doi: 10.1103/PhysRevLett.129.090502. arXiv:2111.03011. D
  54. [308] Y. Kim et al., “Evidence for the utility of quantum computing before fault tolerance,” Nature, vol. 618, no. 7965, pp. 500–505, Jun. 2023, doi: 10.1038/s41586-023-06096-3. D
  55. [309] J. Tindall, M. Fishman, M. Stoudenmire, and D. Sels, “Efficient Tensor Network Simulation of IBM's Eagle Kicked Ising Experiment,” PRX Quantum, vol. 5, no. 1, Art. no. 010308, Jan. 2024, doi: 10.1103/PRXQuantum.5.010308. arXiv:2306.14887. D
  56. [310] IBM, “IBM Commits More Than $10 Billion to Quantum Computing, Funding Its Roadmap from Today's Leading Systems to the World's First Fault-Tolerant Quantum Computers,” Jun. 2, 2026. [Online]. Available: https://newsroom.ibm.com/2026-06-02-ibm-commits-more-than-10-billion-to-quantum-computing,-funding-its-roadmap-from-todays-leading-systems-to-the-worlds-first-fault-tolerant-quantum-computers C
  57. [311] O. W. Kennedy et al., “Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits,” arXiv:2602.12773, Feb. 2026. D
  58. [312] PatSnap, “Quantum Computing Patent Landscape 2026,” Jun. 30, 2026. [Online]. Available: https://www.patsnap.com/resources/blog/rd-blog/quantum-computing-patent-landscape/ P
  59. [313] J. Gambetta, “Expanding the IBM Quantum roadmap to anticipate the future of quantum-centric supercomputing,” IBM Quantum Blog, May 10, 2022. [Online]. Available: https://www.ibm.com/quantum/blog/ibm-quantum-roadmap-2025 C
  60. [314] Quantum Ledger, “DARPA QBI Tracker.” [Online]. Available: https://quantumledger.report/darpa-qbi P
  61. [890] J. R. Guimarães et al., “Quantum environment afterglow from broadband excitation spectroscopy in superconducting qubits,” arXiv:2609.31280, Sep. 2026. P