Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) fab_sc

A Josephson junction is two superconductors across a ~1–2 nm oxide barrier whose area and oxidation fix the critical current and hence the qubit frequency. This node is the process patterning those junctions and their niobium wiring at wafer scale — not a qubit. Lineage: e-beam Dolan-bridge Al/AlOx/Al junctions from the 2007 transmon (Koch et al., Yale), then 193 nm immersion lithography and etch on CMOS lines D[293].

Attributes. Carrier affinity 1.0 — fully fabricated: the manufacturing step itself, with no carrier, mobility, readout or control. Manufacturing — Nb wiring and Al/AlOx junctions on 200→300 mm silicon or sapphire; the error passed downstream is coherent (frequency offset, collision), not stochastic.

Ambegaokar–Baratoff ties critical current to normal-state resistance, and f₀₁≈(√8E_JE_C-E_C)/h, so R_n spread reaches frequency at half weight. imec measured ~8% RSD in junction resistance across a 300 mm wafer (7,872 test structures) and ~4% within a die, both for large junctions; at qubit junction sizes the area scatter adds, and qubit frequencies spread 5–7% RSD — 10–14% in resistance D[293]. That is a lattice problem, not a device problem: fixed-frequency neighbours must clear collision windows tens of MHz wide on a ~5 GHz qubit, so 5% spread (≈250 MHz, 1σ) leaves no collision-free yield at lattice scale. Trimming is a precondition, not an optimisation — alternating-bias assisted annealing moves junction resistance >70% and lands 97.4% of junctions on target D[294].

The second floor is dielectric loss: amorphous AlOx and interface oxides host two-level systems capping T₁ in the tens-to-low-hundreds of µs. imec's 300 mm devices give median T₁ 75 µs, best 161 µs, best T_2e 245 µs, over a 42–113 µs centre-to-edge gradient that is a process signature, not scatter D[293]. TLS drift hourly, and quasiparticle bursts set a floor lithography cannot touch Dfact. What moves it: epitaxial barriers and Ta/Nb base metal; tuneable couplers ease the first floor's frequency collisions, not the loss.

Best on a genuine 300 mm CMOS line: 393 of 400 qubits functional D[293] — but at the frequency spread above, so trimming or tuneability is still required downstream.

Dominant error term: coherent frequency error — spread, collisions, drift. TLS-limited T₁ is what the process cannot remove.

Dolan-bridge shadow evaporation still produces most published qubits; the CMOS route means 193i patterning, RIE, Nb wiring, TSVs, bump bonds. Its advantage is statistics and throughput, not coherence: imec's median T₁ matches e-beam devices, its metrology does not. Trade press claims ~30× device output versus 200 mm; IBM's release states no multiple P[299]. Tooling is unremarkable, so the scarce asset is recipe and trimming capability; single points of failure are refrigerator capacity, high-resistivity silicon and sapphire, and Nb etch expertise shared with the SFQ chain. Cost per wafer is not quotable. Export exposure is indirect: the BIS rule of 2024-09-06 controls cryogenic wafer probers (3B904), sub-4.5 K cryogenic electronics (3A901) and quantum computers by qubit count and C-NOT error together, from 34 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906) fact, but no ECCN names junction lithography G[301].

No control or readout of its own; it sets the ceiling others hit, through escape density and frequency targeting. OQC's package is the current bound: >500 qubits on one die, out-of-plane coax, no wire bonds, 56 nine-to-one readout multiplexing cells — and no per-qubit control lines as measured P[311], so it is a packaging result, not a processor. At 10³ per die the constraint is collisions; at 10⁴ escape density and routing, what Loon targets C[49]; at 10⁶ no fabricated design exists.

Root node of the superconducting family: it requires nothing upstream and provides for transmon, fluxonium, the rf-SQUID flux qubit and planar bosonic modes, plus long-range c-couplers, millikelvin SFQ control, flux-DAC multiplexing, vertical signal delivery, multi-die packaging, multi-chip modules with l-couplers, and cryogenic microwave links. Architectures served: transmon, bosonic cat/GKP, dual-rail erasure, annealing. For a bosonic mode it is the planar alternative to machined 3D cavities. Fan-in is zero, yet its fan-out is the family's widest and every downstream node inherits its spread and yield. It adds nothing to the derived clock (derived clock = sum of the syndrome round: gate layers + transport + readout + reset, 0.65 µs on the transmon lattice) but bounds how many qubits reach it.

Frequency is predicted from junction resistance via Ambegaokar–Baratoff, then confirmed spectroscopically after packaging, so the statistic that matters is R_n RSD — published by nobody except imec D[293]. RB, XEB and cycle benchmarking measure a calibrated lattice, blind to dies discarded and pre-trim collision rates. ABAA's 97.4% is a targeting-success rate from an optimised study, not a worst-case bound D[294]. OQC's numbers are sub-sampled: readout over 54 of >500 sites, 105/108 operational on the characterised subset P[311]. Conflict: OQC's abstract gives a ~100 µs median for T₁ and T_2e together; its body gives T₁ 97 µs and T_2e 129 µs over 105 qubits P[311].

IBM's 2026-05-21 release gives Anderon as a letter of intent subject to definitive documents, with no execution announced by 4 Sep 2026, yet IBM's 2026-08-26 HRL release already calls Anderon "its quantum wafer foundry". The "≈30× device output versus 200 mm" appears only in trade press [299]; IBM's own release states no multiple. The PatSnap H10N 60 counts [312] are portfolio-wide patent records. Not published: a per-wafer or per-qubit cost for any 300 mm superconducting-qubit line; a dated patent family specific to Nb/Al junction lithography at 300 mm; whether Google's Goleta purchase is fab capacity, and the wafer size of its Santa Barbara fabrication facility [805]; and whether the Nb wiring stack of imec's 300 mm line, which uses Al/AlOx/Al overlap junctions, matches IBM's approach.

Money.

• 2026-05-21 · Anderon · CHIPS LOI plus IBM equity · $1 B CHIPS + $1 B IBM cash and IP · US Dept of Commerce · within $2.013 B across nine firms · LOI, unexecuted G[798]fact
• 2026-05-21 · GlobalFoundries · CHIPS LOI, multi-modality foundry · $375 M · US Dept of Commerce · — · LOI G[300]
• 2026-06-02 · IBM · commitment, quantum overall · >$10 B / 5 yr · — · announced C[57]
• 2026-08-26 · IBM · HRL acquisition completed, naming an Anderon collaboration · undisclosed · — · completed C[204]

Market & supply chain. No merchant superconducting-qubit foundry operates as of 4 Sep 2026: the 300 mm lines with published qubit data are IBM's captive Albany line and imec's research pilot, Google fabricates captively in Santa Barbara at an unpublished wafer size P[805], and the proposed merchant line is funded by its prospective customers' largest competitor. Binding scarcities are refrigerator capacity and process know-how, not tools; unit economics are not quotable. G3 and G4 pay directly, G7 indirectly; G1, G2, G5, G6 fund nothing.

IP & standards. PatSnap's landscape of 2026-06-30 counts 783 IBM and 357 Google patent records in superconducting devices (IPC H10N 60) P[312]fact. No patent family specific to 300 mm junction lithography carries a named assignee and year; no standards body governs these processes.

Roadmaps & track record. Anderon (promised 2026-05-21 · foundry serving vendors worldwide · status 2026-09-03: LOI only, yet IBM's 2026-08-26 release calls it "its quantum wafer foundry") G[798]C[204]. Rigetti/ABAA (2024-08 · production frequency targeting · in use under the 108-qubit product, whose 99.5% two-qubit target slipped to "later 2026") D[294]C[36]. IBM's fabrication milestones land on schedule; its merchant-access promise has no record.

Strategic reading. If 300 mm superconducting fab scales, IBM wins twice — vertically integrated, and landlord to everyone else's capacity. Fabless vendors win only with a neutral foundry, which does not exist. Losers are vendors whose differentiator is fabrication skill, not architecture. The threat is capture, not substitution: every superconducting architecture needs this node, and equipment suppliers have no bargaining power against its owner.

Confirm by end-2027 if Anderon executes definitive CHIPS documents and fabricates for a named non-IBM customer; demote the merchant-foundry framing if only IBM designs emerge. Best case by 2029: two or more independent 300 mm lines with published cross-foundry uniformity and post-trim residuals below 1% frequency RSD. Worst case: Anderon stays captive. Open questions: does any line publish post-trim collision yield; can epitaxial barriers lift median T₁ above 200 µs; does a merchant European or Asian line emerge?