On-chip flux-DAC multiplexing ct_fluxdac

An on-chip flux DAC (Φ-DAC) is an SFQ circuit on the mK stage that latches the DC flux bias of one qubit or coupler. SFQ pulses push flux quanta (Φ₀ = h/2e) into a superconducting storage loop, which holds the bias indefinitely with no static dissipation and no room-temperature wire. D-Wave has shipped this in annealers for over a decade; the first gate-model application, a flip-chip fluxonium module, came in January 2026 D[316]C[281].
Attributes: fabricated control layer with no intrinsic gate or readout channel; low-frequency bias at the mK stage.
Error structure is coherent — bias-setting error, crosstalk, drift — not relaxation; fabrication is superconducting multilayer lithography.

The scaling argument is about duty cycle, not power efficiency. Each switching event dissipates ~I_cΦ₀, but a flux bias is reprogrammed on a calibration cadence, not a gate cadence, so thousands of latched channels sit quiescent inside a millikelvin budget that could not host one continuously driven line — unlike SFQ gate control, which pulses at circuit rates. A resource review puts SFQ control at ~1.6 µW/qubit against 2–23 mW/qubit for 4 K cryo-CMOS S[550]fact.
The floor is bias resolution and stability, not coherence. The least significant flux step fixes a residual detuning; thermal cycling and trapped vortices move the working point; and every stored quantum couples magnetically to its neighbours, which is where crosstalk originates. Moving the floor needs low-power SFQ families (ERSFQ — energy-efficient rapid SFQ — and eSFQ) without static bias resistors, finer quantisation, and shielding that keeps the DAC network's fields off the qubit chip.

The annealer ratio is deployed; the gate-model result is one qubit, with coherence but no gate fidelity.

The package bump-bonds a "high-coherence, minimal fabrication" qubit chip to a multilayer control chip across a ~7 µm gap D[316]. The supply chain is the exposure: key components were fabricated at NASA's Jet Propulsion Laboratory C[281] — a government laboratory, not a merchant foundry. D-Wave's 10-Ks state fabrication at "existing third-party foundries" with a second source demonstrated; EDGAR search returns nine "SkyWater" hits in its 2023–2026 filings G[492]. Export exposure is asymmetric and favours SFQ: ECCN 3A901.a controls CMOS ICs designed for ≤4.5 K — a design-intent test capturing a cryo-CMOS design file — while no ECCN names superconducting digital logic; only the finished machine can be caught, under 4A906, and only when its qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits G[301]fact.

The node breaks the one-wire-per-bias law: 200–300 bias wires serve several thousand annealer qubits and tens of thousands of couplers C[281], [316]. Annealer biases are set per program and structurally homogeneous, whereas a gate-model processor retunes per-qubit and per-coupler biases against a drifting calibration. Line count is not the only I/O: bump-bond count, readout and microwave drive are untouched. SFQ pulses are picosecond-scale, so updates are fast; settling time and neighbour disturbance are unpublished. At 10³ D-Wave already operates; at 10⁴ the ~200–300 lines is an annealer ratio, not a fluxonium one; at 10⁶ no path is described and bond density, not wire count, binds.

This Control-layer node underlies the quantum-annealing architecture (D-Wave), is the alternate control of the dual-rail erasure architecture (D-Wave's gate-model line), and requires superconducting Nb/Al junction lithography and SFQ digital logic at the mixing-chamber stage — the DAC is an SFQ flux-storage loop, so the node hangs off SFQ digital control (ct_sfq) and gives that node its second carrier family; it shares cold-stage fabrication capacity. It replaces room-temperature control lines. The switching cost is a second die, flip-chip bond yield as a new failure mode, and loss of arbitrary waveform shaping on the biased node — bandwidth traded for wire count. Flux biases are quasi-static, so this node adds no term to derived clock = sum of the syndrome round: gate layers + transport + readout + reset; the annealing architecture runs no syndrome round in any case, its cadence being calibration, not circuit, and no figure is quotable. Its empty downstream fan-out understates the case: every superconducting roadmap above ~10³ qubits meets this wall.

T1 (relaxation) and T2 (Ramsey) were measured on the single Φ-DAC-controlled fluxonium against a conventional control-line baseline. The comparison has limited sensitivity: T2 ≈ 20 µs is already an order of magnitude below T1 ≈ 200 µs, so "no resolvable increase" bounds rather than measures the DAC's flux noise. Unpublished: any crosstalk matrix, bias drift across thermal cycles, or gate fidelity. The source is a company whitepaper, not peer-reviewed, and unreplicated. Value conflict: D-Wave says 200 bias wires (2026-01-06) C[281] and ~300 (2026-01-23) D[316]; the whitepaper's figure is tied to a described array.

The SkyWater–D-Wave foundry relationship rests on an EDGAR full-text hit count, not a quoted sentence. No ECCN names superconducting digital logic; whether an SFQ control die falls under a catch-all is untested. Not published: the Φ-DAC's settling time, and the scope, capacity or contract terms of JPL's role beyond "key components".

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| D-Wave | developer | CA | Originated Φ-DAC multiplexing; first fluxonium demo | D[316]C[281] |
| NASA JPL | supplier | US | Fabricated key components of the module | C[281] |
| SEEQC | developer | US | SFQ control chips; owns a multilayer superconductor foundry | D[304] |
| IBM | developer | US | Rival 14 nm cryo-CMOS flux-bias ASIC on Heron R2 | C[527] |
| US Dept of Commerce | regulator | US | $100 M CHIPS LOI to D-Wave; BIS sets 3A901.a and 4A906 | G[300], [301] |

Money.
2026-01-20 · D-Wave · M&A, Quantum Circuits Inc. · $550 M ($300 M stock + $250 M cash) · closed C[14]fact
2026-05-21 · D-Wave · CHIPS letter of intent · $100 M · US DoC, $2.013 B package · LOI G[300]fact
2026-05-26 · SEEQC · SPAC registration (Form S-4), Allegro Merger Corp. · $75 M offering + $65 M PIPE, ~$1 B EV · filed G[575]fact; merger terminated 2026-08-25 before closing fact
2026-08-06 · D-Wave · H1-2026 revenue $5.9 M (−67% YoY), cash $546.2 M · reported C[15]fact

Market & supply chain. The scarce input is multilayer niobium capacity: SkyWater as merchant option (quantum ATS revenue +30% YoY on FY2025 revenue $442.1 M G[576]), SEEQC's own Elmsford line, JPL as a government facility with no commercial throughput. No $/channel figure is disclosed. G7 pays most directly; G3/G4 only if the fluxonium route generalises.

IP & standards. No dated patent family specific to on-chip flux-DAC circuits was found; D-Wave's annealer control IP predates this window. SEEQC's SFQ portfolio descends from over $100 M of prior Hypres investment Pfact. No standards activity identified.

Roadmaps & track record. D-Wave gate model: 17 physical qubits (promised 2026-06-01 · for 2026 · reaffirmed 2026-08-06, undelivered as of 4 Sep 2026), then 49 (2027), 181 (2028), 100 logical (2032), Λ = 10 R[14]. Advantage2 GA (promised for 2025 · delivered 2025-05-20) is the clean delivery C[220]. Against that, H1-2026 revenue fell 67% C[15]: the pivot runs on cash, not the business. CFO John Markovich retired effective 2026-09-02; the 8-K of 2026-08-25 states the departure involved no disagreement with the company fact. SEEQC's SPAC merger was terminated on 2026-08-25; its separate S-1 IPO, filed 2026-06-29, had not priced by 30 Sep 2026 fact.

Strategic reading. Three answers compete for one I/O wall: on-chip SFQ Φ-DACs (D-Wave), 4 K cryo-CMOS DACs (IBM, HRL), and needing fewer lines at all — the Shenzhen unified XY+Z architecture drives both through one room-temperature channel per fluxonium at 99.99% 1Q fidelity on eight devices D[315]. That third route is the underrated threat: no cryogenic hardware, and it reports the gate metric the Φ-DAC work omits. If Φ-DACs generalise, D-Wave and Nb foundries gain and room-temperature rack vendors lose per-qubit channel revenue.

Milestones (12–24 months): D-Wave publishes a multi-qubit Φ-DAC result with a crosstalk matrix and gate fidelity (confirm); the 17-qubit 2026 gate-model target ships (confirm); an outside group replicates the coherence result on a second device (confirm) — or the fluxonium line stays a single-device whitepaper through 2027 (demote). Best case 2029: Φ-DAC control of hundreds of independently tuned gate-model qubits, crosstalk below the gate-error budget, adopted outside D-Wave; worst case, proven only for a homogeneous annealer array while cryo-CMOS or line-reduction takes the gate-model market. Open: crosstalk and drift at scale; whether bump-bond density becomes the real wall. Watch: D-Wave's next fluxonium publication, SEEQC's IPO pricing, an SFQ-vs-cryo-CMOS comparison.