Dual-rail erasure qubits on the map bar: Dual-rail erasure

The architecture in the report (§8.3)

8.3.3 Dual-rail erasure — Dual-rail erasure qubits (dualrail)

The idea. One excitation shared between two modes, cavity modes or transmons, is the Dual-rail (erasure) encoding (enc_dualrail): logical |10⟩ and |01⟩; loss on either rail lands in |00⟩, outside the code space. A Mid-circuit erasure check sees that exit without reading the logical state: the dominant error arrives located, cheaper to correct than an unknown Pauli error. The price: two modes per qubit and a check every cycle. The bet: fail more often, but visibly; with 98% of errors converted, the surface-code threshold rises from 0.94% to 4.15% [S][8].

What it needs. The chain is hard: the encoding requires the check, and Erasure-adapted codes require its flags; without the check the qubit is merely lossier, without a flag-using decoder the heralds are wasted. The check's tax: 384 ns on transmons, residual 6.0(2)×10⁻⁴ against 2.54(1)×10⁻² erasure per check [D][85], inside a gate-limited round of at least 2.8 µs [S] (§7.4). Six layers (2–4, 7–9) hold one technology each; the gate technology requires the modes plus a transmon ancilla. Alternates: vertical delivery and on-chip flux-DAC multiplexing replace room-temperature lines, lithography replaces 3D machining, and transmon rails escape the cavities' conflict with a dense lattice.

Where it stands. Nine machines, four devices (Table 8.3): Aqumen Seeker, eight dual-rail cavity qubits (Quantum Circuits Inc., now D-Wave, 2024) [C][14], [86]; OQC GENESIS, 16 sites, deployed September 2025, and OQC's roadmap names TITAN (2,000 sites, 2028), ATHENA (75,000) and ATLAS (1,000,000) [R][874]; the SUSTech four-dual-rail-qubit processor (Nature Physics, 2026) [D][406] and the SUSTech biased-erasure cavity qubit; the AWS dual-rail transmon erasure line, a component; the D-Wave gate-model dual-rail system, 17 qubits due in 2026 [R][94]. The Yale/Quantum Circuits cavity CZ: ~500 ns, 0.53% erasure per gate, post-selected Pauli error below 0.1%, about 80% of its error flagged [D][84]. Seeker's 1.0×10⁻³ is post-selected on no heralded erasure (0.53% per gate), so Table 8.3 shows no unconditioned two-qubit error for the architecture [C][86]. GENESIS publishes no entangling gate — its gate cell reads undisclosed, not none — so Table 8.3 does not count it gate-capable; the table's largest gate-capable device is the SUSTech four-dual-rail-qubit processor, 8 qubits, whose logical CNOT (98.1 % process fidelity at a 13 % erasure rate) is post-selected [D][406]. No machine has run an erasure-decoded code.

Exceptions and borrowings. One off-slot cell and no better-fitting architecture: the SUSTech four-dual-rail-qubit processor entangles its transmon rails through tunable couplers (g_tc), a gate the architecture's slot does not hold — it expects ancilla-mediated bosonic gates [D][406]. Two more sit loosely. GENESIS's carrier alternate is an Atlas gap, ∅G-dimon: one fixed-frequency multimode transmon, three islands and two junctions, two transmon-like modes [C][250], beyond the transmon technology (layer 1 too narrow); its gate is undisclosed (a data gap), its code cell none: error detection by post-selection. The SUSTech qubit is not dual-rail: it encodes in the vacuum and two-photon Fock states of one cavity, with erasure bias above 265 [D][251]; its encoding cell is mislabelled, or the architecture too narrow, its idea being loss-to-erasure, not two rails. The D-Wave system is a hybrid: annealer flux-DAC control. Other architectures borrow the check (Phoenix (Gen-1) and Gen-2, Magne; alkaline-earth Rydberg) and the encoding (Lucy, Belenos; fusion-based photonic), as alternates.

The next test. Two expectations to March 2028 (§5.2). First, the D-Wave 17-qubit system publishes a logical error 2× below physical by mid-2027; if end-2027 passes with no dual-rail machine reporting logical error falling more than 2× per distance step on unconditioned data, the architecture is demoted. Second, the first dual-rail memory of at least ten rounds at distance 3, erasure flags in the decoder, survival reported; the CHIPS-backed design at 100 physical qubits per logical [R][91] presumes it.

What the builders say. D-Wave designs its dual-rail qubits to flag about 90% of errors as they occur, so that correction needs fewer physical qubits [C][831]; its entangling gate runs in about 500 ns, with about 0.5% erasure and under 0.1% residual error per gate [D][84]. It plans 17 physical qubits in 2026 and 100 logical qubits running more than a million operations by 2032 [R][831]. OQC says its dual-rail Dimon needs ten times fewer physical qubits per logical qubit than today's leading approaches [C][832], installed its GENESIS machine in a New York City data centre in September 2025 [C][833], and plans 200 logical qubits by 2028 and 50,000 by 2034 [R][832].

Machines of this architecture (register: 9, of them 4 devices, 3 gate-capable). Oxford Quantum Circuits — OQC ATLAS (planned, 1,000,000), OQC ATHENA (planned, 75,000), OQC TITAN (planned, 2,000), OQC GENESIS (deployed, 16); AWS Center for Quantum Computing (named Amazon Center for Quantum Computing in the Apr 2026 paper) — AWS dual-rail transmon erasure line (demonstrated, 2); D-Wave Quantum — D-Wave gate-model dual-rail system (announced, 17); Quantum Circuits Inc. (acquired by D-Wave, Jan 2026) — Aqumen Seeker (deployed, 8); Southern University of Science and Technology — SUSTech biased-erasure cavity qubit (demonstrated, 1); Southern University of Science and Technology (Huang et al.) — SUSTech four-dual-rail-qubit processor (demonstrated, 8).

Cells outside the architecture's slots (22). OQC ATHENA: L1 ∅G-dimon (Atlas gap — roadmap names 'next-generation multimode qubits' for ATHENA — the Dimon's multimode single); OQC ATHENA: L3 undisclosed where the architecture expects a technology; OQC ATHENA: L4 undisclosed where the architecture expects a technology; OQC ATHENA: L7 undisclosed where the architecture expects a technology; OQC ATHENA: L8 undisclosed where the architecture expects a technology; OQC ATHENA: L9 undisclosed where the architecture expects a technology; OQC ATLAS: L1 ∅G-dimon (Atlas gap — roadmap names an 'advanced multi-mode qubit' for ATLAS — the Dimon's multimode single-devi); OQC ATLAS: L3 undisclosed where the architecture expects a technology; OQC ATLAS: L4 undisclosed where the architecture expects a technology; OQC ATLAS: L7 undisclosed where the architecture expects a technology; OQC ATLAS: L8 undisclosed where the architecture expects a technology; OQC ATLAS: L9 undisclosed where the architecture expects a technology; OQC GENESIS: L1 ∅G-dimon (Atlas gap — Dimon: three islands, two junctions, one dual-rail qubit per device; the transmon node doe); OQC GENESIS: L3 undisclosed where the architecture expects a technology; OQC TITAN: L1 ∅G-dimon (Atlas gap — roadmap names 'multi-mode qubits' for TITAN — the Dimon's multimode single-device dual rai); OQC TITAN: L3 undisclosed where the architecture expects a technology; OQC TITAN: L4 undisclosed where the architecture expects a technology; OQC TITAN: L7 undisclosed where the architecture expects a technology; OQC TITAN: L8 undisclosed where the architecture expects a technology; OQC TITAN: L9 undisclosed where the architecture expects a technology; SUSTech biased-erasure cavity qubit: L2 ∅G-fock02 (Atlas gap — qubit in |0⟩/|2⟩ Fock states of one cavity; photon loss flagged as erasure); SUSTech four-dual-rail-qubit processor: L3 Tunable-coupler CZ / iSWAP (g_tc, primary off the architecture's slots).