SUSTech four-dual-rail-qubit processor

Raveh Neeman

doi:10.5281/zenodo.22674814

Southern University of Science and Technology (Huang et al.)

SUSTech four-dual-rail-qubit processor

Southern University of Science and Technology (Huang et al.) · superconducting circuits · DEMONSTRATED (Nature Physics, 6 Mar 2026; arXiv 16 Apr 2025) (6 Mar 2026 (Nature Physics; arXiv 16 Apr 2025)) · 8 physical qubits · access: lab-only

architecture: Dual-rail erasure qubits · Open on the map

Register profile — the machine's variant of its architecture

qubit type: dual rail from pairs of tunable transmons (millisecond coherence in the logical subspace)

gate mechanism: tunable couplers between logical qubits: coupler-activated XX interaction gives a logical √iSWAP, from which a logical CNOT is synthesised

connectivity: logical qubits coupled pairwise through tunable couplers

control: room-temperature DACs (2 GS/s) and ADCs (1 GS/s); chip at 10 mK in a dilution refrigerator

control placement: room-temp

readout: mid-circuit erasure check per dual rail by an ancilla (conditional π pulse resonant only on |00⟩); erasures post-selected

gate evidence: no published figure

codes: dual_rail

flags: post-selection dominates the result

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▣ §II, Fig. 1b (logical qubit = transmons Q_iA, Q_iB + ancilla A_i) ✅ each dual-rail qubit is a pair of tunable transmons, with an ancilla transmon for erasure checks
2 Encoding	Dual-rail (erasure) encoding · primary ▤ Abstract ✅ dual-rail encoding in pairs of tunable transmons; millisecond-scale coherence, logical 1Q gate error ~1e-5 with erasure post-selection
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▤ §IV (coupler-induced XX coupling, √iSWAP, CNOT); Fig. 4a ✅ tuning the coupler induces an XX coupling in the logical subspace: logical √iSWAP, then a logical CNOT (98.1% at a 13% erasure rate in the Nature Physics version; 96.2% in arXiv v1)
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▣ §II, Fig. 1b ✅ four logical qubits tunably coupled to each other through couplers C_ij
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▤ Supplementary §I (measurement setup) ✅ room-temperature DACs (2 GS/s) and ADCs (1 GS/s); chip at 10 mK in a dilution refrigerator
6 Readout	Mid-circuit erasure check · primary ▣ §III; Fig. 2a (erasure check) ✅ an ancilla per dual rail detects leakage to \|00⟩ mid-circuit (conditional π pulse); erasures post-selected
7 Code	Erasure-adapted codes · primary ▤ 🔎 dual-rail erasure qubits as the route to erasure-adapted QEC; no code run beyond the encoding (L1)
8 Decoder	— none — nothing in this layer ▤ Abstract ('by using post-selection to mitigate erasure errors') ✅ no decoder; erasure errors handled by post-selection
9 Interconnect	Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▣ §II, Fig. 1a; Supplementary §I ✅ flip-chip processor: top qubit chip on a bottom carrier chip (non-galvanic flip-chip assembly)
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▣ Fig. 1a; Supplementary §I ✅ superconducting flip-chip processor (qubit chip + carrier chip)

evidence: ✅ 9 / 10