Dual-rail (erasure) encoding enc_dualrail

A dual-rail qubit is one quantum of excitation shared between two modes: |0_L⟩ = |10⟩, |1_L⟩ = |01⟩. The dominant hardware error — cavity photon loss, transmon T1 decay, waveguide absorption — is the annihilation operator on either rail, and it sends both logical states to |00⟩, outside the code space. A total-excitation measurement therefore commutes with the logical operators: decay is caught and located without disturbing the encoded state, turning the largest error term from unknown Pauli into heralded erasure. What remains is differential dephasing between two rails never quite identical.

Dual-rail is the native photonic qubit: Chuang and Yamamoto (1995) called it "a simple form of error correction" S[398]; Knill, Laflamme and Milburn built linear optics on it in 2000 S[337]. The superconducting transfer was deliberate — AWS proposed transmon pairs (2022-08) S[334], Yale cavities (2022-12) S[399], both demonstrated July 2023 D[400], [401].

Attributes from the technology graph (a affinity; b time; c readout; d mobility; e control @ placement; f errors; g manufacturing):

• a = 0.25, fabricated — engineered modes, not natural levels.
• b = n/a; no gate time of its own.
• c = none; the check is a separate primitive.
• d = none.
• e = none @ none.
• f = erasure: located, heralded loss.
• g = none; a wiring choice, not an object.
  Rank 6 of 111; shared by the photonic and superconducting families.

The energy scale is one quantum — a 6 GHz microwave or 1.5 µm optical photon — and the time scale is the single-excitation lifetime of the worse rail. Either rail can decay, so the erasure rate is roughly twice the single-mode loss rate: the qubit fails more often than a bare one, and wins only if the code eats located errors more cheaply. It does — erasure locations lift the surface-code threshold to 50% in the ideal limit against ≈19% for depolarising noise, and at 1% erasure the tolerable Pauli rate rises 5.2× S[334], [402].

The measured hierarchy is the point: a Yale double-post cavity gave erasure at 3.981(3) ms⁻¹ against in-code-space dephasing below 0.17 ms⁻¹ D[403]; AWS's transmon pair, erasure 2.19(2)×10⁻³ per single-qubit gate with residual ~40× lower and millisecond code-space coherence from far shorter-lived transmons D[400].

Four floors are intrinsic: rail asymmetry, whose differential frequency shift dephases the code space and does not improve with lifetime; false negatives, re-entering as invisible leakage (3.7% D[404], 6–8% in the qutrit variant D[405]); heating out of the single-excitation manifold; and the check's own exposure. Only longer lifetimes, matched shifts and faster checks move them.

Best demonstrated as of 3 Sep 2026: a cavity dual-rail CZ in ~500 ns at ≈0.5% erasure per gate and 0.029(6)% post-selected Pauli error D[84]. Typical at scale: nothing beyond sixteen sites — OQC GENESIS, 16 dual-rail sites with no published entangling gate (2025-09), Quantum Circuits' 8-qubit Aqumen Seeker (2024-11) C[86], SUSTech's four dual-rail transmons (2025-04) D[406].

Dominant term today: control-qubit dephasing during the gate in cavities, 3× the target's D[84]; check exposure and false negatives in transmons D[85]; loss in photonics.

Machined cavities (high-purity aluminium, sapphire-mounted ancillas) give the longest photon lifetimes and no foundry path — Quantum Circuits' line. Planar transmon pairs (AWS, SUSTech) inherit ordinary superconducting fabrication but take twice the die area per site and add a requirement bare transmons lack: the rails must be matched in frequency and coupling, so the frequency-collision problem that limits transmon yield now applies pairwise. No vendor publishes a dual-rail yield, cost or energy per qubit. Photonic dual-rail is the best case — path encoding is free in a waveguide — PsiQuantum's 300 mm silicon-nitride platform running 1.8(2) dB/m waveguide loss and 93.4% median detector efficiency at ~2 K D[169].

Superconducting variants ride the export-controlled stack: refrigerators, amplifiers, microwave I/O (BIS ECCNs 3A904, 4A906, 3B904) G[301] fact. Photonics depends on a 300 mm CMOS-photonics foundry, barium-titanate switches and nanowire detectors — single-source risk at both.

The encoding doubles control fan-out: two drive lines per qubit, or two cavities plus an ancilla transmon and its readout. AWS folds that back with one readout resonator coupled symmetrically to the pair, so the check is a single 384 ns pulse costing 8(3)×10⁻⁵ dephasing D[85] fact; the cavity variant needs a number-splitting ancilla measurement, 1.82 µs standalone D[404], now folded into the gate D[84]. The system burden is the flag path: one bit per qubit per round must reach the decoder inside a syndrome cycle, against NVQLink's 3.84 µs round trip fact. At 10³ qubits that is 2×10³ modes and 10³ flag channels; at 10⁴ the ~10 Gb/s flag bandwidth forces cold-stage aggregation; at 10⁶ only planar or photonic survives.

Dual-rail sits on two architectures: "Dual-rail erasure qubits", as the primary encoding (Quantum Circuits/D-Wave, AWS, OQC, SUSTech), and "Fusion-based photonic (FBQC)", as an alternate (PsiQuantum, Quandela, QuiX). It requires a mid-circuit erasure check and is what that check reads; without one it is merely a lossier qubit. It replaces bare encoding at 2× the modes and conflicts with the plain surface code, which discards heralds. It buys error structure with area, not error rate with coherence.

Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 2.8×10⁻⁶ s on the dual-rail architecture — four 5.0×10⁻⁷ s CZ layers D[84] over a 4.0×10⁻⁷ s check D[85] — gate-set on the cavity and the transmon route alike. Switching away is cheap in hardware, expensive in software: decoder, calibration and benchmarks assume heralds. Neighbouring empty slots: a dual-rail logical memory over repeated rounds, and the erasure-biased code consuming heralds and bias.

Every headline number here is post-selected: erasure rates come from heralded tomography or interleaved benchmarking with flagged shots discarded, so a "99.9% gate" is a conditional fidelity whose companion figure, the survival fraction, decides whether the device is useful. The protocols miss correlated two-rail loss, heating into |11⟩, rail-asymmetry drift, and the erasure fraction under two-qubit gates in a repeated cycle rather than idling. False negatives, the least-reported quantity, set the leakage floor the decoder never sees.

Replication is real: transmon AWS 2023 → SUSTech 2025 → AWS 2026; cavity Yale 2023 → 2025 → Quantum Circuits 2026. Conflicts: the 2026 Nature gate is post-selected Pauli < 0.1% (0.12% at depth) with erasure fraction ≈80% in the main report, 0.029(6)% per gate cited from the same paper, "below 0.1%" in the arXiv abstract D[84] — per-gate versus depth-extrapolated, quoted rather than merged. Second, PsiQuantum waveguide loss is 0.5 dB/m in the main report against 1.8(2) dB/m in Nature D[169].

The ≈80% gate-level erasure fraction of the cavity CZ comes from the main report; the arXiv abstract states only ≈0.5% erasure per gate, and no primary source gives the fraction. OQC's erasure-qubit perspective S[402] is a review by an industrial group, not a hardware commitment, and OQC's Series C release names no dual-rail target C[60]. Not published: whether Quandela's and QuiX's path-encoded linear-optical qubits are dual-rail, so no numbers are attributed to them; a dated primary figure for Quantum Circuits' physical-to-logical overhead, reported elsewhere as 10–20 physical per logical and absent from its dual-rail explainer C[411]; yield, cost or energy per dual-rail qubit, from any actor, superconducting or photonic; a dated patent-family count for dual-rail encodings; and the funding of the dual-rail programmes at AWS, SUSTech and Yale, apart from their parent institutions. Not published in the abstract of [84]: the cavity materials, quality factors and packaging of the 2026 Quantum Circuits device.

Money.

• 2024-08-15 · Quantum Circuits · Series B · > $60 M · ARCH, F-Prime, Sequoia · ≈$84 M cumulative P · closed fact
• 2025-09-10 · PsiQuantum · Series E · $1 B at $7 B · BlackRock · closed fact
• 2025-11-04 · US DOE · NQISRC renewal, C2QA · $125 M of $625 M · awarded fact
• 2025-11-06 · DARPA QBI Stage B · up to $15 M each, eleven teams, no dual-rail vendor G[65] fact
• 2026-01-07 · D-Wave · acquires Quantum Circuits · $550 M ($300 M stock + $250 M cash) · closed 2026-01-20 fact
• 2026-05-21 · D-Wave; PsiQuantum · US DoC CHIPS letters of intent · $100 M each · LOI fact
• 2026-06-03 · Oxford Quantum Circuits · Series C · £260 M · Bullhound · closed C[60] fact
• 2026-07-22 · PsiQuantum · DARPA QBI Stage C expansion · $125 M · switch and cryogenics V&V fact
• 2026-08-06 · D-Wave · Q2-2026 · revenue $3.1 M, cash $546.2 M, $1.57 M NSF grant · reported C[15] fact

Market & supply chain. Nobody sells the encoding; it is priced as hardware multiplicity — two modes plus an ancilla per site — plus the readout chain that reads the herald. On superconductors that is 2–3× die area or a machined cavity assembly with no foundry, so the suppliers that matter are the refrigerator and amplifier vendors under BIS control G[301]. On photonics it is free, and the bill of materials is the foundry, the switch and the detector. G2 pays today for post-selected fidelity, which is what Seeker sells C[86]; G3 and G4 pay once codes run 10⁵–10⁶ rounds; G6 pays on the photonic side; G1, G5 and G7 do not.

IP & standards. Amazon Technologies US 11,748,652 B1, heralded amplitude-damping decay for QEC (granted 2023-09-05), covers the transmon embodiment G[336] fact; Yale US 12,288,135, asymmetric-error-channel processing (granted 2025-04-29), sits with the cavity families that passed to D-Wave in January 2026 G[408]; ORCA Computing holds US 12,437,225, linear-optical encoded GHZ measurements (2025-10-07) G[407]. No dated patent-family count was obtainable from a named database; no standard exists, and Stim's HERALDED_ERASE is the de-facto decoder interface P[397].

Roadmaps & track record.

• D-Wave/Quantum Circuits: promised 2026-06-01, restated 2026-08-06 · DR17 (17 qubits, 2× logical error reduction) 2026, DR49 at 20× 2027, DR181 at 2,000× 2028, 10 logical 2030, 100 logical 2032, Λ = 10 · undelivered as of 2026-09-03 R[409] fact.
• PsiQuantum: promised utility scale "before 2033" · Moreton Bay groundbreaking slipped to 2026-06-17 · at risk fact.
• AWS: no dual-rail product promised · three papers delivered 2022–2026 D[85], [400]. Oxford Quantum Circuits: TITAN announced with the Series C · no dated dual-rail target C[60].
  Credibility: Quantum Circuits/D-Wave publishes the field's best channel numbers and has shipped only the 8-qubit Seeker; AWS publishes and promises nothing; PsiQuantum's components are the best-characterised anywhere, its systems slip.

Strategic reading. If dual-rail wins, the winners own long-lived modes and cheap area — cavity vendors and photonic foundries — and the losers are transmon roadmaps spending their whole budget on T1, since the encoding makes T1 a detected cost, not a fatal one. Substitution runs hard from inside the family: the transmon-qutrit erasure qubit needs one transmon and one ancilla, not two rails, at logical T1 > 500 µs against a physical ~55 µs D[405]; dual-rail cat codes add bias to the same structure S[410]. Bargaining power sits with platform vendors.

Confirm if, within 12–24 months: DR17 ships with a measured 2× logical error reduction; any group runs a code on ≥ 10 dual-rail qubits with Λ > 2 and publishes the survival fraction; someone reports the erasure fraction under two-qubit gates in a repeated cycle. Demote if none lands by end-2027, or if the qutrit erasure qubit matches dual-rail's bias at half the hardware. Best case by 2029: a 181-qubit machine at the promised suppression. Worst case: doubled modes and check dead time eat the threshold gain, and the encoding survives only where it is free, in photonics.

Open questions. (1) Does the erasure fraction hold under two-qubit gates at depth? (2) What is a production check's false-negative rate, and does it scale? (3) Can planar dual-rail reach cavity-grade lifetimes? (4) Is there a regime where doubling modes beats doubling code distance? Watch D-Wave's quarterly disclosures and the first repeated-round dual-rail memory paper.