OQC GENESIS
OQC GENESIS
Register profile — the machine's variant of its architecture
qubit type: Dimon - a fixed-frequency multimode transmon (three islands, two junctions) operated as a dual-rail encoded qubit inside the Coaxmon stack
gate mechanism: no published entangling gate or gate mechanism
connectivity: not published
control: out-of-plane Coaxmon control; NVIDIA GH200 + CUDA-Q alongside
control placement: room-temp (out-of-plane)
readout: error-detected readout; logical bit-flip decay is second-order rather than exponential
gate evidence: no published figure
codes: dual_rail
flags: aggressive roadmap, specification absent
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Transmon · primary ▣ Fig. 1b (multimode qubit in coaxial cQED unit cell); §II ✅ Dimon multimode fixed-frequency transmon as dual-rail qubit in the Coaxmon stack; 16 physical sites, installed Digital Realty JFK10 NYC (Sep 2025) — (Atlas gap: ∅G-dimon) · alternate ▣ Fig. 1a,b (dimon level diagram, unit cell); §II ✅ Dimon: three islands, two junctions, one dual-rail qubit per device; the transmon node does not capture a multimode single-device dual rail |
| 2 Encoding | Dual-rail (erasure) encoding · primary ▣ Fig. 1a (logical subspace, error-detected states); §II ✅ dual-rail within one Dimon; 16 sites marketed as 16 logical (1:1); error-detected lifetime >1 ms, stable over 50 h (Jun 2025) |
| 3 Gate mechanism | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · alternate ▦ 🔎 no published entangling gate or gate mechanism; g_bos is an assumption — undisclosed — exists, nothing published ▦ 🔎 no published entangling gate, gate mechanism or 2Q gate fidelity |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▦ 🔎 nearest-neighbour lattice assumed; topology not published |
| 5 Control | Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring · primary ▣ Fig. 1b (coaxial unit cell); §II (shared coaxial control line) ✅ out-of-plane Coaxmon control; NVIDIA GH200 + CUDA-Q installed alongside at JFK10 (Sep 2025) Room-temperature electronics + per-qubit coax/flex · alternate ▨ 🔎 room-temperature control delivered out-of-plane (Coaxmon); NVIDIA GH200 + CUDA-Q alongside |
| 6 Readout | Mid-circuit erasure check · primary ▣ Fig. 1c,d (EOL three-state readout); Fig. 2 (erasure fraction) ✅ error-detected readout; logical bit-flip decay second-order not exponential; ~10× error-detected coherence vs constituent modes Dispersive microwave readout (+TWPA, Purcell) · alternate ▣ Fig. 1c (EOL readout signal); §II (dispersive shifts χ_QR, χ_DR) ✅ error-detected readout of the dual-rail Dimon; underlying dispersive readout not detailed |
| 7 Code | Erasure-adapted codes · primary ▤ abstract; device section 🔎 dual-rail encoding in a fixed-frequency dimon with erasure detection; the paper uses single-dimon test devices and does not name GENESIS (sweep 7 Oct 2026, source read) |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ §II (device and resonator on opposite sides of substrate; methods per ref. [43]) ✅ superconducting-qubit lithography; roadmap moves to 100 mm wafers for TITAN (2028) |
Standard records
T1 relaxation → 1.0 ms · best-of-line (error-detected logical lifetime, stable over 50 h)
Jun 2025 · source
evidence: ✅ 7 / 14