Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring ct_vio

Lines still start in room-temperature racks (ct_rt); only the last centimetre changes. Instead of a coplanar line routed to a wire-bond pad at the die edge, the signal enters through the chip's face — a spring-loaded or coaxial pin, a contact probe, a superconducting via, or a bump-bonded signal die. Waterloo's quantum socket (2016) pressed spring-mounted coaxial wires onto the chip D[532]; Oxford's coaxial circuit QED (2017) put qubit and resonator on opposite faces with all wiring perpendicular D[533], the root of OQC's coaxmon. RIKEN chose backside superconducting vias over flip-chip interfaces that still bring pads to the edge C[534] and reviewed the packaging this needs G[535].
Attributes: microwave control at room temperature; coherent error; superconducting-lithography fabrication.

Edge routing. In an m × m lattice every line serving a qubit inside a ring crosses the ring's ~4m inter-qubit gaps; with k lines per qubit and c per gap, routing closes at m = 4c/k — for k = 2 and c = 3–5, N ≈ 36–100 S. That is the ~100-qubit plateau QuantWare cites C[536], with "almost 90% of the chip" spent on routing C[537]. A flip-chip signal die raises c, but lines still leave through a perimeter ∝ √N while their number grows ∝ N — polynomial, not the vendor's "exponential fan-out" S. Vertical entry keeps lines per unit area constant, so the lattice tiles.
The line. A vacuum coaxial hole is 50 Ω at a diameter ratio of 2.3 S. OQC's 50 ± 2.5 Ω pins end 0.9 mm (qubit) or 0.4 mm (resonator) from the circuit and couple evanescently below the hole's cutoff: control-line selectivity −40 to −60 dB at 2 mm pitch D[538]. Non-galvanic pins carry no DC, so flux-tuned qubits and couplers need probes, vias or bumps S.
Box modes. A 20 mm silicon die can resonate as low as ~3 GHz, inside the qubit band S; OQC's inductive pillar lifts the enclosure cutoff to 34.3 GHz and bounds parasitic coupling to |J|/2π < 250 kHz D[538].
Heat is set per line, not by the route: OQC's fully wired wafer-scale package is estimated at ≤~3 µW on the MXC against 25–30 µW of cooling at 20 mK D[311].

Among the register's carriers, beyond 256 gate-coupled qubits only claims exist: VIO-40K (VIO is QuantWare's vertical-wiring architecture), 40,000 lines for 10,000 qubits in chiplet modules, shipping 2028 C[536]. No Japanese machine has a two-qubit error in the register, and OQC's package reports coherence and readout, not gates D[311].

Vias: MIT Lincoln Laboratory fabricates qubits on a TSV-bearing surface D[540]; Rigetti's sloped walls let evaporated or sputtered films coat the via D[539]. Pins: OQC's package manages differential thermal contraction across 3 inches with 0.5 mm pin gaps D[311]. Stacks: QuantWare integrates "all signal conditioning components" C[537] and opens KiloFab, Delft, in 2026 at 20× its 2025 capacity C[536]. Pin, via and bump yields at 10³–10⁴ contacts are unpublished as of 2026-09-26.

Vertical delivery moves lines; it does not remove them. RIKEN's 64 qubits take 112 lines C[542], 1.75 per qubit S; OQC's four-qubit device two per qubit D[538]; VIO-40K four C[536]. OQC's wafer-scale package shares each line among nine qubits, control riding on readout D[311] — ~0.11 per qubit S; the dimon, GENESIS's qubit C[543], drives both modes through one control line D[250]. At 10³ qubits that is 10²–4×10³ lines S; at 10⁴ QuantWare claims one cryostat C[537]; at 10⁶ only cold multiplexing — ct_cryocmos, ct_sfq — closes the gap S. Loop latency is unchanged S.

Slot 5 of "Transmon lattice with tunable couplers" and "Dual-rail erasure qubits". It requires ct_rt's electronics behind the vertical wiring and fab_sc's vias, pins and interposers; it and ct_rt replace one another ("edge-routed vs vertical signal delivery"); no provides edge is recorded. What it frees is the die edge, for chip-to-chip links between edge qubits C[537] — a precondition for ic_multidie. Ten register machines carry it (10 as primary). RIKEN 64 and RIKEN–Fujitsu 256 are ✅ on vendor figures; Toshiko's ✅ rests on the four-qubit paper, GENESIS's on the dual-rail paper, VIO-40K's on its announcement. The Fujitsu 1,000-qubit machine is 🔎: the cited article names high-density packaging, not perpendicular wiring P[546]; the 10,000-qubit cell's wiring is undisclosed. Contralto-A17 and Tenor-D64 are not among them: the source presents Contralto-A as "a cost-efficient upgrade path to QuantWare's VIO-powered QPUs", not as one C[544], and the D-line page pictures "VIO 1K" and "VIO 40K" modules without naming a processor C[545]. Gap G-vio, answered: lines per qubit span 0.11–4; routing-layer count is undisclosed by every carrier.

Line crosstalk exists only as OQC's four-qubit selectivity matrix D[538]; RIKEN, Fujitsu and QuantWare publish none in the sources opened, as of 2026-09-26. OQC's package is the one many-qubit dataset: median T1, T2e ~100 µs over ~100 qubits, readout fidelity 97.5% and qubit temperature 36 mK over 54 D[311]. Missing: simultaneous benchmarks over >100 lines; contact yield across thermal cycles.

Not published: whether IBM's Eagle-generation signals enter through the chip face; Rigetti Ankaa's signal delivery; QuantWare's impedance, yield and heat-load data for VIO, and which processor carries "VIO 1K"; and, for OQC's package with nine-way sharing over 56 cells, the number of lines entering the package and whether its qubits are coupled.

Money.

• 2026-05-05 · QuantWare · Series B led by Intel Capital and In-Q-Tel, naming VIO-40K and KiloFab · USD 178 M · announced C[547]
• 2026-06-02 · OQC · Series C led by Bullhound Capital, coaxmon not named · GBP 260 M · announced C[60]

Market & supply chain. RIKEN/Fujitsu and OQC build their own packages; QuantWare sells VIO to "scale the qubit chiplets and designs of third parties" C[547]. Serves G2–G4 (transmon) and G3–G4 (dual-rail).

IP & standards. OQC calls the coaxmon "patented" C[543], no number traced; QuantWare pitches VIO-40K as the standard of its Quantum Open Architecture P[495]. No standards body, as of 2026-09-26.

Roadmaps & track record. In July 2020 RIKEN aimed for a 64-qubit device "within the next three years" C[534] and opened it on 2023-03-27 C[542] — kept. Fujitsu still lists 1,000 qubits for 2026 C[75], no launch found as of 2026-09-26. QuantWare: VIO-40K 2028 C[536]; no interim VIO data, as of 2026-09-26.

Strategic reading. Past ~100 qubits vertical entry decides whether a die tiles, not whether a refrigerator can feed it; value moves to via, bump and pin capacity and to whoever first publishes crosstalk and yield at scale.

Confirm if, by 2027-12-31, a vertically wired processor above 256 qubits publishes two-qubit errors with simultaneous crosstalk; demote if Fujitsu's 1,000-qubit machine passes 2026-12-31 undisclosed or VIO-40K slips past 2028. Open questions. (1) What pitch holds selectivity below −40 dB at 1 mm qubit spacing? (2) Can non-galvanic pins serve flux-tuned couplers? (3) What is contact yield per thermal cycle at 10⁴ pins? (4) Does nine-way line sharing survive coupled qubits and gates? (5) At what scale does the stack's own heat bind?