QuantWare Bass-A10K (VIO-40K)

Raveh Neeman

doi:10.5281/zenodo.22674814

QuantWare · superconducting circuits · ANNOUNCED (A-line page: 'Shipping in 2027'; VIO-40K release: first devices to customers in 2028) (8 Dec 2025) · 10000 physical qubits · access: reservations open

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: tunable transmon

gate mechanism: chiplets stitched by "ultra-high-fidelity chip-to-chip connections" (no fidelity published)

connectivity: chiplet tiling without edge penalties

control: VIO (Vertical I/O): 3-D out-of-plane signal delivery through a stacked interposer

control placement: room-temp (out-of-plane)

readout: dispersive

gate evidence: no published figure

flags: no published error rates, a target, not a device

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▦ §VIO-40K announcement (QPUs with 10 KiloQubits) 🔎 tunable transmon chiplets; 10,000-qubit processor is a 2028 target spec, not a built device
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▦ §VIO-40K announcement (chiplet modules via ultra-high-fidelity chip-to-chip connections) 🔎 chiplets stitched by "ultra-high-fidelity chip-to-chip connections"; no fidelity figure published
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▨ ✅ chiplets tile without edge penalties (VIO removes the edge-routing penalty)
5 Control	Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring · primary ▦ §VIO-40K announcement (40,000 input–output lines; VIO 3D scaling architecture) ✅ VIO: 3-D out-of-plane signal delivery through a stacked interposer; up to 40,000 lines for 10,000 qubits (4 lines/qubit), 2028 target spec Room-temperature electronics + per-qubit coax/flex · alternate ▨ 🔎 room-temperature control lines delivered out-of-plane via VIO interposer (2028 target)
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ◌ 🔎 dispersive
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code run (announced architecture, first shipments 2028); customers run codes
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder (no QEC)
9 Interconnect	Multi-chip modules / l-couplers (same cryostat) · primary ▦ §VIO-40K announcement (consists entirely of chiplet modules connected via chip-to-chip connections) ✅ VIO chiplet tiling via chip-to-chip connections; interface fidelity unpublished; first customer shipments 2028
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▦ §VIO-40K announcement (Kilofab, Delft, opens 2026, 20× capacity) ✅ QuantWare superconducting QPU fab; KiloFab (Delft) opens 2026 for a claimed 20× capacity increase

Standard records

control lines per qubit → 4 lines/qubit · 2028 target specification, not a built device

40,000 I/O for 10,000 qubits · Dec 2025 · source

evidence: ✅ 4 / 11