Multi-chip modules / l-couplers (same cryostat) ic_mcm

A multi-chip module partitions one processor across several superconducting dies sharing a single dilution refrigerator, with quantum-coherent links between them. Two different links wear the label. The short one is a chiplet join: dies flip-chip mounted on a common carrier at sub-millimetre pitch, coupled through indium bumps or vacuum-gap capacitors, so an inter-die coupler is electrically a slightly longer on-chip coupler. The long one is IBM's "l-coupler", a superconducting cable of centimetre-to-metre length carrying a microwave mode between separately packaged modules under one mixing chamber. Both differ from inter-fridge links, which cross a room-temperature gap, and from on-chip long-range couplers, which never leave the die.

Lineage: Rigetti entangled qubits across four separate silicon dies in 2021-09, iSWAP 99.1 ± 0.5% and CZ 98.3 ± 0.3%, with a Bell violation between dies D[747]; SUSTech linked five modules with aluminium coaxial interconnects in 2023-02 D[748]; IBM says l-couplers were "first demonstrated in 2024" on Flamingo C[481], and in 2024-09 published low-loss indium joins for the superconducting cables of such links, tested on 1 m of aluminium coax with no qubit measured through it D[750]. The graph record dates the node to 2025, when tiling became a shipped product rather than a demonstration.

Attributes. Affinity: fully fabricated, a packaging structure with no natural counterpart. Characteristic time and determinism: not applicable — the node carries no entangling primitive, it inherits the gate it transports. Readout: none. Mobility: long-range, the property it exists to supply. Control: microwave at millikelvin. Error structure as the code sees it: coherent. Manufacturing: superconducting lithography plus packaging steps.

The short-link floor is frequency crowding, not loss. Each chiplet is a separate fabrication instance with its own junction-resistance distribution, so tiling k dies convolves k frequency distributions that were never co-targeted; collisions between qubit, coupler and inter-die modes are fixed at packaging time and cannot be tuned away. Hence the coherent error structure: a mis-set detuning is a deterministic phase, not a stochastic click. The bonds themselves are benign — Rigetti's multi-chip tunable couplers, built from vacuum-gap capacitors or indium bumps, reached a CZ of 99.13 ± 0.15% in 56 ns through a coupler bridging four chips, "at the same level" as a single-chip tunable coupler, with no coherence penalty from one or more bonds D[749].

The long-link floor is cable loss and mode density. A metre-scale cable is a multimode resonator whose free spectral range is of order 100 MHz, so tens of modes fall in the 3–5.5 GHz band the qubits use D[750]. Loss sets transfer error: at an internal quality factor of 1.24 × 10⁶ on an indium press-mold cable-to-chip join, photon lifetime is Q/ω ≈ 49 µs, so a 100 ns inter-module SWAP costs about 2 × 10⁻³ S[750]. Joins dominate in practice — contact resistances of 6 × 10⁻⁴ Ω at an inner-conductor splice and 8.5 × 10⁻⁴ Ω cable-to-chip are the measured levers D[750].

Underneath both is a yield argument: monolithic yield falls as y^N in qubit count, and tiling k chiplets of n qubits replaces one exponential with k smaller ones plus an assembly step. The price shows in the only shipped data, 99.5% at four chiplets against 99.1% at twelve C[36], [751]. Moving the floor needs co-targeted junction trimming across a chiplet set Dfact and joins whose loss and mode comb stay out of the way.

Best demonstrated as of 2026-09-03: inter-module SWAP at the 99% level in under 100 ns between two modules in one cryostat, remote-entanglement error near 1% D[752]. Typical at scale: Rigetti's Cepheus-1-108Q, 108 qubits from twelve 9-qubit chiplets, median two-qubit 99.1%, single-qubit 99.9%, ~60 ns gates C[36]. No l-coupled processor exists; IBM's 2026 milestone is two coupled cryogenic cells with no qubits in them C[50].

The dominant term is not the interconnect. Rigetti's own comparison isolates it: same chiplet, same join, three times as many, 40 basis points of two-qubit fidelity lost C[36], [751]. Nothing published attributes that loss, which makes frequency targeting across a tiled set the leading suspect and the leading unknown.

Superconducting lithography plus a packaging line: flip-chip bonding, indium bumps or press-mold joins, through-silicon vias, a carrier. IBM builds on 300 mm at Albany NanoTech Cfact; QuantWare sells 3D vertical integration as a product — a stack of chiplet modules with chip-to-chip connections targeting 10,000 qubits, first delivery 2028, with a Kilofab in Delft opening 2026 to raise capacity 20× P[495]fact. Rigetti fabricates 9-qubit chiplets on its own line C[751].

The single points of failure sit outside the fab. The cryostat is one: IBM's cell architecture is a bespoke refrigerator programme, and the merchant alternative is Bluefors' KIDE, quoted at more than 4,000 RF lines and "over 1000 qubits" on nine pulse tubes Cfact. Bump-bond and TSV capacity for superconducting stacks sits with a handful of lines — Albany, Kilofab, GlobalFoundries under its CHIPS letter of intent fact, SkyWater now inside IonQ fact. Export exposure is uneven. The BIS rule of 2024-09-06 puts dilution refrigerators rated ≥ 600 µW at ≤ 0.1 K under ECCN 3A904, but a quantum computer under 4A906 only when its qubit count and its C-NOT (controlled-NOT gate) error fall in the same band — 34–99 qubits at ≤ 10⁻⁴, 100–199 at ≤ 10⁻³, the ceiling rising to 6 × 10⁻³ below 2,000 qubits, any error from 2,000 on fact. Rigetti's 108 qubits at a median two-qubit error near 9 × 10⁻³ C[36] fall outside 4A906, so a refrigerator of that class can be controlled while the tiled processor it cools is not.

Packaging does not reduce lines per qubit; it relocates them and buys wiring area. At 10³ qubits one merchant cryostat suffices — KIDE's 4,000-plus RF lines cover it Cfact. At 10⁴ the choice is 40,000 lines through vertical I/O, QuantWare's 2028 promise Pfact, or cold multiplexing. At 10⁶ neither works: many cells plus on-chip control generation, whose published pointer is millikelvin SFQ control at 1Q > 99% fact.

Latency is not the l-coupler's problem — the demonstrated inter-module SWAP is under 100 ns D[752] against a 280 ns readout at 99.94% fidelity D[38]. The decoder is: cross-module syndrome extraction must close inside a ~1 µs cycle while a parity check spans two packages, and no such demonstration exists as of 2026-09-03. NVQLink's 3.84 µs round trip Pfact is a host-QPU budget, far too slow for an intra-cryostat check.

Three architectures use it: superconducting transmons, superconducting bosonic cat/GKP, superconducting dual-rail erasure. It requires superconducting-qubit lithography with multilayer routing and flip-chip packaging. It replaces inter-fridge cryogenic links, and the price is thermal: everything shares one cooling budget and one vacuum, so scaling stops at the fridge rather than at the network. Its contribution is manufacturability, not gate physics.

A fabricated carrier acquires far-range connectivity through packaging, where atoms and ions acquire it through motion. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: 0.65 µs, readout at ≈ 280 ns its largest term, and the < 100 ns inter-module SWAP D[752] is at most about 15% of the round (100 of 650 ns), so transport does not bind. Neighbouring empty slots: cross-module error correction, and a qLDPC code whose checks span modules — compilation for such machines exists only in simulation S[753].

Rigetti's 99.1% and 99.5% are company medians without error bars or a stated protocol C[36], [751]; the 2021 die-to-die numbers carry explicit uncertainties D[747]. SUSTech's 99% is a state-transfer and Bell-state fidelity, not a gate fidelity, and its 12-qubit GHZ at 55.8 ± 1.8% shows what five linked modules do at depth D[748]. The Illinois figure is a SWAP efficiency with a separately stated ~1% error called threshold-level; the two should not be conflated D[752]. IBM's coupled-cell result contains no qubits and no fidelity claim C[50]. No value conflicts were found; the gap is that nothing explains the 99.5% → 99.1% step.

Neither arXiv:2308.09240 (Rigetti; cross-chip CZ 99.13 ± 0.15% in 56 ns) nor arXiv:2409.04634 (IBM Quantum, T. J. Watson Research Center; cable joins, no qubit measured) has a journal version as of 2026-09-30. The 40,000 I/O lines of QuantWare's Bass-A10K (VIO-40K) rest only on QuantWare's own release of 2025-12-08 fact, which the trade-press page of 2025-12-10 P[495] omits, and no delivered device confirms them. Not published: a gate fidelity or latency through IBM's l-coupler, "first demonstrated in 2024" on Flamingo C[50], [481], whose cable joins were tested on 1 m of aluminium coax at internal Q ≈ 10⁶ D[750], as of 2026-09-30; and a dated assignee record for Rigetti's chiplet-packaging and QuantWare's vertical-I/O patent families.

Money.

• 2025-11-06 · IBM · DARPA QBI Stage B selection · up to $15 M each · DARPA · announced fact
• 2026-05-05 · QuantWare · Series B · $178 M (€152 M) · Intel Capital, In-Q-Tel, ETF Partners, no single lead · cumulative > $210 M · closed Pfact
• 2026-05-21 · Rigetti · CHIPS letter of intent · up to $100 M · Dept of Commerce, within a $2.013 B package (GlobalFoundries $375 M, IBM/Anderon $1 B) · LOI, non-binding fact
• 2026-07-31 · IonQ · acquisition of SkyWater Technology · ~$1.8 B at announcement · closed fact
• 2026-08 · Rigetti · Q2-2026 results · revenue $5.1 M, GAAP loss $52.6 M, cash $541.3 M · reported fact

Market & supply chain. No one sells an l-coupler; it is a captive design block. The merchant layer is one company deep — QuantWare is the only vendor selling 3D-integrated multi-chip QPUs to third parties P[495] — plus Bluefors for the enclosure and a short list of lines that can do superconducting flip-chip at volume. Who pays: G3 and G4 above all, since Starling depends on modules rather than a bigger die; G7 for deployable multi-cell systems; G2 through wider processors.

IP & standards. IBM holds US 12,517,856, "Modular quantum system with discrete levels of connectivity" (filed 2022-09-28, granted 2026-01-06), and US 12,587,192 on chains of resonators with tunable inductive couplers (granted 2026-03-24) fact — the l-coupler's cable joins are published D[750], a gate fidelity through one is not. For Rigetti's chiplet packaging and QuantWare's vertical I/O, no dated patent fact was found within budget. There is no inter-module interface standard and no open-source packaging stack.

Roadmaps & track record.

• IBM: promised 2025-06-10 · l-couplers demonstrated on Flamingo in 2024 · claimed delivered, no link fidelity published as of 2026-09-30 C[481].
• IBM: promised 2025-06-10 · Cockatoo 2027, entanglement between modules via the universal adapter; Nighthawk on nine l-coupled modules for 1,080 qubits by 2028 · pending R[481] fact.
• IBM: promised 2022-05-10 · Kookaburra, a 1,386-qubit multi-chip processor, for 2025 C[313]; re-promised 2025-06-10 for 2026 as the first module with a qLDPC memory R[481] · not delivered as of 2026-09-30 fact.
• Rigetti: promised 2025-07-16 · 100+ qubit chiplet system at median 99.5% before end-2025 · delivered 2026-04-07 at 99.1%, target moved to "later in 2026" C[36], [751].
• QuantWare: promised 2025-12-08 · VIO-40K (VIO is QuantWare's vertical-wiring architecture), 10,000 qubits, first delivery 2028 · pending Pfact.

Credibility: IBM meets its single-chip processor dates but not its multi-chip one — Kookaburra, promised for 2025, is undelivered — and publishes packaging as architecture rather than measurement, so its modular claims stay unfalsifiable until Cockatoo; Rigetti ships what it describes, a fidelity step behind its own target; QuantWare has money and a fab but no delivered multi-chip QPU at scale to judge.

Strategic reading. If multi-chip modules work, the decisive asset moves from lithography to packaging and cryogenics, and the winner is whoever controls bump-bond, TSV and fridge capacity — IBM by vertical integration, QuantWare by merchant supply, IonQ through SkyWater. The loser is any roadmap assuming a single ever-larger die. Substitution threats: on-chip long-range couplers, which buy connectivity without packaging risk, and inter-fridge links, which buy unlimited scale at the price of a room-temperature crossing. Supplier bargaining power is high: there are more credible qubit vendors than lines that can bond them.

Confirm within 12–24 months if: IBM's Cockatoo demonstrates entanglement between two l-coupled modules with a published fidelity by end-2027 R[481]; Rigetti's 108-qubit system reaches median 99.5% C[36]; anyone runs a stabiliser round whose checks cross a module boundary. Demote if no l-coupler fidelity is published by end-2027. Best case by 2029: a few thousand qubits in coupled cells with cross-module error correction at Λ comparable to monolithic. Worst case: tiling saturates near 10² qubits because frequency targeting across dies does not scale.

Open questions: what causes the 40-basis-point tiling tax, per-join or per-calibration? Can a metre-scale cable's mode comb be pushed out of band without shortening it? What is an l-coupler's fidelity, two years after the claim? Does a qLDPC check spanning modules survive the extra transport error? Watch Rigetti's roadmap update, IBM's first Cockatoo measurement, QuantWare's Kilofab yield, and any paper benchmarking a chiplet boundary as such.