IBM Quantum Kookaburra
IBM Quantum Kookaburra
Register profile — the machine's variant of its architecture
qubit type: fixed-frequency transmon
gate mechanism: tunable coupler + c-coupler
connectivity: degree-6 Tanner graph for [[144,12,12]]
control: room-temperature RF
control placement: room-temp
readout: dispersive
gate evidence: no published figure
decoder mode: planned — named in a roadmap only
codes: gross
flags: schedule risk
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to |2⟩ is the price. |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▤ 🔎 tunable coupler + c-coupler; named first c-coupler vehicle (PLANNED) |
| 4 Connectivity / transport | Long-range on-chip couplers (c-couplers, mm-scale) · primary ▣ Fig. 1a (bicycle architecture: long-range-connected modular hardware) ✅ degree-6 Tanner graph for gross [[144,12,12]] code (intended) |
| 5 Control | |
| 6 Readout | |
| 7 Code | Non-local qLDPC codes (bivariate bicycle, 'gross') · primary ▣ Fig. 1a (qLDPC bicycle architecture); §2.1 Review of bivariate bicycle codes ✅ gross [[144,12,12]] qLDPC memory with attached logical processing unit (LPU); PLANNED 2026, not demonstrated |
| 8 Decoder | Relay-BP for qLDPC (FPGA) · primary ▣ Fig. 8b (Kookaburra memory experiment real-time budget); Fig. 5 (XCVU19P floorplan) ✅ Relay-BP on FPGA for [[144,12,12]], intended in-loop; hardware testing expected as early as 2026 with Kookaburra |
| 9 Interconnect | Multi-chip modules / l-couplers (same cryostat) · primary ▣ Fig. 2 (module components: code, LPU, factory, code-code adapter) ✅ multi-chip module interconnect (intended); not delivered |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 superconducting-qubit lithography (Nb/Al JJ) |
evidence: ✅ 4 / 10
Pictures
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