Relay-BP for qLDPC (FPGA) dec_relaybp

Belief propagation in which each variable node carries its own memory strength — a damping coefficient drawn from a disordered distribution that must include negative values — with decoding run as a chain of relay legs, each restarted from the previous leg's messages. IBM (Müller, Alexander, Beverland, Bühler, Johnson, Maurer, Vandeth) introduced it on 2025-06-02 D[734]; a second IBM team put it on an FPGA on 2025-10-24 for the [[144,12,12]] gross code D[48]fact. Attributes: d = no physical connectivity, an off-chip classical block; e/f/g = no control modality, corrects Pauli errors, no fabrication — an FPGA bitstream (graph record).

The limit is an accuracy-versus-latency budget, not a physical one. Plain BP stalls on degenerate stabiliser codes — distinct error patterns carry identical likelihood, so messages oscillate into trapping sets — and the standard repair, ordered-statistics post-processing, has a data-dependent cost no real-time loop absorbs. Relay-BP's claim is that disordered memory strengths break exactly the symmetry that stalls BP, making the post-processor unnecessary; the paper states a distribution containing negative values is indispensable D[734].

That buys latency: 24 ns per BP iteration and an average per-cycle decoding time under 1 µs for physical error probabilities below 3×10⁻³ D[48]. Average is where the risk sits — iteration count is data-dependent, so the latency distribution has a tail, and a decoder fed a fixed-rate stream at the 1.1 µs superconducting cycle must buffer, the backlog diverging rather than degrading if that tail exceeds the cycle time often enough. Neither paper reports anything but the mean. The second floor is the error rate itself: above 3×10⁻³ iteration counts climb, so the real-time property is conditional on the hardware already being good. What moves the floor: an ASIC, or windowing that commits early cycles while later ones converge.

Both FPGA results are simulation-driven: no gross-code memory has run on any QPU, so Relay-BP has never consumed a hardware syndrome R[72]fact. The target code is IBM's [[144,12,12]], 288 physical qubits at a 0.8% threshold on a degree-6 Tanner graph D[248]fact; the only qLDPC break-even claim anywhere is IonQ's trapped-ion result — within error bars, in one code the paper does not identify, leakage post-selected D[109]fact.

No fabrication process: the deliverable is a bitstream and the supply chain is merchant FPGA silicon, a duopoly restructured in 2025, when Intel's sale of 51% of Altera to Silver Lake at an $8.75 B valuation — ~$4.46 B to Intel, which keeps 49% — closed on 2025-09-15 G[735]fact. Every named real-time decoder here runs on AMD parts (Riverlane's LCD on a VU19P D[238]), and IBM's is reported as AMD by trade press whose page could not be retrieved P[736]fact. No decoder-specific export-control category exists as of 2026-09-04.

The decoder drives nothing; its burden is syndrome bandwidth and fan-in. One gross module is 144 data plus 144 check qubits, so a cycle yields 144 bits — ~0.14 Gbit/s per module at a 1 µs cycle S[248]. Scaled naively, 10⁴ physical qubits is ~5 Gbit/s and 10⁶ ~0.5 Tbit/s at fixed rate: the wall is not BP arithmetic but getting bits out of the cryostat into enough parallel instances.

It requires the bivariate bicycle/gross qLDPC family and replaces minimum-weight perfect matching; the graph records it as the primary decoder on trapped ions with electronic gates and on continuous-variable photonic GKP, and as an alternate on the transmon lattice with tunable couplers and the linear Paul trap with individual laser addressing. Derived clock contribution: < 1.0 µs per cycle (2 s.f.), the first qLDPC decoder figure that fits inside a 1.1 µs superconducting cycle without an offline pass D[48]; surface-code decoders such as Riverlane's LCD already fitted D[238]. Switching costs a code change, not a board change: gross codes need degree-6 long-range couplers IBM has shown only as components, where LCD assumes the nearest-neighbour grid hardware already has D[238]fact. Adjacent empty slot: a merchant decoder ASIC.

Every headline is from simulated syndromes under a uniform circuit-noise model of strength p, with neither leakage nor correlated bursts — the dominant real-device terms D[48], [734]. No independent group has reproduced either number, and Riverlane's LCD uses a different code and FPGA, so the two are not commensurable D[238].

Not published: the FPGA part, its lookup-table (LUT) and memory use and the arithmetic precision — the AMD attribution rests on trade press [736] — and any latency distribution or tail percentile; only the average is given.

Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IBM | Developer | USA | Invented Relay-BP and built the FPGA implementation for its gross code | D[48], [734] |
| AMD | Supplier | USA | Xilinx FPGA silicon under IBM's demonstration and most rival decoders | P[736]fact |
| Altera | Supplier | USA | The only other merchant high-end FPGA source; 51% Silver Lake-owned since 2025 | G[735] |
| Riverlane | Developer | UK | Competing FPGA decoder for the surface code, sold as a product | D[238]fact |
| DARPA | Funder | USA | QBI Stage B funds IBM's fault-tolerance programme this serves | G[65]fact |

Money. 2024-08-06 · Riverlane · Series C · $75 M (its 2026 roadmap says $85 M — unreconciled) · Planet First Partners lead · closed C[661]fact. 2025-09-15 · Intel/Silver Lake · 51% of Altera at $8.75 B valuation, ~$4.46 B to Intel · closed (announced 2025-04-14) G[735]fact. 2025-11-06 · DARPA · QBI Stage B, up to $15 M each, IBM the only transmon vendor · awarded G[65]fact. Relay-BP itself has no round, grant or licence: in-house IBM work as of 2026-09-04.

Market & supply chain. Decoding is priced as bundled firmware, not silicon: Riverlane sells Deltaflow, integrated with Qblox control hardware C[659]fact, IBM ships Relay-BP inside its own stack. Concentration risk is FPGA supply — two vendors, one newly under private-equity control G[735]. Goal exposure is narrow, G3 and G4 only: a real-time decoder is worthless until a code needs it, so willingness to pay is vendors insuring their own 2027–2029 roadmaps.

IP & standards. Riverlane holds GB 2641501 A "Quantum decoder" (published 2025-12-10) on hardware clustering over the decoding hypergraph fact; IBM's bivariate bicycle estate covers the code, not the decoder, and no Relay-BP family appears in any named database. No standards body addresses decoder interfaces.

Roadmaps & track record. IBM: (2025-06 · Relay-BP algorithm · delivered); (2025-10 · FPGA implementation · delivered); (Kookaburra · promised for 2025 in the 2022 roadmap, re-promised for 2026 as the first qLDPC module · not delivered as of 2026-09-30) R[72]factfact. Riverlane: (2026-03 · teraquop decoding from 2033 · too early) Cfact. IBM's decoder software is on time twice over; the hardware it decodes is not.

Strategic reading. If Relay-BP holds up, IBM removes the strongest objection to qLDPC — that its decoder cannot run in real time — and the ~10× qubit saving over the surface code becomes bankable, hurting surface-code-shaped roadmaps and helping whoever can build degree-6 connectivity. If not, matching decoders keep the field. Decoding is becoming a component business with no dedicated supplier: two FPGA vendors, one GPU vendor pushing an alternative, no merchant ASIC. Bargaining power stays with the QPU vendor that picks the code.

Falsifiable (12–24 months): confirm if Kookaburra ships and a gross-code memory is decoded in real time by end-2027; demote if Relay-BP has consumed no hardware syndrome by then. Best case 2029: Relay-BP-class decoding inside IBM's Starling stack at the demonstrated latency. Worst case: gross-code hardware keeps slipping and GPU or matching decoders take the installed base. Open questions: the 99.9th-percentile latency rather than the mean; whether accuracy survives leakage and correlated bursts; whether anyone builds a decoder ASIC. Watch: Kookaburra delivery, any live-syndrome decode, the first latency histogram.