Trapped ions — electronic qubit control (laser-free, microwave-driven gates) on the map bar: Electronic ion gates

The architecture in the report (§8.3)

8.3.6 Electronic ion gates — Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (ion_elec)

The idea. Take the laser out of the entangling gate: currents in the trap chip's electrodes make a microwave field whose gradient couples a hyperfine ion qubit to the shared motion (g_elec); drive traces are shared and local tuning electrodes select the ions [D][257]. A microwave photon reaches no excited state, so laser gates' scattering floor vanishes: 8.4×10⁻⁵ on two ions, without ground-state cooling [D][102]. Speed is the price, since a stronger gradient puts the ion nearer heating surfaces: 225.8 µs per gate [D][102] against ~70 µs on Helios [D][97]. The bet: control that scales like electronics, ~200 sources for 1,000 ions [S] (§7.5).

What it needs. The gate requires chip-integrated microwave control (ct_ionmw), which requires current traces in the trap: the chip is the control system, with no fallback to laser gates. Lasers remain for cooling, state preparation and fluorescence readout. Carrier, gate, control, readout and interconnect have one technology each; elsewhere the options replace each other: chain bus or shuttling, qLDPC or high-rate codes (both require all-to-all), Relay-BP or matching, trap microfabrication or a 300 mm CMOS line. Without transport the derived syndrome round is gate-limited: 1.52 ms, 1.4 ms of it in gates [S] (§7.4).

Where it stands. Seven machines, three devices, no code, decoder or link run. QUARTET (Oxford Ionics/IonQ), at the UK's National Quantum Computing Centre, is the largest at 32 qubits (Table 8.3), a count no primary source gives; its evidence paper shows a seven-zone chip for up to 10 qubits [D][257]. JION (eleQtron with Forschungszentrum Jülich), inaugurated on 3 Sep 2026, runs 30 ytterbium ions with no published fidelity [P][258]; its predecessor QSea I, eleQtron's 10-qubit demonstrator for the DLR Quantum Computing Initiative, has run in Hamburg since July 2024 [C][327]. Hence no best error in Table 8.3: the 99.99% is a two-ion record [D][102]. Superion 256 is orderable: SkyWater-made chips, ions trapped in prototypes, no 256-qubit fidelity [C][119]; IonQ Superion 10K (commercial 2028) [R][119] and NFQC-1k (≥1,000 physical, 50 logical qubits by 2030) [R][126] are plans; XAPHIRO (QUDORA NFQC) is under construction — a first ion trapped in June 2025, fifty qubits due by January 2027; only its emulator is reachable.

Exceptions and borrowings. No cell leaves the architecture's slots; the exceptions are in the evidence. Superion 256 alone fills all ten layers, from plans: a qLDPC code from a resource estimate [S][112], a claimed photonic link [C][119], a Relay-BP cell reading "algorithm not named" while IonQ's published decoder runs on one CPU [S][111] (mislabelled), a metastable-encoding alternate citing nothing. Layers 7–9 are IonQ's intentions. IonQ Superion 10K and NFQC-1k leave four layers undisclosed: early stage. JION's MAGIC (magnetic-gradient-induced coupling) addresses ions by frequency in a static gradient, a second mechanism inside a technology defined by the near-field one: drawn too widely. QUARTET's shuttling alternate has no timeline. Universal Quantum's iQPU (QCCD architecture) borrows the gate and control technologies and fits both architectures equally: a hybrid.

The next test. Superion 256 is due at NVIDIA's research centre and Florida International University in 2027 [C][130], [131]. Confirm if it is commissioned by end-2027 near 10⁻⁴ two-qubit error over the full register, publishing gate time, heating and crosstalk (§5.2). Demote if it slips beyond 2027, or if its error lands tenfold above the two-ion record once hundreds of microwave channels share a die: electronic control would then remain the single-qubit layer of laser-entangled machines.

What the builders say. Oxford Ionics argues that one high-fidelity qubit is worth hundreds of poor ones, projecting 13 physical qubits per logical qubit and, without dates, 10,000+ qubits by replicating its 256-qubit design [C][843]. IonQ, its owner since 2025, expects electronic control to cut the cost per qubit over 300-fold against lasers and takes orders for Superion 256, delivery in 2027 [C][119]; with CMOS on the chip it promises full fault tolerance in its laboratory in 2027 and commercially in 2028 [R][119]. eleQtron calls MAGIC, microwave control with a magnetic-field gradient, a clear path to scale [C][128], [129], and opened JION at Jülich in September 2026 [C][844]. QUDORA's consortium aims within five years at a demonstrator of 1,000 physical and 50 logical qubits below 10⁻⁴ logical gate error [R][126].

Machines of this architecture (register: 7, of them 3 devices, 3 gate-capable). IonQ — IonQ Superion 10K (planned, 10,000), Superion 256 (announced, 256); Oxford Ionics (IonQ) — QUARTET (deployed, 32); QUDORA Technologies — XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative) (announced); QUDORA Technologies-led consortium (TU Braunschweig, Leibniz University Hannover, PTB, Forschungszentrum Jülich, NXP Semiconductors Germany, AQT Germany) — NFQC-1k (planned, 1,000); eleQtron + Forschungszentrum Julich — JION (deployed, 30); eleQtron with NXP Semiconductors and ParityQC, for the DLR Quantum Computing Initiative — QSea I (DLR QCI ion-trap demonstrator) (deployed, 10).

Cells outside the architecture's slots (10). IonQ Superion 10K: L4 undisclosed where the architecture expects a technology; IonQ Superion 10K: L8 undisclosed where the architecture expects a technology; IonQ Superion 10K: L9 undisclosed where the architecture expects a technology; Superion 256: L7 undisclosed where the architecture expects a technology; Superion 256: L8 undisclosed where the architecture expects a technology; XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative): L4 undisclosed where the architecture expects a technology; NFQC-1k: L4 undisclosed where the architecture expects a technology; NFQC-1k: L7 undisclosed where the architecture expects a technology; NFQC-1k: L8 undisclosed where the architecture expects a technology; NFQC-1k: L9 undisclosed where the architecture expects a technology.