Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) fab_trap

A surface-electrode trap flattens the Paul trap into one lithographic plane — electrodes side by side, the ion held tens of micrometres above — so trap geometry becomes mask layout. NIST demonstrated it in 2006, holding ²⁴Mg⁺ about 40 µm above planar gold and measuring the heating rate directly D[806]. The machined 3D trap persists beside it: AQT's Pine trap has four blade electrodes and two endcaps machined from gold-plated titanium on an alumina holder, the blades 0.57 mm from the trap axis D[253]. It is the layer beneath the ion carrier: it fixes electrode count, zone and junction geometry, and the surface chemistry above it.
Attributes: carrier affinity a = 0.0, natural — the carrier served is the ion; the trap itself is fabricated, but MEMS trap-making is the natural carriers' default, so the technology sits in the natural half of the map. Manufacturing g = MEMS lithography moving onto merchant 6–12-inch semiconductor lines C[320].

The floor is anomalous field noise from the electrode surface, not lithographic resolution. Over ion heights of 30–3,000 µm it falls roughly as d⁻⁴ D[807]: halving the height to pack zones costs ~16× in heating. Heating becomes gate error, since entangling gates ride a shared motional mode for tens to hundreds of microseconds, and forces re-cooling between transport steps. The noise is an adsorbate layer, not a bulk property: cooling gold traps to 6 K suppressed heating ~7 orders of magnitude D[808]; argon-ion bombardment cut it 100-fold on an already-clean trap D[809]. The error structure the code sees is coherent and correlated — stray charge on dielectric gaps gives micromotion and phase drift shared across a zone, and one open electrode kills that zone. What moves the floor: niobium electrodes, in-vacuum cleaning, shielded dielectric, cryogenics by default.

Helios's chip is the largest fielded trap; most groups still run bespoke traps of tens to ~100 electrodes. Nobody publishes yield, defect rate or cost per trap, so the layer has no public quality metric, and measured error stays dominated by heating, micromotion and calibration load, not lithographic defects.

Two lineages. Research MEMS lines (Sandia's MESA complex, GTRI, university cleanrooms) put gold or niobium on sapphire, fused silica or oxidised silicon at one-off volumes G[501]. The live shift is merchant fabrication: Infineon's Villach platform runs 6–12-inch wafers with anodic bonding for Oxford Ionics, eleQtron C[129], Innsbruck and ETH Zürich; its Gen-3 out-of-plane electrodes claim ~10× confinement with no heating rate published C[320]. Honeywell fabricates Quantinuum's traps captively, Sol's grid trap included R[118]; IonQ closed SkyWater on 2026-07-31 for design, fabrication and packaging on US lines C[19]. Infineon is the single point of failure: one merchant fab, several vendors, no second source named. Export exposure is mild — the 2024-09-06 BIS rule enumerates quantum computers (4A906) and sub-4.5 K electronics (3A901), but no ECCN names traps G[301].

The trap sets the wiring floor before any optical or microwave line exists: 273 independent signals for 98 ions, 2.8 per qubit, for confinement and transport alone D[97], each a DAC channel, filter and feedthrough. At that ratio 10³ ions needs ~3,000 DC lines, past practical feedthrough counts, and 10⁶ is impossible without switching under the trap. The published escape is on-chip switching: Oxford Ionics' WISE drives 1,000 fully connected ions from ~200 sources, with no chip built and no dissipation budget S[325].

This layer underlies all three trapped-ion architectures — QCCD (Quantinuum), the linear Paul trap with laser addressing (IonQ, AQT, Quantum Art P[125]) and electronic gates with chip control (IonQ/Oxford Ionics, eleQtron) — providing the carrier, the junction and grid geometry, and traces for chip-integrated microwave control. It replaces bespoke MEMS with foundry fabrication, priced in design-rule and UHV qualification and re-measured heating, not physics. Its clock contribution is indirect and large: derived clock = sum of the syndrome round: gate layers + transport + readout + reset, and transport is 9.0 ms of the 9.7 ms round derived for QCCD, against a ~70 µs gate D[97]; measured on H2, transport took 60% of circuit time on average D[110] — so zone count and junction quality buy more clock than gate speed. No neighbouring empty slot in the technology graph.

Electrode and signal counts are vendor-reported and unaudited. Heating is published per trap at one operating point, never as a wafer or batch distribution, and no vendor discloses yield. The 8.4×10⁻⁵ gate is a two-ion measurement without ground-state cooling, not a fleet average, unreplicated externally as of 4 Sep 2026 D[102]. No dated dispute between vendors over fabrication claims was found.

No ECCN names ion traps, and no BIS advisory opinion places a bare ion-trap die inside or outside 4A906. Not published: the defect rate and cost per trap, from IonQ, Quantinuum, Infineon, AQT or eleQtron, as of 2026-09-04; whether Infineon fabricated the chip behind the 8.4×10⁻⁵ result — the Oxford Ionics–Infineon link is asserted at company level only; and a heating rate for Infineon's Gen-3 out-of-plane electrodes, so their ~10× confinement gain is unmeasured.

Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| IonQ | developer | US | Owns trap design house and a US foundry | C[19] |
| Oxford Ionics | developer | UK | Electronic-gate trap chips on commercial fab lines | D[102] |
| Infineon Technologies | supplier | Austria | Merchant trap fab, Villach, 6–12-inch wafers | C[320] |
| SkyWater Technology | supplier | US | US foundry, eight quantum-computing engagements in 2025, IonQ-owned since 2026-07-31 | G[576]C[19] |
| Quantinuum | developer | US | Fields the 1,228-electrode trap; Sol in validation | D[97] |

Money.

• 2025-09-17 · IonQ · M&A (Oxford Ionics) · $1.075 B · — · closed fact
• 2026-07-31 · IonQ · M&A (SkyWater) · ~$1.8 B ($15.00 cash + 0.4883 IonQ shares per share) · — · closed C[19]fact
• 2026-02-25 · SkyWater · FY2025 results (year to 2025-12-28) · $442.1 M revenue, 19.7% GAAP gross margin, quantum-related revenue +30% YoY · filed G[576]
• 2025-11-06 · DARPA · QBI Stage B (IonQ, Quantinuum of eleven) · ≤$15 M each · announced G[65]fact

Market & supply chain. Enabling equipment is ordinary semiconductor capital plus UHV parts, none concentrated; concentration sits in the fab — Infineon merchant, Honeywell captive, Sandia research-only, plus an IonQ–Sandia co-design MOU on 2026-08-04 C[584]. Trap unit economics are unpublished; the nearest number is SkyWater's 19.7% GAAP gross margin on $442.1 M of FY2025 revenue G[576]. G3 and G4 pay for this layer, G7 for rack modules.

IP & standards. PatSnap's 2026 review names MIT Lincoln Laboratory's chip-integrated voltage-source and photonics families (2016, 2019) and ETH Zürich's cryogenic co-fabricated optics (2020) as core integration IP, with no count isolated to trap fabrication P[375]. The key wiring architecture is published, not fenced S[325]; no litigation, no acceptance standard.

Roadmaps & track record. Quantinuum: Sol on a Honeywell-fabricated grid trap (promised 2024-09-10 · for 2027 · in validation as of 2026-09-03) R[118]; Helios shipped on time, so fab-linked credibility is good. IonQ: SkyWater (promised 2026-01-26 · for Q2–Q3 2026 · closed 2026-07-31) C[19], but 10,000 ions on one chip in 2027 rests on no published 2D-trap heating or yield data, and the 2020 roadmap missed its 2026 count ~40×.

Strategic reading. If foundry fabrication works, the differentiator moves off trap craft onto control electronics, packaging and codes. Winners: IonQ, which removes a fab dependency; Quantinuum, already captive-supplied; Infineon, which gains everyone else's volume. Losers: national-lab lines lose their monopoly. The substitution threat is not a rival trap but the clock — fabrication cannot fix a layer time 10³–10⁵× slower than superconducting unless it multiplies zones. Power sits with the fab; IonQ bought one, and carries its ~20% gross margin.

Confirm or demote by end-2027: does a SkyWater-fabricated trap hold ions in a shipped system; does Sol validate on schedule at 1,200+ electrodes in 2D; does anyone publish a yield or per-wafer heating distribution. Best case 2029: merchant trap wafers with published acceptance data and switching that cuts signals per ion five-fold. Worst case: electrode counts plateau near 10³ because feedthroughs and DAC channels are the wall, and tighter 2D geometry raises heating enough to push Apollo right. Open questions: does a 2D grid keep the linear trap's heating rate; can switching run at 4 K inside a dissipation budget; will Infineon stay merchant.