Sol
Sol
Register profile — the machine's variant of its architecture
qubit type: hyperfine clock qubit
gate mechanism: laser Molmer-Sorensen; circuits of up to 10,000 quantum operations
connectivity: 2-D grid trap - the scalability foundation (Helios is a junction-routed racetrack)
control: room-temperature electronics; ~2x faster than Helios
control placement: room-temp + optics
readout: fluorescence
gate evidence: a published figure (source class not yet tagged)
decoder mode: planned — named in a roadmap only
codes: iceberg
flags: a target, not a device
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Trapped atomic ion · primary ▥ §How do we get there? ('Sol will offer hundreds of physical qubits'); roadmap figure under §What is Apollo? ✅ hyperfine clock qubit ions; "hundreds" of physical qubits (PLANNED, post-Helios, pre-2030) |
| 2 Encoding | Hyperfine / clock-state qubit · primary ▥ §How do we get there? (Helios will use 137Ba+ qubits, in contrast to 171Yb+ in H1/H2) 🔎 hyperfine clock qubit (as Helios) |
| 3 Gate mechanism | Mølmer–Sørensen / light-shift laser gate · primary ▥ §How do we get there? (2Q gate errors <2e-4, ~2x faster than Helios); §Opportunity for early value creation discovery in Helios and Sol (up to 10,000 quantum operations) ✅ laser Mølmer–Sørensen; target 2Q error <2×10⁻⁴; circuits of up to 10,000 quantum operations (planned) |
| 4 Connectivity / transport | Ion shuttling (QCCD, junctions, grid traps) · primary ▥ §How do we get there? ('first commercially available 2D-grid-based quantum computer'; 'fully 2D-grid architecture is the scalability launching point') ✅ QCCD on a 2-D grid trap — the scalability foundation (Helios is a junction-routed racetrack) |
| 5 Control | Laser control with integrated photonics (ions) · primary ▥ §How do we get there? ('operating approximately 2x faster than Helios') ✅ room-temperature electronics + optics; ~2× faster than Helios (planned) |
| 6 Readout | |
| 7 Code | High-rate concatenated codes with transversal gates · primary ▥ §Opportunity for early value creation discovery in Helios and Sol (QED + QEM to extend Helios and Sol) ✅ no code stated for Sol; technology carried as Helios (register codes: none) |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · primary ◌ 🔎 surface-electrode 2-D grid trap (fab route as Helios) 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · alternate ▥ §What is Apollo? (Apollo trap chip: 2D array fabricated using standard CMOS processing, CMOS electronics) ✅ alternate: Quantinuum states standard-CMOS fabrication for the Apollo-generation 2-D array, not for Sol itself |
evidence: ✅ 6 / 11