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300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) fab_cmos

Industrial 300 mm CMOS lines fabricating quantum-dot spin qubits, cryo-CMOS controllers and superconducting wiring; the only qubit manufacturing route with wafer-scale yield statistics.

300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)

fab_cmos · layer 10 Manufacturing · demonstrated · since 2022
Open on the map

Intel D1 EUV (24k devices/wafer, 96% tune-up), imec (2Q > 99%), GF 22FDX (1,024 dots), ST FD-SOI; GF now a multi-modality foundry ($375 M LOI).

Reading marks
crossing technology — natural carrier + semiconductor / photonic-chip fabrication
Brief →

Key references

[793] R. Maurand et al., “A CMOS silicon spin qubit,” Nat. Commun., vol. 7, Art. no. 13575, Nov.… · 2016
[794] A.-M. Zwerver et al., “Qubits made by advanced semiconductor manufacturing,” Nat. Electron… · 2022
[199] H. C. George et al., “12-spin-qubit arrays fabricated on a 300 mm semiconductor manufactur… · 2024
[766] S. F. Neyens et al., “Probing single electrons across 300-mm spin qubit wafers,” Nature, v… · 2024
[293] J. Van Damme et al., “Advanced CMOS manufacturing of superconducting qubits on 300 mm wafe… · 2024

Design space — attributes

(a) carrier affinity
fabricated
(b) time · entangling
—
(c) readout
—
(d) mobility
—
(e) control
—
(f) error structure
coherent / calibration
(g) manufacturing
CMOS foundry 300 mm

Evaluation space — dated attributes

wafer-scale statistics → > 24,000 devices/wafer, CD < 0.5 nm
defines: scaling path · 2024-10 · source
wafer-level yield (cryo-prober, 1.6 K) → 96% of 232 twelve-dot devices tuned to single-electron occupancy; 99.8% of dots
defines: scaling path · 2024-05 · source
multi-modality foundry LOI → GlobalFoundries $375 M (SC, ion, photonic, topological, spin)
defines: scaling path · 2026-05 · source

Standard records

device yield → 0.96 · typical
Intel 300 mm Si/SiGe wafer statistics: 'Full 12QD device yield: 96%', quantum-dot yield 99.8%, ohmic and gate yield 100% · 2024-04 · source [D] ⓘ
parameter spread → 0.059 · typical
300 mm Si/SiGe: matched-pair gate threshold-voltage sigma = 59 mV; 1e-voltage random variation 61 mV (30 nm) and 63 mV (50 nm SiGe barrier) · 2024-04 · source [D] ⓘ

Actors & goals — annotations

Silicon / germanium quantum-dot spins — Intel, Diraq, Quantum Motion, HRL→IBM, QuTech/Groove, Quobly, Equal1 · G4 G7
Transmon lattice with tunable couplers (alternate) — IBM (Heron, Nighthawk), Google (Willow), Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu/RIKEN, QuantWare · G2 G3 G4
Trapped ions — QCCD (transport between zones) (alternate) — Quantinuum (H1, H2, Helios, Sol), Universal Quantum · G2 G3 G6 G7
Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (alternate) — Oxford Ionics (IonQ), eleQtron, QUDORA, Universal Quantum · G2 G3 G6 G7

Edges

needed by: Spin shuttling (conveyor mode), Cryo-CMOS controller (4 K / mK), Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge)·, Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring)
alternatives: STM hydrogen-resist lithography (donors), Ion-trap fabrication (surface-electrode chips; machined 3D blade traps)
° one of several that would do · the usual route, not a strict need

Used by 20 machines (13 primary · 7 alternate)

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1 — Fig. 1: Cryo-prober measurement flow.a, The cryo-prober cools 300-mm wafers (upper image) to an electron temperature of 1.6 K in around 2 h. Lower i…
Four-panel figure of a wafer-scale test flow: (a) a whole 300 mm spin-qubit wafer cooled to 1.6 K, with a false-coloured transmission-electron cross-section of a silicon/silicon-germanium quantum-dot device; (b) optical images of the die grid and of a device's pads contacted by probe pins; (c) a measurement sequence of turn-on curves and charge-stability diagrams; (d) a wafer map of threshold voltage by die position. It is Figure 1 of a 2024 Nature article, 'Probing single electrons across 300-mm spin qubit wafers', by Neyens, Zietz, Watson and co-authors. It shows how a cryogenic wafer prober turns spin-qubit devices into foundry-style statistics. “Fig. 1 — Fig. 1: Cryo-prober measurement flow.a, The cryo-prober cools 300-mm wafers (upper image) to an electron temperature of 1.6 K in around 2 h. Lower image shows…” by Neyens et al., www.nature.com/articles/s41586-024-07275-6, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
File:Kirmik buyuklugu ve verim tr.svg
An illustrative drawing, not measured data: three 300 mm wafers tiled with square dies of 40, 20 and 10 mm edge, with the same 30 defects on each; dies hit by a defect are red, clean dies green. Made by Oğuz Ergin (2026-09-15), labels in Turkish, based on Hennessy and Patterson's Computer Architecture: A Quantitative Approach. The yields of 52, 83 and 96 percent show why large chips are costly, which matters as qubit chips move to 300 mm foundry processes. “Kirmik buyuklugu ve verim tr” by Oğuz Ergin, commons.wikimedia.org/wiki/File:Kirmik_buyuklugu_ve_verim_tr…, CC BY SA 4.0 (creativecommons.org/licenses/by-sa/4.0/)
File:Full wafer of Intel quantum computers.jpg
A close-up photograph of the lower half of a patterned silicon wafer on a display stand, lit from behind so that its fine patterning splits the light into rainbow bands; columns of small rectangular chips with rows of square pads cover it. Taken by Steve Jurvetson on 11 April 2018 and titled 'Full wafer of Intel quantum computers', noted as its first public showing. It shows quantum chips made in bulk on an industrial silicon wafer, the route of 300 mm CMOS-foundry fabrication; the wafer diameter and qubit type cannot be read from the picture. “Full wafer of Intel quantum computers” by Steve Jurvetson from Menlo Park, USA, commons.wikimedia.org/wiki/File:Full_wafer_of_Intel_quantum_…, CC BY 2.0 (creativecommons.org/licenses/by/2.0/)
fab_cmos · layer 10 Manufacturing · centrality 17.9 · demonstrated · since 2022 · updated 2026-09-30

300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)

Industrial 300 mm CMOS lines fabricating quantum-dot spin qubits, cryo-CMOS controllers and superconducting wiring; the only qubit manufacturing route with wafer-scale yield statistics.

Verdict. Uniformity is proven (96% device yield, sub-nm CD); fidelity is not yet a foundry deliverable. Demote if no 300 mm device with >20 qubits and all-pairs 2Q ≥ 99.5% appears by end-2027.

Key references

Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).

Identity & lineage

This node is a manufacturing regime, not a qubit: 300 mm CMOS production lines making gate-defined quantum-dot arrays (Si/SiGe, SiMOS, Ge), their cryo-CMOS ASICs, and superconducting qubit and wiring layers. A quantum dot is an accumulation-mode transistor at single-electron occupancy; at 45–100 nm pitch the foundry supplies uniformity, interface quality and isotopic control, not resolution, across tens of thousands of devices per wafer with cryogenic wafer-level test.

CEA-Leti opened the route in 2016 with a spin qubit in a 28 nm FD-SOI flow D[793]. Intel and QuTech made the first all-optically patterned 300 mm qubits in March 2022 D[794], fixing since 2022; Intel added EUV arrays and 1.6 K wafer statistics in 2024 D[199], [766]. imec produced 300 mm transmons in 2024 D[293] and, with Diraq, unit cells above 99% in 2025 D[189]. GlobalFoundries' 22FDX became the merchant option in 2025 D[767], ST started ²⁸Si FD-SOI lots in December 2025 P[795], and US CHIPS letters of intent followed in May 2026 G[300].

Attributes (technology graph):
a, carrier affinity: fabricated, 1.0; the node is fabrication itself.
b, characteristic time: none; no gate time or entangling mode.
c, readout: none.
d, mobility and connectivity: none.
e, control modality: none.
f, error structure: coherent; device-to-device variability read as calibration error.
g, manufacturing: CMOS.

Physics & limits

Mechanism. The fab fixes four inherited quantities: geometric uniformity, critical dimension within 0.5 nm at 45–100 nm pitch D[199]; electrostatic disorder, a random threshold-voltage spread of 59 mV on Intel Si/SiGe D[766]; isotopic purity, 800 ppm residual ²⁹Si at Intel D[199] and 400 ppm at imec D[189]; and interface quality, which sets charge noise and, in Si/SiGe, the valley-splitting distribution.

Scales. T2*/T2echo reach 5/205 µs on ²⁸Si Si/SiGe against 0.6/98 µs on natural silicon D[766]; Hahn-echo T2 reaches 1.31 ms on imec SiMOS D[197].

Floor. For spins it is material: residual ²⁹Si, interface charge noise and the Si/SiGe valley-splitting tail that turns some dots into leakage sinks. For transmons it is junction targeting: across a 300 mm wafer qubit frequencies spread 5–7%, i.e. 10–14% in junction resistance at qubit junction sizes (the ~8% resistance spread is that of large junctions) D[293], an order above collision-free lattice needs; alternating-bias annealing (97.4% targeting D[294]) is post-fabrication, not a foundry property.

As the code sees it: coherent, calibratable error (HRL attributes about 80% of CNOT error on its 54-dot array to control and calibration D[190]) plus leakage and slow drift; nothing is erasure-convertible; wafer gradients D[293] become spatially correlated error. Moving the floor needs 10-ppm-class ²⁸Si, engineered valley splitting (simulation only S[796]), Ge/SiGe holes or in-flow junction trimming.

Engineering state of the art

Best demonstrated: four Diraq/imec unit cells, every operation above 99% (1Q 99.97%, CZ 99.04–99.56%, SPAM 99.95% at 100 µs), gate-set tomography, September 2025 D[189]fact. Typical at scale: Intel's 232 twelve-dot devices on one wafer gave 99.8% dot and 96% full-device yield, May 2024 D[766]; unmodified 22FDX gave 28–40% "good dot" yield over 1,024 dots, January 2025 D[767]; imec's eight-qubit array validated one pair of four, July 2026 D[197].

table
year figure who tag+key
2016 spin qubit in a 300 mm 28 nm FD-SOI flow CEA-Leti D[793]
2022-03 >10,000 dot arrays per wafer; 1Q 99.0–99.1% Intel/QuTech D[794]
2024-09 300 mm transmons: median T1 75 µs, 98.25% yield imec/KU Leuven D[293]
2024-12 >24,000 devices per wafer, CD < 0.5 nm (EUV) Intel D[199]
2025-01 1,024 dots on 22FDX, 1:1,024 cryo-CMOS mux, < 10 min Quantum Motion/GF D[767]
2025-09 CZ 99.04–99.56% on 300 mm SiMOS, 4 of 4 devices > 99% Diraq/imec D[189]
2026-04 4 K CMOS controller (366 DACs, ≤ 3.5 W) runs d=5 repetition code, Λ = 4.7 HRL D[190]fact

Dominant error term: the 2Q plateau at 99.0–99.6% is charge noise plus exchange calibration D[189], [190]; 100 µs readout for 99.9%-class SPAM D[189] sets a 100–300 µs cycle; no 300 mm device above twelve qubits has published all-pairs 2Q; for transmons the limit is junction spread, not coherence D[293].

Manufacturing, materials & supply chain

Platforms. Intel D1: Si/SiGe wells, immersion and EUV lithography, cryo-prober screening D[199], [766]. imec: SiMOS with overlapping polysilicon gates below 100 nm pitch on 400 ppm ²⁸Si D[189], plus a transmon flow with dry-etched overlap junctions D[293]. FD-SOI: GlobalFoundries 22FDX (Quantum Motion D[767]; Equal1 C[797]) and ST 28 nm at Crolles on Soitec ²⁸Si substrates, first lots December 2025 P[795]. HRL and SkyWater run 200 mm D[190]C[19].

Yield. 96% device yield on a quantum-optimised flow D[766] against 28–40% on a merchant flow D[767] is this node's central number.

Cost and energy. No foundry publishes a quantum wafer price; Diraq's < $1 per qubit target R[211] and vendors' rack-scale claims C[200], [355], [771] are unaudited.

Supply chain. Lines: Intel (captive); imec, coordinator of the EU SPINS pilot line G[770]; GlobalFoundries' Quantum Technology Solutions unit C[353]; IBM Albany, becoming Anderon for superconducting wiring, TSVs and bumps C[798]; SkyWater, 200 mm, IonQ-owned since 2026-07-31 C[19]. Materials: enriched ²⁸Si, historically Russian, now also from ASP Isotopes in Pretoria (commercial since 2025-03-27) C[347] and from ORNL and PNNL as 99.9999% ²⁸Si silane (US DOE, announced 2026-07-16) G[348]; Silex completed a plant for up to 20 kg per year in June 2026, commissioning late 2026, for SQC C[799]. Equipment: cryogenic wafer probers from Bluefors/Afore (< 2 K, 300 mm, 768 DC, 48 RF lines) C[800] and FormFactor C[801]. Single points of failure: EUV dots only at Intel and imec; a prober duopoly; ²⁸Si from a handful of enrichers.

Export control. BIS's rule of 2024-09-06 controls cryogenic CMOS ICs for ≤ 4.5 K (ECCN 3A901), cryogenic systems ≥ 600 µW at ≤ 0.1 K (3A904), cryogenic wafer probers (3B904) and quantum computers by qubit count and C-NOT error together, from 34 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906) fact, with License Exception IEC for allies G[301]fact; EU and UK lists match. The same rule controls silicon and germanium enriched beyond set isotope fractions — epitaxial layers, hydrides such as silane, bulk and oxides (3C907–3C909) G[301].

Control, readout & I/O burden

Multiplexing moves on-die or in-package: a 1:1,024 cryo-CMOS multiplexer on 13 lines D[767]; imec's multiplexer routing transmon pulses below 15 mK with > 99.9% 1Q preserved D[802]; a 32-cell 28 nm FD-SOI chip at 7 mK, ~20 nW/MHz per cell D[551]; HRL's 4 K controller, 366 DACs at ≤ 3.5 W (~10 mW per channel), running a repetition code D[190]; IBM's 4 K controller at 23 mW per qubit D[296]. Crossbar sharing needs T = 6√g − 1 lines for a square array of g dots (23 for 16) D[520].

Walls. 10³: per-qubit lines suffice; the burden is tune-up time. 10⁴: at IBM's 23 mW per qubit D[296] the 4 K load is 230 W, at HRL's 3.5 W per 18 qubits D[190] about 2 kW — over a hundred times the 2 W 4 K stage of a Bluefors XLD1000sl, and above the 200 W of Fermilab's Colossus, the largest plant in the resource review S[550] — forcing ≥ 10:1 multiplexing or millikelvin nW-class cells. 10⁶: only crossbar sharing (~6,000 lines D[520]) plus millikelvin CMOS or SFQ closes; whether shared control keeps coherent error below threshold is open. Latency: spin cycles are readout-bound, 100 µs integration D[189].

Role in the stack

A layer-10 root: it requires nothing and provides the dot arrays and cryo-ASICs the quantum-dot spin architecture assumes, its primary home; it is an alternate on the transmon lattice with tunable couplers, trapped-ion QCCD and trapped ions with electronic gates. It replaces STM-lithography donor fabrication (11-qubit registers, serial, no foundry route D[192]); for ion traps it is the alternative to MEMS trap fabs, the switching price being CMOS re-qualification, paid by Oxford Ionics (part of IonQ since 2025-09-17), whose 99.99% two-qubit fidelity on standard-fab chips is reported in an IonQ release C[446]fact. Here natural carriers (trapped ions) inherit semiconductor manufacturing. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture; this node adds no term; the quantum-dot spin architecture's derived round is 8.5 µs, readout-set, against a measured 100–300 µs cycle D[189]. Conveyor shuttling over an effective 10 µm (back and forth) at 99.5% D[196], shown on a Delft-made device, is what uniform 300 mm gates must reproduce. Neighbouring empty slots: no spin-module interconnect (300 mm photonics is the candidate, unproven at millikelvin) and no fabricated cryogenic decoder; a cryo-CMOS predecoder design claims 3,780× syndrome-bandwidth reduction below 0.56 mW S[733].

Evidence — how the numbers were measured

Yield numbers come from cryo-probers at 1.6–1.7 K (automated tune-up, turn-on/pinch-off and charge-sensing criteria D[199], [766]): transistor statistics. Fidelities come from few devices in dilution refrigerators: gate-set tomography (12,263 sequences) for the unit cells D[189], randomised benchmarking on Tunnel Falls D[199], T1/T2 wafer maps for transmons D[293].

Not captured: (1) 1.6 K probing cannot see valley splitting, exchange or coherence, so device yield says nothing about qubit yield; (2) selection: 4 of 20 imec devices characterised D[189], 6 of > 10,000 arrays cooled in 2022 D[794]; (3) criteria: 28–40% and 96% define "working" differently D[766], [767]; (4) no simultaneous all-pairs 2Q on any 300 mm array D[197]; (5) ageing: 3.7% junction drift in 146 days D[293] is absent from fidelity claims.

Replication: imec's SiMOS numbers reproduce across four devices and two institutions D[189]; Intel's are single-vendor. Flagged: Quantum Motion's "first full-stack silicon CMOS quantum computer" without published fidelities C[200]; Equal1's commercial-process dots without qubit metrics C[797].

SPAM for the imec/Diraq unit cells is 99.95% at 100 µs [189], against 99.9% recorded for imec's 300 mm line (2025). Intel's yield figures all come from [766], on 232 twelve-dot devices of one wafer — 99.8% of dots, 96% of full devices, 91% charge-sensing success; [199] restates the 96%, citing [766]. Not published: the dates of Silex's A$5.1 M Defence Trailblazer and A$4.35 M SQC funding [799].

Actors & economics

Who.
Organisation Role Country What they do Evidence
Intel developer; captive supplier US Si/SiGe EUV arrays; cryo-prober wafer statistics; 12-qubit chip at Argonne D[199], [766]; G[207]
imec research; supplier BE 300 mm SiMOS dots, transmons, millikelvin multiplexer; SPINS coordinator D[189], [293], [802]; G[770]
GlobalFoundries supplier (merchant foundry) US 22FDX dots and cryo-CMOS; Quantum Technology Solutions unit; $375 M LOI C[353], [803]; G[300]
IBM developer; supplier US Anderon: 300 mm superconducting wafers, TSVs, bumps; $1 B LOI C[10], [798]; G[300]
Diraq developer AU SiMOS unit cells at imec; QBI Stage B; CHIPS LOI up to $38 M D[189], [197]; G[65], [300]
Quantum Motion developer UK 22FDX 1,024-dot arrays; NQCC system; QBI Stage B D[767]; C[200]; G[65]
Money.
date actor event amount lead or programme cumulative status
2025-11-06 Diraq; Quantum Motion; SQC grant up to $15 M each DARPA QBI Stage B — definitive G[65]fact
2026-01-15 Equal1 round $60 M ISIF > $85 M closed C[771]fact
2026-04-03 imec + 25 partners grant €50 M EU Chips JU SPINS pilot line — announced G[770]
2026-05-07 Quantum Motion Series C $160 M DCVC, Kembara — closed C[355]fact
2026-05-21 GlobalFoundries CHIPS LOI $375 M US Commerce ($2.013 B over nine LOIs) — LOI, non-binding G[300]C[353]fact
2026-05-21 IBM (Anderon) CHIPS LOI $1 B + $1 B IBM cash US Commerce — LOI, non-binding G[300]C[798]
2026-05-21 Diraq CHIPS LOI up to $38 M US Commerce > $100 M raised Pfact LOI, not awarded G[300]
2026-06-03 Quobly Series A €115 M Bpifrance, SEALSQ, STMicroelectronics €134 M closed P[804]fact
2026-06 Silex Systems Q-Si plant completed A$5.1 M + A$4.35 M Defence Trailblazer; SQC — commissioning late 2026 C[799]
2026-07-23 IBM M&A: HRL Laboratories undisclosed — — announced; closed 2026-08-26; potential plans for spin qubits at Anderon C[10]factfact
2026-07-31 IonQ M&A: SkyWater $15.00 + 0.4883 IonQ shares per share (~$1.8 B) — — closed C[19]fact

Market & supply chain. Quantum is immaterial to foundry revenue. Concentration: two EUV-capable dot lines, one merchant FD-SOI option (ST entering), a prober duopoly, a handful of ²⁸Si enrichers. Unit economics: unpublished beyond Diraq's target R[211]. Payers: G4 for 10⁶-qubit CMOS density; G7, as of 3 Sep 2026, for rack-scale spin systems; superconducting vendors buy Anderon/GF wiring for G2–G4; ion vendors buy standard-fab traps for G2, G3, G7.

IP & standards. Portfolios: Intel, HRL, Diraq/UNSW, Quantum Motion/UCL, Quobly (CEA/CNRS licences), Equal1; no litigation public; no dated family count from a named database found. SPINS promises quantum PDKs and multi-project-wafer access G[770]; GF markets FDX cryogenic models C[353]; no open cryogenic device-model standard exists.

Roadmaps & track record. Intel (promised 2022 · wafer-scale qubits · delivered 2024, Argonne 2026-01-06 G[207]fact; no successor or roadmap as of 2026-09-03). Diraq (promised 2026-07-09 · "thousands" by 2029, restated 2026-08-27 as 150,000 physical · eight qubits shown D[197]R[211]fact). Quantum Motion (promised 2025-01 · NQCC system · delivered 2025-09-15, no published fidelity C[200], [803]). Quobly (promised 2025-12 · ST-lot metrics Q1 2026 P[795] · none found as of 2026-09-03). GF, Anderon: no wafer dates promised C[353], [798]. Credibility: imec/Diraq (peer-reviewed, replicated) first; Intel manufactures without a product path; Quantum Motion and Equal1 deliver systems without peer-reviewed metrics (Equal1's RacQ, sold as Bell-1 until May 2026, is installed at ESA's Frascati centre, announced by ESA on 2026-07-15 fact and by Equal1 on 2026-07-31 Cfact), Quobly none yet; roadmap slides last.

Strategic reading. Success rewards foundries and suppliers (GF, imec, ST/Soitec, Bluefors) and spin vendors whose bill of materials shrinks to wafers plus racks; bespoke routes (STM lithography, university lift-off) and MEMS trap fabs lose. Supplier bargaining power is high (few lines, quantum revenue immaterial), but three or four substitutable lines and state money cap what foundries extract. Substitution threats: Ge/SiGe holes, photonic-interconnect fabs, SFQ against cryo-CMOS.

Outlook & open questions

Milestones, 12–24 months: (1) a 300 mm device with > 20 qubits and published all-pairs 2Q ≥ 99.5% confirms; none by end-2027 demotes; (2) SPINS multi-project-wafer runs with a public quantum PDK; (3) GF's LOI made definitive, a named 22FDX quantum product; (4) a spin-qubit lot at Anderon from HRL, IBM-owned since 2026-08-26; (5) Intel naming a Tunnel Falls successor or exiting.

2029 best case: two merchant 300 mm lines with quantum PDKs, 10³-dot arrays with on-die multiplexing, 2Q ≥ 99.5% typical, a below-threshold spin memory. Worst: merchant yields at tens of percent, 2Q at 99–99.6%, roadmaps cut again, GF's unit reduced to packaging for superconducting and photonic customers.

Open questions: can valley splitting and charge noise be made wafer-uniform, or must every array be post-selected? What is the qubit-fidelity yield of a 300 mm flow? Does shared control keep coherent error below threshold? Can in-flow junction targeting reach sub-percent? Watch the first fidelity-yield number, SPINS' first multi-project wafer, definitive CHIPS awards, Intel.

References
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