Spin shuttling (conveyor mode) cx_shuttle

Conveyor-mode spin shuttling moves a single spin along a gate-defined channel on a travelling potential wave: overlapping clavier gates driven with fixed phase offsets by four sinusoids (eight two-tone), the carrier riding the moving minimum. Bucket-brigade shuttling needs one pulsed control per hop; a conveyor needs a control count set by the number of phases, not by distance. That is the node's whole economic case, and this brief is its price. Bluhm's group at RWTH Aachen and Forschungszentrum Jülich introduced it as the QuBus: 420 nm channel, four sinusoids, 99.42 ± 0.02% single-electron shuttling — charge, not spin D[510]. Spin coherence at length followed at Delft D[196].

Attributes. a — affinity: fully fabricated, an electron in a lithographic ²⁸Si/SiGe well. b — time: ~2 × 10⁻⁷ s per 10 µm transit (cumulative, shuttled back and forth) D[196]; entangling not applicable, this is transport. c — readout: none of its own, it borrows the register's charge sensor. d — mobility: transport, the node's entire function. e — control: no modality or placement of its own, one shared radio-frequency drive. f — error as the code sees it: coherent, dephasing and position-dependent rotations, no loss channel. g — manufacturing: CMOS, the same 300 mm line as the dots.

Gates at 180 nm pitch driven to 300 MHz make a moving confinement minimum; the carrier follows adiabatically at 36 m/s single-tone, 64 m/s two-tone D[196]. Adiabaticity bounds transit time from below through orbital and valley splittings, spin coherence from above. Spin–orbit coupling and micromagnet gradients make transport a deterministic, position-dependent rotation — coherent, hence calibratable in principle — and motion also helps, Delft attributing the improved coherence of moving spins to motional averaging D[193]. Charge noise and disorder pin the carrier and excite it at valley–orbit anticrossings S[511]. Nothing thermodynamic bounds any of this, so the floor is materials: valley-splitting uniformity along a line, and charge noise. Moving it takes interface engineering, quieter gate stacks, echo during transport (in germanium, echo lifted the characteristic shuttle number from 64–77 to above 300 D[512]) or confinement modulation S[513]. Surface-code simulation gives a dephasing threshold of several percent and moderate overhead to ~1% error per shuttle S[514] — forgiving, but conditional on gates and readout already sitting below threshold, which on spins they do not.

The dominant error term is counter-intuitive: in the five-qubit parity device the limit is incoherent noise in the exchange interaction, dephasing during shuttling and idling being about a quarter of the total D[349]. Transport has stopped being the worst thing in a shuttling circuit; the static gates are, and the route past 99% is gate-stack change, not faster conveyors. Typical-at-scale does not exist: every result above is on a research-fab heterostructure, and no conveyor link has been published on a 300 mm device.

Bucket-brigade hopping (a spin passed from dot to dot by sequential gate pulses, as opposed to conveyor-mode transport in a moving potential well) now crosses a two-dimensional array: in QuTech's 6×6 germanium hole-dot grid with one shared barrier gate, a spin crossed 26 dot-to-dot transitions over 5.2 µm, with lower bounds of 99.96 ± 0.01% per hop for basis states and 99.68 ± 0.04% for superpositions; the same shuttling tuned 30 of the 36 dots P[898].

Three overlapping gate layers at ~180 nm pitch over an enriched ²⁸Si/SiGe well, 7 nm thick at Delft D[196] — nominally 300 mm-compatible, and the node's hard dependency is exactly that: uniform conveyor gates on a CMOS line. Dots need only resemble each other; a bus must be uniform along its whole length, because one pinning defect breaks the channel and a conveyor carries no redundancy. No yield or uniformity statistic has been published for conveyors, conspicuous beside Intel's 24,000-plus spin devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766]. Supply: enriched ²⁸Si from a handful of isotope separators, the single point of failure the silicon-spin architecture already shares, and SiGe epitaxy and overlay at imec, Intel, GlobalFoundries and STMicroelectronics. Cost per bus is not quotable; no ECCN mapping of the quantum dual-use regime is asserted here.

Four or eight shared radio-frequency lines drive an arbitrarily long bus, so line count scales with the number of buses, not with distance or stops served; a bucket-brigade link of equal reach needs one pulsed line per hop. Sparsity is what makes co-located electronics fit — the argument HRL's 4 K controller makes from the other end at ≤3.5 W and 366 DACs for 18 qubits D[190]fact. The node has no readout; a mobile ancilla is measured at a dedicated site D[349]. Latency is not the binding constraint: 4 ns hops and 58 ns moving-spin gates sit two to three orders below spin readout at 1–100 µs, so shuttling does not lengthen the syndrome cycle. The walls: at 10³ qubits, channel uniformity on 300 mm; at 10⁴, phase calibration across thousands of drifting conveyors; at 10⁶, the dephasing budget — at 10⁻³ per µm, one micron of travel per syndrome extraction is affordable and one hundred is not.

The node belongs to the silicon and germanium quantum-dot spin architecture (Intel, Diraq, Quantum Motion, HRL under IBM, QuTech, Quobly). It requires gate-defined dot spins to move and a 300 mm CMOS foundry for uniform conveyor gates, and provides nothing downstream: its value is realised inside the architecture it serves, which is why it will never be sold as a product. It replaces static nearest-neighbour exchange, which costs no transport error; a shuttled link buys distance with a dephasing budget and a calibration burden, worth paying only when control and readout electronics must be interleaved among the qubits. The node sits far from the fabrication cluster it depends on, its physics set by disorder in research heterostructures and its economics by a 300 mm line it has never run on. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: transport contributes 2.0 × 10⁻⁷ s and gates 5.8 × 10⁻⁸ s each, so the architecture stays readout-limited at 8.5 × 10⁻⁶ s, readout 6.3 µs of it and reset 1 µs. Empty neighbouring slots: transport across a die boundary, and a link with in-flight leakage detection.

The silicon figure comes from interleaved randomised benchmarking of a shuttle "gate" over a 10 µm effective path, shuttled back and forth D[196]; the germanium figure from exponential fits to a characteristic shuttle number D[512]. Different observables, routinely quoted side by side: 99.97% per shuttle in germanium is basis-state only, 99.54% in silicon a spin fidelity over a path. Benchmarking a shuttle also assumes twirlability, questionable for a deterministic position-dependent rotation, since motional averaging can flatten the benchmark below the physical error at any single point. Neither protocol reports leakage out of the valley or orbital subspace, and no shuttling result has been cycle- or mirror-benchmarked, so the correlated error a code would see is unmeasured. Conveyor transport is shown at charge level by RWTH Aachen, at spin level by Delft; the 10 µm figure has no independent replication as of 3 Sep 2026.

The germanium "99.97% per shuttle" [512] is a basis-state figure, not comparable with the silicon conveyor spin fidelity [196]. Not published: ARQUE Systems' funding round, amount and investors [515], its headcount and a dated installation milestone at Jülich Supercomputing Centre; and yield, channel-uniformity or per-bus cost data for conveyor structures on any 300 mm line.

Money.

• 2022-09 · ARQUE Systems · spin-off founded by Bluhm and three colleagues · undisclosed · Jülich, RWTH Aachen · announced C[515]
• 2025-11-06 · DARPA QBI Stage B · eleven teams including Diraq, Quantum Motion · up to $15 M each · announced G[65]fact
• 2026-05-07 · Quantum Motion · Series C · $160 M · DCVC, Kembara · closed C[355]fact
• 2026-05-21 · Diraq · CHIPS letter of intent · up to $38 M · US Commerce · LOI G[300]fact
• 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · closed C[350]fact
• 2026-07-23 · IBM · acquisition of HRL Laboratories · undisclosed · announced; closed 2026-08-26 G[10]factfact

None of these is financing for shuttling as such: it is a feature funded inside spin-qubit companies, not a fundable line item, with ARQUE the sole exception — and its funding undisclosed.

Market & supply chain. Nobody sells a shuttle. Enabling supply is 300 mm lithography and overlay, SiGe epitaxy, enriched ²⁸Si substrates and multi-channel waveform generation. G3 and G4 pay for it, since sparsity only earns its dephasing cost at code scale; G7 marginally, through the Jülich installation; G1 and G5 nothing.

IP & standards. The conveyor family originates with RWTH Aachen and Forschungszentrum Jülich; ARQUE commercialises a patented shuttling mechanism C[515]. No dated family count from a named database exists for this node, so none is quoted, and no standards body covers spin transport.

Roadmaps & track record. (promised 2021-08 · conveyor as a scalable bus · status 2026-09-03: single-channel level only, never on a foundry wafer). (ARQUE Systems, promised 2026 · five-qubit shuttling processor at Jülich · status: installation under way, no acceptance data C[515]). (QuTech, promised 2026-07 · above-99% shuttled parity via gate-stack change · status: 97.7% per shuttle D[349]). (Diraq, promised 2026-08-27 · 150 k physical and 1 k logical qubits by 2029 · status: eight-qubit foundry device with one working pair, its own July release saying "thousands by 2029" Cfactfact). QuTech is the strongest actor here; ARQUE is unproven but the only vehicle with a delivery date; Diraq's numbers move faster than its devices.

Strategic reading. If the conveyor reaches foundry uniformity, the winners are the CMOS spin vendors whose thesis is density-through-sparsity — IBM with HRL, Diraq, Quantum Motion, Quobly — and the cryogenic control suppliers, since sparse lattices are what make co-located electronics fit. Losers: dense nearest-neighbour exchange architectures, and foundries selling dot uniformity rather than line uniformity. Bargaining power sits with the 300 mm lines and the enriched-silicon suppliers; a transport primitive with no standalone product will be absorbed as an IP position, which is what the Aachen and Jülich patents already are.

Falsifiable milestones for 12–24 months. Confirm: a conveyor spin link on a 300 mm foundry device at ≥99% per 10 µm by 2027-09; a shuttled-ancilla parity check above 99%, the target the Delft authors set themselves D[349]; independent replication by a group other than Delft. Demote: if shuttled-ancilla parity stays below ~90% through 2027, the sparse-architecture argument loses its only experimental leg; or if valley-splitting variation along channels proves irreducible on foundry material. Best case by 2029, a distance-3 to distance-5 surface-code patch on a sparse spin lattice with shuttled syndrome extraction; worst case, shuttling stays a Delft and Aachen speciality on research heterostructures.

Open questions. (1) Is benchmarking of a shuttle a meaningful fidelity, or an artefact of motional averaging? (2) Does motional averaging survive foundry-level charge disorder, or invert into pinning? (3) What is the leakage rate at valley anticrossings? (4) Can conveyor phase calibration be automated across thousands of buses? (5) Can a spin cross a die boundary? Watch: any 300 mm shuttling result from imec, Intel, GlobalFoundries or STMicroelectronics; ARQUE's acceptance data at Jülich; QuTech's follow-up to the weight-four parity device.