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Long-range on-chip couplers (c-couplers, mm-scale) cx_lr

Waveguide- or resonator-extended tunable couplers that entangle fixed superconducting qubits millimetres apart, buying the degree-6 graphs that qLDPC codes need.

Long-range on-chip couplers (c-couplers, mm-scale)

cx_lr · layer 4 Connectivity / transport · emerging · since 2023
Open on the map

Resonator/coupler links beyond NN; enables degree-6 qLDPC layouts; 2 mm CZ 99.81% (IQM); IBM Loon components without numbers.

Reading marks
crossing technology — fabricated carrier + far connectivity (transport / long-range)
Brief →

Key references

[477] J. Majer et al., “Coupling superconducting qubits via a cavity bus,” Nature, vol. 449, no.… · 2007
[478] B. Kannan et al., “Waveguide quantum electrodynamics with superconducting artificial giant… · 2020
[479] X. Zhang, E. Kim, D. K. Mark, S. Choi, and O. Painter, “A scalable superconducting quantum… · 2022
[480] F. Marxer et al., “Long-Distance Transmon Coupler with cz-Gate Fidelity above 99.8%,” PRX … · 2023
[481] R. Mandelbaum et al., “How IBM will build the world's first large-scale, fault-tolerant qu… · 2025

Design space — attributes

(a) carrier affinity
fabricated
(b) time · entangling
—
(c) readout
—
(d) mobility
long-range static couplers
(e) control
—
(f) error structure
coherent / calibration
(g) manufacturing
superconducting lithography

Evaluation space — dated attributes

long-range CZ → 99.81% over ≥ 2 mm
defines: scaling path · 2023 · source
IBM Loon → c-couplers + multilayer routing shown, no performance numbers
defines: scaling path · 2025-11 · source

Standard records

connectivity degree → 6 · theory
Design target, not a measured device: gross-code layouts need 'a degree-6 graph that consists of two edge-disjoint planar subgraphs' · 2023-08 · source [S] ⓘ
transport per round → 0.0 ns · theory
Zero: c-couplers and mm-scale resonator links are static wiring, not transport; the gross-code cycle is 7 CNOT layers with no move step · 2023-08 · source [S] ⓘ

Actors & goals — annotations

Quantum annealer — flux qubits — D-Wave · G1 G5
Transmon lattice with tunable couplers (alternate) — IBM (Heron, Nighthawk), Google (Willow), Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu/RIKEN, QuantWare · G2 G3 G4

Edges

needs: Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm)
needed by: Non-local qLDPC codes (bivariate bicycle, 'gross')°
alternatives: Static nearest-neighbour lattice
° one of several that would do · the usual route, not a strict need

Used by 8 machines (8 primary · 0 alternate)

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

Pictures

Every picture carries the story of what it shows and its credit line.

Figures — Long-Distance Transmon Coupler with cz-Gate Fidelity above 99.8% (IQM)
A six-panel paper figure mixing a circuit schematic, simulation and measurement plots, and one real image: panel (b), a false-coloured optical micrograph (100 µm scale bar) of two transmon qubits joined by a long meandering coupler. It comes from 'Long-Distance Transmon Coupler with cz-Gate Fidelity above 99.8%' by Marxer, Vepsäläinen, Jolin et al. of IQM Quantum Computers (PRX Quantum, 2023). Notice how far apart the qubits sit: the coupler lets distant qubits run a controlled-Z gate. Airbridges were painted over to protect IP. “Figures — Long-Distance Transmon Coupler with cz-Gate Fidelity above 99.8% (IQM)” by Fabian Marxer, Antti Vepsäläinen, Shan W. Jolin, et al. (IQM Quantum Computers), journals.aps.org/prxquantum/abstract/10.1103/PRXQuantum.4.01…, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1 — Fig. 1: Implementation of the bivariate bicycle code. a, Schematic of the Kunlun processor. (Upper left) Tanner graph of the bivariate bicycle (BB)…
A four-panel figure of renders, not photographs: the Tanner graph of the [[18,4,4]] bivariate bicycle code on a torus, a layout of the 32-qubit superconducting processor Kunlun (18 data and 14 check qubits), a 10 µm inset of two couplers crossing, plus error, timing and circuit panels. From "Demonstration of low-overhead quantum error correction codes" by Ke Wang, Zhide Lu and co-authors. It shows how a qLDPC code that needs non-local connections is laid out on a flat chip with long-range couplers that cross over one another. “Fig. 1 — Fig. 1: Implementation of the bivariate bicycle code. a, Schematic of the Kunlun processor. (Upper left) Tanner graph of the bivariate bicycle (BB) code…” by Ke Wang et al., arxiv.org/abs/2505.09684, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1 — Figure 1: Description of the Device. a) A schematic showing the full device and circuit geometry: two end qubits, shown in magenta, and seven couple…
A three-panel paper figure: a circuit drawing of a chain of two flux qubits and seven superconducting loop couplers, a microscope image of the chip (1 mm scale) and a close-up of one end (100 µm scale). It comes from arXiv paper 2111.04284 by Tennant and co-authors on long-range correlations in a one-dimensional superconducting Josephson spin chain. It shows rf-SQUID flux qubits and couplers of the kind used in quantum annealers; the coupling is nearest-neighbour along a chain, not a long on-chip coupler line. “Fig. 1 — Figure 1: Description of the Device. a) A schematic showing the full device and circuit geometry: two end qubits, shown in magenta, and seven coupler units…” by Daniel M. Tennant et al., arxiv.org/abs/2111.04284, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
cx_lr · layer 4 Connectivity / transport · centrality 18.4 · emerging · since 2023 · updated 2026-09-30

Long-range on-chip couplers (c-couplers, mm-scale)

Waveguide- or resonator-extended tunable couplers that entangle fixed superconducting qubits millimetres apart, buying the degree-6 graphs that qLDPC codes need.

Verdict. One 2 mm CZ at 99.81% (IQM, 2023) and IBM's Loon components without numbers; demote if no coupler of ≥ 5 mm reports a CZ ≥ 99.5% with error bars by end-2027.

Key references

Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).

Identity & lineage

A long-range on-chip coupler is a microwave element — an extended capacitor, a transmission-line section, a resonator or a chain of them, usually with a flux-tunable transmon or SQUID in the middle — that mediates an exchange or ZZ interaction between superconducting qubits that are not lattice neighbours, millimetres apart, by virtual-photon exchange through the structure's detuned mode. Yale's cavity bus of 2007-09 moved quantum information between qubits "on opposite sides of a chip" through a cavity "a few millimetres long" D[477]; MIT's giant atoms, coupled to one waveguide at several points, gave distant qubits decoherence-free exchange in 2020-07 D[478]; Caltech's metamaterial bus gave ten qubits a tunable hopping range in 2023 D[479]. The graph record dates the node to 2023, when IQM published a CZ of 99.81 ± 0.02% between transmons 1.96 mm apart through a floating transmon coupler whose two "waveguide extenders" carry both the qubit–coupler and the direct qubit–qubit coupling D[480]. IBM's "c-coupler" (2025-06 vocabulary; "l-couplers" link chips C[481]) is the same object built for a code, and Loon (2025-11) the first chip claiming a lattice of them C[49].

Attributes (legend: a = affinity natural↔fabricated; b = time, deterministic/heralded; c = readout; d = mobility; e = control @ placement; f = error structure; g = manufacturing), quoting the graph record:

  • a = 1.0: a fully fabricated carrier.
  • b = no characteristic time, determinism not applicable: the link sets no clock; the CZ it hosts is deterministic, 33 ns in the record device D[480].
  • c = no readout function.
  • d = long-range: connectivity beyond nearest neighbour without moving the qubit.
  • e = no control modality at no placement: the flux line is booked under the qubits joined.
  • f = coherent: residual ZZ, phase miscalibration, crosstalk.
  • g = superconducting lithography.
    Rank 2 of 111; shared by the superconducting and annealing architectures; it pairs a fabricated carrier with far-range mobility.

Physics & limits

At 4 GHz on silicon the guided wavelength is about 30 mm, so IQM's 2 mm extenders are electrically short capacitors; the coupler idles at 3.195 GHz below qubits at 4.10 and 3.89 GHz, with qubit–coupler couplings of 51.5 and 53.9 MHz against a direct 3.7 MHz, the net exchange being their difference D[480]. The gate is a coupler flux excursion that turns on the |11⟩↔|20⟩ interaction for 22 ns plus 11 ns idle; the separation also cuts next-nearest-neighbour coupling below 30 kHz D[480]. Beyond a few millimetres the extender's own standing-wave modes enter the qubit band (a 1 cm half-wave line resonates near 6 GHz), so the coupling must come from a hybridised resonator–transmon mode: Nanjing's 1 cm coupler measures 23.5 MHz of XX coupling and up to 100 MHz of ZZ, switchable by more than 10² and 10⁴ respectively D[482]. Links of 1 cm to 0.5 m exist only in simulation S[483]–[485].

Four floors. Loss: a coupler mode with T1 > 40 µs D[480] costs at most 33 ns/40 µs ≈ 8×10⁻⁴ per gate, ~10⁻⁵ at dispersive participation — below the record's 1.9 ± 0.2 ×10⁻³, attributed "mostly" to one qubit's T1 falling to 14 µs during the flux excursion D[480]. Crowding: each extra mode is a frequency collision, and a degree-6 vertex holds six couplers off resonance at once. Coherent error: residual ZZ under 2 kHz D[480] is 0.013 rad of conditional phase per microsecond of idling per pair, correlated rather than stochastic. Geometry: degree above four needs crossings, hence routing layers; the bivariate bicycle Tanner graph is "a degree-6 graph that consists of two edge-disjoint planar subgraphs" D[248], so two suffice topologically. The floor moves with lower-loss routing layers — Loon claims "multiple high-quality, low-loss routing layers" C[49] — and qubits whose T1 survives flux tuning.

Engineering state of the art

Best demonstrated: 99.81(2)% CZ at 1.96 mm in 33 ns (IQM, published 2023-02) D[480]. Typical at scale, as of 3 Sep 2026: none — no multi-qubit processor with mm-scale couplers has published gate fidelities; Loon shows "6-way qubit connections" without numbers C[49], [486], and IQM's resonator-hub Star devices reach "above 99.3%" on a MOVE–CZ–MOVE sequence C[487].

table
Year Figure Who Tag Src
2007-09 Two qubits on opposite sides of a chip coupled through a few-mm cavity bus Yale D [477]
2023-02 CZ 99.81(2)% across 1.96 mm, 33 ns, ZZ < 2 kHz IQM D [480]
2025-03 6-qubit star resonator: [[4,2,2]] logical error per cycle 0.25(2)–0.91(3)% IQM D [488]
2025-05-20 Advantage2 GA, 4,400+ qubits at degree 20 (16 internal + 2 external + 2 odd couplers) D-Wave C [489] fact
2025-06 1 cm hybrid-mode coupler, XX 23.5 MHz, ZZ contrast > 10⁴, no gate Nanjing D [482]
2025-11-12 Loon: 6-way connections, longer couplers, multilayer routing, no numbers IBM C [49], [486]

Dominant error term today: qubit relaxation during the flux excursion (T1,eff 14 µs on one qubit, 43 µs on the other) D[480]; for degree-6 lattices the budget is unpublished.

Manufacturing, materials & supply chain

Standard Nb/Al Josephson lithography plus multilayer, low-loss routing so couplers can cross qubit rows. IBM builds Loon on 300 mm wafers at Albany NanoTech and credits the line with "a ten-fold increase" in chip complexity C[49], [486]; D-Wave's 10-K describes "a multilayer integrated circuit process" G[490]. Each tunable coupler adds a junction and a flux line: a 288-qubit gross-code module at degree 6 D[248] carries 864 couplers if all are tunable, three per qubit against 1.8 on Nighthawk (218 couplers, 120 qubits) C[49]. Yield per coupler is unpublished.

Supply chain: IBM fabricates in-house with NY CREATES C[49]; IQM in Espoo D[480]; D-Wave uses "existing third-party foundries", demonstrated a second source with the 2000Q LN G[491], and its 10-K filings mention SkyWater (nine full-text hits, 2023–2026) G[492] — a foundry that IonQ, a platform competitor, has owned since 2026-07-31 C[493] fact. The single points of failure are the three or four fabs with qualified low-loss multilayer processes. Export exposure: the BIS rule of 2024-09-06 G[301] fact controls dilution refrigerators (3A904) and quantum computers only where qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits (4A906), not coupler designs.

Control, readout & I/O burden

A tunable long-range coupler needs one flux line and a 22 ns-class flux pulse D[480]; a fixed resonator hub needs none but pays with MOVE operations C[487], [494]. At degree 6 the coupler flux lines alone are three per qubit, on top of drive, qubit flux and multiplexed readout — five to six lines per qubit. At 10³ qubits that is 5,000–6,000 lines and cold multiplexing; at 10⁴ it is the 40,000 lines QuantWare promises for 2028 C[536] fact; at 10⁶ only on-chip flux generation (cryo-CMOS or SFQ, SEEQC's mK control being the published pointer fact) closes the gap. Loop latency is unchanged: a bivariate bicycle round is "a depth-7 circuit composed of nearest-neighbor CNOT gates" D[248]; what the coupler moves is the decoder, since bicycle codes lack the matching decoders that keep surface-code decoding within a microsecond.

Role in the stack

Two architectures: superconducting transmons and quantum annealing. It requires superconducting lithography with multilayer routing and provides the degree-6 long-range checks bivariate bicycle codes consume: 12 logical qubits in 288 physical where a surface code needs "nearly 3000" at 0.1% physical error D[248], and 121 logical qubits from a 5,000-qubit gross system at p = 10⁻³ in IBM's architecture study, whose degree "does not exceed seven" S[496]. It replaces nearest-neighbour couplers at the price of one junction and flux line per added edge, two or more routing layers, and a coupler whose T1 and spurious modes enter the budget — paid per design, not per gate. Across families: a fabricated carrier that buys in lithography the far-range mobility atoms and ions get from motion. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: on the transmon architecture the round is 0.65 µs with readout 282 ns its largest term, and the 33 ns long-range CZ D[480] is 5% of the round, binding only if a MOVE–CZ–MOVE sequence outruns the readout term; on the annealing architecture the anneal schedule is the clock. Neighbouring empty slots: the chip-to-chip l-coupler promised for IBM's Cockatoo in 2027 R[481], and the spin-qubit resonator link, where Delft showed iSWAP oscillations between spins 250 µm apart D[497] without a gate fidelity.

Evidence — how the numbers were measured

The 99.81% is interleaved randomised benchmarking, its 1.9(2)×10⁻³ error decomposed by simulation into a coherence-limited part dominated by one qubit's T1,eff of 14 µs; ZZ < 2 kHz is measured at the idle point D[480]. Nanjing's figures are spectroscopic couplings, not gates D[482]. IQM's star results are logical-state fidelities of a [[4,2,2]] code, folding in readout and idling D[488]; its "above 99.3%" is a company figure without protocol C[487]. Loon's claims are release text C[49], [486].

Not captured: crosstalk on shared extenders when several couplers of one vertex fire together; T1 at the flux points every coupler forces on its qubits; leakage into extender modes; drift of the ZZ null. Independent replications of a mm-scale CZ with error bars: none as of 3 Sep 2026. Conflicts: degree 6 D[248] against "does not exceed seven" S[496] — the seventh edge is the logic-unit adapter, so both hold; the graph record's "≥ 2 mm" is the paper's 1.96 mm D[480]; IQM's 99.3% (Constellation cell) and 99.81% (isolated pair) are different operations, not a regression.

D-Wave's reliance on SkyWater rests on nine EDGAR full-text hits G[492]; D-Wave's own text says "existing third-party foundries", with a second source demonstrated on the 2000Q LN G[491]. IQM's Constellation "above 99.3%" carries no protocol or error bar C[487]. Nanjing's 1 cm coupler has a measured XX of 23.5 MHz, while its 100 MHz ZZ is stated without saying whether it is measured or simulated D[482]. The 282 ns readout behind the derived clock is the superconducting architecture's typical value, not a figure specific to long-range couplers. Patent metadata for [498] comes from Justia's index, not USPTO full-text records. Not published: IBM Loon's qubit count, c-coupler length and any gate fidelity C[49], [486]; the cost, energy and yield per coupler, from any actor; a patent-family count for long-range couplers; and whether IQM's shipped Crystal products use the 2 mm extended coupler of [480].

Actors & economics

Who.
Organisation Role Country What it does with this technology Evidence
IBM developer US c-couplers on Loon; Kookaburra qLDPC module (2026); Starling (2029) C[49], [481] fact
IQM Quantum Computers developer Finland 2 mm coupler record; Star hubs; Constellation 2030+ D[480] C[70], [487], [494]
D-Wave Quantum developer US Zephyr degree-20 annealers C[489] fact
Nanjing University research China 1 cm hybrid-mode coupler; long-range ZZ theory D[482] S[484]
QuTech research Netherlands Resonator link between spins 250 µm apart D[497]
SkyWater Technology supplier US Foundry named in D-Wave's 10-Ks; IonQ-owned since 2026-07-31 G[492] C[493]
QuantWare supplier Netherlands 3D-routed chips; VIO-40K roadmap P[495]
DARPA funder US QBI Stage B includes IBM (up to $15 M) G[65] fact

Money.

  • 2025-09-03 · IQM · Series B · $320 M · closed fact
  • 2025-11-06 · DARPA QBI Stage B · IBM among eleven teams · up to $15 M each · official G[65] fact
  • 2026-05-21 · IBM/Anderon; D-Wave; GlobalFoundries · US DoC CHIPS letters of intent · $1 B (+ $1 B IBM cash); $100 M; $375 M · LOI, non-binding G[300] fact
  • 2026-06-02 · IBM · quantum investment commitment · > $10 B over five years · announced C[57] fact
  • 2026-07-02 · IQM · Nasdaq and Helsinki listing · pro-forma cash €337 M; H1-2026 revenue €8.9 M · closed C[58] fact
  • 2026-07-31 · IonQ · acquisition of SkyWater · ~$1.8 B · closed C[19] fact
  • 2026-08-06 · D-Wave · Q2-2026 results · H1 revenue $5.9 M (Q2 $3.1 M), cash $546.2 M · reported C[15] fact

Market & supply chain. Nobody sells a long-range coupler; it is a design block inside a vendor's chip, and the market is the three or four fabs that can print it — Albany C[49], IQM's own D[480], D-Wave's third-party foundries G[491], [492], GlobalFoundries under its LOI fact — plus QuantWare as the only merchant seller of 3D-routed chips P[495]. The structural cost is 1.5–3 extra couplers per qubit against a 10× saving in physical qubits per logical qubit D[248]. Who pays: G4 (IBM's Starling), G3 if Kookaburra runs, G5 on the annealing architecture C[489], G1/G2 through fewer SWAPs on Star hubs C[494].

IP & standards. IBM: US 12,517,856 (filed 2022-09-28, granted 2026-01-06) on modular connectivity levels, US 12,587,192 (granted 2026-03-24) on resonator chains with tunable inductive couplers, US 2024/0169232 A1 (filed 2022-11-18) on fluxonium long-range coupling G[498]. D-Wave: US 10,268,622 (granted 2019-04-23), US 11,507,871 and US 11,494,683 (both 2022-11) on long-range couplers G[498]. No litigation found; no standard. PatSnap's landscape published on 2026-06-30 counts IBM at 4,388 quantum families, 783 in superconducting devices Pfact; no count exists for long-range couplers.

Roadmaps & track record.

  • IBM: promised 2025-06-10 · Loon in 2025 with c-couplers · delivered 2025-11-12 as components without performance numbers C[49], [481].
  • IBM: promised 2025-06-10 · Kookaburra 2026, Cockatoo 2027 (l-couplers), Starling 2029 (200 logical, 10⁸ gates) · Kookaburra not delivered as of 2026-09-03, the rest pending R[481] C[72] fact.
  • IQM: promised 2026-01-05 · 2Q fidelity above 99.94% in 2025–26; qLDPC demonstrators 2027–28; Constellation with long-range couplers 2030+ · pending R[70].
  • D-Wave: described 2021-09-22 · Zephyr topology · delivered with Advantage2 GA 2025-05-20 C[489] fact.
    Credibility: IBM ships the processor it names in the year it names (Nighthawk delivered 2025-12 fact) but has published no coupler number ten months after Loon; IQM delivered its 2023 physics and ships Star systems, with a roadmap that carries no qubit counts; D-Wave delivered its topology at scale, for annealing only.

Strategic reading. If mm-scale couplers reach nearest-neighbour fidelity at degree 6, physical qubits per logical qubit fall by an order of magnitude D[248]; the winners are the vendors owning both coupler and code — IBM and, later, IQM — plus the fabs holding multilayer processes; the losers are surface-code roadmaps on nearest-neighbour lattices, Google's included fact. Substitution threats: chip-to-chip l-couplers R[481]; atoms and ions, which get connectivity from motion; better nearest-neighbour gates with SWAP networks. Bargaining power sits with platform vendors on design and with the few fabs on routing layers; IonQ–SkyWater is the first platform vendor owning a rival's named foundry G[492] fact.

Outlook & open questions

Confirm within 12–24 months if: IBM publishes c-coupler CZ fidelities ≥ 99.5% with error bars at ≥ 5 mm and a gross-code memory experiment on Kookaburra by end-2027 fact; any group demonstrates a ≥ 1 cm on-chip CZ at ≥ 99.5% D[482]; IQM shows a Constellation cell at ≥ 99.9% C[487]. Demote if by end-2027 no mm-scale coupler reports ≥ 99.9% or no code with long-range checks on superconducting hardware reports Λ > 1. Best case by 2029: Starling-class modules of 288-qubit gross codes with couplers at 99.9% D[248] R[481]. Worst case: couplers stay at 99.8% on isolated pairs, qLDPC codes migrate to atoms and ions, and IBM's 2029 machine becomes a surface-code machine.

Open questions: (1) does a qubit's T1 survive the flux points six couplers force on it? (2) what is the parallel-gate crosstalk on a vertex whose extenders share a routing layer? (3) which decoder runs bicycle codes within the cycle time? Watch: any IBM coupler paper, Kookaburra's 2026 status, IQM's Constellation product date, Nanjing's 1 cm gate.

References
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