Quantum annealer — flux qubits on the map bar: Flux-qubit annealer

The architecture in the report (§8.3)

8.3.17 Flux-qubit annealer — Quantum annealer — flux qubits (anneal)

The idea. Thousands of rf-SQUID flux qubits (fluxq) serve as programmable Ising spins: a loop's persistent current, one way or the other, is the spin; inductive couplers set the interactions; the chip evolves continuously (g_anneal) from a transverse-field ground state toward that of the programmed problem. The problem is static: biases are held on chip, the answer latched as bits. Table 8.3's bet, special-purpose scale now, is a trade: count and connectivity for gates, logical qubits and any route to fault tolerance.

What it needs. The qubits, the long couplers' multilayer routing (cx_lr) and the SFQ flux DACs (ct_fluxdac) all require one superconducting process (fab_sc). Readout (ro_fluxro) requires the qubits and the DACs: a quantum flux parametron latches each qubit's current, on-chip shift registers carry the bit out. Static biases let DACs control "tens of thousands of qubits and couplers with just 200 bias wires" [C][281]. The empty layers mean: no encoding, so a qubit is a Hamiltonian term, not a memory; no readout during the anneal, so no syndrome for a code or decoder. Errors are never detected, only averaged over samples: more qubits buy larger problems, not better answers.

Where it stands. Four machines, three devices, 18 of 42 cells documented (Table 8.1), no gate. Advantage2 (D-Wave, May 2025; 4,400+ qubits, Zephyr 20-way, 12.5 kW [C][220]) supersedes Advantage (2020); Advantage3, a 20,000-qubit system for 2029 on the way to 100,000 qubits by 2031, is D-Wave's named next annealer [R][15]. D-Wave's "beyond-classical" spin-glass result (Science, March 2025) was substantially eroded within weeks by tensor-network and variational methods [D][221]–[223]; D-Wave maintains its largest instances remain unmatched [P][224]. Qilimanjaro's AQPU, a 10-qubit analogue fluxonium annealer, was inaugurated at the Barcelona Supercomputing Center on 28 May 2026 with no published benchmark [C][872]. §2.8 scores only E 4 and F 2; H1-2026 revenue fell 67% [C][15]–[17]; a CHIPS agreement (up to $100 M, 8 September 2026) funds work toward a 100,000-qubit annealer and a gate-model system [C][R][91].

Exceptions and borrowings. No cell falls off the slots; all fit here best. Both Advantage machines list dispersive readout (ro_disp), which the map says replaces the flux latch, as an alternate: perimeter resonators read the shift-register bits after the latch, so the two sit in series: a hybrid, not rivals. Qilimanjaro's coupler and DAC cells are inferred, its readout undisclosed: a data gap. Borrowings run outward: the D-Wave gate-model dual-rail system takes the flux DACs as an alternate, and IBM Quantum Loon and its successors use the long couplers for qLDPC checks.

The next test. §5.2 has no annealing row; D-Wave's roadmap serves. Its 20,000-qubit system for 2029 and 100,000 qubits by 2031 [R][15]–[17] rest on "superconducting interconnect technologies" for "multi-chip fabrics" [C][15]–[17], the layer the architecture leaves empty. Confirmation by March 2028: a multi-chip anneal with couplers across chip boundaries, or a beyond-classical claim surviving a year of classical challenge. Demotion: neither by then, and Advantage3 moved or dropped.

What the builders say. D-Wave's Advantage2 has more than 4,400 qubits, each coupled to 20 others so that larger problems can be embedded [C][220]. D-Wave says an Advantage2 prototype simulated magnetic materials in minutes where a classical supercomputer would need nearly a million years, a result published in Science [D][871]. It plans a multi-chip Advantage3: 20,000 qubits in 2029 and 100,000 by 2031 [R][15], wired through a new input-output design needing at most 20% more lines than today's 4,500-qubit machine [C][15]. Qilimanjaro builds analogue processors from fluxonium qubits, which it calls error-resilient by design and usable before fault tolerance; the first, 10 qubits, runs at the Barcelona Supercomputing Center, with two more generations due in 2026 and 2027 [C][872].

Machines of this architecture (register: 4, of them 3 devices, 0 gate-capable). D-Wave Quantum — Advantage3 (planned, 20,000), Advantage (deployed, 5,000), Advantage2 (deployed, 4,500); Qilimanjaro Quantum Tech — Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC (deployed, 10).

Cells outside the architecture's slots (7). Advantage: L7 ∅G-qac (Atlas gap — quantum annealing correction (penalty-repetition encoding) on up to 1,322 logical qubits o); Advantage2: L7 ∅G-qac (Atlas gap — penalty-spin and stacked quantum annealing correction on Advantage2_system1.10 (sweep 7 Oc); Advantage3: L4 undisclosed where the architecture expects a technology; Advantage3: L9 Multi-chip modules / l-couplers (same cryostat) (ic_mcm, primary off the architecture's slots); Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L4 undisclosed where the architecture expects a technology; Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L5 undisclosed where the architecture expects a technology; Qilimanjaro AQPU (Adiabatic Quantum Processing Unit) at BSC: L6 undisclosed where the architecture expects a technology.