rf-SQUID flux qubit (annealer) fluxq

A superconducting loop with a compound Josephson junction: flux bias sets barrier and tilt; the two circulating-current states are an Ising spin. D-Wave's line, D-Wave One (2011) through Advantage2 (GA 2025-05-20: 4,400+ qubits, Zephyr degree-20, 12.5 kW) P[220], rests on it. No gate set, only a programmable transverse-field Ising Hamiltonian, sampled.
Fabricated carrier; ~3 ns characteristic time, no deterministic entangling operation; dispersive readout ~1 µs, non-destructive, not mid-circuit.
Degree-20 coupling; low-frequency flux control at mK; Pauli plus coherent error; superconducting lithography.

Tunnelling amplitude and persistent current set the well. Landau–Zener demands a sweep slow against the square of the minimum gap, which for hard instances closes exponentially in size: the first floor is combinatorial, not material. The thermal floor binds sooner: at 15–20 mK kT is a few hundred MHz, so below that gap the chip equilibrates with its bath and emits a quasi-Boltzmann sample, not a ground state. 1/f flux noise dephases in the energy eigenbasis, making diabatic loss indistinguishable from a hard gap. Colder stages, larger persistent current or nanosecond quenches move the floor.

Dominant error: thermal excitation near the minimum gap.

D-Wave gives 200 bias wires in its 2026-01-06 release and ~300 in whitepaper 14-1090A-A (2026-01-23), the latter tied to a described array. The scope of the SkyWater relationship rests on nine EDGAR full-text hits in D-Wave's 10-Ks, not a quoted sentence. ECCN 4A906 states its threshold in two-qubit gate error; no ruling says whether an annealer falls inside it. Not published: the identity of D-Wave's Fortune-100 QCaaS customer and of the defence end-customer behind the Anduril/Davidson study.

Nb/Al multilayer superconducting lithography, the transmon fabs' family. The FY2024 10-K cites third-party foundries with a demonstrated second source; EDGAR returns nine SkyWater mentions in D-Wave 10-Ks 2023–26 fact, and SkyWater is IonQ-owned since 2026-07-31 fact — that source sits inside a competitor. The real asset is I/O: multiplexed on-chip flux DACs hold room-temperature line count at O(100) for tens of thousands of qubits and couplers, versus O(qubits) for gate machines — though D-Wave quotes 200 bias wires (2026-01-06) and ~300 (whitepaper, 2026-01-23), unreconciled Cfact. The wall at 10⁴–10⁶ spins is minor-embedding overhead and the 12.5 kW cryoplant, not wiring. ECCN 4A906 keys on two-qubit gate error, undefined here; 3A904 refrigerators bite instead G[301].

Serves the annealing architecture only and feeds no gate-model architecture: D-Wave's gate roadmap runs on acquired Quantum Circuits dual-rail hardware, a different carrier Cfact. The transfer runs the other way: the flux-DAC chip now drives fluxonium, key parts made at NASA JPL C[281]. No derived clock applies, nor randomised benchmarking or quantum volume, so every headline is time-to-solution against a classical solver. The March 2025 claim was eroded within weeks [222], [223]; D-Wave's counter (arXiv:2508.15759) inverts the burden, using the QPU as ground truth to argue tensor-network scaling extrapolations are unreliable P[224]. Unresolved as of 4 Sep 2026.

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| D-Wave Quantum | developer | US/Canada | Sole annealer vendor; Advantage2, Leap | C[15] |
| US Dept of Commerce | investor | US | $100 M CHIPS letter of intent | fact |
| Anduril Industries | user | US | Stride solver on Advantage2 | Pfact |
| Florida Atlantic University | user | US | $20 M campus Advantage2 | P[372] |
| NASA JPL | supplier | US | Made flux-DAC chip parts | C[281] |

Money. 2026-01-20 · D-Wave · M&A, Quantum Circuits · $550 M USD · closed Cfact. 2026-01-27 · FAU sale · $20 M USD · announced P[372]. 2026-01-27 · QCaaS, Fortune 100 · $10 M USD · announced C[373]. 2026-05-21 · CHIPS LOI · $100 M USD · Commerce · non-binding fact. 2026-08-06 · H1-2026 · revenue $5.9 M (−67% YoY), bookings $35.5 M (+1,120%), RPO $40.7 M · reported C[15].

Market & supply chain. One vendor, one carrier, one cryoplant class; foundry capacity shared with gate-model lines. Only G1 and parts of G5 pay for it; G3/G4 cannot, absent a code layer.

IP & standards. PatSnap's landscape published on 2026-06-30 counts 975 D-Wave quantum patent families Pfact; no annealing-specific litigation or standard found.

Roadmaps & track record. (2025-05 · for 2029/2031 · 20,000 then 100,000 qubits · open) R[15]. Scale milestones land on schedule; claims do not survive classical solvers; revenue collapsed while bookings and RPO rose, so monetisation is deferred, not lost.

Strategic reading. D-Wave wins if buyers keep paying for good-enough sampling on cheap I/O, loses if error-mitigated gate machines take the optimisation budget — which is why it bought a gate carrier. Pricing power over customers, none over foundries.

Confirm if a claim on a scientifically posed instance class survives a classical round through 2027; demote if erosion repeats. Best case 2029: 20,000 qubits and a defended claim; worst case, the line freezes at Advantage2 while the gate pivot absorbs the cash. Open: does any instance resist belief propagation and t-VMC?