Advantage

Raveh Neeman

doi:10.5281/zenodo.22674814

D-Wave Quantum

Advantage

D-Wave Quantum · quantum annealers · DEPLOYED (Sep 2020) · 5000 physical qubits · access: cloud (Leap) + on-prem sold

architecture: Quantum annealer — flux qubits · Open on the map

Register profile — the machine's variant of its architecture

qubit type: rf-SQUID flux qubit (analog Hamiltonian carrier)

gate mechanism: analog annealing evolution; not a gate

connectivity: Pegasus, degree 15

control: on-chip flux DACs + superconducting control circuitry

control placement: on-chip flux DAC

readout: QFP / SQUID flux readout through on-chip shift registers

gate evidence: no published figure

codes: qac

flags: annealer reference only

Technologies by layer — the machine's cell per layer

1 Qubit carrier	rf-SQUID flux qubit (annealer) · primary ▤ §Experimental testbed (ADV1: 5,627 qubits, Pegasus, cryostat set point 12 mK) ✅ rf-SQUID flux qubit (analog Hamiltonian carrier); 5,000+ qubits; DEPLOYED Sep 2020, still in service
2 Encoding	— none — nothing in this layer ◌ 🔎 analog annealer has no encoding layer; the anneal architecture declares an empty L2
3 Gate mechanism	Quantum annealing (analogue evolution) · primary ▣ §Quantum annealing (Methods); Fig. 5 (dynamical scaling, ta = 7 ns and 20 ns quenches) ✅ analog annealing evolution; not a gate
4 Connectivity / transport	Long-range on-chip couplers (c-couplers, mm-scale) · primary ▣ Fig. 1 (roadway drawing of Pegasus P3: internal/external/odd couplers); §2 Pegasus family of topologies ✅ Pegasus topology, degree 15
5 Control	On-chip flux-DAC multiplexing · primary ▣ Fig. 3–5 (Φ-DAC schematic, SFQ sources); Fig. 8 (XYZ addressing); §III Design and operation of a Φ-DAC ✅ on-chip flux DACs + superconducting control circuitry
6 Readout	Flux readout via QFP / SQUID shift registers (annealers) · primary ▤ §readout (QFP shift register; microresonator frequency multiplexing) ✅ QFP-based shift registers move qubit states along horizontal and vertical tracks to edge microresonators read in parallel by frequency multiplexing; Advantage_system4 readout 17–235 µs, error ≤ 0.001 (solver properties) Dispersive microwave readout (+TWPA, Purcell) · alternate ◌ 🔎 path-assigned ro_disp describes transmon readout, not annealer readout; actual is QFP/SQUID flux readout
7 Code	— (Atlas gap: ∅G-qac) · primary ▤ abstract ✅ quantum annealing correction (penalty-repetition encoding) on up to 1,322 logical qubits of Advantage 4.1 (sweep 7 Oct 2026, source read)
8 Decoder	— none — nothing in this layer ▦ 🔎 no decoder; QEC not applicable
9 Interconnect	— none — nothing in this layer ◌ 🔎 monolithic single QPU, no interconnect; no machine-specific source
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▣ §III.D Minimizing Φ-DAC footprint (6 Nb metal layers, 250 A/cm² trilayer); Fig. 9 (chip micrograph) ✅ superconducting flux-qubit lithography (in-house D-Wave process not published); no machine-specific fab source

Standard records

connectivity degree → 15 neighbours · typical (Pegasus)

Sep 2020 · source

evidence: ✅ 7 / 11

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1 — Figure 1: Realizing false vacuum decay on a quantum annealer. a The semi-classical energy landscape VV as a function of magnetization MM of a ferrom… — A five-panel figure of diagrams and data, not a hardware photograph: a double-well energy landscape, the anneal schedule, a drawing of the annealer's qubit graph with a spin chain embedded, a sunburst chart of bubble configurations, and a magnetization map. It is Figure 1 of "Stirring the false vacuum via interacting quantized bubbles on a 5564-qubit quantum annealer" by Vodeb, Desaules, Hallam and co-authors. It shows an annealer used as an analog simulator: spins start in a metastable 'false vacuum' and decay by forming bubbles of flipped spins. “Fig. 1 — Figure 1: Realizing false vacuum decay on a quantum annealer. a The semi-classical energy landscape VV as a function of magnetization MM of a ferromagnetic…” by Jaka Vodeb et al., arxiv.org/abs/2406.14718, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)

A close-up photograph of a square processor chip named WASHINGTON, wire-bonded into a gold-plated holder on a green circuit board, with traces running out to fine-pitch connectors. Credited to Mwjohnson0 (2015-11-02); the caption identifies it as the D-Wave TwoX 1000-qubit quantum annealing processor, introduced in 2015 with 128,472 Josephson junctions. The pinkish grid in the centre is the repeated array of superconducting flux-qubit cells; the ring of hundreds of wire bonds shows how many control lines such a chip needs. “D-Wave-Washington-1000Q” by Mwjohnson0, commons.wikimedia.org/wiki/File:D-Wave-Washington-1000Q.jpg, CC BY SA 4.0 (creativecommons.org/licenses/by-sa/4.0/)

File:D-Wave Two 512 qubit Vesuvius chip.jpg — A photograph of the D-Wave Two 512-qubit Vesuvius chip mounted in its gold-plated package, ready for cooling to near absolute zero. Steve Jurvetson took it at D-Wave's Canadian headquarters during a board meeting (uploaded 2018). The processor is a quantum annealer built from superconducting rf-SQUID flux qubits. Notice how small the square silicon die at the centre is compared with the circuit board, connector strips and coaxial cables that carry its control and readout signals. “D-Wave Two 512 qubit Vesuvius chip” by Steve Jurvetson, commons.wikimedia.org/wiki/File:D-Wave_Two_512_qubit_Vesuviu…, CC BY 2.0 (creativecommons.org/licenses/by/2.0/)