IBM Quantum Starling

Raveh Neeman

doi:10.5281/zenodo.22674814

IBM

IBM Quantum Starling

IBM · superconducting circuits · PLANNED (2029) · 22000 physical qubits · access: n/a

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: fixed-frequency transmon

gate mechanism: tunable coupler + c/l-couplers

connectivity: bicycle architecture: BB qLDPC memory blocks + logical processing units

control: room-temperature RF + cryo-CMOS

control placement: room-temp + cryo-CMOS

readout: dispersive

gate evidence: no published figure

decoder mode: planned — named in a roadmap only

codes: bb288, gross, qcga

flags: cryogenic details missing

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▨ ✅ fixed-frequency transmon; planned ~12 cryogenic modules × ≥2,000 physical qubits, order 20–25 k physical (2029, Poughkeepsie)
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▨ 🔎 tunable coupler + c/l-couplers (planned)
4 Connectivity / transport	Long-range on-chip couplers (c-couplers, mm-scale) · primary ▣ Fig. 1a (long-range modular vs short-range monolithic); §1.2 ✅ bicycle architecture: BB qLDPC memory blocks + logical processing units, l-coupled modules; degree 6
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▨ 🔎 room-temperature RF + cryo-CMOS (planned) Cryo-CMOS controller (4 K / mK) · alternate ▨ 🔎 cryo-CMOS control alongside room-temperature RF (planned)
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ◌ 🔎 dispersive readout (planned); no machine-specific source
7 Code	Non-local qLDPC codes (bivariate bicycle, 'gross') · primary ▣ Fig. 2 (module components: code c, LPU u); §2.1 Review of bivariate bicycle codes ✅ bivariate-bicycle qLDPC (gross [[144,12,12]]; qcga; bb288) memory blocks + LPUs; target 200 logical qubits running 10⁸ logical gates (2029) Magic-state factory (cultivation / distillation / code switching) · alternate ▣ Fig. 2 (factory f, code-factory adapter a′); §2.5 T injections ✅ magic-state resource alongside BB qLDPC memory in the bicycle architecture (register: gross; qcga; bb288); planned 2029
8 Decoder	Relay-BP for qLDPC (FPGA) · primary ▣ Fig. 2 (Relay-BP FPGA decoder architecture); Fig. 5 (XCVU19P floorplan); §4 ✅ Relay-BP on FPGA/ASIC, intended in-loop; FPGA demo [[144,12,12]] AMD VU19P: 24 ns/BP iteration, <1 µs per cycle on stored syndromes, not closed loop
9 Interconnect	Multi-chip modules / l-couplers (same cryostat) · primary ▣ Fig. 2 (module connectivity: linear/triangular); §2.4 Inter-module measurements ✅ l-coupled cryogenic modules (~12); enabler l-coupler 2Q 99.3% over ~1 m in-fridge link (Aug 2026) vs 99.9% required
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 superconducting-qubit lithography (IBM); no machine-specific fab source 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · alternate ◌ 🔎 300 mm CMOS foundry for cryo-CMOS control (planned); no machine-specific fab source

evidence: ✅ 6 / 13