Cryo-CMOS controller (4 K / mK) ct_cryocmos

A cryo-CMOS controller is a silicon ASIC on a cold plate in the refrigerator, generating microwave, flux and gate-bias waveforms next to the qubits. Nothing quantum happens in it: the gain is thermal and topological. It became hardware with Horse Ridge (Intel/QuTech, 22 nm FinFET, 4 K, 2019–2020) C[548] and Gooseberry (Microsoft/Sydney, 100 mK) D[549].

Attributes (a affinity; b time; c readout; d mobility; e control @ placement; f error structure; g manufacturing):

• a = 1.0, wholly fabricated; a foundry part, not a carrier.
• b = none; it holds no quantum state.
• c = none; it serves the host's readout.
• d = none; fixed to a cold plate.
• e = microwave @ 4 K; placement is the technology.
• f = coherent: amplitude, phase, timing, crosstalk.
• g = CMOS, 130 nm to 14 nm.

Rank 5 of 111; shared by the superconducting and spin architectures.

The floor is a heat budget, not a coherence time. Plants are small: 2 W at 4 K (Bluefors XLD1000sl), 24 W (IBM Goldeneye concept), 200 W (Fermilab Colossus) S[550]. The only power attached to a working two-qubit gate is IBM's 23 mW per qubit D[296]; the same review's optimistic case is 5 mW, its lowest demonstrations under 2 mW S[550]. A 2 W plant thus holds ~87 qubits at 23 mW, ~1,000 at 2 mW.

At millikelvin the regime changes kind: baseband, duty-cycled cells that hold a gate voltage and refresh it — 18 nW per cell for 100 mV pulses at 100 mK D[549], ~20 nW MHz⁻¹ per cell at 7 mK D[551].

Failure is coherent: drift and quantisation become rotation-angle error — a Delft converter drifted 60 µV/s to 18 mV/s C[552] — jitter becomes over-rotation, finite isolation crosstalk. The stochastic channel is back-action, worth 0.07% of single-qubit fidelity D[551]. The floor moves with a cold-characterised process C[553] or superconducting logic at ~1.6 µW/qubit S[550].

Best demonstrated: HRL's 130 nm RF CMOS controller at 4 K — ≤3.5 W, 366 DACs, a 250 MHz sequencer — driving 54 dots as 18 exchange-only qubits at mean single-qubit error 2×10⁻⁴ and mean CNOT 3×10⁻³ (best reproducible 9×10⁻⁴), closing a distance-5 repetition code at 5.0×10⁻³ over 200 rounds, Λ₅/₃ = 4.7, with nothing warm in the loop D[190] fact. IBM ran 14 nm flux-bias ASICs on a 156-qubit Heron R2 at median two-qubit error ≈2.3×10⁻³, parity with warm electronics on the same processor C[527]. Typical at scale: none — everything else above ~10 qubits runs from warm racks Dfact.

Dominant term: channel-to-channel non-uniformity — mean CNOT 3×10⁻³ against best reproducible 9×10⁻⁴, ~80% of it extrinsic, from control and calibration D[190].

No exotic process; the difficulty is a commercial node run 300 K outside its qualified range: 130 nm RF CMOS (HRL) D[190], 14 nm FinFET (IBM) D[296], 22 nm FinFET (Horse Ridge, Delft converters) C[548], [552], 28 nm FD-SOI (Gooseberry, Sydney) D[549], [551], 22FDX (Equal1) C[273]. The scarce input is the model, not the wafer: design kits stop at −40 °C, so actors keep private cryogenic models or buy a cryo-optimised process — SemiQon quotes 0.32 mV/dec subthreshold swing at 420 mK against ~60 mV/dec at 300 K C[553]. Yield and cost per channel are unpublished. Concentration sits in foundries willing to run unqualified corners and in dilution refrigerators Cfact. Export exposure is direct: the BIS rule of 2024-09-06 created ECCN 3A901.a for CMOS circuits "designed to operate at an ambient temperature equal to or less (better) than 4.5 K", catching this node by design intent rather than performance, beside controls on refrigerators and cryogenic probers G[301] fact. The controlled item can therefore be a design file.

HRL removed warm waveform generation, but the cable count did not fall: 296 lines for 18 qubits, ~16 each — the win was the rack, not the wiring D[190]. The wiring win is a millikelvin one, where demultiplexing turns N terminals into ~log N inputs: Pando Tree's 64 terminals at 10–20 mK C[272], Delft's 648 devices from 96 voltages under 120 µW C[552]. Latency is the second argument: 200 code rounds closed with nothing warm in the loop D[190], against 3.84 µs mean round trip on a warm GPU link fact. The walls follow the heat budget: 10³ qubits needs the sub-2 mW class on a 2 W plant; 10⁴ needs Goldeneye- or Colossus-class cooling at ≤5 mW/qubit; 10⁶ means ~90 modules of 10,000 qubits dissipating 50 W each at 4 K — outside anything sold in 2026 S[550].

Two architectures: superconducting transmons (IBM, Google, IQM) and silicon or germanium quantum-dot spins (Intel, Diraq, Quantum Motion, HRL, Quobly, Equal1). It requires a 300 mm CMOS foundry — a dependency spins already carry, so they get cryo-CMOS as a by-product while superconducting vendors fund it separately. It provides the cold digital substrate a cryogenic decoder needs: a 4 K predecoder costed under 0.56 mW for 3,780× syndrome-bandwidth reduction Sfact. It replaces room-temperature control, the only part of this layer with revenue, and competes with single-flux-quantum control, published above 99% at millikelvin Dfact; switching buys cold silicon on an 18–24-month tape-out loop, paid for in cooling budget that would otherwise buy qubits. The node is a non-quantum object whose only distinguishing attribute is placement at 4 K. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset; this node does not bind it — 4.0 ns sequencer granularity D[190] against a 0.65 µs round whose largest term is 282 ns of readout. Empty slots next door: a cryogenic readout digitiser and a standard cold digital interface.

Every headline number is measured through the qubit, never on the controller: interleaved randomised benchmarking, whose 1.71 and 17.51 instructions per Clifford (single- and two-qubit) must accompany any comparison D[296]; repetition-code Λ scaling across distances 3 and 5 for HRL D[190]; and, for IBM's 2026 flux result, an A/B comparison against warm electronics on the same processor — the right design, and the rarest.

Randomised benchmarking averages over Cliffords and is blind to slow coherent drift, so converter drift C[552] appears in no RB number; back-action, duty-cycle transients, channel non-uniformity and cold reliability need bespoke measurements D[551]. Replication is reasonable at 4 K (IBM, HRL) and at millikelvin (Microsoft, Sydney, Delft, QuTech C[554]).

Conflicts: IBM's 23 mW per qubit D[296] against 5 mW and under 2 mW S[550] are different quantities — active versus idle, drive-only versus full chain — with no common definition; 23 mW is used here as the only figure tied to a working gate. Equal1's fidelity figures are product-page claims C[273] against a published six-qubit device at 0.3 K fact.

On HRL's 54-dot exchange-only chip run by its 4 K CMOS controller, the measured error per exchange in a 12-spin cross-entropy benchmark (1.54×10⁻⁴) was more than ten times what component-level noise predicts (1.15×10⁻⁵) and mostly coherent; the authors suspect the cryo-controller and the signal lines. The controller's memory holds only about 1,000 unique pulse instructions once state preparation and measurement are loaded, so deep sequences had to be built from recursive subroutines P[900].

Gooseberry's 18 nW per cell D[549] and the Sydney chip's ~20 nW MHz⁻¹ per cell D[551] are different quantities. The cooling powers of the Bluefors XLD1000sl, IBM Goldeneye and Fermilab Colossus come from the resource review S[550], not from the makers' specifications. IBM's 2026 cryo-CMOS flux result, including its 14 nm FinFET attribution, exists only as conference abstracts as of 2026-09-03 C[527]. SEEQC's S-1 amendment of 2026-08-28 gives $4.2 M revenue in 2025 and $18.1 M cash at 2026-06-30 C[556] P[557] fact; the $1 B enterprise value and $65 M PIPE describe the terminated Allegro merger. Quantum Machines' ">50% of companies developing quantum computers" is a company claim C[528]. Not published: the cooling power at 4 K of IBM's modular cryogenics; SemiQon's process node, fab location and the size of its 2026-07 PostScriptum investment; SEEQC's offering size; the revenue of Quantum Machines and any comparable figure from Zurich Instruments, Keysight or QBLOX, so the warm-control market cannot be sized; the power, channel count and process node of the QuTech/Fujitsu diamond cryo-CMOS ISSCC 2026 paper beyond its institutional release C[554]; a dated cryo-CMOS patent-family count — PatSnap gives only regional tallies with a completeness disclaimer P[563]; and HRL's controller cost, tape-out schedule and whether IBM retains the 130 nm design, after the acquisition that closed on 2026-08-26 C[10] fact.

Money.

• 2025-02-25 · Quantum Machines · Series C · $170 M · PSG Equity · $280 M cumulative C[528]
• 2025-11-06 · DARPA QBI Stage B · up to $15 M each · eleven teams incl. IBM, Diraq fact
• 2026-05-21 · GlobalFoundries; Diraq · CHIPS letters of intent · $375 M; $38 M · LOI fact
• 2026-06-29 · SEEQC · S-1 for Nasdaq beside an Allegro merger · $1 B enterprise value, $65 M PIPE C[556] P[557]; SPAC merger terminated 2026-08-25, S-1 continues, IPO unpriced as of 30 Sep 2026 fact
• 2026-07-23 · IBM · acquires HRL Laboratories · undisclosed · closed 2026-08-26 C[10] factfact

Market & supply chain. Nobody sells a cryo-CMOS controller as of 3 Sep 2026; the layer's revenue is warm racks from Quantum Machines, Zurich Instruments, Keysight and QBLOX, and Quantum Machines alone has raised $280 M C[528], [558]. Cryo-CMOS itself is captive R&D; merchant offers are pre-revenue: SemiQon, FrostByte (€1.3 M) and Rhonexum ($1 M) C[553], [559] P[560]. G3, G4 and G7 pay for it; G1, G2 and G5 do not.

IP & standards. Microsoft Technology Licensing holds US 11,838,022 on the cryogenic-CMOS qubit interface (granted 2023-12-05), the charge-lock architecture behind Gooseberry G[555]; MIT holds US 12,705,525 on baseband pulsing (2026-08-11) G[561]; Intel's closed-loop calibration filing is an application only G[562]. No database publishes a dated family count P[563]. Standards: none, and no agreed power-per-qubit definition.

Roadmaps & track record.

• Intel: 2020-12-03 · Horse Ridge II for scaled spin systems · no successor fact.
• Microsoft: 2021-01-27 · Gooseberry to "thousands of qubits" · not delivered C[564].
• IBM: 2024-02-14 · cryo-CMOS as the route to scalable control · partly delivered, flux only D[296] C[527].
• HRL: 2026-04-17 · a processor with no warm waveform generators · delivered D[190].
  Credibility: HRL alone named a dated deliverable and shipped it, and IBM bought it; IBM publishes A/B comparisons, not headline claims; Intel has no peer-reviewed fidelity on a Horse Ridge part; Microsoft's line is five years dormant.

Strategic reading. Winners if cold control becomes standard: integrated CMOS houses — IBM with HRL, Intel if it re-engages — and spin companies whose qubits and controllers share a line. Losers: warm-rack vendors, protected only while nobody below a thousand qubits needs an ASIC. The other cold route, SFQ control, is projected to draw less power per qubit S[550] and has no two-qubit gate yet; its developer, SEEQC, has filed for a Nasdaq listing, offering size undisclosed P[557]. Bargaining power stays with platform vendors; the scarce supplier is the refrigerator maker.

Confirm within 12–24 months if IBM publishes a peer-reviewed full chain — drive, flux and readout — on ≥100 superconducting qubits at warm-rack parity; if the HRL controller reappears inside IBM above 18 qubits; if anyone reports a defined power per qubit below 5 mW at 4 K under load. Demote if by end-2027 nothing drives more than about fifty qubits end-to-end in a peer-reviewed result and Heron-class systems still ship warm racks. Best case by 2029: cold control standard on spin machines and IBM's flux path, a 10,000-qubit module on one 4 K plant at ≤5 mW/qubit. Worst case: the budget stays binding, superconducting machines keep warm racks, and cryo-CMOS survives only as millikelvin biasing for spins.

Open questions: (1) a defensible power-per-qubit definition? (2) will a foundry qualify a cryogenic corner? (3) does controller drift dominate below 10⁻⁴ qubit error? (4) must per-qubit power fall, or can the plant grow tenfold? (5) will IBM keep HRL's 130 nm design? Watch ISSCC 2027, IBM's post-acquisition disclosures, and any 4 K plant marketed above 20 W.