foundry 8-qubit array
foundry 8-qubit array
Register profile — the machine's variant of its architecture
qubit type: Si-MOS electron spin, Loss-DiVincenzo
gate mechanism: ESR 1Q by distinct Larmor frequencies (Rabi 141-205 kHz); exchange CZ 2Q - exchange control demonstrated in only one of four qubit pairs
connectivity: 1-D nearest neighbour; the FT plan buys non-locality from electron shuttling confined to localized blocks
control: baseband + ESR from room temperature; cryo-CMOS is the stated scaling route
control placement: room-temp baseband (cryo-CMOS planned)
readout: two SETs at the chain ends plus a cascaded electron-cascade charge-sensing protocol for the central qubits - 8 qubits read through 2 sensors
gate evidence: no published figure
flags: no benchmarks on array
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▣ Fig. 1a (device cross-section: 28Si, plunger/barrier gates); §II.1 Device ✅ 8 Si-MOS electron spins in a linear chain, operated as four two-qubit unit cells (Nat. Commun., Jul 2026) |
| 2 Encoding | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ▣ Fig. 1d (Rabi chevrons, qubits 1-8); Fig. 2a (Larmor frequencies) ✅ bare electron spin-1/2, Loss–DiVincenzo encoding |
| 3 Gate mechanism | Exchange gate (spins; incl. shuttled-spin CZ) · primary ▣ Fig. 3 (P1-P2 exchange, CZ phase calibration); Fig. 2b (Rabi freqs); §II.2 ✅ ESR 1Q by distinct Larmor frequencies (Rabi 141–205 kHz) + exchange CZ; exchange shown in 1 of 4 pairs; no gate fidelities reported |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1a (linear 8-dot array schematic); §II.1 Device ✅ 1-D nearest-neighbour chain of 8 qubits Spin shuttling (conveyor mode) · alternate ▨ ✅ FT plan: non-locality from electron shuttling confined to localized blocks (Iceberg Pinnacle architecture); not on this array |
| 5 Control | Baseband electrical control (spins, Majorana) · primary ▤ §IV.2 Methods: Measurement ✅ baseband + ESR from room temperature; device at ~20 mK, 0.5 T Cryo-CMOS controller (4 K / mK) · alternate ▨ 🔎 cryo-CMOS is the stated scaling route; not used on this array |
| 6 Readout | Spin-to-charge conversion + rf reflectometry · primary ▣ Fig. 1b (direct SET vs cascaded spin-to-charge readout); §II.2 ✅ two SETs at the chain ends + cascaded 'electron-cascade' charge sensing for central qubits — 8 qubits read through 2 sensors |
| 7 Code | Non-local qLDPC codes (bivariate bicycle, 'gross') · alternate ▣ Fig. 1 (Pinnacle examples for RSA-2048); §V.A + Table I (GB codes); Fig. 6 (logical error sims) ✅ roadmap: Pinnacle generalized-bicycle qLDPC compilation (not run) — none — nothing in this layer ◌ §V.A Setup (GB code family, Table I); §IV.C Scalability 🔎 no code on hardware |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▤ §IV.1 Methods: Fabrication ✅ imec 300 mm CMOS pilot line, Leuven (also GlobalFoundries); Δg = 2.17×10⁻³ across the 8-qubit chain |
Standard records
parameter spread → 2.17e-3 · typical (g-factor spread across 8 qubits)
Jul 2026 · source
1Q gate time → 2.4 µs · best (pi-pulse at 205 kHz Rabi)
Jul 2026 · source
T2 coherence (echo/DD) → 1.3 ms · best (Hahn echo across the chain)
Jul 2026 · source
evidence: ✅ 9 / 13