Baseband electrical control (spins, Majorana) ct_base

Baseband control manipulates a qubit with DC-to-few-GHz voltage pulses on lithographic gates rather than a resonant drive: a pulse shifts the electrostatic potential, and with it the exchange coupling between dots or the tunnel coupling of a Majorana junction. The licence is old and precise: DiVincenzo, Bacon, Kempe, Burkard and Whaley showed in 2000 that the Heisenberg interaction alone suffices for universal computation, at about 3× more qubits and ~10× more two-qubit operations S[416]. Every exchange-only architecture since pays that bill to delete microwave hardware.

• Control and placement: low-frequency voltage pulses generated warm, routed to millikelvin gates.
• Error structure: coherent and correlated, not stochastic — miscalibration is what the code sees.

Exchange coupling J depends exponentially on detuning and barrier height, so a rotation angle is the time integral of J and a small voltage error is a proportionally large angle error. There is no drive-frequency selectivity: 1/f charge noise modulates the same potential that carries the signal, and crosstalk from a neighbouring gate is indistinguishable from an intended pulse. Hence the field's most useful number — HRL measures ~80% of its CNOT error as extrinsic, in control and calibration rather than the qubit Dfact. The floor is waveform accuracy and recalibration cadence, not T2: foundry devices reach 1.31(4) ms echo coherence Dfact against 58 ns exchange gates Dfact. Moving it means a shorter electrical path — a controller on the cold stage, ideally on-die — plus automated recalibration.

Dominant term: extrinsic control and calibration, ~80% of the CNOT budget.

Baseband control can drop per-pair barrier pulsing: in a 6×6 germanium hole-dot array, one shared barrier gate held at a fixed voltage, with only the individual plunger gates pulsed, sufficed for electric-dipole spin resonance (EDSR) driving, shuttling and exchange tuning from about 20 kHz to about 80 MHz P[898].

The node rides ordinary CMOS: Intel's 300 mm EUV line reports over 24,000 devices per wafer D[199], with 96% tune-up yield on 232 devices of one wafer D[766], and Quantum Motion characterises 1,024 dots in five minutes on GlobalFoundries 22FDX C[200]. That is the asset and the exposure: each developer sole-sources one foundry it does not own — Quobly to STMicroelectronics, Quantum Motion to GlobalFoundries, Diraq to imec — so a fab-side decision is a company-level failure mode. Room-temperature pulse generation is uncontrolled, but a controller "designed to operate at" ≤4.5 K falls under ECCN 3A901.a from the design file on fact: cold integration imports export control.

Baseband control costs about one line per gate and two to four gates per dot, so a naive 10³-qubit array wants 10³–10⁴ addressed lines from room temperature. HRL's counter-example is the number to hold: 296 lines and 366 DACs at ≤3.5 W driving 54 dots, with a 250 MHz on-chip sequencer and no room-temperature real-time electronics Dfact — ~20 DACs per qubit, cold multiplexing rather than wire elimination. At 10³ the harness is impractical without cold DACs; at 10⁴ per-qubit DAC count must fall an order of magnitude; at 10⁶ nothing exists. The binding constraint is recalibration cadence.

It requires nothing upstream, provides the exchange gate directly, and reaches four architectures: quantum-dot spins (Intel, Diraq, Quantum Motion, HRL/IBM, QuTech, Quobly, Equal1), donor spins (Silicon Quantum Computing), colour-centre spin network nodes and Majorana devices, where gate voltages tune the dots that report parity. It competes with microwave and electric-dipole spin resonance, which buys frequency selectivity at the price of antennas and heating. Its clock contribution is negligible: exchange gates run at ~58 ns Dfact against 6.3 µs readout, so derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 8.5 µs here, set by readout with reset next.

Fidelities come from randomised benchmarking and gate-set tomography, and the headline QuTech number is a lower bound, not a point estimate Dfact. The 80% extrinsic share deserves most scrutiny: it is inferred from measured error against a modelled noise budget, not independently partitioned, and unreplicated. No spin device above 12 qubits has published all-pairs two-qubit fidelities, so simultaneous-operation crosstalk — this node's own failure mode — is uncharacterised at scale. HRL's Λ₅/₃ = 4.7 is a repetition code, bit-flip only, not below-threshold evidence, and its [[4,2,2]] fidelity of 0.95 is post-selected Dfact. On the Majorana side the control works but the qubit does not exist: parity readout is real, X-loop lifetimes ran ~1,000× shorter than Z-loop lifetimes, no two-qubit operation D[13].

Not published: a dated patent-family count for baseband gate-voltage control.

Who.
| Organisation | Role | Country | What exactly they do | Evidence |
|---|---|---|---|---|
| HRL Laboratories | Developer | USA | Only self-sequenced baseband QEC demonstration; acquired by IBM | Dfact |
| Diraq | Developer | Australia | SiMOS exchange qubits on imec's 300 mm line | Dfact |
| Quantum Motion | Developer | UK | Full-stack 300 mm CMOS system at the UK NQCC | Cfact |
| QuTech | Research | Netherlands | Microwave-free hopping control, 2D array | Dfact |
| Microsoft | Developer | USA | Gate-voltage-tuned parity measurement in tetrons | D[13] |

Money. 2025-11-06 · Diraq, Quantum Motion, Silicon Quantum Computing · DARPA QBI Stage B · up to $15 M USD each · programme fact. 2026-05-07 · Quantum Motion · Series C · $160 M USD · DCVC, Kembara · closed Cfact. 2026-05-21 · Diraq · CHIPS letter of intent · up to $38 M USD · US Commerce · non-binding fact. 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicro · €134 M cumulative · closed Cfact. 2026-07-23 · IBM · acquires HRL · undisclosed · closed 2026-08-26 Cfactfact.

Market & supply chain. Nothing is sold as "baseband control"; what sells is foundry capacity, enriched ²⁸Si, and the warm waveform racks Quantum Machines dominates with over half of developers as customers Cfact. Cold integration threatens that rack business, and is why IBM bought HRL. Diraq's under-$1-per-qubit figure is a target, not a cost. This node pays for G3 and G4 on the spin architecture, G4 on the Majorana architecture if a qubit appears.

IP & standards. No patent family specific to baseband gate-voltage control was found in a named dated database as of 4 Sep 2026. The foundational exchange-only claim is a 2000 publication, long out of patent term S[416] — part of why this layer is crowded. IBM's HRL deal brings undisclosed controller IP in-house. No standards body governs gate-pulse interfaces today.

Roadmaps & track record. Diraq (2026-08-27 · 150 k physical, 1 k logical by 2029, > 2 M by 2031 · its 2026-07-09 release said "thousands by 2029") — low on messaging, real on devices fact. Quantum Motion (full-stack delivery · met, NQCC 2025-09-15) — the only met hardware date here. HRL/IBM (no public date · QPU delivered 2026-07-29) — strongest result here. Microsoft ("years not decades" → 2029 · no two-qubit operation) — no base.

Strategic reading. If baseband control scales, foundry-native platforms inherit decades of CMOS investment free while exotic-control platforms fund their own hardware forever — the argument IBM made by buying HRL. Losers are room-temperature control-rack vendors, displaced from inside the cryostat rather than out-competed on price. The live substitution question is warm versus cold placement, not baseband versus microwave drive. Bargaining power sits with the foundries: every developer above depends on a relationship it cannot replace within a product cycle.

Confirm by 2027 if any developer publishes all-pairs two-qubit fidelities above 12 qubits, or an independent group reproduces the extrinsic/intrinsic split; demote if crosstalk caps arrays at ≤20 qubits through 2028. Best case 2029: cold self-sequenced control becomes default and two-qubit errors move from 3×10⁻³ toward 10⁻⁴. Worst case: calibration overhead outruns qubit count and the CMOS argument stalls at demonstration scale. Open questions: does the 80% figure survive independent measurement; can per-qubit DAC counts fall an order of magnitude; does recalibration keep pace with array size; does Majorana control ever get a qubit.