Topological — tetron (Majorana) on the map bar: Majorana parity
Topological — tetron (Majorana)
Derived clocks
- syndrome round
- —
- measured cycle
- n/a (no qubit)
- reaction time
- floor — · no published measurement→operation loop
- coherence
- T1 — · T2 — · ops per coherence —
- idle exposure per round
- t_round/T2 = — · measured idle error —
- notes
- reset time unpublished for ro_qcap; no code on this architecture
Technologies by layer — primary, then alternates
| 1 Qubit carrier | Majorana parity (InAs–Pb tetron) |
| 2 Encoding | Fermion-parity encoding (tetron) |
| 3 Gate mechanism | Measurement-based Majorana gate |
| 4 Connectivity / transport | Static nearest-neighbour lattice |
| 5 Control | Baseband electrical control (spins, Majorana) |
| 6 Readout | rf quantum-capacitance parity readout |
| 7 Code | ∅ empty slot |
| 8 Decoder | ∅ empty slot |
| 9 Interconnect | ∅ empty slot |
| 10 Manufacturing | III-V MBE heterostructures (InAs–Pb wires, QD sources) |
Relations within the architecture
Machines of this architecture · 2
The architecture in the report (§8.3)
8.3.16 Majorana parity — Topological — tetron (Majorana) (topo)
The idea. Four Majorana zero modes on two gate-defined InAs–superconductor wires (majorana) hold one qubit at fixed total fermion parity (enc_parity, the tetron): Z and X are parities of different mode pairs. Gates would be parity-measurement sequences read by rf quantum capacitance (g_mbq, ro_qcap). The claim is a topological gap: with the modes far apart, their splitting falls exponentially with wire length and only an arriving quasiparticle flips a parity. Table 8.3's bet, protection in hardware instead of a code, is an existence claim, at the price of Clifford-only gates and no fallback.
What it needs. One chain, no alternates: the gate requires the wires and the readout, every gate being a measurement; the encoding two wires per tetron; the readout the island's quantum capacitance; the wires an InAs–Pb stack from III-V MBE (fab_mbe), whose disorder can mimic Majorana signatures. No replaces or conflicts edge: with no rival at any layer, one failure strands the architecture. Code, decoder and interconnect are empty (§7.6); a Floquet or measurement-based code awaits a demonstrated qubit. The gate is an empty slot: specified since 2008, never operated.
Where it stands. Two machines, no device: Majorana 1 and Majorana 2 (Microsoft), both contested, 5/30 in §2.7 [D]. Measured: single-wire parity readout at 1% assignment error, not by itself proof of Majorana zero modes (MZMs), the editors noted [D][13], [214]; tetron Z- and X-loop parity lifetimes of 12.4 ms and 14.5 µs, the X–Z succession test deferred [P][20]; a ~20 s InAs–Pb parity switching time in one wire of one tetron, called a qubit lifetime by Microsoft's blog [P][21][C][215]. No braiding, X measurement on Majorana 2, or two-qubit operation. A Nature Matters Arising disputes the topological reading, answered without concession [D][22], [23]; QuTech's independent Kitaev-chain parity qubit has limited protection [P][217].
Exceptions and borrowings. None off-slot: the machine fills all seven technologies and fits no other architecture — weak evidence: the architecture was drawn around it; one machine cannot test its width. The code gap (∅G-pathcode) is telling: Microsoft's own geometric codes need all-to-all connectivity, which its neutral-atom product offers (§3.3) and the intended tetron lattice does not. Of its own technologies only MBE travels: Belenos and Lucy (Quandela), on the fusion architecture, grow quantum-dot photon sources with it.
The next test. Per §5.2, an X-parity lifetime near the Z lifetime, or any two-qubit entanglement, confirms; neither by end-2027 demotes. Since 22 September 2026 DARPA's evaluators have on-site access to a Majorana 2 system in Microsoft's Maryland research centre — access, not a result [C][219]. Expectation: by March 2028 an X/Z lifetime ratio below 10² (now ~10³ [20]) or a joint parity measurement across two tetrons, confirmed by DARPA; without either, the tetron is a materials result, not an architecture.
What the builders say. Microsoft argues that topological qubits suit error correction through inherently low error rates, small size and digital control [C][215], and presented Majorana 1 as eight qubits on a chip designed to scale to a million [C][870]. With lead replacing aluminium in its tetrons (qubits made of two superconducting nanowires with MZMs at their ends), it reports in a preprint parity lifetimes near 20 seconds, some reaching a minute [P][21]. On that basis it halved its timeline and now aims at a scalable, practical quantum computer by 2029, without a qubit count [R][215]. In September 2026 it gave DARPA full on-site access to its Majorana 2 system for independent testing [C][219].
Machines of this architecture (register: 2, of them 0 devices, 0 gate-capable). Microsoft — Majorana 1 (other), Majorana 2 (other).
Cells outside the architecture's slots (1). Majorana 1: L7 ∅G-pathcode (Atlas gap — empty L7 on topo architecture; MS 4D geometric codes [[96,6,8]] need all-to-all, not a tet).