Fermion-parity encoding (tetron) enc_parity

Four Majorana zero modes (MZMs) on two wires joined by a superconducting backbone hold one qubit: Z is the parity of one wire's mode pair, X of a pair spanning both, so neither logical operator is local. Karzig et al. defined the tetron and hexon layouts in 2017, with Cliffords by measurement rather than braiding S[421]. Only Z-type parity has been read with a stated fidelity; the X measurement the encoding requires has not D[21].
a fabricated (1.0) · b not a gate · c no readout · d no transport
e no control · f asymmetric, poisoning-dominated · g inherits the wire fab

Protection is a length and a gap: parity splitting falls exponentially with length over coherence length, poisoning as the gap rises against temperature and quasiparticle density S[421]. Neither is published. Published instead: 12.4 ms on the Z loop against 14.5 µs on the X loop in one device D[20]. Both are fermion parities, so the ~1000× factor is geometric: the X loop encloses both wires and captures quasiparticles over a larger cross-section D[20]. A code needs comparable rates on both bases, and this is not usable bias: the short basis is the one a measurement-based gate projects most. Moving the floor means a larger gap (lead replaced aluminium D[21]), quasiparticle trapping and a smaller X loop.

No logical state prepared, no X measurement, no coherence time or logical error rate for a tetron D[21].

The arXiv text of [20] also gives X ~4 µs and Z ~9.3 ms for other tunings, against the 14.5 µs / 12.4 ms quoted above. No non-Microsoft tetron exists. Not published: a Majorana splitting, a wire length over coherence length or a quasiparticle density for any tetron, so the protection claim cannot be checked numerically; and whether the X/Z asymmetry is geometric or intrinsic.

No process of its own; the encoding fixes a geometry. Two wires, a backbone and the dots closing each loop cost more area and steps than a bare wire, and the X loop's coupling elements are exactly what a Z-only measurement avoids. Bring-up is per device: the 2026 rf technique resolves wire-end-state splitting to µeV so array devices can be tuned at all D[21]. Below it is in-house InAs–Pb epitaxy, unreplicated outside Microsoft; no export-control category specific to it.

Architecture: topological — tetron (Majorana), where it is the primary encoding. It requires two wires per qubit and supplies the logical degree of freedom a measurement-based gate would act on; nothing else consumes it, and it sets no clock. Verification is one-sided: telegraph statistics on parity loops, no logical error per cycle, no Λ, no independent tetron. The dispute runs deeper: Legg's Matters Arising (2026-06-24) argues the regions read out in 2025 were disordered and gapless, making the encoded object trivial rather than protected; Microsoft's same-day reply concedes nothing D[22]. QuTech's parity qubit in coupled Kitaev chains is an alternative encoding with limited protection, not a tetron replication D[217].

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Microsoft Quantum | developer | US | Defined the tetron and holds the only Z/X data | D[20] |
| DARPA | investor | US | US2QC final Validation & Co-Design stage since 2025-02-06 | fact |
| QuTech | research | NL | Competing parity encoding in coupled Kitaev chains | D[217] |
| Nokia Bell Labs | research | US | Fractional-quantum-Hall anyon route, a different encoding | Dfact |

Money. 2025-02-06 · Microsoft · US2QC final Validation & Co-Design stage · undisclosed · DARPA · announced fact. 2026-01-23 · Microsoft · Quantum Pioneers Program, QEC an award topic · ≤ USD 200,000 per proposal · announced Pfact.

Market & supply chain. Nothing is sold; it consumes wires and readout and pays back only in G4, after an X measurement exists.

IP & standards. The tetron layout is Microsoft's published lineage S[421]; no dated patent count specific to it as of 4 Sep 2026.

Roadmaps & track record. (tetron as the fault-tolerance unit, promised 2017, restated for 2029 in 2026; status 4 Sep 2026: no X measurement, no logical qubit) C[215]. Nine years from design to a one-wire measurement, with no interim milestone for the X/Z ratio.

Strategic reading. Every topological claim above sits on this ratio. If it closes, Microsoft's fabrication lead becomes a code; if not, the tetron gives way to a longer Kitaev chain and the wire stack loses its justification. Risk is single-vendor and single-design.

Falsifiable in 12–24 months: any X-basis parity measurement with a stated assignment error; an X/Z ratio below 100×; a joint measurement across two tetrons. Confirm on the first two; demote to theory if none appears by end-2027. Best case, loop redesign and a larger gap bring X into milliseconds; worst case, X-loop poisoning is intrinsic and the design is abandoned. Open: is the asymmetry geometric or intrinsic; does anyone build a tetron outside Microsoft.