HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots)
HRL Laboratories (IBM since 26 Aug 2026)
HRL exchange-only silicon spin processor (18 EO qubits from 54 quantum dots)
Register profile — the machine's variant of its architecture
qubit type: exchange-only (EO) spin qubit: three electron spins in three gate-defined Si/SiGe quantum dots (²⁸Si-enriched, ⁷³Ge-depleted heterostructure)
gate mechanism: baseband exchange pulses only (symmetric exchange): 1Q gates of 4 exchange pulses; CNOT of 37 pulses in 45 timesteps
connectivity: 3×6 square lattice of EO qubits, nearest-neighbour coupling (54 dots in three sparsely coupled rails)
control: custom cryo-CMOS controller (commercial 130-nm RF CMOS SoC): 366 DACs, 78 pulse generators, 156 output channels, ≤3.5 W; superconducting ribbon cable carries 150 time-varying control signals and 35 static biases to the mK qubit board
control placement: 4 K (cryo-CMOS controller); room temperature supplies digital signalling, static biases and readout digitisation
readout: Pauli spin blockade (pairwise singlet/triplet) sensed by a dot charge sensor into a 4 K HEMT transimpedance amplifier (~10 MHz bandwidth); digitised at room temperature
gate evidence: a published figure (source class not yet tagged)
decoder mode: offline — syndromes decoded after the run
codes: quantum_repetition, stab_4_2_2
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▣ Fig. 1c; Methods: Qubit chip ✅ 54 gate-defined quantum dots in a Si/SiGe heterostructure enriched with ²⁸Si and depleted of ⁷³Ge, arrayed in three rails |
| 2 Encoding | Exchange-only / singlet–triplet spin encoding · primary ▣ Abstract; Fig. 1c; Methods: Exchange-only qubits ✅ exchange-only qubits: three spins per encoded qubit, up to 18 EO qubits on the 54-dot chip |
| 3 Gate mechanism | Exchange gate (spins; incl. shuttled-spin CZ) · primary ▣ Fig. 2c; Fig. 3a ✅ all gates by symmetric exchange pulses: 1Q gates of 4 pulses (mean error 2e-4); CNOT of 37 pulses in 45 timesteps (mean error 3e-3, lowest reproducible 9e-4) |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1c ✅ EO qubits in a 3×6 square lattice with nearest-neighbour coupling; the 54 dots sit in three sparsely coupled rails |
| 5 Control | Cryo-CMOS controller (4 K / mK) · primary ▣ Fig. 1a-b; Fig. 2; SI S1.D ✅ custom cryo-CMOS SoC at 4 K (commercial 130-nm RF CMOS; 366 DACs, 78 pulse generators, ≤3.5 W) generates all 150 time-varying control signals; a superconducting ribbon cable carries them to the mK qubit board Baseband electrical control (spins, Majorana) · alternate ▣ Introduction; Fig. 2c ✅ control waveforms are shape-insensitive baseband voltage pulses (T10–90 ≈ 150 ps) from one pulse generator per exchange gate |
| 6 Readout | Spin-to-charge conversion + rf reflectometry · primary ▤ Methods: Exchange-only qubits; SI S3.D; Fig. 1b ✅ Pauli spin blockade (pairwise singlet/triplet) sensed by a dot charge sensor into a 4 K HEMT transimpedance amplifier (~10 MHz bandwidth); digitised at room temperature |
| 7 Code | Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) · primary ▣ Fig. 4a (repetition-code circuit); Fig. 4e; SI S8.D ✅ [[4,2,2]] error detection on 6 EO qubits (slightly improved system): F_L = 0.95 post-selected (~77% of 10,000 shots rejected), 0.59 without; plus a d=5 bit-flip repetition code on 7 EO qubits, Λ5/3 = 4.7 over up to 200 rounds (no technology) — (Atlas gap: ∅G-repetition) · alternate ▣ Fig. 4a (repetition-code circuit); Fig. 4e; SI S8.D ✅ d=5 bit-flip repetition code on 7 exchange-only qubits, Λ5/3 = 4.7 over up to 200 rounds, self-sequenced by the 4 K controller |
| 8 Decoder | — (Atlas gap: ∅G-parity) · primary ▤ Repetition codes section; SI S8.D 🔎 repetition-code syndromes interpreted after the run with a parity-check (majority) decoder, not matching; [[4,2,2]] decoded by post-selection; the 4 K controller sequences syndrome extraction autonomously |
| 9 Interconnect | — none — nothing in this layer ▣ Fig. 1a ✅ one QPU: 4 K controller motherboard, superconducting ribbon cable, mK qubit daughterboard; no inter-module link |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▤ Main text: cryo-controller; Methods: Qubit chip ✅ cryo-controller fabricated in a commercial 130-nm RF CMOS process; qubit chip on 200 mm Si wafers (CVD SiGe, e-beam gates at 70 nm pitch, CVD W vias) by a proprietary qubit-specific process |
evidence: ✅ 11 / 12