Exchange-only / singlet–triplet spin encoding enc_eo

Two or three spins in adjacent dots encode one qubit in a subspace of fixed total spin, every gate a pulse of Heisenberg exchange — baseband voltage, never a microwave tone. The basis is DiVincenzo, Bacon, Kempe, Burkard and Whaley, Nature 408, 339 (2000): exchange alone implements any circuit, so local single-qubit drive disappears S[416]. Scaled three-dot demonstrations date from about 2013. Attributes: affinity — fully composite, the opposite pole from the bare spin; error — leakage plus coherent exchange error, no control modality or fabrication of its own.

Three spins span eight states and the qubit uses two, so population leaks into the spin-3/2 manifold, invisible to a Pauli-frame decoder unless converted into detectable error. That is the encoding-specific floor: 0.015% per Clifford for always-on two-exchange operation against a 0.029% single-exchange average D[417]. In return it is a decoherence-free subspace against uniform field noise, but exchange depends exponentially on barrier voltage, so charge noise enters the gate. Neither term dominates: HRL attributes roughly 80% of its CNOT error to extrinsic control and calibration D[190]. Sweet-spot operation, always-on pulsing (1.9 versus 2.7 pulses per Clifford D[417]) and cold calibration move it.

Dominant term: extrinsic control and calibration, then leakage; best reproducible CNOT 9×10⁻⁴ D[190].

Benchmarked as one system rather than as encoded qubits, 48 spins of HRL's 54-dot device span the whole total-spin-zero space, of dimension C₂₄ ≈ 2⁴⁰ (a Catalan number), which includes the states a three-spin encoding treats as leakage; mirror randomised benchmarking gives an error of 3.2×10⁻⁴ per exchange pulse (2.2×10⁻⁴ device-wide by cross-entropy benchmarking), with the 4 K cryo-CMOS controller in the loop P[900]. That is an error per exchange pulse, not a two-qubit gate error: at 37 exchanges per encoded CNOT the additive estimate is about 1%. The space has no local qubits, and no method yet compiles programs or runs error correction in it P[900].

The 0.2 W per qubit is derived from HRL's published controller power and qubit count; the paper states no scaling figure. HRL's ~80% extrinsic-error attribution is self-reported, and neither the UCLA nor the HRL result has an independent replication. Not published: all-pairs two-qubit fidelities for any exchange-only device.

Three dots per qubit — two for singlet–triplet — triples gate-stack density per logical unit on the hosting 300 mm process, with no encoding-specific step. The win is control: purely baseband, no microwave lines or micromagnets, the sequencer inside a 4 K controller in commercial 130 nm RF CMOS — 366 DACs, 296 lines, ≤3.5 W, no room-temperature real-time electronics D[190] — the first sign a control rack can become a cold ASIC. That sets the wall: ≤3.5 W for 18 qubits is ≈0.2 W per qubit, so 10³ qubits need hundreds of watts at 4 K, one to two orders beyond a standard pulse-tube stage S[190]. Power per qubit, not line count, is the scaling problem.

Requires a gate-defined quantum-dot carrier at three dots per qubit, in the silicon and germanium quantum-dot spin architecture; replaces single-spin encoding, the central fork. Exchange pulses are nanoseconds, but a Clifford costs about two, so the encoding multiplies gate count, not gate time; readout still sets derived clock = sum of the syndrome round: gate layers + transport + readout + reset at 8.5×10⁻⁶ s, 6.3 µs of it readout. Verification: Λ₅/₃ = 4.7 and the 5.0×10⁻³ logical error come from a distance-5 repetition code, bit-flip only, not below-threshold operation of a full code; the [[4,2,2]] fidelity of 0.95 is post-selected D[190]. The UCLA 99.86% is single-qubit blind benchmarking, not device-wide D[417]; neither result is replicated.

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| HRL Laboratories | developer | USA | 18 exchange-only qubits, 4 K controller | D[190] |
| IBM | developer | USA | Acquired HRL; no spin milestone on its roadmap | Cfact |
| UCLA | research | USA | Always-on two-exchange qubit | D[417] |
| Quantum Machines | supplier | Israel | Named control-stack supplier to HRL | Cfact |

Money. 2026-06-02 · IBM · quantum programme commitment · >$10 B over five years · announced Cfact. 2026-08-26 · IBM · HRL acquisition completed · undisclosed · closed Cfact.

Market & supply chain. No encoding-specific supply chain exists; the distinctive asset is HRL's cryogenic controller, now IBM property. Removing microwave generation shrinks the rack vendors' share of the bill — the only spin encoding threatening the control duopoly. Pays into G3.

IP & standards. The 2000 exchange-universality result is prior art out of patent term S[416]; IBM's HRL purchase is the clearest IP consolidation, terms undisclosed Cfact. No dated patent family for the encoding is in a named database as of 4 Sep 2026.

Roadmaps & track record. IBM and HRL (2026-08-26 · acquisition completed · no dated qubit-count milestone, no spin entry on Starling 2029 or Blue Jay) Cfact. The July 2026 paper is a physics demonstration, not a scaling promise.

Strategic reading. If leakage holds near 10⁻⁴ per Clifford at scale, three dots per qubit buys away the microwave subsystem and the rack — a system win for IBM and any fab printing dense arrays. If single-spin encoding closes the calibration gap, the overhead is pure area cost and the rack vendors keep their position.

Confirm or demote in 12–24 months: a second laboratory reproducing the 18-qubit result; a full code below threshold; a dated IBM milestone. Best case 2029: IBM folds the cold sequencer into a foundry-scale device with unconditional performance. Worst case: a single-laboratory result. Open: (1) whether controller power per qubit falls two orders; (2) whether leakage stays flat as arrays grow; (3) whether always-on pulsing becomes the standard.