Exchange gate (spins; incl. shuttled-spin CZ) g_exch

A voltage pulse lowers the tunnel barrier between two neighbouring quantum-dot or donor spins, turning on Heisenberg exchange J for a set time to realise a SWAP-family entangler; nothing is radiated, so no antenna, laser or resonator is needed. Loss and DiVincenzo proposed spin qubits on it in 1998; DiVincenzo, Bacon, Kempe, Burkard and Whaley showed in 2000 that exchange alone is universal at ~3× more qubits and ~10× more two-qubit operations — the encoding HRL builds on S[416]. The shuttled variant moves one electron through a conveyor potential into exchange range with a distant partner.
Attributes: fully fabricated carrier; deterministic entangling at ≈10⁻⁷ s (~100 ns), static nearest-neighbour coupling by default.
Baseband voltage control, room temperature but moving cryogenic; error coherent, Pauli, leakage; manufacturing is CMOS.

J rises exponentially as the barrier is lowered and tunes electrically from near zero to tens of MHz; gate time goes as 1/J, which is why measured gates land at 58–500 ns for 10–90 MHz exchange. The exponential is the liability: the lever that makes J fast makes δJ/J large under gate-voltage and charge-trap noise, so there is a working point rather than a maximum — push J up and charge noise dephases the gate, pull it down and the longer pulse does. Hence HRL's finding that roughly 80% of two-qubit error is extrinsic control and calibration, not decoherence D[190]. Beneath that sit the residual ²⁹Si bath, 1/f charge noise at the oxide interface and small valley splitting, which makes leakage a first-class error. Moving the floor needs ²⁸Si enrichment, better interfaces, and a controller that keeps 1/f noise off the barrier gates.

Best exchange gate: HRL's exchange-only CNOT at 9×10⁻⁴ best reproducible, 3×10⁻³ mean across 18 qubits formed from 54 dots, single-qubit mean 2×10⁻⁴, sequenced by a 4 K controller in commercial 130 nm RF CMOS D[190]. At foundry scale Diraq and imec report 99.04–99.56% two-qubit and 99.9% SPAM on 300 mm SiMOS D[189]. The shuttled variant adds a weight-four parity check at 97.7% per 1.2 µm round trip, motion and idling supplying about a quarter of its error D[349]. SQC's 11-qubit donor device is different in kind: nuclear spins hyperfine-coupled to a shared electron, registers linked by exchange D[192]. Nothing beyond eight qubits publishes all-pairs fidelity.

It needs only gate electrodes and voltage pulses, so it rides existing lines: Intel 300 mm EUV (>24,000 devices per wafer D[199]; 96% tune-up yield on 232 devices of one wafer D[766]), imec 300 mm, GlobalFoundries 22FDX, STMicroelectronics FD-SOI. Two concentrations matter — GlobalFoundries has folded the modality into one business unit behind a USD 375 M CHIPS letter of intent C[353], and Quantum Machines' control stack sits under Diraq, HRL, imec, Equal1, Sandia and the UK NQCC C[449]. Export exposure is direct: the 2024-09-06 BIS rule created ECCN 3A901.a for CMOS circuits designed to run at or below 4.5 K — a design-intent test, so a cryo-CMOS controller design file of the HRL type is itself controlled G[301].

A double dot needs roughly 4–6 baseband channels, so wiring grows faster than qubit count under room-temperature control; HRL's answer is 296 lines and 366 DACs inside the fridge at ≤3.5 W, with no real-time room-temperature loop D[190]. Readout, not the gate, sets the cycle: 1–100 µs against a 58–500 ns gate. At 10³ qubits room-temperature fan-out is impractical without cryogenic integration; at 10⁴–10⁶ the crossbar schemes that cut wire count collide with the need to calibrate every exchange pair separately — this mechanism's unresolved architectural conflict.

It entangles two families: silicon and germanium quantum-dot spins (Intel, Diraq, Quantum Motion, HRL under IBM, Quobly, Equal1) and donor spins (SQC). It requires a gate-defined dot or donor plus baseband control, and provides the entangling layer both families build codes on — at HRL a distance-5 repetition code with Λ(5/3) = 4.7 over 200 rounds, which detects bit flips only and is therefore not a below-threshold result for a full code, plus a post-selected [[4,2,2]] at 0.95 logical fidelity D[190]. It conflicts with crossbar addressing, calibration being per pair. Derived round 8.5 µs on dot spins and 7.7 µs on donors, readout-limited, against the ~100–300 µs typically run: the gate is not the bottleneck. Neighbouring empty slot: an all-pairs, same-chip result past eight qubits.

HRL's headline figures and the 80% calibration split are vendor-reported and unreplicated D[190]. Diraq and imec's 99.04–99.56% is a population statistic over foundry devices, not an all-pairs same-chip result; imec's eight-qubit device validates exchange on one of four pairs D[197]. Nature's July 2026 spin-qubit feature was corrected on 2026-08-04, revising single-qubit error rates attributed to HRL and QuTech P[450]. No below-threshold logical memory exists on any spin platform as of 2026-09-04.

SQC's fidelities in [192] read 99.5–99.99%, with Bell states beyond 99%, in the arXiv abstract, and 99.10–99.99%, with Bell states up to 99.5%, in the Nature version; the main report's single 99.90% donor nuclear CZ does not appear in the abstract. Diraq's total raised (">USD 100 M") comes from trade press, not a company release. Not published: the financial terms of IBM's acquisition of HRL, and a dated patent-family count for exchange gates.

Money.

• 2025-11-06 · DARPA · QBI Stage B · ≤USD 15 M each · Diraq, Quantum Motion, SQC of eleven · awarded G[65]
• 2026-05-07 · Quantum Motion · Series C · USD 160 M · DCVC, Kembara · closed C[355]
• 2026-05-21 · Diraq · CHIPS letter of intent · up to USD 38 M · US Commerce · LOI, not an award G[300]
• 2026-08-26 · IBM · M&A, HRL Laboratories · terms undisclosed · closed C[204]

Market & supply chain. No lasers, no vacuum: the equipment is a CMOS line plus baseband electronics, so the supply chain is four foundry lines and one control vendor — a cost argument and a concentration risk at once. Diraq's "<USD 1 per qubit by 2031" is a target, not a cost R[211]. It sells G1 and G2 devices; IBM's purchase bets it carries to G3 and G4.

IP & standards. The foundational results — Loss–DiVincenzo 1998 and exchange-only universality in 2000 S[416] — are published, not proprietary, so defensible IP sits in device geometry, cryogenic control silicon and calibration software. No dated patent-family count specific to this gate was found as of 2026-09-04.

Roadmaps & track record. Diraq (promised 2026-08-27 · 150 k physical, 1 k logical by 2029 · six weeks earlier the same company said "thousands by 2029") R[211] — inconsistent. Intel (promised 2026-01 · Tunnel Falls scaling to "hundreds of dots" · no dated follow-up) C[207] — unscorable. IBM (promised 2026-07-23 · HRL close by end Q3 2026 · closed 2026-08-26) C[10], [204] — met.

Strategic reading. If exchange gates reach fault-tolerant fidelity, the winners are the foundries and whoever owns the cryogenic controller — the qubit becomes a process option, not a product — and the losers are platforms whose cost base is optics and vacuum. IBM's acquisition turns HRL into a hyperscaler's spin programme and forces Diraq, Quantum Motion and Quobly to compete on balance sheet. If calibration burden persists, spins stay a G1/G2 curiosity.

Falsifiable in 12–24 months: confirm/demote that a foundry device publishes all-pairs fidelity past eight qubits, and that IBM places a dated spin milestone on a public roadmap. Best case by 2029: a cryogenically sequenced foundry chip shows below-threshold logical memory with a full code. Worst case: uniformity stalls past ten qubits and roadmaps stay two orders ahead of hardware. Open: can calibration error fall without importing the controller's own error budget; does shuttled CZ displace static exchange; what IBM does with HRL's silicon.