Alloy Pioneer (Quobly)

Quobly · semiconductor spins · PLANNED (end-2026 target (cloud access for early users)) · 15 physical qubits · access: n/a

qubit type: Si FD-SOI gate-defined spin (CEA-Leti lineage)

gate mechanism: exchange 2Q

connectivity: 1-D linear nearest neighbour (per the Pioneer emulator model)

control: baseband; cryo-CMOS as the scaling route

control placement: room-temp baseband

readout: spin-to-charge + rf reflectometry

gate evidence: no published figure

flags: no device yet

1 Qubit carrier	Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▨ 🔎 Si FD-SOI gate-defined spin qubits (CEA-Leti lineage); PLANNED, target 100 physical qubits on a commercial chip; no device result published
2 Encoding	Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ◌ 🔎 single electron spin-1/2 in a gate-defined dot; no machine-specific encoding source
3 Gate mechanism	Exchange gate (spins; incl. shuttled-spin CZ) · primary ▨ 🔎 exchange 2Q; no gate fidelity published
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▨ 🔎 nearest neighbour; no device connectivity published
5 Control	Baseband electrical control (spins, Majorana) · primary ▨ 🔎 room-temperature baseband control; cryo-CMOS as the scaling route Cryo-CMOS controller (4 K / mK) · alternate ▨ 🔎 cryo-CMOS on FD-SOI as the stated scaling route; no implementation detail published
6 Readout	Spin-to-charge conversion + rf reflectometry · primary ◌ 🔎 spin-to-charge conversion + rf reflectometry; no machine-specific readout source
7 Code	— none — nothing in this layer ▨ 🔎 no code published; PLANNED device
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder published
9 Interconnect	— none — nothing in this layer ◌ 🔎 none
10 Manufacturing	300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▨ 🔎 STMicroelectronics 300 mm, 28 nm FD-SOI; isotopically enriched Si-28 entered ST production Dec 2025

evidence: ✅ 0 / 11