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Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) qd_spin

Electron or hole spin in a lithographically gated dot; exchange gives deterministic ns-scale two-qubit gates on a CMOS die.

Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge)

qd_spin · layer 1 Qubit carrier · demonstrated · since 2012
Open on the map

Electron/hole spin in a CMOS-fabricated dot; exchange (10–100 MHz) gives ns–100 ns gates; readout via charge sensor.

Brief →

Key references

[346] X. Xue et al., “Quantum logic with spin qubits crossing the surface code threshold,” Natur… · 2022
[194] J. Y. Huang et al., “High-fidelity spin qubit operation and algorithmic initialization abo… · 2024
[189] P. Steinacker et al., “Industry-compatible silicon spin-qubit unit cells exceeding 99% fid… · 2025
[195] J. Dijkema et al., “Simultaneous operation of an 18-qubit modular array in germanium,” arX… · 2026
[193] Y. Matsumoto et al., “Two-qubit logic and teleportation with mobile spin qubits in silicon… · 2026

Design space — attributes

(a) carrier affinity
fabricated
(b) time · entangling
50 ns · deterministic
(c) readout
spin-to-charge + rf reflectometry · 6.3 µs · non-destructive · mid-circuit
(d) mobility
static nearest-neighbour wiring
(e) control
low-frequency electrical @ room temperature
(f) error structure
coherent / calibration, stochastic Pauli, leakage
(g) manufacturing
CMOS foundry 300 mm

Evaluation space — dated attributes

2Q on 300 mm foundry wafer → 99.04–99.56% (Diraq/imec)
defines: error channel · 2025-09 · source
largest arrays → 18 qubits (Groove/QuTech Ge; HRL EO)
defines: count with quality · 2026-04 · source

Intel, Diraq, Quantum Motion, HRL→IBM, QuTech, Quobly, Equal1.

Standard records

T1 relaxation → 9.5 s · typical
300 mm foundry Si/SiGe (Diraq/imec), device A: spin relaxation T1 = 9.5 s · 2025-09 · source [D] ⓘ
T2 coherence (echo/DD) → 1.9 ms · typical
300 mm foundry Si/SiGe device A: Hahn-echo T2 = 1.9 ms; Ramsey T2* = 40.6 us. No CPMG reported · 2025-09 · source [D] ⓘ
1Q gate time → 400 ns · typical
300 mm foundry Si/SiGe: single-qubit (EDSR) gates ~400 ns at 99.45-99.97% fidelity; CZ 100-500 ns · 2025-09 · source [D] ⓘ
idle / memory error per round → not published · typical
No spin-qubit QEC round has been run; no idle/memory error per round is published · 2025-09 · source [D] ⓘ
leakage per gate → not published · typical
Leakage to valley or triplet states per gate is not reported in the 300 mm foundry paper or its device tables · 2025-09 · source [D] ⓘ

Actors & goals — annotations

Silicon / germanium quantum-dot spins — Intel, Diraq, Quantum Motion, HRL→IBM, QuTech/Groove, Quobly, Equal1 · G4 G7

Edges

needs: 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring)·
needed by: Exchange gate (spins; incl. shuttled-spin CZ)°, Exchange-only / singlet–triplet spin encoding, Spin shuttling (conveyor mode), Crossbar shared-line control (spins), Spin-to-charge conversion + rf reflectometry°, Single-spin (Loss–DiVincenzo) / nuclear-spin encoding°, Microwave / optical spin gates (defect centres, 1Q spins)°
alternatives: Donor spin (P in ²⁸Si)
° one of several that would do · the usual route, not a strict need

Used by 9 machines (9 primary · 0 alternate)

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1 — Fig. 1: Device and measurement protocol of the 18-qubit modular array. a, False-colored scanning electron microscope image of the 18-qubit device. O…
A composite figure: a false-coloured scanning electron micrograph of an 18-qubit gate-defined quantum-dot array (100 nm scale bar), plus charge-stability maps and calibration plots. It is Fig. 1 of "Simultaneous operation of an 18-qubit modular array in germanium" by J.J. Dijkema, N.W. Hendrickx and colleagues. Each spin qubit sits under a blue plunger gate, with red barrier gates tuning the coupling between neighbours; the arrowed panels show the tune-up chain, from charge stability and Pauli spin blockade to Rabi and two-qubit spectroscopy. “Fig. 1 — Fig. 1: Device and measurement protocol of the 18-qubit modular array. a, False-colored scanning electron microscope image of the 18-qubit device. Ohmic…” by J.J. Dijkema et al., arxiv.org/abs/2604.01063, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 2 — Fig. 2: Statistical analysis of single-qubit coherence and gate fidelities across the array. a, Chevron pattern measurements for all 18 spin-qubits,…
A data figure for 18 spin qubits in gate-defined germanium quantum dots. (a) Rabi chevrons, one colour map per qubit: spin-flip probability versus drive frequency (about 200–370 MHz across the array) and number of rotations; (b) grids of each qubit's driving efficiency and g-factor (0.29–0.51); (c)–(e) distributions across the array of dephasing time T2* (average 6.2 µs), coherence time T2 under CPMG decoupling, and single-qubit gate error (average fidelity near 99.8%). It comes from Dijkema, Zhang, Hendrickx and co-authors, 'Simultaneous operation of an 18-qubit modular array in germanium'; all were measured without changing the dc voltage settings. The g-factor spread gives each qubit its own drive frequency. “Fig. 2 — Fig. 2: Statistical analysis of single-qubit coherence and gate fidelities across the array. a, Chevron pattern measurements for all 18 spin-qubits, showing…” by J.J. Dijkema et al., arxiv.org/abs/2604.01063, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1 — Figure 1: a 3D model of the device. 3-layer TiN gate architecture (orange, blue, red) on the SiGe heterostructure (cyan and green). SiO2 (grey) insu…
Five-panel paper figure: (a) a cut-away 3-D model of a silicon/silicon-germanium spin-qubit device with three layers of titanium-nitride gates, an encapsulated cobalt micromagnet and vias above two quantum dots in the buried silicon layer; (b) a false-coloured scanning electron micrograph with gate labels and a 100 nm scale bar; (c) Coulomb oscillations; (d) a 1/f charge-noise spectrum; (e) a charge-stability diagram with occupations (0,0) to (2,2). It is Figure 1 of arXiv 2409.12731 by Koch, Godfrin, Adam and co-authors, on spin qubits processed on industrial 300 mm wafers. Notice that the micromagnet and vias belong to the same layered stack. “Fig. 1 — Figure 1: a 3D model of the device. 3-layer TiN gate architecture (orange, blue, red) on the SiGe heterostructure (cyan and green). SiO2 (grey) insulates the…” by Thomas Koch et al., arxiv.org/abs/2409.12731, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
qd_spin · layer 1 Qubit carrier · centrality 9.9 · demonstrated · since 2012 · updated 2026-09-30

Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge)

Electron or hole spin in a lithographically gated dot; exchange gives deterministic ns-scale two-qubit gates on a CMOS die.

Verdict. Only carrier fabricated on a 300 mm line at scale, but two-qubit fidelity has sat at 99.0–99.6% on foundry devices for a year and no array above 12 qubits has published all-pairs numbers.

Key references

Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).

Identity & lineage

An electron or hole is trapped in an electrostatic well ~50 nm across, formed by metal gates over a Si/SiGe quantum well, an electron accumulation layer at the SiMOS Si/SiO₂ interface, or a Ge/SiGe hole gas. The spin is the computational degree of freedom; the barrier between neighbouring dots sets an exchange coupling J, and pulsing J for ħπ/J gives a deterministic entangling gate. Loss and DiVincenzo proposed the architecture in 1998; the first single-spin and singlet–triplet qubits in silicon appeared 2010–2012, the lineage date used here.

Attributes, as the graph record records them:

  • a — affinity: 1.0, wholly fabricated; every dot is a lithography outcome.
  • b — characteristic time: ~50 ns per operation, entangling deterministic via exchange, not heralded.
  • c — readout: spin-to-charge conversion on an rf charge sensor, ~6 µs, non-destructive, mid-circuit capable.
  • d — mobility: static, unless a separate shuttling mechanism is invoked.
  • e — control: baseband gate voltages plus microwave or EDSR drive, electronics normally at room temperature.
  • f — error structure as the code sees it: coherent, Pauli, and leakage into valley or charge states.
  • g — manufacturing: CMOS.

Physics & limits

Three energy scales govern everything. Zeeman splitting (~10–100 µeV at 0.3–1 T) defines the qubit; exchange J, tunable over 10–100 MHz, defines the gate; valley splitting in silicon (0.1–0.3 meV, non-uniform because it tracks interface roughness) defines the leakage floor. Ge hole dots have no valley degeneracy and need no micromagnet, but their spin–orbit coupling turns electrical noise directly into dephasing.

Two baths set the coherence floor. Nuclear spins are suppressible: ²⁸Si enrichment gives Hahn-echo T2 of 1.31(4) ms on foundry material and Ramsey T2 of 41(2) µs D[197]. Charge noise is not — 1/f fluctuators in the oxide couple through exchange, so fidelity degrades exactly when J is on: the entangling interaction is also the dominant noise channel. Errors reach the code as coherent over-/under-rotation, Pauli dephasing, and leakage that repetition and surface codes miss without leakage reduction units (LRUs). HRL's dissection is the most useful single statement of where the error lives: about 80% of its CNOT error is extrinsic — control and calibration, not physics* D[190]. Moving the floor needs quieter dielectrics, more uniform valley splitting and better calibration, in that order of difficulty and the inverse order of cost.

Engineering state of the art

Best demonstrated as of 3 Sep 2026: two-qubit fidelity 99.04–99.56% on a 300 mm foundry SiMOS device D[189]; 18 qubits in one array, twice, on different materials D[190]D[195]. Typical at scale is worse, and the gap is the story — imec's eight-qubit 300 mm device validated a two-qubit gate on one of four double-dot pairs D[197]. No device above 12 qubits has published all-pairs two-qubit fidelities on this platform.

table
Year Figure Who Tag+key
2022-01 2Q 99.5% (gate-set tomography), Si/SiGe — first crossing of the surface-code threshold QuTech/TU Delft D[346]
2024-03 2Q 98.9% at 1 K operating temperature Diraq/UNSW D[194]
2025-09 2Q 99.04–99.56%, SPAM 99.9%, on 300 mm foundry SiMOS Diraq + imec D[189]
2026-04 18-qubit Ge 2×N array; 1Q mean 99.8%, median 99.9% Groove Quantum + QuTech D[195]
2026-05 CZ between two moving spins, 98.86 ± 0.29%, 58 ns QuTech/TU Delft D[193]
2026-07 8-qubit 300 mm device; Hahn-echo T2 1.31 ms; 2Q on 1 of 4 pairs imec + Diraq D[197]
2026-07 18 exchange-only qubits from 54 dots; 1Q 2×10⁻⁴, CNOT 3×10⁻³; d=5 repetition code, 200 rounds, Λ₅/₃ = 4.7 HRL Laboratories D[190]

The dominant error term today is not decoherence but calibration drift: 54 dots need hundreds of interdependent voltages, and the tune-up surface limits array size, not T2.

The first germanium array beyond a quasi-one-dimensional layout, a 6×6 hole-dot grid with one shared ('merged') barrier gate and individual plunger gates (QuTech, October 2026), formed 34 of its 36 dots, reached 30 coherently and ran 10 qubits placed sparsely, driven and read out five at a time; the sparse placement cut crosstalk 42× and gave simultaneous single-qubit Clifford fidelities above 99% P[898].

Manufacturing, materials & supply chain

The distinguishing claim is fabrication on unmodified CMOS lines — Intel reports >24,000 devices per 300 mm EUV wafer D[199] and 96% tune-up yield over 232 twelve-dot devices of one wafer D[766], and Quantum Motion characterised 1,024 dots in five minutes on GlobalFoundries 22FDX C[200]. Process detail belongs to the 300 mm CMOS foundry brief; wafer-scale statistics exist here and for no other carrier.

Materials are the exposure. Enriched ²⁸Si is a genuine single point of failure: ASP Isotopes began commercial production of enriched silicon-28 at its second Pretoria facility on 2025-03-27, with two undisclosed US customers C[347]. On 2026-07-16 the US DOE Office of Isotope R&D and Production announced that ORNL and PNNL now make silane at 99.9999% ²⁸Si and germane with Ge-73 below 1 ppm, "at least 100×" more depleted than any commercial material — a deliberate re-shoring G[348]. Ge/SiGe heterostructures come from a handful of academic reactors (Scappucci's group at Delft), a narrower bottleneck than the fab. Export-control exposure is indirect: the dies are ordinary CMOS, but enriched isotopes and dilution refrigerators fall under the 2024 multilateral quantum controls (US ECCN 3A901/3A904).

Control, readout & I/O burden

Baseband voltages plus a microwave or EDSR drive per qubit, and one rf reflectometry sensor per one-to-several dots. No lasers — the I/O problem is line count and heat. HRL's 4 K controller (≤3.5 W typical, 366 DACs, 296 lines) sequenced a full 18-qubit QEC experiment with no room-temperature real-time electronics D[190]; UNSW/Diraq have shown mK cryo-CMOS beside the qubits D[203]. Those controllers are the cryo-CMOS control brief's subject.

The wall is readout, not gates. At ~6 µs spin-to-charge conversion plus settling the cycle runs to hundreds of microseconds — three orders slower than the 50 ns gate, so the syndrome round sets the logical clock. At 10³ qubits line count is survivable only with crossbar shared-line addressing; at 10⁴ sensor count and dissipation dominate; at 10⁶ neither dedicated lines nor per-qubit sensors survive.

Role in the stack

The node sits on one architecture, Silicon / germanium quantum-dot spins. It requires a 300 mm CMOS foundry; it provides the dots consumed by exchange gates, exchange-only and singlet–triplet encoding, conveyor-mode spin shuttling, crossbar shared-line control and spin-to-charge readout. It replaces donor spins (SQC's precision-placed phosphorus), which buy 99.10–99.99% gates on 11 qubits D[192] at the cost of no foundry path — the switching price in one line.

Derived clock for the architecture = sum of the syndrome round: gate layers + transport + readout + reset = 8.5 µs, readout 6.3 µs of it and reset 1 µs. Everything the node enables is downstream of it, so a failure here has no fallback elsewhere. The neighbouring empty slot is fast sensor-free readout — Pauli spin blockade (PSB) below 1 µs at >99.9%; nothing in the graph fills it.

Evidence — how the numbers were measured

Headline two-qubit numbers come from interleaved randomised benchmarking or gate-set tomography on the best pair on the die — a legitimate protocol reporting an illegitimate summary, capturing neither crosstalk nor calibration drift. HRL's d=5 repetition code over 200 rounds is the only spin result measuring error in situ under continuous operation, and its Λ₅/₃ = 4.7 D[190] is bit-flip-only, not below-threshold logical memory, which no spin platform has shown.

Conflicts. Diraq's messaging conflicts on scale: a 2026-07-09 release said "thousands of qubits by 2029", the 2026-08-27 roadmap says 150,000 physical and 1,000 logical by 2029 R[211]fact; take the roadmap as the company's position and the discrepancy as evidence about the company. No replication of the 300 mm two-qubit result outside the imec line exists.

On a single-hole Ge/SiGe qubit (T2 = 136 ns, Rabi frequency 19 MHz) the same idle gate scores 99.21(3)% by interleaved randomised benchmarking but 97.48(9)% by gate-set tomography, whose sequences contain long runs of consecutive idles that exceed T2, while the X/2 and Y/2 gates agree within 0.3 points (99.81% and 99.88% by gate-set tomography) P[888]. An idle or memory figure for this carrier is meaningful only with its protocol named.

SemiQon's €17.5 M comes from paywalled trade press with the round type unstated P[354]P[352], and Groove Quantum's €16 M (2026-04-30) has no primary source Pfact. The PatSnap dataset (~60 records) omits HRL, imec, Diraq and Quantum Motion, so it is a sample, not a census P[356]. Not published: SemiQon's cumulative funding and the PostScriptum amount; Groove Quantum's investors; the value of the IBM–HRL deal, and any dated spin milestone on IBM's roadmap C[204]; and ASP Isotopes' enrichment level, capacity and customers, with the DOE quantities and funding C[347]G[348].

Actors & economics

Who.
Organisation Role Country What exactly they do Evidence
Diraq developer AU SiMOS qubits on imec 300 mm; 2Q 99.04–99.56%; 1 K operation D[189]D[194]
HRL Laboratories developer US Exchange-only SiGe, 18 qubits, self-sequenced d=5 QEC D[190]
IBM investor US Acquired HRL; adds spins to a superconducting roadmap C[204]
Intel developer US 300 mm EUV spin devices; 12-qubit Tunnel Falls at Argonne D[199]P[207]
Quantum Motion developer UK 22FDX dots; full-stack CMOS system delivered to NQCC C[200]
QuTech (TU Delft) research NL Shuttled-spin gates, parity checks, Ge heterostructures D[193]D[349]
Groove Quantum developer NL 18-qubit Ge array, spun out of the Delft Ge programme D[195]
Quobly developer FR ²⁸Si FD-SOI lots at ST Crolles since 2025-12 C[350]
Equal1 developer IE Six-qubit rack unit, sold as Bell-1 and since May 2026 as RacQ; installed at ESA Frascati in July 2026 C[351] fact fact
SemiQon supplier FI VTT spin-out; cryo-CMOS chips fabricated in Espoo P[352]
GlobalFoundries supplier US Quantum Technology Solutions unit; 22FDX wafers C[353]

Money.

  • 2025-02-24 · SemiQon · round · €17.5 M (€15 M equity + €2.5 M grant) · European Innovation Council · closed P[354]
  • 2025-11-06 · Diraq, Quantum Motion, SQC · DARPA QBI Stage B · up to $15 M each · DARPA · three of eleven · announced fact[65]
  • 2026-01-15 · Equal1 · round · $60 M · ISIF · >$85 M cumulative · closed Cfact[351]
  • 2026-04-30 · Groove Quantum · round · €16 M · undisclosed · €26 M cumulative · closed Pfact
  • 2026-05-07 · Quantum Motion · Series C · $160 M · DCVC, Kembara · closed C[355]
  • 2026-05-21 · Diraq · US CHIPS letter of intent · up to $38 M · Dept of Commerce · LOI G[300]
  • 2026-05-21 · GlobalFoundries · US CHIPS LOI, multi-modality quantum foundry · $375 M · Dept of Commerce · LOI G[300]C[353]
  • 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · €134 M cumulative · closed C[350]
  • 2026-06 · Silicon Quantum Computing · NRFC (donor route) · A$60 M · Australia NRFC · closed fact
  • 2026-07-03 · SemiQon · strategic investment · undisclosed · PostScriptum · closed P[352]
  • 2026-08-26 · IBM / HRL · M&A completed (announced 2026-07-23) · terms undisclosed · sellers Boeing and General Motors, still application partners · definitive C[204]

Market & supply chain. Nobody sells spin qubits; the sold goods are foundry runs, enriched isotopes and cryo-electronics. Foundry access is bought from imec, GlobalFoundries and STMicroelectronics, with GF productising it as a business unit in 2026 and naming Diraq, Equal1 and Quantum Motion as customers C[353]. Isotope supply is the concentrated risk — one commercial producer of scale plus a restarted US national-lab capability C[347]G[348]. Diraq's "<$1/qubit at two million qubits" R[211] is a projection, not a price. What pays today is G3 (HRL's QEC work, QBI Stage B) and G7 (Quantum Motion at NQCC, Equal1 at ESA); nothing here is bought for G1, G2 or G5.

IP & standards. The one dated database view available — a PatSnap analysis of 2026-06-02, updated 2026-08-21 — is thin: ~60 records 2005–2026, with NewSouth Innovations (UNSW, Diraq's licensing root) largest at five filings, ahead of SIAT/SIMIT, MIT, Intel and SQC P[356]. Too small to be a census. No litigation is on record, no spin-specific standards body exists, and HRL's controller IP is now unpublished inside IBM.

Roadmaps & track record. Diraq (promised 2026-08-27 · for 2029 · 150 k physical / 1 k logical, >2 M by 2031) — six weeks earlier it said "thousands by 2029" R[211]: keep the fidelities, discount the counts. Quobly (2026-06 · for 2032 · millions of qubits) — funded and fabbing at ST, no published multi-qubit device: an intention. SQC (for 2033 · commercial scale) — real 11-qubit donor result D[192], unfalsifiable until 2030. Quantum Motion — the only actor to have delivered a system to a customer on schedule C[200]. Intel — 12 qubits at Argonne, no successor chip and no dated roadmap as of 3 Sep 2026 P[207]: alive but unguided. IBM/HRL — no spin milestone yet on Starling (2029) or Blue Jay (mid-2030s) C[204].

Strategic reading. If the platform succeeds the winners are foundries and isotope suppliers, not qubit designers: a SiMOS qubit is a process recipe, and once qualified the marginal die is cheap and differentiation moves to calibration software. That is why IBM bought HRL — not for 18 qubits but for a cryo-CMOS control stack and packaging reusable across modalities: a supplier acquisition dressed as a platform bet. The losers are pure-play spin startups, whose bargaining power against a foundry that has just productised quantum manufacturing is falling. Manufacturability is the platform's only defensible argument, and if 2Q fidelity is still 99.0–99.6% through 2027 with arrays under 20 qubits, it stops being enough.

Outlook & open questions

Confirm if by end-2027 a group publishes all-pairs two-qubit fidelities above 99% on a ≥16-qubit array, or a spin device shows below-threshold logical memory in a distance-3-to-5 surface code, or IBM places a dated spin milestone on its public roadmap. Demote if foundry two-qubit fidelity is still 99.0–99.6% in mid-2027, if Intel makes no further spin announcement, or if Diraq revises its 2029 figure downward a second time.

Best case by 2029: a few hundred physical qubits on a qualified 300 mm process with shared-line control and a working logical memory — two orders of magnitude short of Diraq's 150 k. Worst case: the platform stays a foundry demonstration, the startups consolidate into IBM, GlobalFoundries and STMicroelectronics, and spin qubits become a control-electronics business with qubits attached.

Open questions. (1) Is 99.5%-class two-qubit fidelity reproducible across all pairs of a die, or only the pair that tunes up? (2) Can valley splitting be made uniform enough that leakage stops being a per-device lottery? (3) Does readout get below 1 µs without a charge sensor per qubit? (4) Did IBM buy a qubit or a control stack?

References
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