QM-One
QM-One
Register profile — the machine's variant of its architecture
qubit type: Si-MOS gate-defined electron spin
gate mechanism: exchange 2Q, ESR/EDSR 1Q
connectivity: "scalable tile architecture"; degree not published
control: integrated cryo-CMOS on the qubit die; three 19-inch server racks with the dilution refrigerator inside the footprint
control placement: cryo-CMOS on-die
readout: rf single-electron-box gate-based reflectometry - 99.2% in under 6 us
gate evidence: no published figure
flags: count unpublished, no published error rates, source not confirmed
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▣ Fig. 1a (SEM of Si nanowire transistor with split gates); Fig. 3a (wrap-around-gate device) ✅ Si-MOS gate-defined electron spin; delivered system's qubit count not published |
| 2 Encoding | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ▤ §II Spin-dependent tunneling (single-electron spin up/down in a QD) ✅ bare electron spin-1/2, Loss–DiVincenzo encoding |
| 3 Gate mechanism | |
| 4 Connectivity / transport | |
| 5 Control | Cryo-CMOS controller (4 K / mK) · primary ▨ ✅ integrated cryo-CMOS on the qubit die; three 19-inch server racks with dilution refrigerator inside the footprint (NQCC, Sep 2025) |
| 6 Readout | Spin-to-charge conversion + rf reflectometry · primary ▣ Fig. 1 (device and measurement setup); Fig. 2, Fig. 4 (spin readout fidelity); §II–III; §VI.B ✅ rf single-electron-box gate-based reflectometry, 99.2% in <6 µs (Oakes et al., PRX 13, 011023, 2023) |
| 7 Code | — none — nothing in this layer ▨ 🔎 no code family named in public material; SiQEC FT project and CUDA-Q Logical compilation; nothing on hardware |
| 8 Decoder | |
| 9 Interconnect | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) · primary ◌ 🔎 on-die fan-out by the integrated cryo-CMOS (inferred from the related 384-qubit chip with integrated cryogenic CMOS control); no fan-out figure published for the delivered system |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▤ §VI.A Fabrication details ✅ 300 mm CMOS-compatible commercial foundry process |
Standard records
QND fidelity / survival → 0.992 · best (rf single-electron-box readout in under 6 us)
2023 · source
evidence: ✅ 6 / 11