Single-spin (Loss–DiVincenzo) / nuclear-spin encoding enc_spin_ld

One physical spin-1/2 is one qubit: an electron or hole in a gate-defined dot, or a nucleus bound to a donor or defect. Loss and DiVincenzo set it out in 1998 — dot-confined electron spins, rotations by a local resonant field, two-qubit gates by pulsed exchange D[819]. The nuclear variant drives a ³¹P or defect nucleus by radio frequency through hyperfine coupling to an electron, trading speed for coherence: nuclei as data, electrons as ancillas. Attributes: affinity — a near-natural carrier with no composite structure; error — coherent dephasing plus Pauli error, no leakage subspace, no control modality or fabrication of its own.

The computational space is the whole two-level system: nothing leaks out, so every error is Pauli or coherent as the codes assume — and nothing is filtered out either. T2* is set by residual ²⁹Si hyperfine coupling and by charge noise turned into a frequency shift through the g-factor or a micromagnet; ²⁸Si purification removes the first term. Coherence is not the limit today: QuTech's microwave-free array bounds its hopping gate at ≥99.50(6)% D[820] and foundry two-qubit gates sit at 99.04–99.56% D[189] — a calibration-limited plateau, not a T2 limit. Deeper purification, baseband control and cold calibration move the floor.

Dominant term: calibration drift across the array; no device above 12 qubits publishes all-pairs fidelities.

The 99.90% donor nuclear-spin CZ fidelity cannot be isolated in the SQC abstract, whose published range is 99.10–99.99%. Intel's "scale to hundreds of dots" carries no date or milestone.

The encoding adds no structure — one dot or donor per qubit, about a third of the dots an exchange-only qubit needs — and inherits the carrier's process: Intel's 300 mm EUV line at >24,000 devices per wafer D[199] and 96% tune-up yield on 232 devices of one wafer D[766], plus 22FDX, FD-SOI and imec 300 mm. The burden it imposes is control: one resonant drive per qubit frequency, so at 10³ qubits the wall is frequency crowding and microwave power at millikelvin, at 10⁴–10⁶ the count of addressable tones.

The base encoding for the silicon and germanium quantum-dot architecture, the donor architecture and defect-spin network nodes. It is replaced in some designs by exchange-only encoding — the central fork: microwave hardware for minimum footprint and no leakage, against extra dots for baseband-only control and a leakage channel. It adds nothing to derived clock = sum of the syndrome round: gate layers + transport + readout + reset, which on silicon stays readout-dominated at 8.5×10⁻⁶ s. Verification: the 99.50(6)% is a lower bound and the accompanying ~49 µs Hahn-echo a maximum, both routinely requoted as point estimates D[820]; the main report's "99.90% donor nuclear CZ" conflicts with the published SQC range D[192]; and HRL's 2×10⁻⁴ single-qubit error belongs to exchange-only encoding, not this one D[190].

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| Intel | developer | USA | 300 mm EUV single-spin devices | D[199] |
| Diraq | developer | Australia | Electron spins on 300 mm imec SiMOS | D[189] |
| QuTech/TU Delft | research | Netherlands | Microwave-free baseband control | D[820] |
| Silicon Quantum Computing | developer | Australia | Nuclear-spin encoding on donors | D[192] |
| Quobly | developer | France | Single spins on STMicroelectronics FD-SOI | Cfact |

Money. 2026-06-03 · Quobly · Series A · €115 M · Bpifrance, SEALSQ, STMicroelectronics · €134 M cumulative · closed Cfact. 2026-06 · SQC · NRFC · A$60 M · Australia's National Reconstruction Fund · closed fact.

Market & supply chain. No supplier is specific to this encoding — it is a layout and pulse-sequence choice on shared CMOS lines — and its one distinctive demand, a resonant drive per qubit, is what the control-electronics duopoly sells. Pays into G2, G3 and G6.

IP & standards. The 1998 proposal is prior art long out of patent term D[819]; no dated patent family for single-spin encoding found in a named database as of 4 Sep 2026.

Roadmaps & track record. Intel (2026-01-06 · 12 qubits at Argonne, "scale to hundreds of dots" · no successor chip, no dated roadmap) fact. Diraq (2026-08-27 · 150 k physical, 1 k logical by 2029 · its 2026-07-09 release said "thousands by 2029") Rfact. Both are orders of magnitude beyond any demonstrated device.

Strategic reading. Every spin team can fall back on it, so it differentiates nobody: value accrues to the fab and the control stack. If baseband control matures the microwave vendors lose their strongest claim; if encoded qubits win, area matters less than wafer economics.

Confirm or demote in 12–24 months: all-pairs fidelities above 12 qubits; baseband control beyond a 2×2 array. Best case 2029: baseband plus 1 K operation removes most microwave I/O at >99.5% two-qubit fidelity. Worst case: the plateau holds. Open: (1) whether hopping-gate control scales past four qubits; (2) whether the calibration-limited diagnosis generalises; (3) which platform shows a below-threshold logical qubit.