Tunnel Falls
Tunnel Falls
Register profile — the machine's variant of its architecture
qubit type: Si/SiGe gate-defined electron spin, Loss-DiVincenzo encoding
gate mechanism: EDSR/ESR 1Q + voltage-pulsed exchange 2Q; native CZ
connectivity: 1-D nearest neighbour, degree <= 2
control: Horse Ridge II - 22 nm CMOS cryo-controller at 4 K, 16 spin qubits per chip, 22 high-speed DAC channels; Pando Tree - 10-20 mK demultiplexer giving bias and pulses to up to 64 qubit terminals from one signal line and nine digital lines
control placement: cryo-CMOS at 4 K (qubits at ~1.1-1.2 K)
readout: spin-to-charge conversion sensed by SET / rf reflectometry
gate evidence: no published figure
codes: quantum_repetition
flags: no published error rates
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▤ Abstract (Tunnel Falls 12-dot linear arrays) ✅ 12-qubit linear array of Si/SiGe gate-defined electron spins (Jun 2023); deployed to Argonne Jan 2026 |
| 2 Encoding | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ◌ 🔎 bare electron spin-1/2, Loss–DiVincenzo encoding |
| 3 Gate mechanism | Exchange gate (spins; incl. shuttled-spin CZ) · primary ▨ 🔎 EDSR/ESR 1Q + voltage-pulsed exchange 2Q, native CZ; 1Q ~99.9%; no published 2Q fidelity for Tunnel Falls itself |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▨ 🔎 1-D nearest neighbour, degree ≤ 2 (12-dot linear array); 2-D arrays stated as next step, not shown |
| 5 Control | Cryo-CMOS controller (4 K / mK) · primary ▨ ✅ Horse Ridge II: 22 nm cryo-CMOS controller at 4 K, 16 spin qubits/chip, 22 DAC channels; Pando Tree: mK router demultiplexing to 64 qubit channels Room-temperature electronics + per-qubit coax/flex · alternate ▨ 🔎 Tunnel Falls itself is driven from room temperature; Horse Ridge is the separate 4 K vehicle |
| 6 Readout | Spin-to-charge conversion + rf reflectometry · primary ◌ 🔎 spin-to-charge conversion sensed by SET / rf reflectometry |
| 7 Code | |
| 8 Decoder | |
| 9 Interconnect | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) · primary ▦ blog post (Pando Tree integration with Tunnel Falls) ✅ Pando Tree demultiplexer at 10–20 mK: bias and pulses to up to 64 qubit terminals from one signal line + nine digital lines (Horse Ridge II), on the same PCB as a Tunnel Falls chip (20 Jun 2024) |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▤ Abstract (300 mm manufacturing line; EUV lithography) ✅ Intel D1 Hillsboro, 300 mm DUV + EUV; >24,000 devices/wafer, ~95% wafer yield, 96% full 12-dot device yield |
Standard records
control lines per qubit → 0.156 lines/qubit · best (Pando Tree: 1 signal + 9 digital lines from Horse Ridge II for 64 qubit terminals — per terminal; per qubit higher, a spin qubit uses several terminals)
corrected 26 Sep 2026: the earlier 1.56e-2 counted one line and read terminals as qubits; dated 20 Jun 2024 by Intel · 2024 · source
device yield → 0.96 · typical (full 12-dot device yield; ~95% wafer yield, >24,000 devices per wafer)
2024 · source
evidence: ✅ 4 / 11