Diraq 8-qubit silicon spin quantum computer at Equinix Sydney

Raveh Neeman

doi:10.5281/zenodo.22674814

Diraq (with Equinix) · semiconductor spins · ANNOUNCED (installation due Oct 2026) (Sep 2026) · 8 physical qubits · access: n/a (not yet installed; access model not published)

architecture: Silicon / germanium quantum-dot spins · Open on the map

Register profile — the machine's variant of its architecture

qubit type: silicon spin qubit (modified silicon transistors)

gate mechanism: not published

control: self-contained cryogenic cooling and control electronics; whole system draws less than 20 kW

flags: no published error rates, press sources only, a target, not a device

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▨ opening paragraph (silicon spin quantum computer inside an Equinix data center in Sydney) ✅ silicon spin quantum computer with one 8-qubit silicon chip; qubits are modified silicon transistors
2 Encoding	Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ◌ 🔎 single-spin qubit assumed (family-determined)
3 Gate mechanism	Exchange gate (spins; incl. shuttled-spin CZ) · primary ◌ 🔎 exchange two-qubit gate assumed (family-determined; gates not described)
4 Connectivity / transport	Static nearest-neighbour lattice · primary ◌ 🔎 static nearest-neighbour coupling assumed; Diraq and imec showed an eight-qubit linear Si-MOS array (Jul 2026), not confirmed as this chip
5 Control	— undisclosed — exists, nothing published ▨ 🔎 cryogenic cooling and control electronics self-contained in the system, under 20 kW; Diraq technology page describes chip-packaged cryogenic electronics, not confirmed here
6 Readout	Spin-to-charge conversion + rf reflectometry · primary ◌ 🔎 spin-to-charge readout (family-determined)
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code announced; system for testing and partner work
8 Decoder	— none — nothing in this layer ◌ 🔎 no decoder; no QEC announced
9 Interconnect	— none — nothing in this layer ▨ 🔎 one 8-qubit chip; upgrades by chip replacement
10 Manufacturing	300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▨ manufacturing paragraph (existing semiconductor foundries) ✅ qubits made like phone and laptop chips, in existing semiconductor foundries

evidence: ✅ 2 / 10