RacQ (Bell-1)
RacQ (Bell-1)
Register profile — the machine's variant of its architecture
qubit type: Si electron spin in quantum dots (GlobalFoundries 22FDX)
gate mechanism: exchange 2Q; ESR 1Q (mechanism not named on Equal1's pages); average gate durations 140 ns (1Q), 200 ns (2Q)
connectivity: nearest neighbour (family-determined; array layout not published)
control: UnityQ quantum system-on-chip: qubits, control electronics and error-correction logic in CMOS; multi-tile controller and cryogenic ARM cores at 300 mK; closed-cycle cryocooler at 0.3 K, no dilution refrigerator; 19-inch rack, 400 kg (unveiling release; the product page gives 200 kg), 1,600 W single-phase; Dell PowerEdge R770 server alongside
control placement: cryo-CMOS on-die at 0.3 K
readout: spin-to-charge, parity readout, 99% readout fidelity (UnityQ page; the RacQ product page lists 99.9%)
gate evidence: a number stated by the vendor, protocol unstated
flags: conflicting claims, company claim
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Gate-defined quantum-dot spin (Si/SiGe, SiMOS, Ge) · primary ▦ UnityQ page ('Spin qubits', 'Quantum dots demonstrated in commercial CMOS') ✅ silicon spin qubits in quantum dots made in commercial CMOS; RacQ 'is powered by UnityQ' |
| 2 Encoding | Single-spin (Loss–DiVincenzo) / nuclear-spin encoding · primary ▦ UnityQ page (qubit state 'electron spin ↑ / ↓') ✅ single electron spin up/down (Loss–DiVincenzo) |
| 3 Gate mechanism | Exchange gate (spins; incl. shuttled-spin CZ) · primary ▦ 🔎 UnityQ: 1Q 99.9% (Clifford RB), 2Q 99.3% (interleaved RB), 140 ns / 200 ns average; gate mechanism not named (exchange, as for Bell-1) |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ◌ 🔎 exchange-coupled neighbouring dots (family-determined); array layout not published ('35 monolithic quantum cells') |
| 5 Control | Cryo-CMOS controller (4 K / mK) · primary ▦ UnityQ page ('Multi-tile controller operating at 300 mK'; 'Precision control and measurement wrapped around the qubit array') ✅ control and measurement electronics in CMOS around the qubit array; multi-tile controller at 300 mK; closed-cycle cryocooler at 0.3 K, 1,600 W, one 19-inch rack |
| 6 Readout | Spin-to-charge conversion + rf reflectometry · primary ▦ UnityQ specifications ('Readout fidelity 99%', 'Parity readout') ✅ parity readout, 99% readout fidelity |
| 7 Code | |
| 8 Decoder | Cryogenic / on-chip decoder (cryo-CMOS, SFQ) · alternate ▦ UnityQ page ('ARM cores operating at cryogenic temperatures'; 'Low-latency foundation for real-time error correction') ✅ not run: UnityQ integrates 'error-correction logic' and cryogenic ARM cores at 300 mK as a 'low-latency foundation for real-time error correction' |
| 9 Interconnect | Cryogenic signal fan-out for spin arrays (router die, 3D stacked wiring) · primary ◌ 🔎 on-die routing between the qubit array and the co-integrated controller (22FDX, 0.3 K); no separate fan-out published |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▦ UnityQ page ('Built on GlobalFoundries 22FDX') ✅ GlobalFoundries 22FDX; RacQ 'built using standard semiconductor processes' |
evidence: ✅ 7 / 12