Donor spins in silicon on the map bar: Donor spins

The architecture in the report (§8.3)

8.3.14 Donor spins — Donor spins in silicon (spin_donor)

The idea. A Donor spin (P in ²⁸Si) (donor), written atom by atom by STM hydrogen-resist lithography (fab_stm): the ³¹P nucleus is the data qubit, the bound electron its drive, coupler and readout probe. The fact exploited: a nucleus has no orbital degree of freedom, hence no first-order coupling to the charge noise that holds foundry dots at 99.04–99.56% [D][189]; every gate still passes through the electron, which has one. The bet (Table 8.3): the longest coherence in a solid is worth a write process with no foundry.

What it needs. Nine of ten layers filled, one primary technology each, alternates in layers 3 and 5. The donor requires STM placement because exchange between donor electrons falls exponentially with separation, so a donor a few nanometres off leaves a dead register [G]. Exchange requires baseband gate pulses; readout requires a charge sensor beside the electron; the surface code requires a 2D lattice, which two registers of four and five nuclei [D][192] do not form. Two replaces edges, dot vs donor and foundry vs STM, separate it from the quantum-dot architecture; every other technology is shared. Layer 9 is empty: the dot architecture's fan-out requires a CMOS router die and cryo-CMOS control, both absent here, so a large array would be a hybrid with the dot architecture.

Where it stands. One machine, one device: the 11-qubit donor processor (Silicon Quantum Computing), demonstrated: nine ³¹P nuclear qubits in two registers with two electron ancillas; an electron CROT (controlled rotation) at 99.64% in 1.25 µs, 3.6×10⁻³, the family's best among devices (§8.4, H2); single-qubit gates to 99.99%; GHZ states over eight nuclei [D][192]. Nuclear Hahn echo reaches 660 ms [P][275]. No code runs; readout is non-demolition through the electron; control sits at room temperature. Six of ten cells documented. SQC holds a QBI Stage B slot [65], [66]; its roadmap dates no intermediate milestone. Flag: no foundry route.

Exceptions and borrowings. A single machine cannot test the architecture's drawing; SQC, fitting no other architecture better, amends layer 4. Inside a register the nuclei couple all-to-all through the shared electron, a star rather than a lattice; nearest neighbour holds only between registers (layer 4 too narrow). The nuclear gates are hyperfine-conditional rotations driven by ESR and NMR (nuclear magnetic resonance), not exchange, which serves only the electron CROT; baseband control excludes that resonant drive, which the architecture carries as alternates — Microwave / optical spin gates (g_mwspin) in layer 3, room-temperature electronics (ct_rt) in layer 5 — while SQC's cells record only exchange and baseband control. The fan-out cell records the missing slot, not a component (data gap: none). The manufacturing cell's SkyWater partnership is no foundry route: SkyWater's stated role is superconducting resonators and packaging [C][276] and it has been IonQ's since 31 July 2026 [C][19]. No other architecture uses donor or STM; single-spin encoding and baseband control recur on colour-centre machines and on Majorana 1 (and Majorana 2).

The next test. By March 2028 (§5.2 names no donor milestone): a donor device beyond eleven qubits, or a placement-yield distribution for SQC's automated patterning, hours to minutes per 70-dot device and hundreds of thousands of dots patterned [C][277], confirms the write step scales; eleven qubits and no yield figure then demote it to a physics testbed. QBI Stage C would be the first independent check.

What the builders say. Silicon Quantum Computing argues from purity and precision: its processors contain only silicon and phosphorus atoms, which it says cuts bit-flip errors [C][863], and it places phosphorus atoms with 0.13 nm precision and claims qubit quality rises as qubits are added [C][864]. Its 11-qubit processor, two multi-atom registers, reached Bell-state fidelities up to 99.5% on local and non-local nuclear-spin pairs [D][192]. In November 2025 SQC entered Stage B of DARPA's Quantum Benchmarking Initiative, committing to a detailed research roadmap to 2033 [C][865], the year its site gives for universal, fault-tolerant quantum computers [R][863].

Machines of this architecture (register: 1, of them 1 devices, 1 gate-capable). Silicon Quantum Computing — 11-qubit donor processor (demonstrated, 11).

Cells outside the architecture's slots: none — every cell of every machine sits in a slot of the architecture.